Self-referencing PUF device, read-write circuit, and read-write circuit array

Abstract

A self-referencing PUF device, a read-write circuit, and a read-write circuit array. The PUF device comprises: an intermediate magnetic tunnel junction (MTJ) (10), and a first MTJ (20) and a second MTJ (30) respectively located on two sides of the intermediate MTJ (10). There are gaps between the first MTJ (20) and the intermediate MTJ (10) and between the second MTJ (30) and the intermediate MTJ (10), respectively. The first MTJ (20), the intermediate MTJ (10), and the second MTJ (30) use the same free layer. The width of the free layer gradually decreases from the part located on the intermediate MTJ (10) to the part located on the first MTJ (20) and to the part located on the second MTJ (30), respectively, so as to form magnetic anisotropy gradients. A voltage control layer (40) is disposed on the free layer and in an area located on the intermediate MTJ (10). In the present application, the MTJs at two ends can serve as read-write devices, and in an initial state, a magnetic domain wall is fixed in an area of the intermediate MTJ (10), so that by driving the magnetic domain wall to randomly relax toward two sides on the basis of anisotropy, a low-resistance state is formed when the magnetic domain wall is stabilized on the MTJ at one side, while the MTJ at the other side is in a high-resistance state, so as to form a self-referencing structure of the device, thereby increasing the read margin of the device.

Description

Self-referenced PUF device, read / write circuit and read / write circuit array Technical Field

[0001] This disclosure belongs to the field of semiconductor technology, specifically relating to a self-referenced Physical Unclonable Function (PUF) device, read / write circuit, and read / write circuit array. Background Technology

[0002] As people's requirements for the integration, high computing power and data security of electronic devices gradually increase, the storage devices of electronic devices can be designed as in-memory computing circuits, and PUF devices are used as encryption devices in in-memory computing circuits to generate keys for data.

[0003] The principle behind key generation by PUF devices lies in constructing a physically non-clonable function based on ferromagnetic properties and the non-ideal characteristics of the device, which serves as the key for data. Correspondingly, the formation of PUF devices requires collaboration between magnetic domain wall devices and the circuit. In-memory computing circuits, on the other hand, determine the storage state based on resistance magnitude, thereby performing data reading and writing. Therefore, the storage reliability of in-memory computing circuits depends on the sense margin (SM) of the resistance.

[0004] However, conventional PUF devices contain domain wall devices with low tunnel magnetoresistivity (TMR), which makes them prone to misreading under disturbances, resulting in low storage reliability of in-memory computing circuits. Summary of the Invention

[0005] This disclosure proposes a self-referenced PUF device, a read / write circuit, and a read / write circuit array. By designing a PUF device formed by three magnetic tunnel junctions (MTJs), and triggering domain wall fluctuations to one side of the MTJs, complementary high and low resistance states are generated inside the PUF device, thereby improving the read margin of the device.

[0006] The first aspect of this disclosure provides a self-referenced magnetic tunnel junction (PUF) device, the PUF device comprising: a central magnetic tunnel junction (MTJ), and a first MTJ and a second MTJ located on both sides of the central MTJ respectively;

[0007] There are gaps between the first MTJ and the second MTJ and the intermediate MTJ respectively. The first MTJ, the intermediate MTJ and the second MTJ use the same free layer. The width of the free layer gradually decreases from the part located in the intermediate MTJ to the parts of the first MTJ and the second MTJ respectively, so as to form a magnetic anisotropy gradient.

[0008] A pressure-controlled layer is provided above the free layer and in the region located in the middle MTJ.

[0009] In this embodiment of the disclosure, in the initial state, the first MTJ receives an input current, and a single magnetic domain wall is formed in the first MTJ.

[0010] In this embodiment of the disclosure, when the voltage control layer applies a voltage to the intermediate MTJ, the domain walls are pinned to the pinning region in the intermediate MTJ corresponding to the voltage control layer, so that the PUF device enters a state where it can generate keys.

[0011] In this embodiment of the disclosure, after the voltage control layer stops applying voltage to the intermediate MTJ, the magnetic domain wall relaxes to the first MTJ or the second MTJ under the drive of the magnetic anisotropy gradient, and stabilizes in the region with the smallest width in the first MTJ or the region with the smallest width in the second MTJ.

[0012] In this embodiment of the disclosure, in the initial state, the region of the free layer corresponding to the first MTJ and the region corresponding to the second MTJ both have their magnetic moment direction spin-down;

[0013] If the domain wall is stable in the region where the width of the first MTJ is the smallest, the free layer rotates in the direction of the magnetic moment in the region where the domain wall of the first MTJ is stable with spin upward, so that the resistance of the first MTJ is less than the resistance of the second MTJ.

[0014] If the domain wall is stable in the region where the width of the second MTJ is the smallest, the free layer rotates in the direction of the magnetic moment in the region where the domain wall of the second MTJ is stable with spin upward, so that the resistance of the second MTJ is less than the resistance of the first MTJ.

[0015] In this embodiment of the disclosure, the material of the pressure control layer is a composite oxide.

[0016] An embodiment of the second aspect of this disclosure provides a read / write circuit, the read / write circuit including a first driving circuit, a second driving circuit, a third driving circuit, and a self-referenced PUF device, the self-referenced PUF device being as described in the first aspect;

[0017] The first driving circuit is connected to the first MTJ and is used to input a level signal to the first MTJ;

[0018] The second driving circuit is connected to the second MTJ and is used to input a level signal to the second MTJ;

[0019] The third driving circuit is connected to the intermediate MTJ and is used to input a level signal to the intermediate MTJ.

[0020] In this embodiment of the disclosure, a state control line is also included, which is connected to the voltage control layer of the intermediate MTJ;

[0021] The first driving circuit includes a first bit line and a first switching device; the second driving circuit includes a second bit line and a second switching device; the third driving circuit includes a read / write control circuit and a third switching device.

[0022] The source of the first switching device is connected to the first bit line, the gate of the first switching device is connected in parallel with the state control line, and the drain of the first switching device is connected to the bottom electrode of the first MTJ.

[0023] The source of the second switching device is connected to the second bit line, the gate of the second switching device is connected to the state control circuit, and the drain of the second switching device is connected to the bottom electrode of the second MTJ.

[0024] The drain of the third switching device is connected to the bottom electrode of the intermediate MTJ, and the gate of the third switching device is connected to the read / write control circuit.

[0025] In this embodiment of the disclosure, when a high-level signal is input to the voltage-controlled layer of the intermediate MTJ through the state control line,

[0026] The first bit line drives the first switching device to input a high-level signal to the first MTJ, the second bit line drives the second switching device to input a low-level signal to the second MTJ, and the read / write control circuit drives the third switching device to input a low-level signal to the intermediate MTJ. The self-reference PUF device generates a key, and the read / write circuit is in write data state.

[0027] The first bit line drives the first switching device to input a high-level signal to the first MTJ, the second bit line drives the second switching device to input a high-level signal to the second MTJ, and the read / write control line drives the third switching device to input a high-level signal to the intermediate MTJ. The read / write circuit is in read data state.

[0028] An embodiment of the third aspect of this disclosure provides a read / write circuit array, including a preset number of read / write circuits, a control circuit, and a precharge amplifier, wherein any read / write circuit is as described in the second aspect;

[0029] The control circuit includes clamping circuits connected in parallel with the preset number of read and write circuits, so as to control the working state of the corresponding read and write circuits by outputting voltage through the clamping circuits.

[0030] The precharge amplifier includes an amplification circuit, and a first voltage detection circuit and a second voltage detection circuit connected in parallel with the amplification circuit; the first voltage detection circuit is connected in parallel with the first MTJ of the preset number of read / write circuits; the second voltage detection circuit is connected in parallel with the second MTJ of the preset number of read / write circuits.

[0031] For the read / write circuit that is controlled by the control circuit to enter the data reading state, the voltage of the first MTJ in the read / write circuit is read by the first voltage detection circuit, the voltage of the second MTJ in the read / write circuit is read by the second voltage detection circuit, the difference between the voltage read by the first voltage detection circuit and the voltage read by the second voltage detection circuit is amplified, and the read data is output based on the amplified difference.

[0032] The technical solutions provided in this disclosure have at least the following technical effects or advantages:

[0033] The PUF device proposed in this disclosure includes: a central magnetic tunnel junction (MTJ), and a first MTJ and a second MTJ located on either side of the central MTJ. The first MTJ, the central MTJ, and the second MTJ share the same free layer, the width of which gradually decreases from the portion located in the central MTJ towards the portions of the first and second MTJs. This creates a magnetic anisotropy gradient. A voltage-controlled layer is provided above the free layer in the region of the central MTJ. Thus, the two MTJs can be used as readout devices. In the initial state, the domain walls can be fixed in the region of the central MTJ. Then, by driving the domain walls to randomly relax anisotropically to both sides, after the domain walls stabilize on one side of the MTJ, that MTJ forms a low-resistivity state, while the corresponding MTJ on the other side forms a high-resistivity state, thereby constituting a self-reference structure for the device. This mode improves the readout margin of the device.

[0034] Additional aspects and advantages of this disclosure will be set forth in part in the description which follows, and in part will be obvious from the description or may be learned by practice of this disclosure. Attached Figure Description

[0035] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure. Furthermore, the same reference numerals denote the same parts throughout the drawings.

[0036] In the attached diagram:

[0037] Figure 1 shows a schematic diagram of the structure of a self-referenced PUF device provided in an embodiment of the present disclosure;

[0038] Figure 2 shows an exemplary partitioning diagram of the free layer of the self-referenced PUF device in Figure 1;

[0039] Figure 3 illustrates an exemplary scenario of magnetic domain wall relaxation provided in an embodiment of this disclosure;

[0040] Figure 4 shows a schematic diagram of the read / write circuit provided in an embodiment of the present disclosure;

[0041] Figure 5 shows a schematic diagram of the structure of a read / write circuit array provided in an embodiment of the present disclosure;

[0042] Figure 6 illustrates a schematic diagram of the encryption and decryption process provided in an embodiment of this disclosure;

[0043] Figure 7 shows a schematic diagram comparing the simulation results of the reading features provided in an embodiment of this disclosure. Detailed Implementation

[0044] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0045] The terminology used in the following embodiments of this disclosure is for the purpose of describing particular embodiments and is not intended to limit the technical solutions of this disclosure. As used in the specification and appended claims of this disclosure, the singular expressions “a,” “an,” “the,” “the,” “the,” and “this” are intended to include the plural expressions as well, unless the context clearly indicates otherwise. It should also be understood that although the terms first, second, etc., may be used in the following embodiments to describe a class of objects, the objects are not limited to these terms. These terms are used to distinguish specific implementations of that class of objects. For example, the terms first, second, etc., are used in the following embodiments to describe MTJs, but MTJs are not limited to these terms. These terms are only used to distinguish different MTJs. Other classes of objects that may be described using the terms first, second, etc. in the following embodiments are similarly described and will not be repeated here.

[0046] It should be noted that, unless otherwise stated, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0047] The following describes the implementation scenarios and related technologies involved in the embodiments of this disclosure.

[0048] This disclosure relates to in-memory computing technology scenarios. In-memory computing circuits, as a type of integrated circuit, integrate data computation and data storage on the same chip or circuit unit, significantly reducing data transfer between the processor and memory, thereby reducing power consumption and improving data processing speed and efficiency. Therefore, they are widely used in various electronic devices. To improve data security while ensuring integration, PUF (Power Activated Field Function) devices are typically integrated into the in-memory computing circuit. In this circuit, the PUF device acts as a key generation and storage component. During data writing, the key generated by the PUF is used for data encryption; during data reading, the key generated by the PUF is used for decryption.

[0049] PUF (Programmable Array) devices utilize the physical property of ferromagnetic materials forming random magnetic domain wall structures during manufacturing to generate unique and uncopyable authentication keys. In other words, the functionality of PUF devices relies on ferromagnetic properties. Correspondingly, PUF devices are typically semiconductor devices with ferromagnetic properties, such as MTJ (Metal-Metal-Jet) devices.

[0050] In the process of reading and writing data, the in-memory computing circuit uses a reference resistor R. ref It represents the state of the stored data. Specifically, according to R... ref The reference voltage V can be obtained. ref If the voltage V is read read Greater than the reference voltage V ref The output is high, and the read data is, for example, "1"; if the read voltage V read Less than the reference voltage V ref The output is low, and the read data is, for example, "0". Correspondingly, read margin is typically used to characterize the reliability of in-memory computing circuits. Read margin refers to the ability to accurately distinguish different storage states (such as "0" and "1") when reading data from a memory cell (which can be understood as an in-memory computing circuit). Read margin can be expressed as: |V read -V ref | / V ref ×100%.

[0051] Taking a commonly used 1T1M spin-transfer torque (STT) memory consisting of one transistor (T) and one magnetic tunnel junction (MTJ), or a 2T1M spin-orbit torque (SOT) magnetic random access memory consisting of two transistors (T) and one magnetic tunnel junction (MTJ), as an example, the reference resistor R... ref All can be characterized as R ref =1 / 2(R)p +R ap ), where R p R is the resistance of the MTJ when the reference layer and the free layer are magnetized in parallel. ap The resistance of the MTJ when the reference layer and free layer are magnetized in antiparallel mode.

[0052] Because the tunnel magnetoresistance (TMR) of the same MTJ is low, the read margin of conventional in-memory computing circuits is low, and the fluctuation of the MTJ spin process can easily cause misreading of the MTJ state, thereby reducing the read and write reliability of the in-memory computing circuit.

[0053] In view of this, the technical solution proposed in this disclosure improves the read margin of the device by designing a PUF device formed by three magnetic tunnel junctions (MTJs), and by triggering the domain wall fluctuations to one side of the MTJ, complementary self-reference high and low resistance states are generated inside the PUF device, thereby improving the read margin of the device and thus improving the read and write reliability of the in-memory computing circuit.

[0054] The following description, in conjunction with the accompanying drawings, describes a self-referenced PUF device, a read / write circuit, and a read / write circuit array according to embodiments of the present disclosure.

[0055] As shown in Figure 1, this embodiment of the present disclosure provides a self-referenced PUF device, which includes: an intermediate MTJ 10, and a first MTJ 20 and a second MTJ 30 located on both sides of the intermediate MTJ 10. The first MTJ 20 and the second MTJ 30 have gaps with the intermediate MTJ 10. The first MTJ 20, the intermediate MTJ 10, and the second MTJ 30 use the same free layer 100, and the width of the free layer 100 gradually decreases from the portion located in the intermediate MTJ 10 towards the portions of the first MTJ 20 and the second MTJ 30 to form a magnetic anisotropy gradient. A voltage-controlled layer 40 is provided above the free layer 100 and in the region located in the intermediate MTJ 10.

[0056] For example, the width of the widest part of the free layer 100 is, for example, 50 nanometers (nm), and the free layer 100 gradually shrinks from the part located in the middle MTJ 10 toward the parts of the first MTJ 20 and the second MTJ 30, for example, it can form a rhombus shape.

[0057] It should be understood that the width of the free layer 100 gradually decreases from the middle MTJ 10 towards the first MTJ 20 and the second MTJ 30, respectively, in order to form a magnetic anisotropy gradient to support the relaxation of magnetic domain walls between MTJs under anisotropic action. Therefore, the rhomboid shape of the free layer 100 shown in Figure 1 is merely schematic and does not limit the structure of the self-referenced PUF device of this disclosure. In some other implementations, the free layer 100 may also be elliptical, and this disclosure is not restrictive in this regard.

[0058] To facilitate the explanation of the relaxation process of the magnetic domain walls between the intermediate MTJ 10, the first MTJ 20 and the second MTJ 30, as well as the rotation of the magnetic moment direction in each region of the free layer 100, the embodiments of this disclosure divide the free layer 100 in FIG1 into several regions.

[0059] An exemplary partition of the free layer 100 in Figure 1 is shown in Figure 2, including 5 regions. Region 1 can correspond to the first MTJ 20; Region 2 can correspond to the gap between the first MTJ 20 and the intermediate MTJ 10, that is, the barrier region between the first MTJ 20 and the intermediate MTJ 10; Region 3 can correspond to the intermediate MTJ 10; Region 4 can correspond to the gap between the intermediate MTJ 10 and the second MTJ 30, that is, the barrier region between the second MTJ 30 and the intermediate MTJ 10; Region 5 can correspond to the second MTJ 30.

[0060] For example, the lengths of regions 1 and 5 can be 31 nm, meaning the lengths of both the first MTJ 20 and the second MTJ 30 are 31 nm. The lengths of regions 2 and 4 can be 45 nm, and the length of region 3 can be 20 nm, meaning the length of the middle MTJ 10 is 20 nm.

[0061] Each of the intermediate MTJ 10, the first MTJ 20, and the second MTJ 30 comprises, from top to bottom, a free layer (FL) (also called the top ferromagnetic layer), a barrier layer (BL), a reference layer (RL), and a bottom electrode (BE), which will not be detailed here. In the initial state, i.e., without any input current or voltage, the magnetic moment direction of the free layer 100 is spin-down. Furthermore, the magnetic moments of the reference layers in the intermediate MTJ 10, the first MTJ 20, and the second MTJ 30 are all spin-down. Therefore, the magnetic moment direction of the reference layer in the first MTJ 20 is parallel to the magnetic moment direction of region 1 of the free layer 100, and the first MTJ 20 is in a high-resistivity state. Similarly, the magnetic moment direction of the reference layer in the second MTJ 30 is parallel to the magnetic moment direction of region 5 of the free layer 100, and the second MTJ 30 is also in a high-resistivity state.

[0062] For example, the first MTJ 20 receives the input current and forms a single magnetic domain wall. Then, if the voltage-controlled layer 40 applies a voltage to the intermediate MTJ, the magnetic domain wall can be pinned to region 3 shown in Figure 2, i.e., the pinning region in the intermediate MTJ 10 corresponding to the voltage-controlled layer 40, allowing the PUF device to enter a key-generating state. At this time, the magnetic domain wall can oscillate with the aid of thermal perturbation.

[0063] It should be understood that the above explanation is only based on the example of the first MTJ 20 receiving the input current. In another implementation, the second MTJ 30 receives the input current, and if the voltage control layer 40 applies a voltage to the intermediate MTJ, the magnetic domain walls can also be pinned to region 3 shown in Figure 2. This will not be repeated here.

[0064] Furthermore, after the voltage control layer 40 stops applying voltage to the intermediate MTJ 10, the magnetic domain wall relaxes to the first MTJ 20 or the second MTJ 30 under the drive of the magnetic anisotropy gradient, and stabilizes in the region with the smallest width in the first MTJ 20 or the region with the smallest width in the second MTJ 30.

[0065] Referring to Figure 3, which illustrates an exemplary scenario of domain wall relaxation according to an embodiment of this disclosure, for example, during a time interval of 0 to 2 nanoseconds (ns), a current is applied to the first MTJ 20, forming a single domain wall and driving it to move to region 3. Simultaneously, a pinning voltage is applied to the voltage-controlled layer 40, forming a low magnetocrystalline anisotropy potential well pinning region in region 3. At this time, as shown in Figure 3 from 2 ns to 20 ns, the domain wall is pinned in region 3 and oscillates randomly around its geometric center at room temperature. During key creation, the domain wall is in a metastable state after the voltage control voltage of the voltage-controlled layer 40 is removed, and under the influence of thermal perturbation and shape anisotropy, it randomly relaxes from region 3 to region 2 or region 4, and after oscillation, it stabilizes in the region with the smallest width in region 1.

[0066] The phenomenon of domain walls stabilizing in any MTJ can be called "nucleation." If the domain wall stabilizes in the region with the smallest width of the first MTJ 20, the magnetic moment direction of the free layer 100 in the region where the domain wall of the first MTJ 20 is stable (i.e., region 1 in Figure 2) rotates to spin-up, making the resistance of the first MTJ 20 less than that of the second MTJ 30. Similarly, if the domain wall stabilizes in the region with the smallest width of the second MTJ 30, the magnetic moment direction of the free layer in the region where the domain wall of the second MTJ 30 is stable (i.e., region 5 in Figure 2) rotates to spin-up, making the resistance of the second MTJ 30 less than that of the first MTJ 20.

[0067] It should be noted that during the random relaxation of the magnetic domain walls, the pinned magnetic domain walls remain in region 3, while the degree of fluctuation in the relaxed region varies depending on the degree of thermal perturbation, and the range of the nucleation region also varies. Correspondingly, the size of the region in the free layer 100 where the magnetic moment direction rotates to spin-up is relatively random.

[0068] It can be seen that if the two MTJs are used as readout devices, the domain walls can be driven to relax randomly to both sides based on anisotropy. After the domain walls stabilize on one side of the MTJ, the MTJ forms a low-resistivity state, while the corresponding MTJ on the other side is in a high-resistivity state, thus forming a self-reference structure of the device. This mode can improve the readout margin of the device.

[0069] In the process of digital storage and in-memory encryption, the first MTJ 20 and the second MTJ 30 can be used as read devices. After the self-reference PUF device is nucleated, the normalized vertical magnetization (M) of the PUF device is used. z This can be embodied in the following way: For example, if the reference layer in the first MTJ 20 is parallel to the magnetization direction of region 1 of the free layer 100, it is considered that the magnetic domain wall precesses to M. z=-1, during the reading process, the first MTJ 20 exhibits low resistance, and the data stored in the first MTJ 20 is "0". If the magnetization direction of the reference layer in the first MTJ 20 is antiparallel to the magnetization direction of region 1 of the free layer 100, it is considered that the magnetic domain wall has precessed to M. z =1. During the reading process, the first MTJ 20 exhibits high resistance, and the data stored in the first MTJ 20 is "1". At the same time, the magnetization direction of the free layer 100 in region 5 (corresponding to the second MTJ 30) is opposite to the magnetization direction in region 1 (corresponding to the first MTJ 20). Therefore, the key information generated by the self-referenced PUF device can be determined.

[0070] As can be seen, in this embodiment, the first MTJ is used as the storage terminal of the key unit, and the second MTJ is used as a reference resistor instead of a traditional reference resistor. Therefore, the read margin can be expressed as: |V 第一MTJ -V 第二MTJ | / V 第二MTJ ×100%, while the read margin is greater than the traditional read margin.

[0071] In some implementations, the voltage-controlled layer 40 in Figure 1 can be made of composite oxides, such as barium titanate (BaTiO3), bismuth ferrite (BiFeO3), or hafnium zirconium oxide (HfZrO2). Since composite oxides possess spontaneous polarization that can be tunable by an external electric field, their saturation polarization can be achieved via a bipolar approach. The ferroelectricity originates from the non-centrosymmetric displacement of atoms in the lattice below the Curie temperature, and this displacement can affect the ferromagnetic / ferroelectric (multiferroic) interface. Based on this, using composite oxide materials as the voltage-controlled layer offers advantages such as fast write / read speeds, good durability, and high energy efficiency.

[0072] In summary, this disclosure presents a PUF device formed by three MTJs. By triggering domain wall fluctuations to one side of the MTJ, complementary high and low resistance states are generated inside the PUF device, thereby forming a self-referenced structure on the same device. This not only improves the read margin of the device but also helps to reduce the size of the device and improve the integration level.

[0073] Referring to Figure 4, Figure 4 shows a schematic diagram of the structure of a read / write circuit provided in an embodiment of the present disclosure. The read / write circuit shown in Figure 4 includes a first driving circuit 41, a second driving circuit 42, a third driving circuit 43, and a self-referenced PUF device. The self-referenced PUF device is as shown in the embodiment illustrated in Figure 1, and will not be described in detail here.

[0074] The first driving circuit 41 is connected to the first MTJ and is used to input a level signal to the first MTJ; the second driving circuit 42 is connected to the second MTJ and is used to input a level signal to the second MTJ; the third driving circuit 43 is connected to the intermediate MTJ and is used to input a level signal to the intermediate MTJ. The first driving circuit 41, the second driving circuit 42, and the third driving circuit 43 can be used to collaboratively drive the self-referenced PUF device to generate keys and read data.

[0075] For example, referring again to Figure 4, the read / write circuit also includes a state control line 44, which is connected to the voltage-controlled layer of the intermediate MTJ.

[0076] The first driving circuit 41 includes a first bit line 411 and a first switching device 412. The source of the first switching device 412 is connected to the first bit line 411, the gate of the first switching device 412 is connected in parallel with the state control line 44, and the drain of the first switching device 412 is connected to the bottom electrode of the first MTJ. In this way, current can be output to the source of the first switching device 412 through the first bit line 411, and a level signal can be output to the bottom electrode of the first MTJ through the drain of the first switching device 412, thereby driving the operating state of the first MTJ.

[0077] The second driving circuit 42 includes a second bit line 421 and a second switching device 422. The source of the second switching device 422 is connected to the second bit line 421, the gate of the second switching device 422 is connected to the state control line 44, and the drain of the second switching device 422 is connected to the bottom electrode of the second MTJ. In this way, current can be output to the source of the second switching device 422 through the second bit line 421, and a level signal can be output to the bottom electrode of the second MTJ through the drain of the second switching device 422, thereby driving the operating state of the second MTJ.

[0078] The third driving circuit 43 includes a read / write control line 431 and a third switching device 432. The drain of the third switching device 432 is connected to the bottom electrode of the intermediate MTJ, and the gate of the third switching device 432 is connected to the read / write control line 431. The read / write control line 431 can output current to the source of the third switching device 432, thereby outputting a level signal to the bottom electrode of the intermediate MTJ through the drain of the third switching device 432, thus driving the operating state of the intermediate MTJ.

[0079] In some implementations, the state control line 44 can be a line used to control the operating states of the first switching device 412, the second switching device 422, and the third switching device 432, as well as the self-referenced PUF device. The read / write control line 431 can be a line used to control the write data state or the read data state of the read / write circuit.

[0080] Based on the above description of the operation process of the self-referenced PUF device, it can be seen that after power-on, the read / write circuit can enter a preparatory state. At this time, the state of the self-referenced PUF device can be that the domain walls are pinned to the pinned region. Accordingly, the first bit line 411 can drive the first switching device 412 to input a low-level signal to the first MTJ, the second bit line 421 can drive the second switching device 422 to output a high-level signal to the bottom electrode of the second MTJ, and the state control line 44 can input a high-level signal to the voltage-controlled layer of the intermediate MTJ. Since this is the preparatory state for operation, rather than the process of generating a key or reading data, the read / write control line 431 can drive the third switching device 432 to input a low level to the intermediate MTJ.

[0081] It should be understood that the above is only an illustrative example using the first MTJ terminal receiving a high-level signal and the second MTJ terminal receiving a low-level signal. In another implementation, the second MTJ terminal can also receive a high-level signal and the first MTJ terminal a low-level signal. This will not be elaborated upon here.

[0082] Furthermore, in the ready state, the read / write circuit can be controlled to generate a key or read data through the coordinated action of the first bit line 411, the second bit line 421, and the read / write control line 431.

[0083] In some embodiments, if the first switching device 412 is driven by the first bit line 411 to input a high-level signal to the first MTJ, the second switching device 422 is driven by the second bit line 421 to input a low-level signal to the second MTJ, and the third switching device 432 is driven by the read / write control line 431 to input a low-level signal to the intermediate MTJ, then the self-referenced PUF device can be driven to generate a key. In this case, the read / write circuit can be in write data state. The implementation process of the self-referenced PUF device generating the key, and the domain wall relaxation process involved in the key generation process, are described in the above embodiments and will not be repeated here.

[0084] In other embodiments, if the first switching device 412 is driven by the first bit line 411 to input a high-level signal to the first MTJ, the second switching device 422 is driven by the second bit line 421 to input a high-level signal to the second MTJ, and the third switching device 432 is driven by the read / write control line 431 to input a high-level signal to the intermediate MTJ, the read / write circuit is in a data reading state.

[0085] The drive levels for the read / write circuit to enter each operating state can be shown in Table 1, for example:

[0086] Table 1

[0087] For example, the first switching device 412, the second switching device 422, and the third switching device 432 can be implemented as transistors. Since the two ends MTJ of the self-reference PUF device are used as read / write terminals, the read / write circuit described in this embodiment can be referred to as a 3T2M memristor unit.

[0088] As can be seen, due to the adoption of the 3T2M structure, the memristor cell of this embodiment has a high read margin, which helps to reduce misreads caused by spin process fluctuations, thereby improving the reliability of read and write operations.

[0089] The read / write circuit shown in Figure 4 can be a 3T2M memristor unit in a memory-computing integrated circuit. A 3T2M memristor unit stores 1 bit of data. If the data read and written by the memory-computing integrated circuit includes multiple bits, the memory-computing integrated circuit can be implemented as a read / write circuit array.

[0090] Referring to Figure 5, which shows a schematic diagram of the structure of a read / write circuit array provided in an embodiment of this disclosure, the read / write circuit array provided in this embodiment may include a preset number of read / write circuits 50, control circuits 51, and pre-charge sense amplifiers (PCSA) 52. Any read / write circuit can be as shown in the embodiment illustrated in Figure 4.

[0091] The specific value of the preset quantity can be determined based on the number of bits of data processed by the read / write circuit array. For example, if the read / write circuit array processes 64 bits of data, then the preset quantity can be 64, meaning the read / write circuit array can include 64 3T2M memristor units. This disclosure does not limit this aspect.

[0092] The control circuit 51 includes clamping circuits connected in parallel with the preset number of read / write circuits 50, so as to control the working state of the corresponding read / write circuits by outputting voltage through the clamping circuits.

[0093] For example, the control circuit 51 can be connected to the status control line and read / write control line of the read / write circuit, and the clamping circuit of the control circuit 51 can be connected to the first bit line and the second bit line of the read / write circuit. Further, the control circuit 51 can be connected to the address signal (V... access From a preset number of read / write circuits 50, a read / write circuit is selected, and then a clamping voltage (V) is output to the first and second bit lines of the selected read / write circuit. clamp The system outputs pulses to the read / write circuit to drive it to generate a key or read data.

[0094] Referring to the enlarged view of the precharge amplifier 52 in Figure 5, the precharge amplifier 52 may include an amplification circuit, and a first voltage detection circuit and a second voltage detection circuit connected in parallel with the amplification circuit; the first voltage detection circuit is connected in parallel with the first MTJ of the preset number of read / write circuits; the second voltage detection circuit is connected in parallel with the second MTJ of the preset number of read / write circuits. For the read / write circuits controlled by the control circuit to enter the data reading state, the voltage of the first MTJ in the read / write circuit is read through the first voltage detection circuit, and the voltage of the second MTJ in the read / write circuit is read through the second voltage detection circuit. The difference between the voltages read by the first voltage detection circuit and the voltages read by the second voltage detection circuit is amplified, and the read data is output based on the amplified difference.

[0095] The first voltage detection circuit and the second voltage detection circuit can be implemented as transistors, such as transistor T in Figure 5. x and transistor T y .

[0096] It should be noted that the precharge amplifier 52 is used to amplify the data read from the read / write circuit when the read / write circuit is in a data reading state. For example, for any read / write circuit, the precharge amplifier 52 can initially charge the amplifier circuit to Vamplifier. dd When the read / write circuit is driven into read data state, the precharge amplifier 52 receives the read enable signal (i.e., CLK signal) of the read / write circuit and sets the voltage V on the first MTJ side of the read / write circuit to... L Set as the gate voltage of transistor Tx, and the voltage V on the second MTJ side of the read / write circuit. R Set as transistor T y The gate voltage, and thus the discharge rate of the amplifier branch, affects V. L and V R Differential amplification produces complementary output results. Where V out Output high voltage level to facilitate the first MTJ storing data bit "1"; V out The low output voltage level facilitates the storage of data bit "0" in the first MTJ, enabling the key reading operation of the memristor unit in the circuit.

[0097] Referring to Figure 6, during the data writing phase of the read / write circuit array described in Figure 5, the difference between the initial data and the key (two binary strings of equal length) can be obtained through XOR Boolean logic operations. This difference is then used to calculate the Hamming distance (HD) between the two strings, generating the encrypted data bits for that data bit, thus obtaining the encrypted data of the initial data. During the decryption phase, a key can be generated by driving each read / write circuit in the array. Then, the encrypted data and the key are decrypted using an inverse operation to obtain the initial data.

[0098] To verify the performance of the 3T2M device in this embodiment, a 2T1M device is used as a comparison. In a simulation example, referring to Figures 7(a) and (b), for example, a level signal is input to the state control line WL of the two circuits at 300ps in the circuit. The V of the 2T1M device... L and V R The output read voltage is shown in Figure 7(a), while the V of the 3T2M device is... L and V R The output read voltage is shown in Figure 7(b). For example, with a 500ps enable pulse on the PCSA, the PCSA's voltage to the device's V... L and V R Differential amplification is performed, and the data stored in the device is output.

[0099] As can be seen from the comparison of Figures 7(a) and (b), when the circuit reaches steady state, the read margins of the 2T1M device are 26% and 29.8%, respectively, while the margins of the 3T2M device reach 132.6% and 67.2%, respectively. The read margin of the 3T2M device is much higher than that of the 2T1M device. This demonstrates that the 3T2M device exhibits higher reading accuracy when facing process fluctuations or external interference.

[0100] To further verify the tolerance of the 3T2M device and the reference generator circuit in handling fluctuations, the simulations described above in this disclosure introduce a σ = 5% variation on the transistor to obtain the V of the 2T1M device. L and V R The corresponding output is shown in Figure 7(c), where V of the 3T2M device is... L and V R The corresponding output is shown in Figure 7(d). It can be seen that regardless of whether the reading is "1" or "0", with the high read margin of the 3T2M device, V L and V R The voltage values ​​do not overlap during process fluctuations. Therefore, the technical solution disclosed herein can effectively avoid misreading during the reading process.

[0101] In summary, the PUF device proposed in this disclosure includes: a central magnetic tunnel junction (MTJ), and a first MTJ and a second MTJ located on either side of the central MTJ. The first MTJ, the central MTJ, and the second MTJ share the same free layer, the width of which gradually decreases from the portion located in the central MTJ towards the portions of the first and second MTJs. This creates a magnetic anisotropy gradient. A voltage-controlled layer is provided above the free layer in the region of the central MTJ. Thus, both MTJs can be used as readout devices. In the initial state, the domain walls can be fixed in the region of the central MTJ. Then, by driving the domain walls to randomly relax anisotropically to both sides, after the domain walls stabilize on one side of the MTJ, that MTJ forms a low-resistivity state, while the corresponding MTJ on the other side forms a high-resistivity state, thereby constituting a self-reference structure for the device. This mode improves the readout margin of the device.

[0102] Although alternative embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make further changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0103] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this disclosure. It should be understood that the above description is only a specific embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of this disclosure should be included within the scope of protection of this invention.

Claims

1. A self-referenced physically unclonable function (PUF) device, characterized in that, The PUF device includes: a central magnetic tunnel junction (MTJ), and a first MTJ and a second MTJ located on both sides of the central MTJ, respectively; There are gaps between the first MTJ and the second MTJ and the intermediate MTJ respectively. The first MTJ, the intermediate MTJ and the second MTJ use the same free layer. The width of the free layer gradually decreases from the part located in the intermediate MTJ to the parts of the first MTJ and the second MTJ respectively, so as to form a magnetic anisotropy gradient. A pressure-controlled layer is provided above the free layer and in the region located in the middle MTJ.

2. The self-referenced PUF device according to claim 1, characterized in that, In the initial state, the first MTJ receives the input current, and a single magnetic domain wall is formed in the first MTJ.

3. The self-referenced PUF device according to claim 2, characterized in that, When the voltage control layer applies a voltage to the intermediate MTJ, the magnetic domain wall is pinned to the pinning region in the intermediate MTJ corresponding to the voltage control layer, so that the PUF device enters a state where it can generate a key.

4. The self-referenced PUF device according to claim 3, characterized in that, After the voltage control layer stops applying voltage to the intermediate MTJ, the magnetic domain wall relaxes to the first MTJ or the second MTJ under the drive of the magnetic anisotropy gradient, and stabilizes in the region with the smallest width in the first MTJ or the region with the smallest width in the second MTJ.

5. The self-referenced PUF device according to claim 4, characterized in that, In the initial state, the free layer has a spin-down magnetic moment in the regions corresponding to the first MTJ and the second MTJ. If the domain wall is stable in the region where the width of the first MTJ is the smallest, the free layer rotates in the direction of the magnetic moment in the region where the domain wall of the first MTJ is stable with spin upward, so that the resistance of the first MTJ is less than the resistance of the second MTJ. If the domain wall is stable in the region where the width of the second MTJ is the smallest, the free layer rotates in the direction of the magnetic moment in the region where the domain wall of the second MTJ is stable with spin upward, so that the resistance of the second MTJ is less than the resistance of the first MTJ.

6. The self-referenced PUF device according to any one of claims 1-5, characterized in that, The pressure control layer is made of a composite oxide.

7. A read / write circuit, characterized in that, The read / write circuit includes a first driving circuit, a second driving circuit, a third driving circuit, and a self-referenced PUF device, wherein the self-referenced PUF device is as described in any one of claims 1 to 6; The first driving circuit is connected to the first MTJ and is used to input a level signal to the first MTJ; The second driving circuit is connected to the second MTJ and is used to input a level signal to the second MTJ; The third driving circuit is connected to the intermediate MTJ and is used to input a level signal to the intermediate MTJ.

8. The read / write circuit according to claim 7, characterized in that, It also includes a status control line, which is connected to the voltage control layer of the intermediate MTJ; The first driving circuit includes a first bit line and a first switching device; the second driving circuit includes a second bit line and a second switching device; the third driving circuit includes a read / write control circuit and a third switching device. The source of the first switching device is connected to the first bit line, the gate of the first switching device is connected in parallel with the state control line, and the drain of the first switching device is connected to the bottom electrode of the first MTJ. The source of the second switching device is connected to the second bit line, the gate of the second switching device is connected to the state control circuit, and the drain of the second switching device is connected to the bottom electrode of the second MTJ. The drain of the third switching device is connected to the bottom electrode of the intermediate MTJ, and the gate of the third switching device is connected to the read / write control circuit.

9. The read / write circuit according to claim 8, characterized in that, When a high-level signal is input to the voltage-controlled layer of the intermediate MTJ through the state control line. The first bit line drives the first switching device to input a high-level signal to the first MTJ, the second bit line drives the second switching device to input a low-level signal to the second MTJ, and the read / write control circuit drives the third switching device to input a low-level signal to the intermediate MTJ. The self-reference PUF device generates a key, and the read / write circuit is in write data state. The first bit line drives the first switching device to input a high-level signal to the first MTJ, the second bit line drives the second switching device to input a high-level signal to the second MTJ, and the read / write control line drives the third switching device to input a high-level signal to the intermediate MTJ. The read / write circuit is in read data state.

10. A read / write circuit array, characterized in that, The read / write circuit array includes a preset number of read / write circuits, control circuits, and pre-charge amplifiers, wherein any read / write circuit is as described in any one of claims 7 to 9; The control circuit includes clamping circuits connected in parallel with the preset number of read and write circuits, so as to control the working state of the corresponding read and write circuits by outputting voltage through the clamping circuits. The precharge amplifier includes an amplification circuit, and a first voltage detection circuit and a second voltage detection circuit connected in parallel with the amplification circuit; the first voltage detection circuit is connected in parallel with the first MTJ of the preset number of read / write circuits; the second voltage detection circuit is connected in parallel with the second MTJ of the preset number of read / write circuits. For the read / write circuit that is controlled by the control circuit to enter the data reading state, the voltage of the first MTJ in the read / write circuit is read by the first voltage detection circuit, the voltage of the second MTJ in the read / write circuit is read by the second voltage detection circuit, the difference between the voltage read by the first voltage detection circuit and the voltage read by the second voltage detection circuit is amplified, and the read data is output based on the amplified difference.

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