Compound semiconductor substrate and method for manufacturing compound semiconductor substrate

Abstract

This compound semiconductor substrate has a main surface. The compound semiconductor substrate contains impurities. The compound semiconductor substrate is formed of gallium arsenide or indium phosphide. In an X-ray topography image of the main surface, a ripple-like pattern caused by impurities is confirmed. The ripple-like pattern has a shape corresponding to a part of the wave pattern concentrically spreading from a wave source. The ripple-like pattern corresponds to a part of the wave pattern concentrically spreading from the wave source. The value obtained by dividing the distance between the center of the main surface and the wave source by the radius of the main surface is 0.1 to 0.9 inclusive.

Description

Compound Semiconductor Substrate and Method for Manufacturing Compound Semiconductor Substrate

[0001] The present disclosure relates to a compound semiconductor substrate and a method for manufacturing a compound semiconductor substrate.

[0002] International Publication No. 2020 / 245215 (Patent Document 1) describes a method for manufacturing a semiconductor crystal using the vertical Bridgman method or the vertical temperature gradient solidification method and a manufacturing apparatus in which a plurality of crucibles are arranged. Usually, a compound semiconductor substrate is manufactured by slicing a compound semiconductor crystal into a disk shape.

[0003] International Publication No. 2020 / 245215

[0004] The compound semiconductor substrate according to the present disclosure has a main surface. The compound semiconductor substrate contains impurities. The compound semiconductor substrate is formed of gallium arsenide or indium phosphide. In the X-ray topographic image of the main surface, a wavy pattern caused by impurities is confirmed. The wavy pattern has a shape corresponding to a part of the waves spreading concentrically from the wave source. The value obtained by dividing the distance between the center of the main surface and the wave source by the radius of the main surface is 0.1 or more and 0.9 or less.

[0005] FIG. 1 is a schematic plan view showing the configuration of the compound semiconductor substrate according to the present embodiment. FIG. 2 is a schematic side view showing the configuration of the compound semiconductor substrate according to the present embodiment. FIG. 3 is a schematic diagram for explaining the wavy pattern. FIG. 4 is a schematic cross-sectional view showing the configuration of the manufacturing apparatus for the compound semiconductor crystal according to the present embodiment. FIG. 5 is a schematic cross-sectional view taken along line V-V of FIG. 4. FIG. 6 is a flowchart schematically showing the method for manufacturing the compound semiconductor substrate according to the present embodiment. FIG. 7 is a schematic cross-sectional view showing a crucible in which a seed crystal, a compound semiconductor raw material, and a sealing material are arranged. FIG. 8 is a schematic cross-sectional view showing the step of growing a crystal. FIG. 9 is a schematic cross-sectional view showing the method for manufacturing the compound semiconductor substrate according to the first comparative example. FIG. 10 is a schematic cross-sectional view showing the method for manufacturing the compound semiconductor substrate according to the second comparative example.

[0006] [Problems this disclosure aims to solve] Compound semiconductor substrates manufactured by slicing compound semiconductor crystals sometimes exhibit defects such as cracking and chipping. In this case, the slicing yield in the manufacturing of compound semiconductor substrates decreases.

[0007] The object of this disclosure is to provide a compound semiconductor substrate capable of improving slice yield and a method for manufacturing a compound semiconductor substrate.

[0008] [Effects of this disclosure] According to this disclosure, it is possible to provide a compound semiconductor substrate capable of improving slice yield and a method for manufacturing a compound semiconductor substrate.

[0009] [Outline of Embodiments] First, an outline of the embodiments of the present disclosure (hereinafter also referred to as these embodiments) will be described.

[0010] (1) The compound semiconductor substrate relating to this disclosure has a main surface. The compound semiconductor substrate contains impurities. The compound semiconductor substrate is formed of gallium arsenide or indium phosphide. A wave-like pattern caused by impurities is observed in the X-ray topography image of the main surface. The wave-like pattern has a shape corresponding to a part of a wave that spreads concentrically from a wave source. The value obtained by dividing the distance between the center of the main surface and the wave source by the radius of the main surface is 0.1 or more and 0.9 or less. This makes it possible to improve the slice yield.

[0011] (2) In the compound semiconductor substrate described in (1) above, the value obtained by dividing the distance between the center of the main surface and the wave source by the radius of the main surface may be 0.3 or more and 0.7 or less. This makes it possible to effectively improve the slice yield.

[0012] (3) In the compound semiconductor substrate described in (2) above, the value obtained by dividing the distance between the center of the main surface and the wave source by the radius of the main surface may be 0.4 or more and 0.6 or less. This makes it possible to effectively improve the slice yield.

[0013] (4) In the case of a compound semiconductor substrate according to any of (1) to (3) above, the diameter of the main surface may be 100 mm or more and 205 mm or less.

[0014] (5) The compound semiconductor substrate according to any of (1) to (4) above may be formed of gallium arsenide. The impurities may include at least one of silicon, boron, tellurium, or zinc.

[0015] (6) The compound semiconductor substrate according to any of (1) to (4) above may be formed of indium phosphide. The impurities may include at least one of sulfur, tin, or zinc.

[0016] (7) The method for manufacturing a compound semiconductor substrate according to the present disclosure uses a vertical boat method. The method for manufacturing a compound semiconductor substrate has the following steps: A seed crystal and raw materials are placed inside a crucible. A raw material melt is prepared by melting a part of the seed crystal and the raw materials. A compound semiconductor crystal is grown by solidifying the raw material melt. In the step of growing the compound semiconductor crystal, the solid-liquid interface is convex in the vertical upward direction. The value obtained by dividing the radial distance of the crucible between the central axis of the crucible and the apex of the solid-liquid interface by half the inner diameter of the crucible is 0.1 or more and 0.9 or less. This makes it possible to improve the slice yield.

[0017] [Details of Embodiments] The details of embodiments of this disclosure will be described below with reference to the drawings. In the following drawings, identical or corresponding parts are given the same reference numerals, and their descriptions will not be repeated. In the crystallographic description herein, individual planes are indicated in parentheses.

[0018] (Compound Semiconductor Substrate) First, the configuration of the compound semiconductor substrate according to this embodiment will be described. Figure 1 is a schematic plan view showing the configuration of the compound semiconductor substrate 100 according to this embodiment. Figure 2 is a schematic side view showing the configuration of the compound semiconductor substrate 100 according to this embodiment. As shown in Figures 1 and 2, the compound semiconductor substrate 100 has a first main surface 1, a second main surface 2, and an outer peripheral surface 3. The compound semiconductor substrate 100 is formed of either gallium arsenide (GaAs) or indium phosphide (InP). The crystal structure of the compound semiconductor substrate 100 is cubic.

[0019] As shown in Figure 2, the second main surface 2 is opposite the first main surface 1. The outer circumferential surface 3 is connected to both the first main surface 1 and the second main surface 2. The ridge line between the first main surface 1 and the outer circumferential surface 3 is defined as the outer edge 8.

[0020] The direction from the first main surface 1 to the second main surface 2 is parallel to the growth direction of the compound semiconductor crystal when manufacturing the compound semiconductor substrate 100. The thickness of the compound semiconductor substrate 100 in the direction from the first main surface 1 to the second main surface 2 is, for example, less than 1 mm.

[0021] Figure 1 shows the structure of the compound semiconductor substrate 100 as viewed perpendicular to the first main surface 1. As shown in Figure 1, when viewed perpendicular to the first main surface 1, the shape of the first main surface 1 is, for example, circular. The first main surface 1 has a center A. Center A is, for example, the center of the outer edge 8.

[0022] The first main surface 1 is, for example, the (100) surface. The first main surface 1 may be inclined with respect to the (100) surface, for example. If the first main surface 1 is inclined with respect to the (100) surface, the inclination angle (off-angle) of the first main surface 1 with respect to the (100) surface is, for example, 0° or more and 15° or less.

[0023] The diameter D of the first main surface 1 is, for example, 100 mm or more and 205 mm or less. The diameter D may be 4 inches (101.6 mm) or more, or 6 inches (152.4 mm) or more. The diameter D may be, for example, 8 inches (203.2 mm) or less. The diameter D is the longest distance between two different points on the outer edge 8. The radius of the first main surface 1 (first radius R1) is half the diameter D.

[0024] The outer circumferential surface 3 may have at least one of a notch, an orientation flat (OF), or an index flat (IF). If at least one of a notch, OF, or IF is provided on the outer circumferential surface 3, the center of the circle that overlaps with the arc-shaped outer edge 8 when viewed perpendicular to the first main surface 1 is defined as the center A of the first main surface 1.

[0025] The compound semiconductor substrate 100 contains impurities. If the compound semiconductor substrate 100 is formed of GaAs, the impurities include at least one of silicon (Si), boron (B), tellurium (Te), or zinc (Zn). If the compound semiconductor substrate 100 is formed of InP, the impurities include at least one of sulfur (S), Sn, or Zn. The concentration of impurities in the compound semiconductor substrate 100 is, for example, 1.0 × 10⁻⁶. １６ The above 9.0 x 10 １９ The following, preferably 1.0 × 10 １６ The above 8.0 x 10 １８ The following, and more preferably 9.0 × 10 １７ The above 4.5 x 10 １８ The following applies:

[0026] <Wave Pattern> According to the compound semiconductor substrate 100 of this embodiment, a wave pattern P is observed in the X-ray topography image of the first main surface 1. Figure 3 is a schematic diagram illustrating the wave pattern. In Figure 3, the wave pattern P is shown using dashed lines.

[0027] As shown in Figure 3, the ripple pattern P has a shape that corresponds to a part of the ripples that spread concentrically from the wave source X. A "ripple pattern" is a pattern that can be likened to the wave patterns (ripples) that appear when an object falls into the water and spread out in multiple rings. The "wave source" of a ripple pattern is the starting point where the waves of the ripple pattern are generated.

[0028] The wave pattern P is formed, for example, by circles 91 and convex arcs 92 in the direction from the wave source X toward the center A. The number of circles 91 and arcs 92 in the wave pattern P is not particularly limited. The wave pattern P may be formed by arcs 92 only. The center of the circle 91 and the center of the circle that overlaps with the arc 92 are considered to be the wave source X. The wave source X is located on the first main surface 1. In other words, the wave source X is located inside the outer edge 8. The wave source X is spaced apart from the center A.

[0029] The value obtained by dividing the distance between the center A of the first principal surface 1 and the wave source X (first distance E1) by the radius of the first principal surface 1 (first radius R1) is called the central displacement ratio. If the central displacement ratio is 1 or less, the wave source X is located inside the outer edge 8. Conversely, if the central displacement ratio is greater than 1, the wave source X is located outside the outer edge 8. If the central displacement ratio is 0, the wave source X overlaps with the center A.

[0030] According to the compound semiconductor substrate 100 of this embodiment, the central displacement ratio is 0.1 or more and 0.9 or less. The central displacement ratio may be 0.2 or more and 0.8 or less, 0.3 or more and 0.7 or less, 0.4 or more and 0.6 or less, or 0.45 or more and 0.55 or less.

[0031] Next, a method for confirming wave-like patterns using X-ray topography (XRT) will be explained. For XRT, for example, the XRTmicron™ manufactured by Rigaku Corporation or the JVSensus-600™ series manufactured by Bruker can be used. XRT is a method for evaluating the internal structure of a crystal.

[0032] In the acquisition of an X-ray topography image, transmission XRT is performed. Specifically, X-rays are irradiated onto the second main surface 2. The intensity of the X-rays that are reflected at the diffraction plane of the compound semiconductor substrate 100 and then pass through the first main surface 1 to the outside of the compound semiconductor substrate 100 is measured. An X-ray topography image of the first main surface 1 is created by representing the intensity of the above X-rays across the entire surface of the first main surface 1 with shades of color. By observing the shades of color in the X-ray topography image, a wave-like pattern P can be confirmed.

[0033] If the angle between the diffraction plane and the X-ray is defined as the incident angle θ (also called the Bragg angle), the lattice constant of the crystal is d, and the wavelength of the X-ray is λ, then the incident angle θ, lattice constant d, and wavelength λ satisfy the following equation 1. In equation 1, n is an integer. Equation 1 is also called the Bragg condition. nλ = 2dsinθ ... (Equation 1) In X-ray topography imaging, the X-ray target is Mo (Mo Kα). When the wavelength λ is set to 0.062 nm, the transmission image is captured using the following Bragg angle. Specifically, in X-ray topography imaging of a compound semiconductor single crystal substrate 100 formed of GaAs, if the diffraction plane is the (022) plane, the Bragg angle is 8.94°. If the diffraction plane is the (040) plane, the Bragg angle is 12.69°. In InP X-ray topography imaging, the Bragg angle is 8.60° when the diffraction plane is the (022) plane. When the diffraction plane is the (040) plane, the Bragg angle is 12.21°. A high-sensitivity, high-resolution X-ray camera, the CCD camera "XTOP" (manufactured by Rigaku Corporation), is used as the X-ray intensity detector.

[0034] The ripple pattern P is caused by impurities. Specifically, the ripple pattern P is thought to be caused by the distribution of impurity concentrations added to the compound semiconductor substrate 100 as dopants, etc. In the X-ray topography image of the compound semiconductor substrate 100, the X-ray intensity is higher in areas with high impurity concentrations compared to areas with low impurity concentrations. Therefore, it is thought that the ripple pattern P can be confirmed by visualizing the distribution of impurity concentrations in the compound semiconductor substrate 100 using XRT.

[0035] (Manufacturing apparatus for compound semiconductor crystals) Next, the configuration of the manufacturing apparatus 300 for compound semiconductor crystals according to this embodiment (hereinafter also simply referred to as the manufacturing apparatus 300) will be described. Figure 4 is a schematic cross-sectional view showing the configuration of the manufacturing apparatus 300 for compound semiconductor crystals according to this embodiment. As shown in Figure 4, the manufacturing apparatus 300 mainly comprises a crucible 40, a crucible holder 49, a heating unit 48, an insulating material 50, and a high-pressure vessel (not shown).

[0036] The crucible 40 is made of a material that can withstand the heating required to melt the raw materials. Specifically, the crucible 40 is made of, for example, pyrolytic boron nitride (pBN). The crucible 40 has a seed crystal holding section 41 and a crystal growth section 42.

[0037] The crucible 40 has a cylindrical shape. The central axis of the crucible 40 is the first central axis C1. The crucible 40 opens in the vertically upward direction 111. The vertically upward direction 111 is the same direction as the growth direction of the compound semiconductor crystal 400, which will be described later. The direction opposite to the vertically upward direction 111 is the vertically downward direction 112. The first central axis C1 extends along the vertically upward direction 111. The direction perpendicular to the first central axis C1 and toward the crystal growth section 42 is the radial direction 113.

[0038] The seed crystal holding section 41 has a bottomed cylindrical shape. The seed crystal holding section 41 holds the seed crystal. The seed crystal holding section 41 opens vertically upward 111. The crystal growth section 42 holds the raw material. The crystal growth section 42 is connected to the seed crystal holding section 41. The crystal growth section 42 is provided vertically upward 111 relative to the seed crystal holding section 41. The crystal growth section 42 has a diameter-increasing section 42a and a straight section 42b.

[0039] The diameter-increasing portion 42a is connected to the seed crystal holding portion 41. The diameter-increasing portion 42a has an annular shape. The diameter-increasing portion 42a surrounds the first central axis C1. As the diameter-increasing portion 42a moves away from the seed crystal holding portion 41 along the vertical upward direction 111, both the inner diameter and the outer diameter of the diameter-increasing portion 42a increase.

[0040] The straight section 42b is connected to the diameter-increasing section 42a. The straight section 42b is positioned vertically upward 111 relative to the diameter-increasing section 42a. The shape of the straight section 42b is a hollow cylinder. When viewed vertically downward 112, the shape of the straight section 42b is circular. The straight section 42b surrounds the first central axis C1. The inner diameter of the straight section 42b is, for example, 100 mm or more. The inner diameter of the straight section 42b is the inner diameter of the crucible 40. Half of the inner diameter of the crucible 40 is the second radius R2.

[0041] The heating unit 48 heats the crucible 40. Specifically, the heating unit 48 heats the crucible 40 when power is supplied to it. The heating unit 48 is, for example, a resistance heater. From another point of view, the crucible 40 is heated, for example, by a resistance heating method. The heating unit 48 may also be a coil. From another point of view, the crucible 40 may be heated by a high-frequency induction heating method.

[0042] The heating section 48 has a cylindrical shape. The heating section 48 surrounds the crucible 40. The heating section 48 is spaced apart from the crucible 40. The central axis of the heating section 48 is the second central axis C2. The second central axis C2 may be parallel to the first central axis C1. The second central axis C2 is spaced apart from the first central axis C1.

[0043] The second central axis C2 is located between the first central axis C1 and the crucible 40. In the radial direction 113, the distance between the first central axis C1 and the second central axis C2 is defined as the second distance E2. The value obtained by dividing the second distance E2 by the radius of the crucible 40 (second radius R2) is, for example, between 0.1 and 0.9. The second distance E2 may be the same as the first distance E1 in the compound semiconductor substrate 100 described above (see Figure 3).

[0044] The heating section 48 includes, for example, an upper heating member 48a and a lower heating member 48b. The upper heating member 48a surrounds the crystal growth section 42. When viewed in the vertically downward direction 112, the shape of the upper heating member 48a is annular. The lower heating member 48b is provided vertically downward 112 relative to the upper heating member 48a. The lower heating member 48b surrounds the seed crystal holding section 41. When viewed in the vertically downward direction 112, the shape of the lower heating member 48b is annular.

[0045] The crucible holder 49 holds the crucible 40. The crucible holder 49 surrounds the seed crystal holding section 41 and the diameter-increasing section 42a. The heat insulating material 50 surrounds the crucible 40 and the heating section 48. A high-pressure vessel (not shown) surrounds the crucible 40 and the heating section 48. The high-pressure vessel is made of, for example, metal. The manufacturing apparatus 300 may also have a container (not shown) surrounding the crucible 40. This container is made of quartz.

[0046] Figure 5 is a schematic cross-sectional view along the line V-V in Figure 4. As shown in Figure 5, the crucible 40 is eccentric with respect to the heating section 48. The first central axis C1 is located radially 113 with respect to the second central axis C2. The central axis of the insulating material 50 coincides with the second central axis C2. In other words, in cross-sectional view, the heating section 48 and the insulating material 50 are arranged concentrically around the second central axis C2.

[0047] (Method for Manufacturing Compound Semiconductor Substrates) Next, a method for manufacturing the compound semiconductor substrate 100 according to this embodiment will be described. The compound semiconductor substrate 100 is manufactured using the vertical boat method. In this specification, the vertical boat method includes, for example, the Vertical Bridgeman (VB) method, the Vertical Gradient Freeze (VGF) method, and hybrid methods combining the VB method and the VGF method.

[0048] Figure 6 is a schematic flowchart showing the manufacturing method of the compound semiconductor substrate 100 according to this embodiment. As shown in Figure 6, the manufacturing method of the compound semiconductor substrate 100 according to this embodiment mainly comprises the steps of preparing the manufacturing apparatus (S10), arranging the raw materials (S20), melting the raw materials (S30), growing the crystals (S40), and cutting the crystals (S50).

[0049] First, the process of preparing the manufacturing apparatus (S10) is carried out. Specifically, the manufacturing apparatus 300 according to the above embodiment (see Figures 4 and 5) is prepared. In the process of preparing the manufacturing apparatus (S10), the crucible 40 is heated in an oxygen atmosphere, thereby causing boron oxide (B) to form on the surface of the crucible 40. ２ O ３ A film (not shown) may be formed. The boron oxide film functions as a sealant.

[0050] Next, the process of arranging the raw materials (S20) is carried out. Figure 7 is a schematic cross-sectional view of the crucible 40 in which the seed crystal 84, compound semiconductor raw material 85, and encapsulating material 86 are arranged. For the sake of explanation, the insulating material 50 is not shown in Figure 7 and subsequent figures.

[0051] As shown in Figure 7, a seed crystal 84 is placed inside the seed crystal holding portion 41. The seed crystal 84 is made of either GaAs or InP. The seed crystal 84 may also contain elements that the compound semiconductor substrate 100 contains as impurities. Multiple compound semiconductor raw materials 85 are placed on the seed crystal 84. Each of the multiple compound semiconductor raw materials 85 is made of a polycrystalline compound semiconductor.

[0052] If the seed crystal 84 is formed of GaAs, the compound semiconductor raw material 85 is formed of GaAs. Similarly, if the seed crystal 84 is formed of InP, the compound semiconductor raw material 85 is formed of InP. The shape of each of the multiple compound semiconductor raw materials 85 is, for example, cylindrical. The multiple compound semiconductor raw materials 85 are stacked on the seed crystal 84. Impurity raw materials (not shown) are placed inside the crucible 40. The impurity raw materials are formed of elements that the compound semiconductor substrate 100 contains as impurities. In the raw material placement step (S20), a very small amount of carbon, carbon dioxide, or carbon monoxide may be introduced into the crucible 40.

[0053] As shown in Figure 7, the encapsulant 86 may be arranged on a plurality of compound semiconductor raw materials 85. The encapsulant 86 is formed of, for example, boron oxide. The shape of the encapsulant 86 is cylindrical. The encapsulant 86 suppresses the decomposition of the compound semiconductor.

[0054] Next, the process of melting the raw materials (S30) is carried out. The crucible 40 is heated by supplying power to the heating unit 48. The power supplied to the upper heating member 48a is greater than the power supplied to the lower heating member 48b. Therefore, the temperature of the crucible 40 increases as you move away from the bottom of the crucible 40 along the vertically upward direction 111. As a result, a portion of the seed crystal 84 and the compound semiconductor raw material 85 melt. The melted portion of the seed crystal 84 and the compound semiconductor raw material 85 become the raw material melt 87. The raw material melt 87 comes into contact with the rest of the seed crystal 84. As the sealing material 86 melts, the sealing material 86 becomes a liquid sealing material 88. The liquid sealing material 88 covers the raw material melt 87. Thus, the raw material melt 87 is prepared.

[0055] Next, the crystal growth process (S40) is carried out. Figure 8 is a schematic cross-sectional view showing the crystal growth process. As shown in Figure 8, for example, the crucible 40 is pulled down along arrow B. The direction of arrow B is the same as the vertical downward direction 112. The speed at which the crucible 40 is pulled down is, for example, 0.1 mm / h or more and 10.0 mm / h or less. The temperature of the raw material melt 87 near the remainder of the seed crystal 84 decreases. As the raw material melt 87 in contact with the remainder of the seed crystal 84 solidifies, a compound semiconductor crystal 400 grows on the seed crystal 84.

[0056] Because the crucible 40 is eccentric with respect to the heating section 48, the amount of heat received by the crucible 40 from the heating section 48 is uneven. As a result, the temperature of the raw material molten 87 is lowest in the portion of the plane perpendicular to the first central axis C1 that is closest to the central axis (second central axis C2) of the heating section 48. Therefore, the solid-liquid interface S between the compound semiconductor crystal 400 and the raw material molten 87 is convex in the vertically upward direction. The second central axis C2 may pass through the apex T of the solid-liquid interface S. The apex T is the portion of the solid-liquid interface S closest to the opening of the crucible 40 in the vertically upward direction 111.

[0057] The radial distance 113 between the first central axis C1 and the apex T of the solid-liquid interface S is defined as the third distance E3. The value obtained by dividing the third distance E3 by the second radius R2 is between 0.1 and 0.9. The value obtained by dividing the third distance E3 by the second radius R2 may be between 0.2 and 0.8, between 0.3 and 0.7, between 0.4 and 0.6, or between 0.45 and 0.55. The third distance E3 may be the same as the first distance E1 of the compound semiconductor substrate 100 described above (see Figure 3). The third distance E3 may also be the same as the second distance E2 described above (see Figures 4 and 5).

[0058] As the crucible 40 is continuously lowered, the compound semiconductor crystal 400 continues to grow. After the crystal growth is complete, the power supply to the heating unit 48 is reduced. Finally, the power supply is stopped. As a result, the temperatures of the heating unit 48, the crucible 40, and the compound semiconductor crystal 400 gradually decrease. In this way, the compound semiconductor crystal 400 is manufactured. The maximum diameter of the compound semiconductor crystal 400 is substantially the same as the inner diameter of the crucible 40. Note that the cross-section shown in Figure 8 is a cross-section that includes the first central axis C1 and the vertex T.

[0059] Next, a crystal cutting step (S50) is performed. For example, using a wire saw, the compound semiconductor crystal 400 is sliced ​​along a plane perpendicular to the growth direction of the compound semiconductor crystal 400. This forms the compound semiconductor substrate 100. After that, the surface of the compound semiconductor substrate 100 may be polished or the compound semiconductor substrate 100 may be washed. The compound semiconductor substrate 100 is then manufactured.

[0060] Next, the effects of the compound semiconductor substrate and the method for manufacturing the compound semiconductor substrate according to this embodiment will be explained.

[0061] Typically, compound semiconductor substrates 100 are manufactured by slicing compound semiconductor crystals 400 into disc shapes. However, defects sometimes occurred in the manufactured compound semiconductor substrates 100 due to the slicing process. Specifically, defects such as cracks and chips sometimes occurred in the compound semiconductor substrates 100 after slicing. This resulted in a decrease in the slicing yield during the manufacturing of compound semiconductor substrates 100.

[0062] As the compound semiconductor crystal 400 grows, the raw material molten 87 solidifies in the region perpendicular to the central axis of the crucible 40, starting from the portion of the molten raw material 87 with a lower temperature. Specifically, for example, the raw material molten 87 solidifies along a direction radiating outward from the second central axis C2, starting from the apex T of the solid-liquid interface S. Consequently, a temperature difference arises between the portion of the raw material molten 87 near the apex T and the portion of the raw material molten 87 far from the apex T. This temperature difference causes residual strain to occur in the compound semiconductor crystal 400.

[0063] The distribution of residual strain corresponds to the temperature distribution of the raw material melt 87. Specifically, in a plane perpendicular to the central axis (first central axis C1) of the crucible 40, the residual strain is small in the portion of the compound semiconductor crystal 400 that solidified relatively quickly, and large in the portion of the compound semiconductor crystal 400 that solidified relatively slowly. From another perspective, the residual strain of the compound semiconductor crystal 400 increases as it moves away from the second central axis C2.

[0064] Figure 9 is a schematic cross-sectional view showing a method for manufacturing a compound semiconductor substrate according to the first comparative example. As shown in Figure 9, when the second central axis C2 and the first central axis C1 overlap, the raw material melt 87 solidifies radially outward from the first central axis C1. Therefore, in the compound semiconductor crystal 400, residual strain is distributed point-symmetrically around the first central axis C1. In this case, it is thought that the residual strain is more easily released when slicing the compound semiconductor crystal 400. This makes it easier for cracks and chips to occur in the compound semiconductor substrate 100.

[0065] Figure 10 is a schematic cross-sectional view showing a method for manufacturing a compound semiconductor substrate according to the second comparative example. As shown in Figure 10, if the distance between the first central axis C1 and the second central axis C2 (second distance E2) is excessively long, it is thought that the residual strain becomes excessively large in the portion of the compound semiconductor crystal 400 that is far from the second central axis C2. The portion of the compound semiconductor crystal 400 with excessively large residual strain is likely to become the starting point for cracks and chips to occur in the compound semiconductor substrate 100 when the compound semiconductor crystal 400 is sliced. Therefore, if the second distance E2 is excessively long, the slice yield decreases in the manufacturing of the compound semiconductor substrate 100.

[0066] According to the compound semiconductor substrate 100 of this embodiment, a wave-like pattern P is observed in the X-ray topography image of the first main surface 1. The value obtained by dividing the distance between the center A of the first main surface 1 and the wave source X of the wave-like pattern P by the radius of the first main surface 1 (center displacement ratio) is 0.1 or more and 0.9 or less.

[0067] During the crystal growth process, the growth rate of the crystal is not necessarily constant. Changes in the crystal growth rate cause slight changes in the segregation coefficient of impurities. This results in minute variations in the distribution of impurity concentrations in the compound semiconductor crystal 400. This distribution of impurity concentrations is thought to be similar to the shape of the solid-liquid interface S. Therefore, the shape of the ripple pattern P caused by impurities is similar to the shape of the solid-liquid interface S during crystal growth. Consequently, the position of the wave source X in the ripple pattern P corresponds to the position of the vertex T of the solid-liquid interface S. Note that, as shown in Figure 10, when the second central axis C2 passes outside the crucible 40, the position of the wave source X corresponds to the position of the second central axis C2.

[0068] If the central displacement ratio is excessively small, the residual strain is distributed point-symmetrically around the center A of the first main surface 1 in the compound semiconductor substrate 100, similar to the case where the second central axis C2 and the first central axis C1 overlap (see Figure 9). Therefore, cracks and chips are more likely to occur when slicing the compound semiconductor crystal 400 during the manufacturing of the compound semiconductor substrate 100. Consequently, the slicing yield decreases.

[0069] In the compound semiconductor substrate 100 according to this embodiment, the central displacement ratio is 0.1 or higher, which prevents the residual strain from being distributed symmetrically around the center A. From another perspective, it can be said that the residual strain in the compound semiconductor substrate 100 is dispersed. Therefore, in the manufacturing of the compound semiconductor substrate 100, it is possible to prevent the occurrence of cracks and chips when slicing the compound semiconductor crystal 400. Consequently, the slicing yield can be improved.

[0070] If residual strain is distributed symmetrically around the center A in the compound semiconductor substrate 100, the compound semiconductor substrate 100 may deform due to heating during the formation of an epitaxial layer on the substrate 100. This reduces the yield of the epitaxial substrate. According to the compound semiconductor substrate 100 of this embodiment, the distribution of residual strain symmetrically around the center A is prevented. Therefore, when the compound semiconductor substrate 100 is heated during the formation of an epitaxial layer on the substrate 100, deformation of the compound semiconductor substrate 100 due to residual strain can be prevented. This improves the yield of the epitaxial substrate when manufacturing an epitaxial substrate using the compound semiconductor substrate 100.

[0071] If the central displacement ratio is excessively large, the residual strain becomes excessively large in the portion of the compound semiconductor substrate 100 that is far from the wave source X, similar to the case where the second distance E2 described above is excessively long (see Figure 10). Therefore, when slicing the compound semiconductor crystal 400, this portion is likely to become the starting point for cracks and chips in the compound semiconductor substrate 100. As a result, the slicing yield decreases.

[0072] According to the compound semiconductor substrate 100 of this embodiment, the central displacement ratio is 0.9 or less, which prevents excessive residual strain from occurring in the compound semiconductor substrate 100. Therefore, when slicing the compound semiconductor crystal 400 during the manufacturing of the compound semiconductor substrate 100, the occurrence of cracks and chips can be prevented. Consequently, the slicing yield can be improved.

[0073] If there are areas with excessively large residual strain in the compound semiconductor substrate 100, these areas may deform due to heating during the formation of an epitaxial layer on the compound semiconductor substrate 100. This reduces the yield of the epitaxial substrate. According to the compound semiconductor substrate 100 of this embodiment, excessive residual strain is prevented. Therefore, when the compound semiconductor substrate 100 is heated during the formation of an epitaxial layer on the compound semiconductor substrate 100, deformation of the compound semiconductor substrate 100 due to residual strain can be prevented. This improves the yield of the epitaxial substrate when manufacturing an epitaxial substrate using the compound semiconductor substrate 100.

[0074] In the method for manufacturing the compound semiconductor substrate 100 according to this embodiment, in the crystal growth step (S40), the solid-liquid interface S is convex in the vertically upward direction 111. The value obtained by dividing the radial distance 113 between the first central axis C1 and the apex T of the solid-liquid interface S (third distance E3) by half the inner diameter of the crucible 40 (second radius R2) is 0.1 or more and 0.9 or less.

[0075] The value obtained by dividing the third distance E3 by the second radius R2 is 0.1 or greater, so the second central axis C2 is sufficiently separated from the first central axis C1. This prevents the residual strain from being distributed point-symmetrically around the first central axis C1 in the compound semiconductor crystal 400. Therefore, when slicing the compound semiconductor crystal 400, the occurrence of cracks and chips can be prevented. Consequently, the slicing yield can be improved.

[0076] By keeping the value obtained by dividing the third distance E3 by the second radius R2 at 0.9 or less, excessive residual strain is prevented in the compound semiconductor crystal 400. Therefore, cracking and chipping can be prevented when slicing the compound semiconductor crystal 400. Consequently, the slicing yield can be improved.

[0077] In the above, a method for manufacturing the compound semiconductor substrate 100 using the vertical boat method was described. However, when the diameter D of the first main surface 1 is about 4 inches or less, it is possible to manufacture the compound semiconductor substrate 100 according to this embodiment using the pulling method (Czochralski method).

[0078] In the above description, the heating section 48 of the manufacturing apparatus 300 was cylindrical, but the heating section 48 may also be parallel flat plates. Specifically, the heating section 48 may be formed by, for example, two flat plates. A crucible 40 is placed between the two flat plates. The two flat plates are parallel to each other. The second central axis C2 passes through the center of the space between the two flat plates.

[0079] (Sample Preparation) The effect of the central displacement ratio on slice yield was investigated. First, compound semiconductor substrates 100 corresponding to samples 1-1 to 1-13 were prepared. Specifically, the compound semiconductor substrates 100 were prepared in accordance with the manufacturing method of the compound semiconductor substrate 100 according to the present embodiment described above. Samples 1-1 and 1-11 to 1-13 were comparative examples. Samples 1-2 to 1-10 were examples.

[0080] In samples 1-1 to 1-13, the compound semiconductor substrate 100 was formed of GaAs. The compound semiconductor substrate 100 contained Si as an impurity. The diameter D of the first main surface 1 was 4 inches (101.6 mm). In samples 1-1 to 1-13, the central displacement ratio was varied. The central displacement ratio was between 0 and 1.5.

[0081] (Evaluation Method) For all samples, the average values ​​of impurity concentration, dislocation density, residual strain (hereinafter also referred to as |Sr-St|), and slice yield were measured.

[0082] In the measurement of impurity concentration, glow discharge mass spectrometry (GDMS: Glow Discharge Mass Spectrometry) was used. In GDMS, a glow discharge is generated with the sample as the cathode in an argon (Ar) atmosphere, and the constituent elements of the sample are sputtered when the Ar gas collides with the sample. The elements released by sputtering are ionized in the Ar plasma. The ionized constituent elements are measured with a mass spectrometer. A semi-quantitative value is calculated by correcting the ion intensity ratio between the main component element and the target element (impurity element) of the sample with the relative sensitivity coefficient. The calculated semi-quantitative value was taken as the impurity concentration of the sample.

[0083] In this technical field, dislocations correspond to etch pits that are confirmed using the measurement method described below. Therefore, the number of dislocations can be indirectly measured by measuring the number of such etch pits. In this specification, the dislocation density is measured by measuring the number of such etch pits.

[0084] When the compound semiconductor substrate 100 is formed of GaAs, in the measurement of dislocation density, molten potassium hydroxide is prepared. The temperature of the molten potassium hydroxide is set to 600°C. The first main surface 1 of the compound semiconductor substrate 100 is immersed in the molten potassium hydroxide for 45 minutes. As a result, etch pits are formed on the first main surface 1. Next, the first main surface 1 is observed using an optical microscope. Specifically, a plurality of measurement regions are set on the first main surface 1. The size of each of the plurality of measurement regions is 1 mm × 1 mm. The interval between the plurality of measurement regions is 1 mm.

[0085] The value obtained by dividing the number of etch pits measured in the measurement region by the area (1 cm ２ ) of the measurement region was taken as the dislocation density in the measurement region. The value obtained by dividing the total value of the dislocation densities of each of the plurality of measurement regions by the total number of the plurality of measurement regions was taken as the dislocation density of the first main surface 1. As the optical microscope, for example, "ECLIPSE (registered trademark) LV150N" manufactured by Nikon Corporation can be used. The magnification was set to 100 times.

[0086] The residual strain (|Sr - St|) in the first main surface 1 is expressed as the absolute value of the difference between the radial strain component (Sr) and the tangential strain component (St). The direction of the residual strain can be divided into the radial direction and the tangential direction. The radial direction is the direction in which the line segment extends, connecting the central axis passing through the center A of the first main surface 1 and perpendicular to the first main surface 1, to the arbitrarily specified point. The tangential direction is the direction perpendicular to the radial direction at that point. The tangential direction is also called the circumferential direction.

[0087] The |Sr-St| on the first main surface 1 can be measured using the photoelastic method described in Appl. Phys. Lett. 47 (1985) pp. 365-367. First, the first main surface 1 is polished. This makes the arithmetic mean roughness Ra on the first main surface 1 between 0.1 nm and 0.5 nm. Next, the |Sr-St| is measured over the entire surface of the first main surface 1 using the photoelastic method described above. In the photoelastic method, |Sr-St| is expressed by the following equation 2.

[0088]

[0089] In the above equation 2, λ is the wavelength of the light used for measurement. d is the thickness of the compound semiconductor substrate 100 used for measurement. ０ P is the refractive index. δ is the phase difference caused by the birefringence of the compound semiconductor substrate 100 used for measurement. φ is the principal vibration azimuth angle. P １１ , P １２ , P ４４ is the photoelastic constant.

[0090] According to the photoelastic method described above, |Sr-St| can be determined by measuring the phase difference δ and the principal vibration azimuth angle φ. |Sr-St| was measured across the entire surface of the first principal surface 1, and the average value of |Sr-St| on the first principal surface 1 was determined.

[0091] The slice yield was determined by the following method. Specifically, 1000 compound semiconductor substrates 100 were prepared for each sample. Of these 1000 compound semiconductor substrates 100, the number of good compound semiconductor substrates 100 that did not crack or chip during slicing was counted. The ratio of these good compound semiconductor substrates 100 to the 1000 compound semiconductor substrates 100 was defined as the slice yield. In other words, the slice yield was calculated by dividing the number of good compound semiconductor substrates 100 by 1000.

[0092] (Measurement results)

[0093]

[0094] Table 1 shows the measurement results for samples 1-1 to 1-13. As shown in Table 1, the impurity concentration in samples 1-1 to 1-13 was 9.0 × 10⁻⁶. １７ / cm ３ The above 1.1 x 10 １８ / cm ３ The following was observed: The dislocation density was 11 dislocations / cm³. ２ More than 16 pieces / cm ２ The following was observed: The average value of |Sr-St| was 4.5 × 10⁻⁶. －６ The above 5.2 x 10 －６ The results were as follows:

[0095] In sample 1-1, where the central deviation ratio was 0, the slice yield was 91.3%. In samples with a central deviation ratio of 1 or more (samples 1-11 to 1-13), the slice yield was 92.1% or less. On the other hand, in samples with a central deviation ratio between 0.1 and 0.9 (samples 1-2 to 1-10), the slice yield was 94.3% or more. Furthermore, in samples with a central deviation ratio between 0.3 and 0.7 (samples 1-4 to 1-8), the slice yield was 97.4% or more. Furthermore, in samples with a central deviation ratio between 0.4 and 0.6 (samples 1-5 to 1-7), the slice yield was 98.5% or more.

[0096] Based on the above, it was confirmed that the slice yield can be improved by using the sample according to the example compared to the sample according to the comparative example. Furthermore, it was confirmed that the slice yield can be effectively improved when the center deviation ratio is between 0.3 and 0.7. Moreover, it was confirmed that the slice yield can be improved even more effectively when the center deviation ratio is between 0.4 and 0.6.

[0097] (Sample Preparation) Next, the effect of the center displacement rate on slice yield was investigated when the diameter D of the first main surface 1 was 6 inches or 8 inches. First, compound semiconductor substrates 100 for samples 2-1 to 2-13 and 3-1 to 3-13 were prepared. The compound semiconductor substrates 100 for samples 2-1 to 2-13 and 3-1 to 3-13 were prepared using the same method as the compound semiconductor substrates 100 for samples 1-1 to 1-13, except that the inner diameter of the crucible 40 was different.

[0098] In samples 2-1 to 2-13 and 3-1 to 3-13, the compound semiconductor substrate 100 was formed of GaAs. The compound semiconductor substrate 100 contained Si as an impurity. In samples 2-1 to 2-13, the diameter D of the first main surface 1 was 6 inches. In samples 3-1 to 3-13, the diameter D of the first main surface 1 was 8 inches.

[0099] (Evaluation Method) For all samples, the impurity concentration, dislocation density, average value of |Sr-St|, and slice yield were measured using the method described above.

[0100] (Evaluation results)

[0101]

[0102]

[0103] Table 2 shows the measurement results for samples 2-1 to 2-13. Table 3 shows the measurement results for samples 3-1 to 3-13.

[0104] As shown in Table 2, the impurity concentration in samples 2-1 to 2-13 was 9.0 × 10⁻⁶. １７ / cm３ The above 1.2 x 10 １８ / cm ３ The following was observed: The dislocation density was 10 dislocations / cm³. ２ More than 20 pieces / cm ２ The following was observed: The average value of |Sr-St| was 4.1 × 10⁻⁶. －６ The above 5.5 x 10 －６ The results were as follows:

[0105] In sample 2-1, where the central deviation ratio was 0, the slice yield was 91.1%. In samples with a central deviation ratio of 1 or more (samples 2-11 to 2-13), the slice yield was 91.9% or less. On the other hand, in samples with a central deviation ratio between 0.1 and 0.9 (samples 2-2 to 2-10), the slice yield was 94.1% or more. Furthermore, in samples with a central deviation ratio between 0.3 and 0.7 (samples 2-4 to 2-8), the slice yield was 97.2% or more. Furthermore, in samples with a central deviation ratio between 0.4 and 0.6 (samples 2-5 to 2-7), the slice yield was 98.3% or more.

[0106] As shown in Table 3, the impurity concentration in samples 3-1 to 3-13 was 9.0 × 10⁻⁶. １７ / cm ３ The above 1.2 x 10 １８ / cm ３ The following was observed: The dislocation density was 10 dislocations / cm³. ２ More than 20 pieces / cm ２ The following was observed: The average value of |Sr-St| was 4.1 × 10⁻⁶. －６ The above 5.5 x 10 －６ The results were as follows:

[0107] In sample 3-1, where the central deviation ratio was 0, the slice yield was 90.7%. In samples with a central deviation ratio of 1 or more (samples 3-11 to 3-13), the slice yield was 91.5% or less. On the other hand, in samples with a central deviation ratio between 0.1 and 0.9 (samples 3-2 to 3-10), the slice yield was 93.1% or more. Furthermore, in samples with a central deviation ratio between 0.3 and 0.7 (samples 3-4 to 3-8), the slice yield was 96.8% or more. Furthermore, in samples with a central deviation ratio between 0.4 and 0.6 (samples 3-5 to 3-7), the slice yield was 97.9% or more.

[0108] Based on the above, it was confirmed that even when the diameter D of the first main surface 1 is 6 inches or 8 inches, the slice yield can be improved by having a central displacement ratio of 0.1 or more and 0.9 or less.

[0109] (Sample Preparation) Next, the effect of the center displacement ratio on slice yield was investigated when the impurities contained in the compound semiconductor substrate 100 were Zn or B. First, compound semiconductor substrates 100 corresponding to samples 4-1 to 4-13 and 5-1 to 5-13 were prepared. The compound semiconductor substrates 100 corresponding to samples 4-1 to 4-13 and 5-1 to 5-13 were prepared using the same method as the compound semiconductor substrates 100 corresponding to samples 2-1 to 2-13, except that the impurity elements were different.

[0110] In samples 4-1 to 4-13 and 5-1 to 5-13, the compound semiconductor substrate 100 was formed of GaAs. The diameter D of the first main surface 1 was 6 inches. In samples 4-1 to 4-13, the compound semiconductor substrate 100 contained Zn as an impurity. In samples 5-1 to 5-13, the compound semiconductor substrate 100 contained B as an impurity.

[0111] (Evaluation Method) For all samples, the impurity concentration, dislocation density, average value of |Sr-St|, and slice yield were measured using the method described above.

[0112] (Evaluation results)

[0113]

[0114]

[0115] Table 4 shows the measurement results for samples 4-1 to 4-13. Table 5 shows the measurement results for samples 5-1 to 5-13.

[0116] As shown in Table 4, the impurity concentration in samples 4-1 to 4-13 was 9.0 × 10⁻⁶. １７ / cm ３ The above 1.2 x 10 １８ / cm ３ The following was observed: The dislocation density was 11 dislocations / cm³. ２ More than 16 pieces / cm ２ The following was observed: The average value of |Sr-St| was 4.6 × 10⁻⁶. －６ The above 5.2 x 10 －６ The results were as follows:

[0117] In sample 4-1, where the central deviation ratio was 0, the slice yield was 90.8%. In samples with a central deviation ratio of 1 or more (samples 4-11 to 4-13), the slice yield was 91.6% or less. On the other hand, in samples with a central deviation ratio between 0.1 and 0.9 (samples 4-2 to 4-10), the slice yield was 93.2% or more. Furthermore, in samples with a central deviation ratio between 0.3 and 0.7 (samples 4-4 to 4-8), the slice yield was 96.9% or more. Furthermore, in samples with a central deviation ratio between 0.4 and 0.6 (samples 4-5 to 4-7), the slice yield was 98% or more.

[0118] As shown in Table 5, the impurity concentration in samples 5-1 to 5-13 was 9.0 × 10⁻⁶. １７ / cm ３ The above 1.2 x 10 １８ / cm ３ The following was observed: The dislocation density was 11 dislocations / cm³. ２ More than 20 pieces / cm ２ The following was observed: The average value of |Sr-St| was 4.1 × 10⁻⁶. －６ The above 5.5 x 10 －６ The results were as follows:

[0119] In sample 5-1, where the central deviation ratio was 0, the slice yield was 90.6%. In samples with a central deviation ratio of 1 or more (samples 5-11 to 5-13), the slice yield was 91.4% or less. On the other hand, in samples with a central deviation ratio between 0.1 and 0.9 (samples 5-2 to 5-10), the slice yield was 93% or more. Furthermore, in samples with a central deviation ratio between 0.3 and 0.7 (samples 5-4 to 5-8), the slice yield was 96.7% or more. Furthermore, in samples with a central deviation ratio between 0.4 and 0.6 (samples 5-5 to 5-7), the slice yield was 97.8% or more.

[0120] Based on the above, it was confirmed that even when the impurity is Zn or B, the slice yield can be improved by having a central displacement ratio of 0.1 to 0.9.

[0121] Next, the effect of the center displacement rate on slice yield was investigated when the compound semiconductor substrate 100 is formed of InP. First, compound semiconductor substrates 100 corresponding to samples 6-1 to 6-13 and 7-1 to 7-13 were prepared.

[0122] The compound semiconductor substrates 100 for samples 6-1 to 6-13 were prepared using the same method as the compound semiconductor substrates 100 for samples 1-1 to 1-13, except that the seed crystal 84 and compound semiconductor raw material 85 were each formed of InP. The compound semiconductor substrates 100 for samples 7-1 to 7-13 were prepared using the same method as the compound semiconductor substrates 100 for samples 2-1 to 2-13, except that the seed crystal 84 and compound semiconductor raw material 85 were each formed of InP.

[0123] In samples 6-1 to 6-13 and 7-1 to 7-13, the compound semiconductor substrate 100 was formed of InP. The compound semiconductor substrate 100 contained S as an impurity. In samples 6-1 to 6-13, the diameter D of the first main surface 1 was 4 inches. In samples 7-1 to 7-13, the diameter D of the first main surface 1 was 6 inches.

[0124] (Evaluation Method) For all samples, the impurity concentration, dislocation density, average value of |Sr-St|, and slice yield were measured. The impurity concentration, average value of |Sr-St|, and slice yield were each measured using the method described above.

[0125] In measuring the dislocation density of a compound semiconductor substrate 100 formed of InP, a Huber etching solution was prepared instead of molten potassium hydroxide. The Huber etching solution contains phosphoric acid and hydrogen bromide. The mass ratio of phosphoric acid to hydrogen bromide in the Huber etching solution is 2:1. The temperature of the Huber etching solution was set to 20°C. For example, the compound semiconductor substrate 100 was immersed in the Huber etching solution for a period of 2 to 7 minutes. This formed etch pits on the first main surface 1.

[0126] (Evaluation results)

[0127]

[0128]

[0129] Table 6 shows the measurement results for samples 6-1 to 6-13. Table 7 shows the measurement results for samples 7-1 to 7-13.

[0130] As shown in Table 6, the impurity concentration in samples 6-1 to 6-13 was 9.0 × 10⁻⁶. １７ / cm ３ The above 1.2 x 10 １８ / cm ３ The following was observed: The dislocation density was 10 dislocations / cm³. ２ More than 80 pieces / cm ２ The following was observed: The average value of |Sr-St| was 4.0 × 10⁻⁶. －６ The above 5.5 x 10－６ The results were as follows:

[0131] In sample 6-1, where the central deviation ratio was 0, the slice yield was 91%. In samples with a central deviation ratio of 1 or more (samples 6-11 to 6-13), the slice yield was 91.8% or less. On the other hand, in samples with a central deviation ratio between 0.1 and 0.9 (samples 6-2 to 6-10), the slice yield was 93.4% or more. Furthermore, in samples with a central deviation ratio between 0.3 and 0.7 (samples 6-4 to 6-8), the slice yield was 97.1% or more. Furthermore, in samples with a central deviation ratio between 0.4 and 0.6 (samples 6-5 to 6-7), the slice yield was 98.2% or more.

[0132] As shown in Table 7, the impurity concentration in samples 7-1 to 7-13 was 2.7 × 10⁻⁶. １８ / cm ３ The above 3.3 x 10 １８ / cm ３ The following was observed: The dislocation density was 20 dislocations / cm³. ２ More than 190 pieces / cm ２ The following was observed: The average value of |Sr-St| was 3.9 × 10⁻⁶. －６ The above 5.5 x 10 －６ The results were as follows:

[0133] In sample 7-1, where the central deviation ratio was 0, the slice yield was 90.8%. In samples with a central deviation ratio of 1 or more (samples 7-11 to 7-13), the slice yield was 91.9% or less. On the other hand, in samples with a central deviation ratio between 0.1 and 0.9 (samples 7-2 to 7-10), the slice yield was 93.4% or more. Furthermore, in samples with a central deviation ratio between 0.3 and 0.7 (samples 7-4 to 7-8), the slice yield was 96.9% or more. Furthermore, in samples with a central deviation ratio between 0.4 and 0.6 (samples 7-5 to 7-7), the slice yield was 97.9% or more.

[0134] Based on the above, it has been confirmed that even when the compound semiconductor substrate 100 is formed of InP, the slice yield can be improved by having a center displacement ratio of 0.1 or more and 0.9 or less.

[0135] Next, the effect of the center displacement ratio on slice yield was investigated when the compound semiconductor substrate 100 is formed of InP and the impurity is Sn or Zn. First, compound semiconductor substrates 100 corresponding to samples 8-1 to 8-13 and 9-1 to 9-13 were prepared. The compound semiconductor substrates 100 corresponding to samples 8-1 to 8-13 and 9-1 to 9-13 were prepared using the same method as the compound semiconductor substrates 100 corresponding to samples 6-1 to 6-13, except that the impurity elements were different.

[0136] In samples 8-1 to 8-13 and 9-1 to 9-13, the compound semiconductor substrate 100 was formed of InP. The diameter D of the first main surface 1 was 4 inches. In samples 8-1 to 8-13, the compound semiconductor substrate 100 contained Sn as an impurity. In samples 9-1 to 9-13, the compound semiconductor substrate 100 contained Zn as an impurity.

[0137] (Evaluation Method) For all samples, the impurity concentration, dislocation density, average value of |Sr-St|, and slice yield were measured using the method described above.

[0138] (Evaluation results)

[0139]

[0140]

[0141] Table 8 shows the measurement results for samples 8-1 to 8-13. Table 9 shows the measurement results for samples 9-1 to 9-13.

[0142] As shown in Table 8, the impurity concentration in samples 8-1 to 8-13 was 9.0 × 10⁻⁶. １７ / cm ３ The above 1.2 x 10 １８ / cm ３ The following was observed: The dislocation density was 400 dislocations / cm³.２ More than 970 pieces / cm ２ The following was observed: The average value of |Sr-St| was 4.2 × 10⁻⁶. －６ The above 5.5 x 10 －６ The results were as follows:

[0143] In sample 8-1, where the central deviation ratio was 0, the slice yield was 91.9%. In samples with a central deviation ratio of 1 or more (samples 8-11 to 8-13), the slice yield was 92% or less. On the other hand, in samples with a central deviation ratio between 0.1 and 0.9 (samples 8-2 to 8-10), the slice yield was 93.5% or more. Furthermore, in samples with a central deviation ratio between 0.3 and 0.7 (samples 8-4 to 8-8), the slice yield was 97% or more. Furthermore, in samples with a central deviation ratio between 0.4 and 0.6 (samples 8-5 to 8-7), the slice yield was 98% or more.

[0144] As shown in Table 9, the impurity concentration in samples 9-1 to 9-13 was 1.5 × 10⁻⁶. １７ / cm ３ The above 1.4 x 10 １８ / cm ３ The following was observed: The dislocation density was 100 dislocations / cm³. ２ More than 200 pieces / cm ２ The following was observed: The average value of |Sr-St| was 3.9 × 10⁻⁶. －６ The above 5.6 x 10 －６ The results were as follows:

[0145] In sample 9-1, where the central deviation ratio was 0, the slice yield was 91.8%. In samples with a central deviation ratio of 1 or more (samples 9-11 to 9-13), the slice yield was 91.9% or less. On the other hand, in samples with a central deviation ratio between 0.1 and 0.9 (samples 9-2 to 9-10), the slice yield was 93.4% or more. Furthermore, in samples with a central deviation ratio between 0.3 and 0.7 (samples 9-4 to 9-8), the slice yield was 96.9% or more. Furthermore, in samples with a central deviation ratio between 0.4 and 0.6 (samples 9-5 to 9-7), the slice yield was 97.9% or more.

[0146] Based on the above, it has been confirmed that even when the compound semiconductor substrate 100 is formed of InP and the impurities are Sn or Zn, the slice yield can be improved by having a center displacement ratio of 0.1 or more and 0.9 or less.

[0147] The embodiments and examples disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of the present invention is indicated by the claims rather than the embodiments and examples described above, and all modifications within the scope of the claims are intended to be included in the meaning of equivalents and within the scope.

[0148] 1 First main surface, 2 Second main surface, 3 Outer surface, 8 Outer edge, 40 Crucible, 41 Seed crystal holding section, 42 Crystal growth section, 42a Diameter increasing section, 42b Straight body section, 48 Heating section, 48a Upper heating member, 48b Lower heating member, 49 Crucible holder, 50 Thermal insulation material, 84 Seed crystal, 85 Compound semiconductor raw material, 86 Sealing material, 87 Melt of raw material, 88 Liquid sealing material, 91 Circle, 92 Circular arc, 100 Compound semiconductor substrate, 111 Vertical upward direction, 112 Vertical downward direction, 113 Radial direction, 300 Manufacturing apparatus, 400 Compound semiconductor crystal, A Center, C1 First central axis, C2 Second central axis, D Diameter, E1 First distance, E2 Second distance, E3 Third distance, P Wave pattern, R1 First radius, R2 second radius, S solid-liquid interface, T apex, X wave source.

Claims

1. A compound semiconductor substrate having a main surface, which contains impurities and is formed of gallium arsenide or indium phosphide, wherein a wave-like pattern caused by the impurities is observed in an X-ray topographic image of the main surface, the wave-like pattern has a shape corresponding to a part of a wave spreading concentrically from a wave source, and the value obtained by dividing the distance between the center of the main surface and the wave source by the radius of the main surface is 0.1 or more and 0.9 or less.

2. The compound semiconductor substrate according to claim 1, wherein the value obtained by dividing the distance between the center of the main surface and the wave source by the radius of the main surface is 0.3 or more and 0.7 or less.

3. The compound semiconductor substrate according to claim 2, wherein the value obtained by dividing the distance between the center of the main surface and the wave source by the radius of the main surface is 0.4 or more and 0.6 or less.

4. The compound semiconductor substrate according to any one of claims 1 to 3, wherein the diameter of the main surface is 100 mm or more and 205 mm or less.

5. The compound semiconductor substrate according to any one of claims 1 to 4, wherein the compound semiconductor substrate is formed of gallium arsenide, and the impurity comprises at least one of silicon, boron, tellurium, or zinc.

6. The compound semiconductor substrate according to any one of claims 1 to 4, wherein the compound semiconductor substrate is formed of indium phosphide, and the impurity comprises at least one of sulfur, tin, or zinc.

7. A method for manufacturing a compound semiconductor substrate using a vertical boat method, comprising: a step of arranging a seed crystal and raw materials inside a crucible; a step of preparing a raw material melt by melting a part of the seed crystal and the raw materials; and a step of growing a compound semiconductor crystal by solidifying the raw material melt, wherein in the step of growing the compound semiconductor crystal, the solid-liquid interface is convex in the vertically upward direction, and the value obtained by dividing the radial distance of the crucible between the central axis of the crucible and the apex of the solid-liquid interface by half the inner diameter of the crucible is 0.1 or more and 0.9 or less.

Images