Dual-layer coatings for enhanced semiconductor processing chamber protection

Abstract

Exemplary coating methods may include providing one or more coating precursors to a processing region of a semiconductor processing chamber. The processing region may be at least partially defined by a lid and one or more walls. The coating methods may include forming plasma effluents of the one or more coating precursors. The coating methods may include depositing a first portion of a coating on the lid and one or more walls at a first pressure. The coating methods may include, subsequent to a first period of time, increasing a pressure within the processing region to a second pressure over a second period of time while depositing a second portion of the coating on the first portion of the coating. The coating methods may include depositing a third portion of the coating on the second portion of the coating over a third period of time at the second pressure.

Description

PATENT Attorney Docket No : 080042-44025398W001-1471356DUAL-LAYER COATINGS FOR ENHANCED SEMICONDUCTOR PROCESSING CHAMBER PROTECTION TECHNICAL FIELD

[0001] The present technology relates to semiconductor systems, processes, and equipment. More specifically, the present technology relates to forming coatings on semiconductor processing chambers and semiconductor processing chambers indulging coatings.BACKGROUND

[0002] Integrated circuits are made possible by processes which produce intricately patterned material layers on substrate surfaces. Producing patterned material on a substrate requires controlled methods for removal of exposed material. Chemical etching is used for a variety of purposes including transferring a pattern in photoresist into underlying layers, thinning layers, or thinning lateral dimensions of features already present on the surface. Often it is desirable to have an etch process that etches one material faster than another facilitating, for example, a pattern transfer process. Such an etch process is said to be selective to the first material. As a result of the diversity of materials, circuits, and processes, etch processes have been developed with a selectivity towards a variety of materials.

[0003] Etch processes may be termed wet or dry' based on the materials used in the process. A wet HF etch preferentially removes silicon oxide over other dielectrics and materials. However, wet processes may have difficulty penetrating some constrained trenches and also may sometimes deform the remaining material. Wet processes may also damage chamber components. For example, HF etchants may chemically attack chamber components made from metals, such as aluminum alloys. Dry etches produced in local plasmas formed within the substrate processing region can penetrate more constrained trenches and exhibit less deformation of delicate remaining structures. However, local plasmas may damage the substrate through the production of electric arcs as they discharge. Local plasmas, as well as plasma effluents, may also damage chamber components.

[0004] Thus, there is a need for improved systems and methods that can be used to produce high quality’ devices and structures. These and other needs are addressed by the present technology.BRIEF SUMMARY

[0005] Exemplary coating methods may include providing one or more coating precursors to a processing region of a semiconductor processing chamber. The processing region may¬ be at least partially defined by a lid and one or more walls. The coating methods may include forming plasma effluents of the one or more coating precursors. The coating methods may include depositing a first portion of a coating on the lid and one or more walls at least partially defining the processing region at a first pressure. The coating methods may include, subsequent to a first period of time, increasing a pressure within the processing region to a second pressure over a second period of time while depositing a second portion of the coating on the first portion of the coating. The coating methods may include depositing a third portion of the coating on the second portion of the coating over a third period of time at the second pressure.

[0006] In some embodiments, the one or more coating precursors may be or include a silicon-containing precursor. The silicon-containing precursor may be or include a silicon-and-halogen-containing precursor. The silicon-containing precursor may be or include dichlorosilane (SiCE) or silicon tetrafluoride (SiCU). The one or more coating precursors may be or include an oxygen-containing precursor. The oxy gen-containing precursor may be or include diatomic oxygen (O2). The first pressure may be less than or about 15 mTorr. The first period of time may be less than or about 20 seconds. The second pressure may be greater than or about 50 mTorr. The second period of time may be greater than or about 2 seconds. The third portion of the coating may be characterized by a reduced density compared to the first portion of the coating. The pressure may be ramped from the first pressure to the second pressure at a rate of less than or about 20 mTorr / second. The coating may be or include a silicon-and-oxygen-containing material.

[0007] Embodiments of the present technology may encompass coating methods. The methods may include providing a silicon-containing precursor and an oxygen-containing precursor to a processing region of a semiconductor processing chamber. The processing region may be at least partially defined by a lid, one or more walls, and an electrostatic chuck (ESC). The methods may include forming plasma effluents of the silicon-containingprecursor and the oxygen-containing precursor. The methods may include depositing a first portion of a coating on the lid and one or more walls at least partially defining the processing region at a first pressure. The first portion of the coating may preferentially form on the lid and / or the ESC. The methods may include, subsequent to a first period of time, increasing a pressure within the processing region to a second pressure over a second period of time w hile depositing a second portion of the coating on the first portion of the coating. The methods may include depositing a third portion of the coating on the second portion of the coating over a third period of time at the second pressure. The third portion may preferentially form on the one or more walls.

[0008] In some embodiments, the silicon-containing precursor may further include a halogen. The plasma effluents of the silicon-containing precursor and the oxygen-containing precursor may be formed at a source power of greater than or about 500 W. The methods may include, subsequent to depositing the third portion of the coating, halting a flow of the silicon-containing precursor while maintaining a flow of the oxy gen-containing precursor and formation of plasma effluents of the oxy gen-containing precursor. The methods may include contacting the third portion of the coating with the plasma effluents of the oxy gen-containing precursor to further oxidize a portion of the coating.

[0009] Embodiments of the present technology may encompass coating methods. The methods may include providing a silicon-and-chlorine-containing precursor and an oxy gencontaining precursor to a processing region of a semiconductor processing chamber. The processing region may be at least partially defined by a lid, one or more walls, and an electrostatic chuck (ESC). The methods may include forming plasma effluents of the silicon-containing precursor and the oxygen-containing precursor at a source power of less than or about 1,500 W. The methods may include depositing a first portion of a coating on the lid and one or more walls at least partially defining the processing region at a first pressure less than or about 10 mTorr. The first portion may preferentially form on the lid and / or the ESC. The methods may include, subsequent to a first period of time, increasing a pressure within the processing region to a second pressure greater than or about 60 mTorr over a second period of time while depositing a second portion of the coating on the first portion of the coating. The methods may include depositing a third portion of the coating on the second portion of the coating over a third period of time at the second pressure. The third portion may preferentially form on the one or more walls.

[0010] In some embodiments, the second period of time may be between about 2 seconds and about 30 seconds. A temperature in the processing region may be maintained at less than or about 100 °C.

[0011] Such technology may provide numerous benefits over conventional systems and techniques. For example, embodiments of the present technology may more uniformly protect surfaces defining processing regions of semiconductor processing chambers.Additionally, by depositing coatings at both low pressure and high pressure, the coatings may uniformly protect from particles within components, such as yttrium (Y) and aluminum (Al) particles, from contaminating substrates being processed. Further, by depositing coatings at both low pressure and high pressure, removal of byproducts or residual materials may be made easier from an outer porous portion of the coatings. These and other embodiments, along with many of their advantages and features, are described in more detail in conjunction with the below description and attached figures.BRIEF DESCRIPTION OF THE DRAWINGS

[0012] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings.

[0013] FIG. 1 shows a top plan view of an exemplary processing system according to some embodiments of the present technology'.

[0014] FIG. 2 show s a schematic cross-sectional view of an exemplary processing chamber according to embodiments of the present technology.

[0015] FIG. 3 shows exemplary operations in a method according to some embodiments of the present technology.

[0016] FIGS. 4A-4D show a schematic partial cross-sectional view' of an exemplary' chamber component according to some embodiments of the present technology.

[0017] FIGS. 5A-5D show a schematic partial cross-sectional view of another exemplary chamber component according to some embodiments of the present technology.

[0018] Several of the figures are included as schematics. It is to be understood that the figures are for illustrative purposes and are not to be considered of scale unless specifically' stated to be of scale. Additionally, as schematics, the figures are provided to aidcomprehension and may not include all aspects or information compared to realistic representations and may include exaggerated material for illustrative purposes.

[0019] In the appended figures, similar components and / or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a letter that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the letter.DETAILED DESCRIPTION

[0020] Semiconductor processing may include a number of operations that produce intricately patterned material on a substrate. The operations may include a number of formation and removal processes, which may utilize corrosive or erosive materials, including plasma-enhanced materials formed either remotely or at the substrate level. While an etchant may preferentially etch the substrate material, the chemical etchant may also contact other components within the chamber. The etchant may chemically attack the components, and depending on the process performed, one or more of the components may be bombarded with plasma effluents, which may also erode component materials. The chemical and physical damage to the chamber components caused by the etchant may cause wear over time, which may increase replacement costs and down time for the chamber, as well as potentially contaminate the chamber with chamber substrate-reactive species formed from erosion of chamber walls. As one non-limiting example, in some local or substrate-level plasma operations, a showerhead, manifold, or other lid portion may operate as a ground electrode to develop plasma in the substrate processing region, where the substrate support or some other component may operate as the plasma-generating electrode. The showerhead operating as the ground electrode may be bombarded by plasma species, releasing metallic species that form the showerhead into the plasma, and potentially contaminating substrates being processed with metallic specs from the showerhead. A similar consequence may result from the plasma species interacting with the pedestal or electrostatic chuck (ESC) as well as chamber walls or other components defining the processing region.

[0021] Conventional technologies have struggled to uniformly form coatings on component surfaces defining the processing region. Some conventional technologies have utilized low- pressure for coating depositions. However, the low pressure may result in the predominant coating of lower portions of the processing region. Conversely, some conventionaltechnologies have utilized high pressure for coating depositions. However, the high pressure may result in the predominant coating of upper portions of the processing region.Accordingly, these conventional technologies may not uniformly form coatings on component surfaces defining the processing region and may require routinely replacing components that become damaged during processing. Additionally, the non-uniform coatings of conventional technologies may result in particle contamination of substrates being processed.

[0022] The present technology overcomes these issues and others by coating component surfaces defining the processing region with dual-layer coatings. For example, the present technology may form a first portion of a coating at a first pressure followed by ramping to a second pressure. By depositing coatings at multiple pressures, coatings may more uniformly deposit on component surfaces defining the processing region. For example, the first portion of the coating may be deposited at a low pressure to predominantly form the coating on lower portions of the processing region as well as tighter or smaller portions of the components defining the processing region due to the larger mean-free path. Pressure may then be ramped to a higher pressure. The higher pressure may reduce the mean-free path, resulting in a subsequent portion of the coating being deposited on upper portions of the processing region. The pressure may be gradually ramped from the low pressure to the high pressure to ensure adequate bonding of the coating and to prevent separation, flaking, and / or fracturing. Further, the low-pressure deposition may deposit a dense / hard coating to protect the components from plasma species used in subsequent processing. The high-pressure deposition may deposit a more porous coating that may help with removing byproducts or residual precursor(s) during subsequent processing.

[0023] Although the remaining disclosure will routinely identify specific etching and deposition processes utilizing the disclosed technology’, it will be readily understood that the systems and methods are equally applicable to deposition and cleaning processes and chambers as may occur in the described chambers or other chambers. Accordingly, the technology should not be considered to be so limited as for use with any particular etching processes or chambers alone. Moreover, although an exemplary' chamber is described to provide foundation for the present technology, it is to be understood that the present technology can be applied to virtually any semiconductor processing chamber that may allow the operations described.

[0024] FIG. 1 shows a top plan view of one embodiment of a processing system 10 of deposition, etching, baking, and / or curing chambers according to embodiments. The tool or processing system 10 depicted in FIG. 1 may contain a plurality of process chambers, 24a-d, a transfer chamber 20, a sendee chamber 26, an integrated metrology chamber 28, and a pair of load lock chambers 16a-b. The process chambers may include any number of structures or components, as well as any number or combination of processing chambers.

[0025] To transport substrates among the chambers, the transfer chamber 20 may contain a robotic transport mechanism 22. The transport mechanism 22 may have a pair of substrate transport blades 22a attached to the distal ends of extendible arms 22b, respectively. The blades 22a may be used for carry ing individual substrates to and from the process chambers. In operation, one of the substrate transport blades such as blade 22a of the transport mechanism 22 may retrieve a substrate W from one of the load lock chambers such as chambers 16a-b and carry substrate W to a first stage of processing, for example, a treatment process as described below in chambers 24a-d. The chambers may be included to perform individual or combined operations of the described technology'. For example, while one or more chambers may be configured to perform a deposition or etching operation, one or more other chambers may be configured to perform a pre-treatment operation and / or one or more post-treatment operations described. Any number of configurations are encompassed by the present technology, which may also perform any number of additional fabrication operations typically performed in semiconductor processing.

[0026] If the chamber is occupied, the robot may wait until the processing is complete and then remove the processed substrate from the chamber with one blade 22a and may insert a new substrate with a second blade. Once the substrate is processed, it may then be moved to a second stage of processing. For each move, the transport mechanism 22 generally may- have one blade carrying a substrate and one blade empty- to execute a substrate exchange. The transport mechanism 22 may wait at each chamber until an exchange can be accomplished.

[0027] Once processing is complete within the process chambers, the transport mechanism 22 may move the substrate W from the last process chamber and transport the substrate W to a cassette within the load lock chambers 16a-b. From the load lock chambers 16a-b, the substrate may move into a factory interface 12. The factory interface 12 generally may operate to transfer substrates between pod loaders 14a-d in an atmospheric pressure cleanenvironment and the load lock chambers 16a-b. The clean environment in factory interface 12 may be generally provided through air filtration processes, such as HEP A filtration, for example. Factory interface 12 may also include a substrate ori enter / align er that may be used to properly align the substrates prior to processing. At least one substrate robot, such as robots 18a-b, may be positioned in factory interface 12 to transport substrates between various positions / locations within factory’ interface 12 and to other locations in communication therewith. Robots 18a-b may be configured to travel along a track system within factory' interface 12 from a first end to a second end of the factory interface 12.

[0028] The processing system 10 may further include an integrated metrology chamber 28 to provide control signals, which may provide adaptive control over any of the processes being performed in the processing chambers. The integrated metrology chamber 28 may include any of a variety of metrological devices to measure various film properties, such as thickness, roughness, composition, and the metrology devices may further be capable of characterizing grating parameters such as critical dimensions, sidewall angle, and feature height under vacuum in an automated manner.

[0029] Each of processing chambers 24a-d may be configured to perform one or more process steps in the fabrication of a semiconductor structure, and any number of processing chambers and combinations of processing chambers may be used on multi-chamber processing system 10. For example, any of the processing chambers may be configured to perform a number of substrate processing operations including any number of deposition processes including cyclical layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, as well as other operations including etch, pre-clean, pre-treatment, post-treatment, anneal, plasma processing, degas, orientation, and other substrate processes. Some specific processes that may be performed in any of the chambers or in any combination of chambers may be metal deposition, surface cleaning and preparation, thermal annealing such as rapid thermal processing, and plasma processing. Any other processes may similarly be performed in specific chambers incorporated into multichamber processing system 10, including any process described below', as would be readily appreciated by the skilled artisan.

[0030] FIG. 2 illustrates a schematic cross-sectional view of an exemplary processing chamber 100 suitable for patterning a material layer disposed on a substrate 302 in the processing chamber 100. The exemplar}' processing chamber 100 is suitable for performing apatterning process, although it is to be understood that aspects of the present technology may be performed in any number of chambers, and substrate supports according to the present technology may be included in etching chambers, deposition chambers, treatment chambers, or any other processing chamber. The plasma processing chamber 100 may include a chamber body 105 defining a chamber volume 101 in which a substrate may be processed. The chamber body 105 may have sidewalls 112 and a bottom 118 which are coupled with ground 126. The sidewalls 112 may have a liner 115 to protect the sidewalls 112 and extend the time between maintenance cycles of the plasma processing chamber 100. The dimensions of the chamber body 105 and related components of the plasma processing chamber 100 are not limited and generally may be proportionally larger than the size of the substrate 302 to be processed therein. Examples of substrate sizes include 200 mm diameter. 250 mm diameter, 300 mm diameter and 450 mm diameter, among others, such as display or solar cell substrates as well.

[0031] The chamber body 105 may support a chamber lid assembly 110 to enclose the chamber volume 101. The chamber body 105 may be fabricated from aluminum or other suitable materials. A substrate access port 113 may be formed through the sidewall 112 of the chamber body 105, facilitating the transfer of the substrate 302 into and out of the plasma processing chamber 100. The access port 113 may be coupled with atransfer chamber and / or other chambers of a substrate processing system as previously described. A pumping port 145 may be formed through the sidewall 112 of the chamber body 105 and connected to the chamber volume 101. A pumping device may be coupled through the pumping port 145 to the chamber volume 101 to evacuate and control the pressure within the processing volume. The pumping device may include one or more pumps and throttle valves.

[0032] A gas panel 160 may be coupled by a gas line 167 with the chamber body 105 to supply process gases into the chamber volume 101. The gas panel 160 may include one or more process gas sources 161, 162, 163. 164 and may additionally include inert gases, non-reactive gases, and reactive gases, as may be utilized for any number of processes. Examples of process gases that may be provided by the gas panel 160 include, but are not limited to, hydrocarbon containing gas including methane, sulfur hexafluoride, silicon chloride, carbon tetrafluoride, hydrogen bromide, hydrocarbon containing gas. argon gas, chlorine, nitrogen, helium, or oxygen gas, as well as any number of additional materials. Additionally, process gasses may include nitrogen, chlorine, fluorine, oxygen, and hydrogen containing gases such as H2. NH3, H2O, H2O2, NF3, HF, F2, CF , CHF3, C2F6, C2F4, C3F6, C4F6, C F8, BrF3, C1F3,SF6, CH3F, CH2F2, BCh, PF3, PH3, COS, and SO2, among any number of additional precursors.

[0033] Valves 166 may control the flow of the process gases from the sources 161. 162, 163, 164 from the gas panel 160 and may be managed by a controller 165. The flow of the gases supplied to the chamber body 105 from the gas panel 160 may include combinations of the gases form one or more sources. The lid assembly 110 may include a nozzle 114. The nozzle 114 may be one or more ports for introducing the process gases from the sources 161.162, 164, 163 of the gas panel 160 into the chamber volume 101. After the process gases are introduced into the plasma processing chamber 100, the gases may be energized to form plasma. An antenna 148, such as one or more inductor coils, may be provided adjacent to the plasma processing chamber 100. An antenna power supply 142 may power the antenna 148 through a match circuit 141 to inductively couple energy, such as RF energy, to the process gas to maintain a plasma formed from the process gas in the chamber volume 101 of the plasma processing chamber 100. Alternatively, or in addition to the antenna power supply 142, process electrodes below the substrate 302 and / or above the substrate 302 may be used to capacitively couple RF power to the process gases to maintain the plasma within the chamber volume 101. The operation of the antenna power supply 142 may be controlled by a controller, such as controller 165, that also controls the operation of other components in the plasma processing chamber 100.

[0034] A substrate support pedestal 135 may be disposed in the chamber volume 101 to support the substrate 302 during processing. The substrate support pedestal 135 may include an electrostatic chuck (‘‘ESC’’) 122 for holding the substrate 302 during processing. The ESC 122 may use the electrostatic attraction to hold the substrate 302 to the substrate support pedestal 135. The ESC 122 may be powered by an RF power supply 125 integrated with a match circuit 124. The ESC 122 may include an electrode 121 embedded within a dielectric body. The electrode 121 may be coupled with the RF power supply 125 and may provide a bias which attracts plasma ions, formed by the process gases in the chamber volume 101, to the ESC 122 and substrate 302 seated on the pedestal. The RF power supply 125 may cycle on and off, or pulse, during processing of the substrate 302. The ESC 122 may have an isolator 128 for the purpose of making the sidewall of the ESC 122 less attractive to the plasma to prolong the maintenance life cycle of the ESC 122. Additionally, the substrate support pedestal 135 may have a cathode liner 136 to protect the sidewalls of the substratesupport pedestal 135 from the plasma gases and to extend the time between maintenance of the plasma processing chamber 100.

[0035] Electrode 121 may be coupled with a power source 150. The power source 150 may provide a chucking voltage of about 500 volts to about 15,000 volts to the electrode 121. The power source 150 may also include a system controller for controlling the operation of the electrode 121 by directing a DC current to the electrode 121 for chucking and dechucking the substrate 302. For example, similar to the RF power supply 125, power source 150 may provide a bias which attracts plasma ions, formed by the process gases in the chamber volume 101, to the ESC 122 and substrate 302 seated on the pedestal. The power source 150 may cycle on and off, or pulse, during processing of the substrate 302. In embodiments, the power source 150 may supply RF power, DC current or voltage for chucking and / or bias, or a combination thereof. In additional embodiments, multiple power supplies may be configured to supply RF power and DC current or voltage for chucking and / or bias. The ESC 122 may include heaters disposed within the pedestal and connected to a power source for heating the substrate, while a cooling base 129 supporting the ESC 122 may include conduits for circulating a heat transfer fluid to maintain a temperature of the ESC 122 and substrate 302 disposed thereon. The ESC 122 may be configured to perform in the temperature range required by the thermal budget of the device being fabricated on the substrate 302. For example, the ESC 122 may be configured to maintain the substrate 302 at a temperature of about -150 °C or lower to about 500 °C or higher depending on the process being performed.

[0036] The cooling base 129 may be provided to assist in controlling the temperature of the substrate 302. To mitigate process drift and time, the temperature of the substrate 302 may be maintained substantially constant by the cooling base 129 throughout the time the substrate 302 is in the cleaning chamber. In some embodiments, the temperature of the substrate 302 may be maintained throughout subsequent cleaning processes at temperatures between about -150 °C and about 500 °C, although any temperatures may be utilized. A cover ring 130 may be disposed on the ESC 122 and along the periphery of the substrate support pedestal 135. The cover ring 130 may be configured to confine etching gases to a desired portion of the exposed top surface of the substrate 302, while shielding the top surface of the substrate support pedestal 135 from the plasma environment inside the plasma processing chamber 100. Lift pins may be selectively translated through the substrate support pedestal 135 to lift the substrate 302 above the substrate support pedestal 135 to facilitateaccess to the substrate 302 by a transfer robot or other suitable transfer mechanism as previously described.

[0037] The controller 165 may be utilized to control the process sequence, regulating the gas flows from the gas panel 160 into the plasma processing chamber 100, and other process parameters. Software routines, when executed by the CPU, transform the CPU into a specific purpose computer such as a controller, which may control the plasma processing chamber 100 such that the processes are performed in accordance with the present disclosure. The software routines may also be stored and / or executed by a second controller that may be associated with the plasma processing chamber 100.

[0038] FIG. 3 shows exemplary operations in a method 300 according to some embodiments of the present technology'. The method may be performed in a variety' of semiconductor processing chambers, including processing chamber 100 described above. Method 300 may include a number of optional operations, which may or may not be specifically7associated w ith some embodiments of methods according to the present technology. For example, many of the operations are described in order to provide a broader scope of the structural formation, but are not critical to the technology, or may be performed by alternative methodology as would be readily appreciated.

[0039] Method 300 may include additional operations prior to initiation of the listed operations. For example, additional processing operations may include forming or providing chamber components. Prior processing operations may be performed in the chamber in which method 300 may be performed, or processing may be performed in one or more other processing chambers prior to delivering or installing the chamber component(s) into the semiconductor processing chamber in which method 300 may7be performed. Method 300 describes operations shown schematically in FIGS. 4A-4D and FIGS. 5A-5D, the illustrations of which w ill be described in conjunction with the operations of method 300. It is to be understood that FIGS. 4A-4D and FIGS. 5A-5D illustrate only partial schematic views, and one or more chamber component(s) may include further structure than illustrated in the figures, as w ell as alternative structure, of any size or configuration that may still benefit from aspects of the present technology.

[0040] FIGS. 4A-4D and FIGS. 5A-5D illustrate a chamber component 400, 500 that may be coated according to embodiments of the present technology. As discussed above, the chamber component 400, 500 may be any one or more chamber components having a surfaceexposed to an interior of a semiconductor processing chamber, such as process chamber 24a-d or processing chamber 100 discussed above. As such, the chamber component 400, 500 may at least partially define a processing region of the semiconductor processing chamber. Namely, in embodiments, the chamber component 400, 500 may be any one or more components used in a plasma processing chamber, such as a plasma processing chamber used for deposition and / or etching. For example, the chamber component 400. 500 may be a lid, a wall, an electrostatic chuck (ESC), or any other component defining the processing region. In embodiments, the chamber component 400 may be disposed at an upper portion of the processing region, such as an upper half of a volume of the processing region. For example, the chamber component 400 may be a portion of the lid or an upper portion of a wall.Conversely, chamber component 500 may be disposed at a lower portion of the processing region, such as a lower half of a volume of the processing region. For example, the chamber component 500 may be a portion of ESC or a lower portion of a wall. It is also contemplated that the chamber component 400, 500 may be a bellows, a lid stack, a faceplate, a showerhead, a gas line, a gas panel, a mass flow controller (MFC), a foreline, a cooling plate, an ion suppressor, a baffle, supplies, inlets, outlets, and supports thereof, or the like. In embodiments, the chamber component 400, 500 may be assembled in a process chamber 24a-d or a processing chamber 100 (e.g., for an in-situ process as will be discussed in greater detail below).

[0041] At operation 305, method 300 may include providing one or more coating precursors to the processing region of the semiconductor processing chamber. As previously discussed, the processing region may be at least partially defined by one or more chamber components 400, 500, such as a lid, one or more walls, and an ESC. The one or more coating precursors may include, but are not limited to, a silicon-containing precursor and an oxygencontaining precursor. Other precursors may be provided depending on the desired coating material. For example, to form a silicon-and-oxygen-containing coating, the coating precursors may include the silicon-containing precursor and the oxy gen-containing precursor. If a silicon-oxygen-and-carbon-containing coating is desired, the coating precursors may further include a carbon-containing precursor.

[0042] The silicon-containing precursor may be any silicon-containing material used or useful in forming a silicon-and-oxygen-containing material. For example, the silicon-containing precursor may be or include silane (SiFU), disilane (Si2He), higher-order silanes, tetraethyl orthosilicate (TEOS), or any other silicon-containing precursor used or useful insemiconductor processing. In embodiments, the silicon-containing precursor may include a halogen. As such, the silicon-containing precursor may be a silicon-and-halogen-containing precursor. For example, the silicon-containing precursor may be or include dichlorosilane (SiCh) or silicon tetrafluoride (SiCU).

[0043] A flow rate of the silicon-containing precursor may be between about 5 seem and about 500 seem. In embodiments, the flow rate of the silicon-containing precursor may be less than or about 500 seem, and may be less than or about 450 seem, less than or about 400 seem, less than or about 350 seem, less than or about 300 seem, less than or about 250 seem, less than or about 200 seem, less than or about 180 seem, less than or about 160 seem, less than or about 140 seem, less than or about 120 seem, less than or about 100 seem, less than or about 80 seem, less than or about 60 seem, or less. Increased flow rates of the silicon-containing precursor may increase a deposition rate of the coating, which may result in an overly thick coating being deposited. While a thicker coating may better separate the chamber component 400, 500 and the processing region, such as a substrate being processed in the processing region, a thicker coating may be harder to strip and may be unnecessarily excessive compared to a thinner coating. However, the flow rate of the silicon-containing precursor may be greater than or about 10 seem, and may be greater than or about 20 seem, greater than or about 30 seem, greater than or about 40 seem, greater than or about 50 seem, greater than or about 60 seem, greater than or about 70 seem, greater than or about 80 seem, greater than or about 90 seem, greater than or about 100 seem, or more.

[0044] Exemplary oxygen-containing precursors may be or include diatomic oxygen (O2), ozone (Ch), nitrogen dioxide (NO2), nitrous oxide (N2O), water or steam (H2O), or any other oxygen-containing precursor used or useful in semiconductor processing.

[0045] A flow rate of the oxygen-containing precursor may be between about 5 seem and about 750 seem. In embodiments, the flow rate of the oxy gen-containing precursor may be less than or about 500 seem, and may be less than or about 450 seem, less than or about 400 seem, less than or about 350 seem, less than or about 325 seem, less than or about 300 seem, less than or about 275 seem, less than or about 250 seem, less than or about 225 seem, less than or about 200 seem, less than or about 190 seem, less than or about 180 seem, less than or about 170 seem, less than or about 160 seem, less than or about 150 seem, or less. Similar to the silicon-containing precursor, increased flow rates of the oxy gen-containing precursor may increase the deposition rate of the coating, which may result in an overly thick coating beingdeposited. While a thicker coating may better separate the chamber component 400, 500 and the processing region, such as a substrate being processed in the processing region, a thicker coating may be harder to strip and may be unnecessarily excessive compared to a thinner coating. However, the flow rate of the oxygen-containing precursor may be greater than or about 25 seem, and may be greater than or about 50 seem, greater than or about 75 seem, greater than or about 100 seem, greater than or about 120 seem, greater than or about 140 seem, greater than or about 150 seem, greater than or about 160 seem, greater than or about 170 seem, greater than or about 180 seem, greater than or about 190 seem, greater than or about 200 seem, or more.

[0046] As previously discussed, other precursors may be provided depending on the desired coating material. Other precursors may be or include, but are not limited to, carbon-containing precursors, hydrogen-containing precursor, nitrogen-containing precursor, or other precursors useful in forming coatings. Additionally, the one or more coating precursors may be provided with an inert gas and / or carrier gas. The inert gas and / or carrier gas may be or include, for example, argon (Ar), helium (He), xenon (Xe), or other noble, inert, or useful gases or precursors. The inert gas and / or carrier gas may be used to dilute the one or more coating precursors or to assist in distributing the one or more coating precursors throughout the processing region.

[0047] Method 300 may include forming plasma effluents of the one or more coating precursors at operation 310. The plasma effluents of the one or more coating precursors may be formed directly in the processing region. However, it is also contemplated that the plasma effluents of some or all of the one or more coating precursors may be formed remotely, such as in a remote plasma system. A source power used to form the plasma effluents of the one or more coating precursors may be related to deposition rate of the coating. At higher source powers, dissociation of the coating precursors may increase, which may result in the deposition rate increasing. To control the deposition rate, the source power may be between about 250 W and about 2,000 W. For example, the source power used to form plasma effluents of the coating precursors may be greater than or about 250 W, and may be greater than or about 500 W, greater than or about 750 W. greater than or about 800 W, greater than or about 850 W, greater than or about 900 W, greater than or about 950 W, greater than or about 1 ,000 W, greater than or 1 ,050 W, greater than or about 1 , 100 W, greater than or about 1,150 W, greater than or about 1,200 W, greater than or about 1,250 W, or more.Conversely, the source power used to form plasma effluents of the coating precursors may beless than or about 2,000 W, and may be less than or about 1,750 W, less than or about 1,500 W, less than or about 1,250 W. less than or about 1,200 W, less than or about 1,150 W. less than or 1,100 W, less than or about 1,050 W, less than or about 1,000 W, or less.

[0048] At operation 315, method 300 may include contacting the chamber components 400, 500 with the plasma effluents of the one or more coating precursors. The contacting may deposit a first portion of a coating 410 on the chamber components 400, 500 at least partially defining the processing region. As illustrated in FIG. 4B and FIG. 5B. the first portion of the coating 410 may preferentially form on chamber component 500. That is, the thickness of the first portion of the coating 410 on chamber component 500 may be thicker than the thickness of the first portion of the coating 410 on chamber component 400.

[0049] Operation 315 may be performed at a first pressure. The first pressure may be between about 5 mTorr and about 15 mTorr. At lower pressures, the plasma effluents of the one or more coating precursors may be afforded a longer mean-free path. As such, the plasma effluents may be able to reach and fully coat tighter or smaller portions of the components defining the processing region. For example, at lower pressures, the plasma effluents of the one or more coating precursors may better coat comers of the processing region, such as between a wall and a lid of the semiconductor processing region. In embodiments, the first pressure may be less than or about 15 mTorr, and may be less than or about 14 mTorr, less than or about 13 mTorr, less than or about 12 mTorr, less than or about 11 mTorr, less than or about 10 mTorr, less than or about 9 mTorr, less than or about 8 mTorr, less than or about 7 mTorr. less than or about 6 mTorr, or less. Additionally, at lower pressures, a dense / hard coating may be formed, which may protect the lid and / or the ESC. More specifically, the lid be made from and at least partially include yttrium (Y). The ESC may be made from and at least partially include aluminum (Al). The dense first portion of the coating 410 may protect from Y escaping the lid and from Al escaping the ESC during subsequent plasma processing.

[0050] The first period of time may be sufficient to form the first portion of the coating 410. As previously discussed, increased deposition of the coating may not result in any increased protection and / or may result in excessive thickness of the coating. As such, the first period of time may be less than or about 20 seconds, and may be less than or about 18 seconds, less than or about 16 seconds, less than or about 14 seconds, less than or about 12 seconds, less than or about 10 seconds, less than or about 9 seconds, less than or about 8seconds, less than or about 7 seconds, less than or about 6 seconds, less than or about 5 seconds, or less. Conversely, to sufficiently form the first portion of the coating 510 in smaller or tighter aspects of the processing region, the first period of time may be greater than or about 2 seconds, and may be greater than or about 2.5 seconds, greater than or about 3 seconds, greater than or about 3.5 seconds, greater than or about 4 seconds, greater than or about 4.5 seconds, greater than or about 5 seconds, greater than or about 6 seconds, greater than or about 7 seconds, greater than or about 8 seconds, greater than or about 9 seconds, greater than or about 10 seconds, or more.

[0051] A thickness of the first portion of the coating 410 may be between about 10 nm and about 150 nm. For example, the thickness of the first portion of the coating 410 may be less than or about 150 nm, and may be less than or about 125 nm, less than or about 100 nm, less than or about 75 nm, less than or about 50 nm. less than or about 25 nm, less than or about 20 nm, less than or about 15 nm, less than or about 10 nm, or less. Conversely, the thickness of the first portion of the coating 410 may be greater than or about 10 nm, and may be greater than or about 15 nm, greater than or about 25 nm, greater than or about 25 nm, greater than or about 50 nm, greater than or about 75 nm, greater than or about 100 nm, greater than or about 125 nm, greater than or about 150 nm, or more.

[0052] Subsequent to a first period of time, method 300 may include increasing a pressure within the processing region to a second pressure at operation 320. Flow rates of the one or more coating precursors may be maintained or substantially maintained between operation 315 and 320. As such, the chamber components 400, 500 may continuously be contacted with the plasma effluents of the one or more coating precursors during operation 320. As illustrated in FIG. 4C and FIG. 5C, a second portion of the coating 415 may be deposited on the first portion of the coating 410 over the second period of time.

[0053] The second pressure may be between about 50 mTorr and about 150 mTorr. At increased pressures, the plasma effluents of the one or more coating precursors may be afforded a shorter mean-free path. As such, the portion of the coating deposited at the second pressure may be characterized by a reduced density and / or increased porosity compared to the portion of the coating deposited at the second pressure. A reduced porosity of the portion of the coating deposited at the second pressure may allow for absorption of ions and / or radicals during processing during subsequent plasma processing along with subsequent release of these ions and / or radicals during post-plasma processing operations, such ascleaning. In embodiments, the second pressure may be greater than or about 50 mTorr. and may be greater than or about 55 mTorr, greater than or about 60 mTorr. greater than or about 65 mTorr, greater than or about 66 mTorr, greater than or about 68 mTorr, greater than or about 70 mTorr, greater than or about 72 mTorr, greater than or about 74 mTorr, greater than or about 76 mTorr, greater than or about 78 mTorr, greater than or about 80 mTorr, or more.

[0054] By increasing the pressure, the coating may predominantly form on upper portions of the processing region, such as the one or more walls or upper portions of the one or more walls defining the processing region. At increased pressures, the mean free path of the plasma effluents may reduce, which may predominantly form the coating on upper portions of the processing region. By utilizing both a low-pressure deposition and a high-pressure deposition the coating may more fully cover upper and lower portions of the processing region, which may be resultant due to plasma volume expansion during the deposition. This may minimize particle contamination while maximizing equipment longevity and manufacturing quality.

[0055] The second period of time, in which the pressure is ramped from the first pressure to the second pressure, may be between about 2 seconds and about 30 seconds. For example, the second period of time may be greater than or about 2 seconds, and may be greater than or about 2.5 seconds, greater than or about 3 seconds, greater than or about 3.5 seconds, greater than or about 4 seconds, greater than or about 4.5 seconds, greater than or about 5 seconds, greater than or about 6 seconds, greater than or about 7 seconds, greater than or about 8 seconds, greater than or about 9 seconds, greater than or about 10 seconds, or more.Conversely, the second period of time may be less than or about 30 seconds, and may be less than or about 25 seconds, less than or about 20 seconds, less than or about 15 seconds, less than or about 10 seconds, less than or about 9 seconds, less than or about 8 seconds, less than or about 7 seconds, less than or about 6 seconds, less than or about 5 seconds, or less.

[0056] Pressure may be increased, or ramped, from the first pressure to the second pressure over a second period of time. While various second pressures and second periods of time are contemplated, the pressure may be ramped from the first pressure to the second pressure at a rate of less than or about 20 mTorr / second. At increased rates, due to the difference in the first pressure and the second pressure and / or the second period of time, pressure may be increased too quickly. At too quick of an increase in pressure, the coating may be characterized by a lattice mismatch. As such, the coating may be prone to separation,flaking, and / or fracturing. Therefore, the pressure may be ramped from the first pressure to the second pressure at a rate of less than or about 18 mTorr / second, less than or about 16 mTorr / second, less than or about 14 mTorr / second, less than or about 12 mTorr / second, less than or about 10 mTorr / second less than or about 8 mTorr / second, less than or about 6 mTorr / second, less than or about 5 mTorr / second, or less. At rates of less than or about 20 mTorr / second, the first portion of the coating 410 may be bonded to a third portion of the coating, discussed below, via the second portion of the coating 415. The second portion of the coating 415 may provide a gradient of the coating serving as a beneficial lattice match between the first portion of the coating 410 and the third portion of the coating, discussed below.

[0057] A thickness of the second portion of the coating 515 may be between about 5 nm and about 50 nm. For example, the thickness of the second portion of the coating 515 may be less than or about 50 nm, and may be less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, less than or about 5 nm, or less. Conversely, the thickness of the second portion of the coating 515 may be greater than or about 5 nm, and may be greater than or about 10 nm, greater than or about 20 nm, greater than or about 30 nm, greater than or about 40 nm, greater than or about 50 nm, or more

[0058] At operation 325, method 300 may include depositing a third portion of the coating 520 on the second portion of the coating 415 over a third period of time at the second pressure. Flow rates of the one or more coating precursors may be maintained or substantially maintained between operation 320 and 325. As such, the chamber components 400, 500 may continuously be contacted with the plasma effluents of the one or more coating precursors during operation 320. As illustrated in FIG. 4D and FIG. 5D, the second portion of the coating 420 may preferentially form on chamber component 400. That is, the thickness of the third portion of the coating 420 on chamber component 400 may be thicker than the thickness of the third portion of the coating 420 on chamber component 500.

[0059] Similar to the first period of time, the third period of time may be sufficient to form the third portion of the coating 420. As previously discussed, increased deposition of the coating may not result in any increased protection and / or may result in excessive thickness of the coating. As such, the third period of time may be less than or about 20 seconds, and may be less than or about 18 seconds, less than or about 16 seconds, less than or about 14 seconds, less than or about 12 seconds, less than or about 10 seconds, less than or about 9 seconds, lessthan or about 8 seconds, less than or about 7 seconds, less than or about 6 seconds, less than or about 5 seconds, or less. Conversely, the third period of time may be greater than or about 2 seconds, and may be greater than or about 2.5 seconds, greater than or about 3 seconds, greater than or about 3.5 seconds, greater than or about 4 seconds, greater than or about 4.5 seconds, greater than or about 5 seconds, greater than or about 6 seconds, greater than or about 7 seconds, greater than or about 8 seconds, greater than or about 9 seconds, greater than or about 10 seconds, or more.

[0060] A thickness of the third portion of the coating 420 may be between about 10 nm and about 150 nm. For example, the thickness of the third portion of the coating 420 may be less than or about 150 nm, and may be less than or about 125 nm, less than or about 100 nm, less than or about 75 nm, less than or about 50 nm. less than or about 25 nm, less than or about 20 nm. less than or about 15 nm, less than or about 10 nm, or less. Conversely, the thickness of the third portion of the coating 420 may be greater than or about 10 nm, and may be greater than or about 15 nm, greater than or about 25 nm, greater than or about 25 nm, greater than or about 50 nm, greater than or about 75 nm, greater than or about 100 nm, greater than or about 125 nm, greater than or about 150 nm, or more.

[0061] Subsequent to depositing the third portion of the coating 420, method 300 may include halting a flow of one or more of the coating precursors at optional operation 330. For example, a flow of the silicon-containing precursor may be halted while maintaining a flow of the oxy gen-containing precursor. In embodiments, formation of plasma effluents of the oxygen-containing precursor may also be maintained. At optional operation 335. method 300 may include contacting the third portion of the coating 420 with, for example, the plasma effluents of the oxy gen-containing precursor. Contacting the third portion of the coating 420 with the plasma effluents of the oxygen-containing precursor may further oxidize an outer portion of the coating.

[0062] In embodiments, subsequent to depositing the third portion of the coating 420, the flow rate of the oxy gen-containing precursor and / or the source power may be increased prior to or simultaneously to contacting the third portion of the coating 420 with, for example, the plasma effluents of the oxy gen-containing precursor at optional operation 335. For example, the flow rate of the oxygen-containing precursor may be increased to greater than or about 400 seem, and may be increased to greater than or about 450 seem, greater than or about 500 seem, greater than or about 550 seem, greater than or about 600 seem, greater than or about650 seem, greater than or about 700 seem, greater than or about 750 seem, greater than or about 800 seem, or more. Similarly, the source power may be increased to greater than or about 750 W, and may be increased to greater than or about 1,000 W, greater than or about 1,250 W, greater than or about 1,500 W, greater than or about 1,600 W, greater than or about 1,700 W, greater than or about 1,750 W, greater than or about 1,800 W, greater than or about 1,900 W, greater than or about 2.000 W, or more.

[0063] In embodiments, the method 300 may be performed at a temperature between about -100 °C and about 100 °C. At increased temperatures, reactivity of the precursors may increase, which may result in accelerated chemical reactions and / or deposition rates. As such, to ensure controlled and optimized coating, method 300 may be performed at a temperature less than or about 90 °C, and may be performed at a temperature less than or about 80 °C, less than or about 70 °C, less than or about 60 °C, less than or about 50 °C, less than or about 40 °C, less than or about 30 °C, less than or about 20 °C, less than or about 10 °C, less than or about 0 °C, less than or about -20 °C, less than or about -40 °C, less than or about -60 °C, less than or about -80 °C, or less. Conversely, at reduced temperatures, formation of the coating may reduce, which may result in thinner and less conformal coatings. As such, method 300 may be performed at a temperature greater than or about -80 °C, and may be performed at a temperature greater than or about -60 °C, greater than or about -40 °C, greater than or about -20 °C, greater than or about 0 °C, greater than or about 10 °C, greater than or about 20 °C, greater than or about 30 °C. greater than or about 40 °C, greater than or about 50 °C, greater than or about 60 °C. greater than or about 70 °C. greater than or about 80 °C, greater than or about 90 °C, or more.

[0064] By depositing the coating at multiple temperatures, such that a dual-layer coating may be formed, the present technology may better coat component surfaces defining the processing region. The coating may be more uniform and / or smoother compared to conventional technologies. Additionally, the coating may better protect components from contaminating substrates being processed as well as absorbing ions and / or radicals during processing and releasing the ions and / or radicals after processing. Further, by ramping the pressure during the deposition of the coating, the more porous outer coating may be strongly bonded to the denser / harder inner coating, which may reduce and / or prevent separation, flaking, and / or fracturing.

[0065] In the preceding description, for the purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. It will be apparent to one skilled in the art, however, that certain embodiments may be practiced without some of these details, or with additional details.

[0066] Having disclosed several embodiments, it will be recognized by those of skill in the art that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. Additionally, a number of well-known processes and elements have not been described in order to avoid unnecessarily obscuring the present technology. Accordingly, the above description should not be taken as limiting the scope of the technology.

[0067] Where a range of values is provided, it is understood that each intervening value, to the smallest fraction of the unit of the lower limit, unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Any narrower range between any stated values or unstated intervening values in a stated range and any other stated or intervening value in that stated range is encompassed. The upper and lower limits of those smaller ranges may independently be included or excluded in the range, and each range where either, neither, or both limits are included in the smaller ranges is also encompassed within the technology, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0068] As used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural references unless the context clearly dictates otherwise. Thus, for example, reference to “a layer” includes a plurality of such layers, and reference to “the precursor” includes reference to one or more precursors and equivalents thereof known to those skilled in the art, and so forth. “About” and / or “approximately” as used herein when referring to a measurable value such as an amount, a temporal duration, and the like, encompasses variations of ±20% or ±10%, ±5%, or ±0.1% from the specified value, as such variations are appropriate to in the context of the systems, devices, circuits, methods, and other implementations described herein. “Substantially” as used herein when referring to a measurable value such as an amount, a temporal duration, a physical attribute (such as frequency), and the like, also encompasses variations of ±20% or ±10%, ±5%, or ±0.1% fromthe specified value, as such variations are appropriate to in the context of the systems, devices, circuits, methods, and other implementations described herein.

[0069] Also, the words “comprise(s)”. “comprising’; “contain(s)”, “containing”, “include(s)”, and “including”, when used in this specification and in the following claims, are intended to specify the presence of stated features, integers, components, or operations, but they do not preclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.

Claims

WHAT IS CLAIMED IS:

1. A coating method comprising:providing one or more coating precursors to a processing region of a semiconductor processing chamber, wherein the processing region is at least partially defined by a lid and one or more walls;forming plasma effluents of the one or more coating precursors; depositing a first portion of a coating on the lid and one or more walls at least partially defining the processing region at a first pressure;subsequent to a first period of time, increasing a pressure within the processing region to a second pressure over a second period of time while depositing a second portion of the coating on the first portion of the coating; anddepositing a third portion of the coating on the second portion of the coating over a third period of time at the second pressure.

2. The coating method of claim 1 , wherein the one or more coating precursors comprise a silicon-containing precursor.

3. The coating method of claim 2. wherein the silicon-containing precursor comprises a silicon-and-halogen-containing precursor.

4. The coating method of claim 2. wherein the silicon-containing precursor comprises dichlorosilane (SiCh) or silicon tetrafluoride (SiCU).

5. The coating method of claim 1, wherein the one or more coating precursors comprise an oxygen-containing precursor.

6. The coating method of claim 1, wherein the oxy gen-containing precursor comprises diatomic oxygen (O2).

7. The coating method of claim 1. wherein the first pressure is less than or about 15 mTorr.

8. The coating method of claim 1, wherein the first period of time is less than or about 20 seconds.

9. The coating method of claim 1. wherein the second pressure is greater than or about 50 mTorr.

10. The coating method of claim 1. wherein the second period of time is greater than or about 2 seconds.

11. The coating method of claim 1 , wherein the third portion of the coating is characterized by a reduced density compared to the first portion of the coating.

12. The coating method of claim 1, wherein the pressure is ramped from the first pressure to the second pressure at a rate of less than or about 20 mTorr / second.

13. The coating method of claim 1. wherein the coating comprises a silicon-and-oxy gen-containing material.

14. A coating method comprising:providing a silicon-containing precursor and an oxy gen-containing precursor to a processing region of a semiconductor processing chamber, wherein the processing region is at least partially defined by a lid, one or more walls, and an electrostatic chuck (ESC);forming plasma effluents of the silicon-containing precursor and the oxy gencontaining precursor;depositing a first portion of a coating on the lid and one or more walls at least partially defining the processing region at a first pressure, wherein the first portion of the coating preferentially forms on the lid and / or the ESC;subsequent to a first period of time, increasing a pressure within the processing region to a second pressure over a second period of time while depositing a second portion of the coating on the first portion of the coating; anddepositing a third portion of the coating on the second portion of the coating over a third period of time at the second pressure, wherein the third portion preferentially forms on the one or more walls.

15. The coating method of claim 14, wherein the silicon-containing precursor further comprises a halogen.

16. The coating method of claim 14, wherein the plasma effluents of the silicon-containing precursor and the oxygen-containing precursor are formed at a source power of greater than or about 500 W.

17. The coating method of claim 14, further comprising:subsequent to depositing the third portion of the coating, halting a flow of the silicon-containing precursor while maintaining a flow of the oxy gen-containing precursor and formation of plasma effluents of the oxy gen-containing precursor; andcontacting the third portion of the coating with the plasma effluents of the oxygen-containing precursor to further oxidize a portion of the coating.

18. A coating method comprising:providing a silicon-and-chlorine-containing precursor and an oxy gencontaining precursor to a processing region of a semiconductor processing chamber, wherein the processing region is at least partially defined by a lid, one or more walls, and an electrostatic chuck (ESC);forming plasma effluents of the silicon-containing precursor and the oxy gencontaining precursor at a source power of less than or about 1,500 W;depositing a first portion of a coating on the lid and one or more walls at least partially defining the processing region at a first pressure less than or about 10 mTorr, wherein the first portion preferentially forms on the lid and / or the ESC:subsequent to a first period of time, increasing a pressure within the processing region to a second pressure greater than or about 60 mTorr over a second period of time while depositing a second portion of the coating on the first portion of the coating; anddepositing a third portion of the coating on the second portion of the coating over a third period of time at the second pressure, wherein the third portion preferentially forms on the one or more walls.

19. The coating method of claim 18, wherein the second period of time is between about 2 seconds and about 30 seconds.

20. The coating method of claim 18, wherein a temperature in the processing region is maintained at less than or about 100 °C.

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