Device and method for testing performance degradation caused by transistor lattice deformation

A technology of a testing device and a testing method, applied in the field of microelectronics, can solve the problems of inaccurate calculation of the lattice deformation of the transistor, uneven stress on the transistor, uneven stress on the chip, etc. The effect of overcoming the limited range of mechanical stress and improving the range of mechanical stress

CN102967814AActive Publication Date: 2013-03-13云南凝慧电子科技有限公司
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Publication Date
2013-03-13

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Abstract

The invention discloses a device and method for testing performance degradation caused by transistor lattice deformation. The device for testing the performance degradation caused by the transistor lattice deformation comprises a base, a precise displacement platform, a cushion block, a carrier and a pressing block. The method for testing the performance degradation caused by the transistor lattice deformation comprises the following steps of (1) thinning a chip; (2) cutting the chip; (3) sticking the chip; (4) leading an electrode out of a transistor; (5) fixing the carrier; (6) testing the transistor before applying the stress; (7) applying the mechanical stress onto the chip; (8) testing the transistor under the stress; (9) judging whether the performance of the transistor degrades; and (10) obtaining the lattice deformation value when the performance of the transistor degrades. The device and method for testing the performance degradation caused by the transistor lattice deformation has the advantages of easily applying compression stress onto the chip, and being large in range of the applicable mechanical stress, good in chip bend uniform, simple and accurate in lattice tension amount calculation, and is suitable for analyzing the influence of the transistor lattice deformation on the performance of the transistor.
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Description

technical field

[0001] The invention belongs to the technical field of microelectronics, and further relates to a testing device and a method for performance degradation caused by lattice deformation of transistors in the technical field of semiconductor testing. The invention can be used for gallium nitride (Gallium Nitride, GaN) High Electron Mobility Transistors (High Electron Mobility Transistors, HEMTs) and other semiconductor transistor lattice deformation to cause performance degradation test, provide for the influence of transistor lattice deformation on transistor performance A more intuitive and convenient analysis method was developed. Background technique

[0002] During the working process of transistors, the generation of lattice deformation will lead to the degradation of transistor performance. This effect is more pronounced for gallium nitride high electron mobility transistors and other semiconductor devices with piezoelectric effect. Therefore, it is ver...

Examples

Embodiment Construction

[0035] Refer to attached figure 1 , a test device for performance degradation caused by transistor lattice deformation, including five parts: 1 is a base, 2 is a precision displacement platform, 3 is a spacer, 4 is a carrier, and 5 is a pressing block. in,

[0036]The cuboid base 1 is located at the bottom of the device, and one end is provided with two rows and two columns of four screw holes, which are connected with the precision displacement platform 2 on it with screws; the other end is provided with four rows and three columns of twelve screw holes. When the invention fixes the spacer 3, it can be connected with the spacer 3 on it with screws through one row of screw holes according to the specific lattice deformation test requirements. In the embodiment of the present invention, the spacer 3 is fixed on a row of screw holes on the side closest to the precise displacement platform 2 with screws.

[0037] The precision displacement platform 2 is located on the upper lef...