A GNSS satellite receiver baseband hardware platform circuit structure based on SOC architecture

Abstract

The present invention provides a GNSS satellite receiver baseband hardware platform circuit structure based on SOC architecture, which mainly includes a SOC processor module, a platform hardware basic resource module and an input / output interface module. The GNSS receiver baseband hardware circuit platform based on SOC architecture provided by the present invention enables the existing GNSS receiver to open up the bottleneck of receiving and processing the data transmission, processing and diversified interfaces of numerous GNSS satellite signals available worldwide, and adapts to the current GNSS development and the needs of users for the use of multi-mode and multi-frequency satellite signals. The circuit structure is simple and practical, the function is powerful, the use process is convenient and fast, the working performance is stable and reliable, and the scope of application is relatively wide.

Description

Technical Field

[0001] The present invention relates to the application field of GNSS navigation satellite receivers, and in particular to a baseband hardware platform circuit structure for GNSS satellite signal processing based on SOC. Background Art

[0002] GNSS (Global Navigation Satellite System) is a global navigation satellite system that uses satellites to transmit signals and receivers on the surface of the earth or near the ground to receive signals to measure the position and time of the observed object. GNSS satellite signals include the Beidou Navigation Satellite System (BDS), the United States' GPS, Russia's GLONASS, Europe's GALILEO, and related augmentation systems such as the United States' WAAS (Wide Area Augmentation System), Europe's EGNOS (European Geostationary Navigation Overlay System) and Japan's MSAS (Multi-purpose Transport Satellite Augmentation System), etc., and also covers other satellite navigation systems that are under construction and to be built in the future.

[0003] Among them, BDS, GPS and GALILEO signals are synthesized using typical code division multiple access (CDMA) modulation technology, and GLONASS signals are synthesized using frequency division multiple access (FDMA) modulation technology. The complete signal mainly includes three components: carrier, pseudo-random code and data code. The BDS signal carriers are denoted as B1 (1561.098MHz), B2 (1207.14MHz) and B3 (1268.52MHz). The GPS signal carriers are denoted as L1 (1575.42MHz), L2 (1227.6MHz) and L5 (1176.45MHz). The GLONASS signal carriers are denoted as G1 (1602MHz) and G2 (1246MHz). The GALILEO signal carriers are denoted as E1 (1589.74MHz), E2 (1561.1MHz), E5a (1176.45MHz), E5b (1207.14MHz) and E6 (1278.75MHz). There are four systems and thirteen frequencies in total. Each satellite in each satellite system transmits and broadcasts ranging codes and navigation information on its own two or three carrier frequencies. After the RF channel receives all the signals, the baseband circuit platform performs signal correlation, capture, tracking, navigation message analysis, positioning, and RTK (Real-time kinematic, carrier phase difference technology) high-precision calculation on the signals, and outputs the original observation data, RTK, and PPP (precise point positioning, precise single-point positioning) positioning result data.

[0004] In the prior art, there is a design scheme that selects a separate platform as the GNSS receiver baseband platform, using one FPGA (Field-Programmable Gate Array) chip plus one MCU chip (MCU here includes ARM or DSP, hereinafter collectively referred to as MCU), both of which are placed independently on the same circuit board of the receiver to work together, generally using EMIF (external memory connection interface) to complete the processing of GNSS intermediate frequency signals, wherein the FPGA chip mainly completes correlation, capture, and tracking, and the MCU chip completes the control of the FPGA, navigation message analysis, positioning solution and high-precision solution, etc. The data output interface includes UART (Universal Asynchronous Receiver / Transmitter), USB, and 10M Ethernet, and does not have a large-capacity storage function.

[0005] Each satellite system has multiple satellites, with an average of about 9 to 10 visible satellites. If calculated based on a total of thirteen frequency points, the amount of data transmitted from the FPGA to the MCU is very large. In addition, due to the high real-time requirements of the GNSS receiver, when a separate platform is used, the transmission of data between the two chips becomes a bottleneck, resulting in the inability of existing GNSS receivers to achieve comprehensive multi-system reception and processing, and to be compatible with a variety of external device interfaces. Summary of the invention

[0006] In view of the above-mentioned deficiencies in the current GNSS navigation satellite receiver field, the present invention provides a GNSS receiver baseband hardware circuit structure that can effectively solve the existing GNSS multi-system satellite environment and has multiple data communication interface forms and large-capacity storage functions. The specific solution is as follows:

[0007] The present invention provides a GNSS satellite receiver baseband hardware platform circuit structure based on SOC architecture, the structure comprising a SOC processor module, a platform hardware basic resource module and an input and output interface module;

[0008] The SOC processor module includes a PLPL (Programmable Logic) processor and a PS (Processing System) dual-core processor, and the PS dual-core processor includes a PS-A core and a PS-B core;

[0009] The platform hardware basic resource modules include Nor Flash circuit unit, communication circuit unit, extended memory circuit unit, storage circuit unit and OCXO clock circuit unit;

[0010] The input and output interface module includes an external event input signal circuit unit, a second pulse signal output circuit unit, a UART circuit unit generated by a PL processor, an SPI (Serial Peripheral Interface) circuit unit, an RTC (Real-Time Clock) circuit unit, a TCXO (Temperature Compensated Crystal Oscillator) unit, an IIC (Inter-Integrated Circuit) interface circuit unit, a CAN (Control Area Network) interface circuit unit, a USB interface circuit unit, a UART interface circuit unit generated by a PS dual-core processor, and an Ethernet circuit unit;

[0011] The SOC processor module receives the GNSS intermediate frequency signal generated by the external RF circuit, and outputs it to the PS-B core after processing by the PL processor. The PS-B core parses the original data of the GNSS signal message, performs GNSS positioning calculation and high-precision calculation, and generates the original data and positioning of the GNSS satellite, which are then transmitted to the PS-A core. The PS-A core outputs the data to the input and output interface module, which then outputs the data for data exchange and communication with peripheral devices.

[0012] The circuit structure of the GNSS satellite receiver baseband hardware platform of the above-mentioned SOC architecture adopts LPDDR2 (Low Power Double Data Rate) memory as an extended memory circuit unit, adopts EMMC (Embedded MultiMedia Card) memory as a storage circuit unit, and outputs the original observation data, RTK, and PPP positioning result data through the input and output interface module;

[0013] The LPDDR2 memory data interface is 32 bits and the address bit width is 10 bits.

[0014] The above-mentioned GNSS satellite receiver baseband hardware platform circuit structure of the SOC architecture, wherein the SOC processor module is a single SOC chip, the GNSS baseband signal is processed by the PL processor, the GNSS data is solved by the PS dual-core processor, and the PL processor and the PS dual-core processor use the AXI_ACP communication bus inside the SOC chip for data exchange.

[0015] In the above-mentioned SOC-architecture GNSS satellite receiver baseband hardware platform circuit structure, the TCXO unit / OCXO clock circuit unit is used to generate local time and output it to the PL processor as a clock source for reproducing the local time of the GNSS signal.

[0016] In the above-mentioned SOC-architecture GNSS satellite receiver baseband hardware platform circuit structure, an SDIO communication interface circuit is used between the storage circuit unit and the SOC processor module, and the storage content includes the receiver application and GNSS application data.

[0017] The above-mentioned GNSS satellite receiver baseband hardware platform circuit structure with a SOC architecture, wherein the communication circuit unit includes a WiFi / BT chip circuit, a Bluetooth antenna circuit, a WiFi antenna circuit, a communication working status switch control circuit and a digital communication interface SDIO circuit.

[0018] In the above-mentioned circuit structure of the GNSS satellite receiver baseband hardware platform with a SOC architecture, the Nor Flash circuit unit includes a Nor Flash circuit and a QSPI working mode circuit, and the Nor Flash is used to complete the BOOT program storage of the baseband platform.

[0019] The above-mentioned GNSS satellite receiver baseband hardware platform circuit structure of a SOC architecture, wherein the Ethernet circuit unit includes an Ethernet physical layer transceiver circuit and a network clock circuit, the Ethernet physical layer transceiver circuit is connected to the MIO interface of the PS-B core, and the network physical layer circuit is controlled by the PS-B core;

[0020] The Ethernet circuit unit provides 10M and 100M data transmission interfaces.

[0021] The above-mentioned GNSS satellite receiver baseband hardware platform circuit structure with a SOC architecture, wherein the UART interface circuit unit generated by the PS dual-core processor has a short circuit / static protection circuit, which is composed of an RS232 circuit and an LVTTL circuit. The RS232 circuit includes an LVTTL-1.8V conversion standard RS232 circuit, and the LVTTL circuit is an LVTTL-1.8V conversion LVTTL-3.3V circuit with short circuit protection and static protection circuits.

[0022] The above-mentioned GNSS satellite receiver baseband hardware platform circuit structure with a SOC architecture, wherein the USB interface circuit unit is composed of a USB transceiver circuit and a USB-HUBR circuit unit, the USB transceiver circuit is used to convert the universal serial bus of the PS dual-core processor into a USB OTG interface, and the USB-HUBR circuit unit is used to expand one USB into multiple USB interface circuits.

[0023] In the above-mentioned SOC-architecture GNSS satellite receiver baseband hardware platform circuit structure, the CAN interface circuit unit converts the LVTTL-1.8V signal of the PS-A core into an LVTTL-3.3V signal, and then uses the RS485 level conversion circuit to convert the signal into a differential signal.

[0024] The above-mentioned GNSS satellite receiver baseband hardware platform circuit structure with a SOC architecture, wherein the IIC interface circuit unit includes an IIC interface clock, a data signal protection circuit and a drive circuit, and is a standard IIC communication interface to the outside for connecting to an external IIC interface master device.

[0025] The above-mentioned GNSS satellite receiver baseband hardware platform circuit structure of the SOC architecture, wherein the TCXO unit includes a power supply voltage regulator circuit and a clock amplifier circuit. The power supply voltage regulator circuit provides a 1.8V low-noise DC power supply for the TCXO unit. The clock amplifier circuit shapes and amplifies the clock signal generated by the TCXO unit, and then outputs it to the PS dual-core processor as a clock source.

[0026] The above-mentioned GNSS satellite receiver baseband hardware platform circuit structure with a SOC architecture, wherein the RTC circuit unit includes an RTC power supply circuit and an RTC clock circuit, the RTC power supply circuit includes an RTC power supply charging circuit and a discharging circuit, and the RTC clock circuit includes a data transmission circuit and a time interrupt generation circuit.

[0027] In the above-mentioned circuit structure of the GNSS satellite receiver baseband hardware platform with a SOC architecture, the input signal of the SPI circuit unit is generated by the PL processor.

[0028] In the above-mentioned GNSS satellite receiver baseband hardware platform circuit structure of a SOC architecture, the external event input signal circuit unit includes:

[0029] An external signal input detection circuit unit is used to detect an external signal;

[0030] A signal shaping circuit unit, used for shaping and filtering the signal;

[0031] The electrostatic protection circuit unit is used to protect circuit signals.

[0032] The above-mentioned GNSS satellite receiver baseband hardware platform circuit structure with a SOC architecture, wherein the second pulse signal output circuit unit includes a pulse generating circuit unit, a signal driving circuit unit and a short-circuit protection circuit unit connected in series, the pulse generating circuit outputs an LVTTL-1.8V square wave signal, the signal driving circuit unit amplifies the signal of the pulse generating circuit, including voltage amplification and current amplification, and then transmits it to the short-circuit protection circuit unit for external output.

[0033] The present invention provides a GNSS receiver baseband hardware circuit design with a SOC architecture, a circuit structure for converting GPS satellite signals into baseband signals, which can effectively solve the problem of large data volume transmission of GNSS multi-mode and multi-frequency channel signals, has powerful hardware basic resources, reduces the size of hardware circuits, enriches external data communication interfaces, and has a simple and practical circuit structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The present invention and its features, configurations and advantages will become more apparent by reading the detailed description of non-limiting embodiments with reference to the following drawings. The same reference numerals indicate the same parts throughout the drawings. The drawings are not drawn to scale, but rather to illustrate the subject matter of the present invention.

[0035] Figure 1 A circuit structure diagram of a GNSS satellite receiver baseband hardware platform with a SOC architecture provided by the present invention. DETAILED DESCRIPTION

[0036] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0037] In order to fully understand the present invention, detailed steps and detailed structures will be proposed in the following description to illustrate the technical solution of the present invention. The preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0038] The present invention provides a GNSS satellite receiver baseband hardware platform circuit structure based on SOC architecture, which includes a SOC processor module, a platform hardware basic resource module and an input and output interface module. Specifically,

[0039] The SOC processor module includes a PL processor and a PS dual-core processor, and the PS dual-core processor includes a PS-A core and a PS-B core;

[0040] The platform hardware basic resource modules include Nor Flash circuit unit, communication circuit unit, extended memory circuit unit, storage circuit unit and OCXO clock circuit unit;

[0041] The input and output interface module includes an external event input signal circuit unit, a second pulse signal output circuit unit, a UART circuit unit generated by a PL processor, an SPI circuit unit, an RTC circuit unit, a TCXO unit, an IIC interface circuit unit, a CAN interface circuit unit, a USB interface circuit unit, a UART interface circuit unit generated by a PS dual-core processor, and an Ethernet circuit unit;

[0042] The SOC processor module receives the GNSS intermediate frequency signal generated by the external RF circuit, and outputs it to the PS-B core after processing by the PL processor. The PS-B core parses the original data of the GNSS signal message, performs GNSS positioning calculation and high-precision calculation, and generates the original data and positioning of the GNSS satellite, which are then transmitted to the PS-A core. The PS-A core outputs the data to the input and output interface module, which then outputs the data for data exchange and communication with peripheral devices.

[0043] In an optional embodiment of the present invention, LPDDR2 memory is used as an extended memory circuit unit, EMMC memory is used as a storage circuit unit, and the original observation data, RTK, and PPP positioning result data are output through an input and output interface module. Optionally, the LPDDR2 memory data interface is 32 bits and the address bit width is 10 bits.

[0044] In an optional embodiment of the present invention, the SOC processor module is a single SOC chip, the GNSS baseband signal is processed by a PL processor, the GNSS data is solved by a PS dual-core processor, and the PL processor and the PS dual-core processor use the AXI_ACP communication bus inside the SOC chip for data exchange.

[0045] In an optional embodiment of the present invention, the TCXO unit / OCXO clock circuit unit is used to generate local time and output it to the PL processor as a clock source for reproducing the local time of the GNSS signal.

[0046] In an optional embodiment of the present invention, an SDIO communication interface circuit is used between the storage circuit unit and the SOC processor module, and the storage content includes the application program of the receiver and the application data of the GNSS.

[0047] In an optional embodiment of the present invention, the communication circuit unit includes a WiFi / BT chip circuit, a Bluetooth antenna circuit, a WiFi antenna circuit, a communication working state switch control circuit and a digital communication interface SDIO circuit.

[0048] In an optional embodiment of the present invention, the Nor Flash circuit unit includes a Nor Flash circuit and a QSPI working mode circuit, and the Nor Flash is used to complete the BOOT program storage of the baseband platform.

[0049] In an optional embodiment of the present invention, the Ethernet circuit unit includes an Ethernet physical layer transceiver circuit and a network clock circuit. The Ethernet physical layer transceiver circuit is connected to the MIO interface of the PS-B core, and the network physical layer circuit is controlled by the PS-B core; the Ethernet circuit unit provides a data transmission interface with 10M and 100M rates to the outside.

[0050] In an optional embodiment of the present invention, the UART interface circuit unit generated by the PS dual-core processor has a short circuit / static protection circuit, which is composed of one RS232 circuit and one LVTTL circuit. The RS232 circuit includes an LVTTL-1.8V conversion standard RS232 circuit, and the LVTTL circuit includes an LVTTL-1.8V conversion LVTTL-3.3V circuit, which has short circuit protection and static protection circuits.

[0051] In an optional embodiment of the present invention, the USB interface circuit unit is composed of a USB transceiver circuit and a USB-HUBR circuit unit. The USB transceiver circuit is used to convert the universal serial bus of the PS dual-core processor into a USB OTG interface, and the USB-HUBR circuit unit is used to expand one USB into multiple USB interface circuits.

[0052] In an optional embodiment of the present invention, the CAN interface circuit unit converts the LVTTL-1.8V signal of the PS-A core into an LVTTL-3.3V signal, and then uses an RS485 level conversion circuit to convert the signal into a differential signal.

[0053] In an optional embodiment of the present invention, the IIC interface circuit unit includes an IIC interface clock, a data signal protection circuit and a drive circuit, and is a standard IIC communication interface to the outside for connecting to an external IIC interface master device.

[0054] In an optional embodiment of the present invention, the TCXO unit includes a power supply voltage stabilization circuit and a clock amplifier circuit. The power supply voltage stabilization circuit provides a 1.8V low-noise DC power supply for the TCXO unit. The clock amplifier circuit shapes and amplifies the clock signal generated by the TCXO unit, and then outputs it to the PS dual-core processor as a clock source.

[0055] In an optional embodiment of the present invention, the RTC circuit unit includes an RTC power supply circuit and an RTC clock circuit, the RTC power supply circuit includes an RTC power supply charging circuit and a discharging circuit, and the RTC clock circuit includes a data transmission circuit and a time interruption generating circuit.

[0056] In an optional embodiment of the present invention, the input signal of the SPI circuit unit is generated by a PL processor.

[0057] In an optional embodiment of the present invention, the external event input signal circuit unit includes:

[0058] An external signal input detection circuit unit is used to detect an external signal;

[0059] A signal shaping circuit unit, used for shaping and filtering the signal;

[0060] The electrostatic protection circuit unit is used to protect circuit signals.

[0061] In an optional embodiment of the present invention, the second pulse signal output circuit unit includes a pulse generating circuit unit, a signal driving circuit unit and a short-circuit protection circuit unit connected in series. The pulse generating circuit outputs an LVTTL-1.8V square wave signal. The signal driving circuit unit amplifies the signal of the pulse generating circuit, including voltage amplification and current amplification, and then transmits it to the short-circuit protection circuit unit for external output.

[0062] The present invention provides a GNSS receiver baseband hardware circuit structure with a SOC architecture. The SOC processor circuit unit is connected to a platform hardware basic resource circuit unit and a data input / output interface circuit unit. The SOC processor circuit unit receives a GNSS intermediate frequency signal generated by other radio frequency circuits. The PL part circuit in the SOC processor circuit unit performs signal correlation, capture, and tracking processing. The original data of the GNSS signal telegram is output to the PS-B core in the SOC processor circuit unit through the AXI_ACP bus inside the SOC chip. The PS-B core of the SOC processor circuit unit parses the original data of the GNSS signal telegram, performs GNSS positioning calculation and high-precision calculation, and generates original data and positioning of GNSS satellites. The PS-B core of the SOC processor circuit unit transmits the data to the PS-A core of the SOC processor circuit unit through the internal AXI_ACP bus. The PS-A core of the SOC processor circuit unit connects the data to the data input / output interface circuit unit. Finally, the data input / output interface circuit unit performs data interactive communication with other devices.

[0063] Due to the use of SOC single-chip hardware platform, a large amount of GNSS satellite data is transmitted inside the SOC chip, and ARM's AXI_ACP bus is used, the transmission of big data and data real-time performance have been greatly improved. In addition, the SOC chip has two independent PS processor cores. The two independent PS processing cores focus on PS-B and GNSS data calculation and processing, and the PS-A core is responsible for external communication transmission.

[0064] The GNSS receiver baseband hardware circuit platform based on the SOC architecture provided by the present invention enables the existing GNSS receiver to open up the bottleneck of receiving and processing the data transmission, processing and diversified interfaces of numerous GNSS satellite signals available worldwide, and adapts to the current GNSS development and the needs of users for the use of multi-mode and multi-frequency satellite signals. The circuit structure is simple and practical, the function is powerful, the use process is convenient and fast, the working performance is stable and reliable, and the application range is relatively wide.

[0065] The above describes the preferred embodiments of the present invention. It should be understood that the present invention is not limited to the above-mentioned specific embodiments, and the devices and structures that are not described in detail should be understood to be implemented in a common manner in the art; any technician familiar with the art can use the above-disclosed methods and technical contents to make many possible changes and modifications to the technical solutions of the present invention without departing from the scope of the technical solutions of the present invention, or modify them into equivalent embodiments of equivalent changes, which does not affect the essential content of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention are still within the scope of protection of the technical solutions of the present invention.

Claims

1. A GNSS satellite receiver baseband hardware platform circuit structure based on SOC architecture, characterized in that: The structure includes a SOC processor module, a platform hardware basic resource module and an input and output interface module; The SOC processor module includes a PL processor and a PS dual-core processor, and the PS dual-core processor includes a PS-A core and a PS-B core; The platform hardware basic resource modules include Nor Flash circuit unit, communication circuit unit, extended memory circuit unit, storage circuit unit and OCXO clock circuit unit; The input and output interface module includes an external event input signal circuit unit, a second pulse signal output circuit unit, a UART circuit unit generated by a PL processor, an SPI circuit unit, an RTC circuit unit, a TCXO unit, an IIC interface circuit unit, a CAN interface circuit unit, a USB interface circuit unit, a UART interface circuit unit generated by a PS dual-core processor, and an Ethernet circuit unit; The SOC processor module receives the GNSS intermediate frequency signal generated by the external RF circuit, and outputs it to the PS-B core after processing by the PL processor. The PS-B core parses the original data of the GNSS signal message, performs GNSS positioning calculation and high-precision calculation, and generates the original data and positioning of the GNSS satellite, and then transmits it to the PS-A core. The PS-A core outputs the data to the input and output interface module, which then outputs the data and communicates with the peripheral devices. The TCXO unit / OCXO clock circuit unit is used to generate a local clock and output it to the PL processor as a clock source for local time reproduction of GNSS signals; An SDIO communication interface circuit is used between the storage circuit unit and the SOC processor module, and the storage content includes the application program of the receiver and the application data of the GNSS.

2. According to the circuit structure of a GNSS satellite receiver baseband hardware platform of a SOC architecture as described in claim 1, it is characterized in that: LPDDR2 memory is used as the extended memory circuit unit, EMMC memory is used as the storage circuit unit, and the original observation data, RTK, and PPP positioning result data are output through the input and output interface module; The LPDDR2 memory data interface is 32 bits and the address bit width is 10 bits.

3. The circuit structure of a GNSS satellite receiver baseband hardware platform based on a SOC architecture according to claim 1, characterized in that: The SOC processor module is a single SOC chip. The GNSS baseband signal is processed by the PL processor, and the GNSS data is solved by the PS dual-core processor. The PL processor and the PS dual-core processor use the AXI_ACP communication bus inside the SOC chip for data exchange.

4. The circuit structure of a GNSS satellite receiver baseband hardware platform based on a SOC architecture according to claim 1, characterized in that: The communication circuit unit includes a WiFi / BT chip circuit, a Bluetooth antenna circuit, a WiFi antenna circuit, a communication working state switch control circuit and a digital communication interface SDIO circuit.

5. The circuit structure of a GNSS satellite receiver baseband hardware platform based on a SOC architecture according to claim 1, characterized in that: The Nor Flash circuit unit includes a Nor Flash circuit and a QSPI working mode circuit. Nor Flash is used to complete the BOOT program storage of the baseband platform.

6. The circuit structure of a GNSS satellite receiver baseband hardware platform based on a SOC architecture according to claim 1, characterized in that: The Ethernet circuit unit includes an Ethernet physical layer transceiver circuit and a network clock circuit. The Ethernet physical layer transceiver circuit is connected to the MIO interface of the PS-B core, and the network physical layer circuit is controlled by the PS-B core. The Ethernet circuit unit provides 10M and 100M data transmission interfaces.

7. The circuit structure of a GNSS satellite receiver baseband hardware platform based on a SOC architecture according to claim 1, characterized in that: The UART interface circuit unit generated by the PS dual-core processor has a short circuit / static protection circuit, which consists of an RS232 circuit and an LVTTL circuit. The RS232 circuit includes an LVTTL-1.8V conversion standard RS232 circuit, and the LVTTL circuit is an LVTTL-1.8V conversion LVTTL-3.3V circuit with short circuit protection and static protection circuits.

8. The circuit structure of a GNSS satellite receiver baseband hardware platform based on a SOC architecture according to claim 1, characterized in that: The USB interface circuit unit consists of a USB transceiver circuit and a USB-HUBR circuit unit. The USB transceiver circuit is used to convert the universal serial bus of the PS dual-core processor into a USB OTG interface, and the USB-HUBR circuit unit is used to expand one USB into multiple USB interface circuits.

9. The circuit structure of a GNSS satellite receiver baseband hardware platform based on a SOC architecture according to claim 1, characterized in that: The CAN interface circuit unit converts the LVTTL-1.8V signal of the PS-A core into an LVTTL-3.3V signal, and then uses the RS485 level conversion circuit to convert the signal into a differential signal.

10. The circuit structure of a GNSS satellite receiver baseband hardware platform based on a SOC architecture according to claim 1, characterized in that: The IIC interface circuit unit includes an IIC interface clock, a data signal protection circuit and a drive circuit. It is a standard IIC communication interface to the outside and is used to connect to an external IIC interface master device.

11. The circuit structure of a GNSS satellite receiver baseband hardware platform based on a SOC architecture according to claim 1, characterized in that: The TCXO unit includes a power supply voltage regulator circuit and a clock amplifier circuit. The power supply voltage regulator circuit provides a 1.8V low-noise DC power supply for the TCXO unit. The clock amplifier circuit shapes and amplifies the clock signal generated by the TCXO unit, and then outputs it to the PS dual-core processor as a clock source.

12. The circuit structure of a GNSS satellite receiver baseband hardware platform based on a SOC architecture according to claim 1, characterized in that: The RTC circuit unit includes an RTC power supply circuit and an RTC clock circuit. The RTC power supply circuit includes an RTC power supply charging circuit and a discharging circuit. The RTC clock circuit includes a data transmission circuit and a time interruption generating circuit.

13. The circuit structure of a GNSS satellite receiver baseband hardware platform based on a SOC architecture according to claim 1, characterized in that: The input signal of the SPI circuit unit is generated by the PL processor.

14. The circuit structure of a GNSS satellite receiver baseband hardware platform based on a SOC architecture according to claim 1, characterized in that: The external event input signal circuit unit includes: An external signal input detection circuit unit is used to detect an external signal; A signal shaping circuit unit, used for shaping and filtering the signal; The electrostatic protection circuit unit is used to protect circuit signals.

15. The circuit structure of a GNSS satellite receiver baseband hardware platform based on a SOC architecture according to claim 1, characterized in that: The second pulse signal output circuit unit includes a pulse generating circuit unit, a signal driving circuit unit and a short-circuit protection circuit unit connected in series. The pulse generating circuit outputs an LVTTL-1.8V square wave signal. The signal driving circuit unit amplifies the signal of the pulse generating circuit, including voltage amplification and current amplification, and then transmits it to the short-circuit protection circuit unit for external output.

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