Method and apparatus for ensuring data consistency

Abstract

Embodiments of the present disclosure relate to methods and apparatus for ensuring data consistency. The method includes writing data to a first temporary buffer located in a first processor. The method also includes sending the data to a second processor to update a copy of the data in the second processor in response to the data being written into the first temporary buffer. Further, the method includes copying the data from the first temporary buffer into a first working buffer of the first processor in response to receiving an indication that the second processor has received the data.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to the field of data storage, and in particular, to a method and apparatus for ensuring data consistency. BACKGROUND

[0002] In a common storage device, a system architecture of attaching a plurality of storage processors (SPs, also referred to as processing nodes) to a shared storage disk is often utilized to improve the computing power and input / output (IO) throughput of the storage product. In such a storage system architecture, configuration information (e.g., state information and mapping table of a redundant array of independent disks, etc.) for managing the storage disk can be cached in the memory of the plurality of SPs, and the configuration information is also stored on the shared storage disk.

[0003] When an event such as a storage disk failure or a disk array expansion occurs, the configuration information on a certain SP can be updated. The updated configuration information can then be synchronized to other SPs and eventually saved to the storage disk. During the above data updating process, any SP can be restarted or crashed due to software or hardware failure, resulting in data inconsistency problems between the memories of the plurality of SPs or between the memory and the storage disk. The data inconsistency problem can have a serious impact on users, such as data loss or data unavailability, etc. SUMMARY

[0004] Embodiments of the present disclosure provide a method and apparatus for ensuring data consistency.

[0005] In a first aspect of the present disclosure, a method for ensuring data consistency is provided. The method includes writing data to a first temporary buffer located in a first processor. The method also includes sending the data to a second processor to update a copy of the data in the second processor in response to the data being written to the first temporary buffer. In addition, the method further includes copying the data from the first temporary buffer to a first working buffer of the first processor in response to receiving an indication that the second processor has received the data.

[0006] In a second aspect of the present disclosure, a method for ensuring data consistency is provided. The method includes writing data to a second temporary buffer located in a second processor in response to receiving the data to be updated from a first processor. The method also includes sending an indication that the second processor has received the data to the first processor in response to the data being written to the second temporary buffer. In addition, the method further includes copying the data from the second temporary buffer to a second working buffer of the second processor.

[0007] In a third aspect of this disclosure, an apparatus for ensuring data consistency is provided. The apparatus includes at least one processing unit and at least one memory. The at least one memory is coupled to the at least one processing unit and stores instructions for execution by the at least one processing unit. When executed by the at least one processing unit, the instructions cause the apparatus to: write data to a first temporary buffer located in a first processor; in response to the data being written to the first temporary buffer, send the data to a second processor to update a copy of the data in the second processor; and in response to receiving an indication that the second processor has received the data, copy the data from the first temporary buffer to a first working buffer of the first processor.

[0008] In a fourth aspect of this disclosure, an apparatus for ensuring data consistency is provided. The apparatus includes at least one processing unit and at least one memory. The at least one memory is coupled to the at least one processing unit and stores instructions for execution by the at least one processing unit. When executed by the at least one processing unit, the instructions cause the apparatus to: write data to a first temporary buffer located in a first processor; write the data to a second temporary buffer located in a second processor in response to receiving data to be updated from the first processor; send an indication to the first processor that the second processor has received the data in response to the data being written to the second temporary buffer; and copy the data from the second temporary buffer to a second working buffer of the second processor.

[0009] In a fifth aspect of this disclosure, a computer program product is provided. This computer program product is tangibly stored on a non-transitory computer-readable medium and includes machine-executable instructions. When executed, the machine-executable instructions cause a machine to perform any step of the method described in the first aspect of this disclosure.

[0010] In a sixth aspect of this disclosure, a computer program product is provided. This computer program product is tangibly stored on a non-transitory computer-readable medium and includes machine-executable instructions. When executed, the machine-executable instructions cause a machine to perform any step of the method described in the second aspect of this disclosure.

[0011] The summary section is provided to present the chosen concepts in a simplified form, which will be further described in the detailed description below. The summary section is not intended to identify key or principal features of this disclosure, nor is it intended to limit the scope of this disclosure. Attached Figure Description

[0012] The above and other objects, features and advantages of this disclosure will become more apparent from the accompanying drawings, in which like reference numerals generally denote like parts.

[0013] Figure 1 An architectural diagram of an example storage system 100 with two SPs sharing a storage disk is shown;

[0014] Figure 2 An architectural diagram of a storage system 200 is shown, in accordance with an embodiment of the present disclosure;

[0015] Figure 3 A flow diagram of a method 300 for maintaining data consistency is illustrated, in accordance with an embodiment of the present disclosure;

[0016] Figure 4 A block diagram of an apparatus 400 for maintaining data consistency is illustrated, in accordance with an embodiment of the present disclosure;

[0017] Figure 5 A block diagram of an apparatus 500 for maintaining data consistency is illustrated, in accordance with an embodiment of the present disclosure; and

[0018] Figure 6 A block diagram of a computer system 600 suitable for implementing example embodiments of the present disclosure is illustrated.

[0019] In the various drawings, like or corresponding elements are denoted by like or corresponding reference numerals. DETAILED DESCRIPTION

[0020] Preferred embodiments of the present disclosure will be described herein below with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it is understood that the present disclosure can be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the present disclosure to those skilled in the art.

[0021] The term "comprising" and variations thereof as used herein are intended to mean "including but not limited to." The term "or" as used herein is intended to mean "and / or." The term "based on" means "based, at least in part, on." The term "one example embodiment" and "an embodiment" means "at least one example embodiment." The term "another embodiment" means "at least one additional embodiment." The terms "first," "second," and the like can refer to different or identical objects. Also, the terms "exemplary" and "example" mean "an example of" and "one example," respectively. Other explicit or implicit definitions can also be included below.

[0022] As described above, in a storage system with multiple SPs sharing a storage disk, if data on a certain SP is updated, the updated data can be synchronized to other SPs and eventually saved to the storage disk. During this process, any SP can be restarted or crashed due to software or hardware failure, resulting in data inconsistency issues between the memories of multiple SPs or between the memory and the storage disk.

[0023] To at least partially address one or more of the above-referenced issues and other potential issues, example embodiments of the present disclosure propose a scheme for guaranteeing data consistency. The scheme first updates data to temporary buffers in the SPs, and copies the data from the temporary buffers of the SPs to working buffers after the data is updated to the temporary buffers of all SPs, thereby guaranteeing data consistency between the memories of multiple SPs. In addition, during flushing of the data from the memories of the SPs to the storage disk, the scheme guarantees data consistency between the memory and the storage disk by applying a temporary area on the storage disk.

[0024] Figure 1 An architectural diagram of an example storage system 100 with two SPs sharing a storage disk is shown. As shown in Figure 1 In the storage system 100, there are two SPs, i.e., SP 101 and SP 102, sharing a storage disk 103. For the purpose of example, only two SPs are shown in Figure 1 However, it should be understood that embodiments of the present disclosure are also applicable to storage systems with multiple SPs. In addition, for the convenience of description, a disk or a disk array will be taken as an example of the storage disk 103 hereinafter. However, this is merely exemplary, and any currently known or future developed storage medium based on other mechanisms can serve as the storage disk 103.

[0025] As shown, the two SPs can have their respective memories, i.e., memories 111 and 112, respectively. The two SPs can interact (e.g., transmit heartbeat signals) through a command interface (CMI) 104. During booting of the SPs, the two SPs can determine their respective roles through handshaking. For example, the first SP to start can act as an active SP (also referred to as a “first SP”), while the other SP acts as a passive SP (also referred to as a “second SP”).

[0026] Generally, the IO requests of the system can be served by the active SP. When the active SP fails, the IO requests can be failed over to the passive SP, and the IO requests are served by the passive SP. For the convenience of description, SP 101 will be taken as the active SP, i.e., the first SP, and SP 102 will be taken as the passive SP, i.e., the second SP, hereinafter.

[0027] The storage disk 103 can be a single disk or a disk array (e.g., Redundant Array of Independent Disks (RAID)) including multiple disks. For example, when the storage disk 103 is a RAID, each disk therein can be divided into multiple disk extents, and a RAID group can organize several disk extents into a RAID stripe. Configuration information for managing the storage disk 103 (e.g., state information of the disk extents and mapping relationship between the RAID stripes and the disk extents) can be cached on the memories (e.g., the memories 111 and 112) of the SPs (e.g., the SP 101 and the SP 102) and can be saved in the storage disk 103.

[0028] When a disk failure or a disk extent expansion occurs, the configuration information for managing the storage disk 103 can need to be updated. That is, the copies of the configuration information in the memory 111, the memory 112, and the storage disk 103 need to be updated respectively. In the process of updating the configuration information, the SP 101 or the SP 102 can be restarted or crashed due to software or hardware failure, resulting in data inconsistency among the SP 101, the SP 102, and the storage disk 103.

[0029] Embodiments of the present disclosure propose to use temporary buffers in the memories of the SPs and temporary extents on the storage disk to solve the above-mentioned data inconsistency problem.

[0030] Figure 2 FIG. 1 illustrates an architecture diagram of a storage system 100 according to an embodiment of the present disclosure. As shown in FIG. 1, the storage system 100 includes an SP 101 and an SP 102, both of which share a storage disk 103 and interact through a CMI 104. Figure 1 The storage system 200 also includes the SP 101 and the SP 102, both of which share the storage disk 103 and interact through the CMI 104, as the storage system 100 shown.

[0031] The SP 101 and the SP 102 respectively have their own memories, i.e., the memory 111 and the memory 112. As the storage system 100 shown, the memory 111 includes a working buffer 201 and a temporary buffer 211; similarly, the memory 112 includes a working buffer 202 and a temporary buffer 212. Figure 1 Unlike the storage system 100 shown, the memory 111 can include the working buffer 201 and the temporary buffer 211; similarly, the memory 112 can include the working buffer 202 and the temporary buffer 212. Among them, the working buffers 201 and 202 are visible to users and are finally used to cache the configuration information of the storage disk 103. While the temporary buffers (also referred to as “shadow” buffers) 211 and 212 are invisible to users and are used to ensure data consistency between the memory 111 and the memory 112. In some embodiments, the temporary buffers 211 and / or 212 can be pre-allocated. In other embodiments, the temporary buffers 211 and / or 212 can be temporarily allocated for the data to be updated and can be released after the data is copied to the working buffer 201 and / or 202.

[0032] In addition, storage disk 103 may include a working area 203 and a temporary area (also known as a journal area) 204. The working area 203 is used for the final configuration information of storage disk 103, while the temporary area 204 is used to ensure data consistency between storage devices 111 and 112 and storage disk 103.

[0033] Figure 3 A flowchart illustrating a method 300 for ensuring data consistency according to an embodiment of the present disclosure is shown. The following is in conjunction with... Figure 2 This describes the actions involved in method 300. For ease of discussion, the description of method 300 involves two SPs, namely SP 101 and SP 102. Figure 3 For example, the actions on the left are performed by SP 101, while the actions on the right are performed by SP 102. In the following description, working buffer 201 and the first working buffer can be used interchangeably; working buffer 202 and the second working buffer can be used interchangeably; temporary buffer 211 and the first temporary buffer can be used interchangeably; and temporary buffer 212 and the second temporary buffer can be used interchangeably. It should be understood that method 300 may also include additional actions not shown and / or the actions shown may be omitted, and the scope of this disclosure is not limited in this respect.

[0034] In block 301, data is written to the first temporary buffer 211 in SP 101. For example, this data could be configuration information for the storage disk 103 to be updated, such as RAID status information and mapping tables. Alternatively, this data could be any other data that has copies in SP 101, SP 102, and storage disk 103. In block 302, when this data is written to temporary buffer 211, SP 101 can send the data to SP 102 via CMI 104 to update the copy of the data in SP 102.

[0035] Accordingly, in block 311, when SP 102 receives data to be updated from SP 101, SP 102 can write the data to the second temporary buffer 212. Then, in block 312, an indication that SP 102 has received the data is sent to SP 101.

[0036] At block 303, upon receiving the indication, SP 101 can copy the data from the temporary buffer 211 to the working buffer 201. Additionally or alternatively, in some embodiments, if the temporary buffer 211 is temporarily allocated for the data to be updated, the temporary buffer 211 can be released after the data is copied to the working buffer 201. On the other side, at block 313, SP 102 can also copy the data from the temporary buffer 212 to the working buffer 202. Additionally or alternatively, in some embodiments, if the temporary buffer 212 is temporarily allocated for the data to be updated, the temporary buffer 212 can be released after the data is copied to the working buffer 202.

[0037] That is, according to embodiments of the present disclosure, neither SP 101 nor SP 102 changes the data in its respective working buffer until both SP 101 and 102 update the data to their respective temporary buffers. In this way, if one or both of SP 101 and 102 fails or crashes, the data in SP 101 and 102 can remain consistent.

[0038] After the data is synchronized to SP 102 and copied from the respective temporary buffers to the working buffers on SP 101 and 102, saving the data to the storage disk 103 can begin. As shown in FIG. 3, at block 304, SP 101 writes the data to a temporary area 204 on the storage disk 103 that is shared by SP 101 and SP 102. Then, at block 305, a flag (e.g., a log header) associated with the temporary area 204 is set to indicate that the data in the temporary area 204 is valid. Additionally or alternatively, at block 306, SP 101 can send a first message containing the flag to SP 102. Figure 3

[0039] Accordingly, at block 314, upon receiving the first message from SP 101 indicating that the data is updated to the temporary area 204 on the storage disk 103, SP 102 can obtain the flag from the first message indicating that the data in the temporary area 204 is valid. Then, at block 315, a first acknowledgement is sent to SP 101 that SP 102 has received the first message.

[0040] Next, at block 307, SP 101 can write the data to a working area 203 on the storage disk 103. Additionally or alternatively, upon receiving the first acknowledgement, SP 101 can write the data to the working area 203. Then, at block 308, SP 101 can set the flag (e.g., a log header) associated with the temporary area 204 to indicate that the data in the temporary area 204 is invalid.​

[0041] In some embodiments, additionally or alternatively, at block 309, SP 101 can also send a second message containing the flag to SP 102. Accordingly, at block 316, when SP 102 receives the second message from SP 101 indicating that the data is updated to the working area 203 on the storage disk 103, SP 102 can obtain the flag indicating that the data in the temporary area 204 is invalid from the second message. Then, at block 317, SP 103 can send a second acknowledgement to SP 101 that SP 102 has received the second message.

[0042] That is, if the system fails before the log header is marked as invalid, the system will check the log header in the next startup process and replay the data of the log area into the working area on the storage disk 103, because the log header indicates that there is valid data in the log area to be flushed to the storage disk. In this way, the data on the storage disk 103 and the SPs (e.g., SPs 101 and 102) can be kept consistent.

[0043] During the execution of the method 300, the system can fail, causing SP 101 and / or SP 102 to not function properly. Embodiments of the present disclosure can ensure data consistency between SP 101, SP 102, and the storage disk 103 in various failure situations.

[0044] In some embodiments, at block 301 or 302, if SP 101 fails, the data update request can be failed back to the requester; and if SP 102 fails, SP 102 can determine that SP 101 fails by detecting the stop of the heartbeat signal transmitted via the CMI 104, and then continue the process of data update without SP synchronization.

[0045] In some embodiments, at blocks 311-313 or 303-305, if SP 101 fails, the update request can be failed over to SP 102. Since SP 102 has already obtained the data to be updated, SP 102 can continue the process of data update without SP synchronization. At blocks 311-313 or 303-305, if SP 102 fails, SP 101 can continue the process of data update without SP synchronization.

[0046] In some embodiments, if SP 101 fails at block 314-315 or 307-309, the update request can be failed over to SP 102, and SP 102 can act as the active SP to continue the data update process from block 307 without SP synchronization, since SP 102 has obtained the log head and knows that the data in log region 204 is valid. If SP 102 fails at block 314-315 or 307-308, SP 101 can continue the data update process without SP synchronization.

[0047] In some embodiments, if SP 101 fails at block 316 or 317, the update request can be failed over to SP 102, and SP 102 can act as the active SP to continue the data update process from block 316 without SP synchronization. SP 102 can simply clear the corresponding data structure and then report to the requester that the update is complete. If SP 102 fails at block 316 or 317, SP 101 can continue the data update process without SP synchronization.

[0048] In some embodiments, if both SP 101 and SP 102 fail at block 305 or before block 305, although part or all of the data in the memory on the SPs have been updated, the data on storage disk 103 is not updated. In this case, SP 101 and SP 102 can be restarted to reload the data from storage disk 103 during boot up. Thus, after the restart, the data on SP 101, SP 102 and storage disk 103 will still be the data before the update. Since the log head is invalid, the process associated with the log region will not occur during the restart.

[0049] In some embodiments, if both SP 101 and SP 102 fail after block 305 and before (including at) block 308, SP 101 and SP 102 can be restarted. During the restart, the data in the log region can be replayed or flushed into working region 203 on storage disk 103 by detecting that the log head is valid. After the log replay, the data on storage disk 103 will be the updated data, and by reloading the data on storage disk 103 into SP 101 and 102, the data on SP 101, SP 102 and storage disk 103 will be consistent, i.e., the updated data.

[0050] In some embodiments, if both SP 101 and SP 102 fail simultaneously after box 308, SP 101 and SP 102 can be restarted. During the restart, an invalid log header indicates that the data on storage disk 103 has been updated. By reloading the data on storage disk 103 into SP 101 and 102, the data on SP 101, SP 102, and storage disk 103 will be consistent, i.e., updated data.

[0051] As described above, embodiments of this disclosure ensure data consistency between the memories of multiple SPs by first updating the data to a temporary buffer in the SP and then copying the data from the temporary buffers of the SPs to the working buffers after the data has been updated to the temporary buffers of all SPs. Furthermore, during the flushing of data from the SP's memory to the storage disk, embodiments of this disclosure ensure data consistency between the memory and the storage disk by applying a log area on the storage disk.

[0052] Figure 4 A block diagram of an apparatus 400 for maintaining data consistency according to an embodiment of the present disclosure is illustrated. For example, such as Figure 2 SP 101 shown can be implemented by device 400. For example... Figure 4 As shown, device 400 may include access control module 410, configured to write data to temporary buffer 211 located in SP 101. Device 400 may also include transmission module 420, configured to send the data to SP 102 to update the copy of the data in SP 102 in response to the data being written to temporary buffer 211. In addition, access control module 410 is also configured to copy the data from temporary buffer 211 to working buffer 201 of SP 101 in response to receiving an indication that SP 102 has received the data.

[0053] Figure 5 A block diagram of an apparatus 500 for maintaining data consistency according to an embodiment of the present disclosure is illustrated. For example, such as Figure 2 SP 102 shown can be implemented by device 500. For example... Figure 5 As shown, device 500 may include access control module 510, configured to write data to temporary buffer 212 located in SP 102 in response to receiving data to be updated from SP 101. Device 500 may also include transmission module 520, configured to send an indication to SP 101 that SP 102 has received the data in response to the data being written to temporary buffer 212. In addition, access control module 510 is also configured to copy the data from temporary buffer 212 to working buffer 202 of SP 102.

[0054] For the sake of clarity, in the following description Figure 4 and / or Figure 5 Certain optional modules of the apparatus 400 and / or 500 are not shown in Figures 2-3 The various features described above in relation to the apparatus 300 are equally applicable to the apparatus 400 and / or 500. Moreover, the various modules of the apparatus 400 and / or 500 can be hardware modules or software modules. For example, in certain embodiments, the apparatus 400 and / or 500 can be implemented in part or in whole with software and / or firmware, e.g., as a computer program product embodied on a computer readable medium. Alternatively or additionally, the apparatus 400 and / or 500 can be implemented in part or in whole based on hardware, e.g., as an integrated circuit (IC), an application specific integrated circuit (ASIC), a system on a chip (SOC), a field programmable gate array (FPGA), etc. The scope of the present disclosure is not limited in this regard.

[0055] Figure 6 A schematic block diagram of an example device 600 that can be used to implement embodiments of the present disclosure is shown. For example, the SP 101 and / or the SP 102 as shown in Figure 2 may be implemented by the device 600. As shown, the device 600 includes a central processing unit (CPU) 601 that can perform various appropriate actions and processes according to computer program instructions stored in a read-only memory (ROM) 602 or loaded into a random access memory (RAM) 603 from a storage unit 608. Various programs and data required for operation of the device 600 can also be stored in the RAM 603. The CPU 601, the ROM 602, and the RAM 603 are connected to each other via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0056] A plurality of components in the device 600 are connected to the I / O interface 605, including: an input unit 606, e.g., a keyboard, a mouse, etc.; an output unit 607, e.g., various types of displays, speakers, etc.; the storage unit 608, e.g., magnetic disks, optical disks, etc.; and a communication unit 609, e.g., a network card, a modem, a wireless communication transceiver, etc. The communication unit 609 allows the device 600 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0057] The various processes and processes described above, such as the method 300, can be performed by the processing unit 601. For example, in some embodiments, the method 300 can be implemented as a computer software program tangibly embodied in a machine readable medium, such as the storage unit 608. In some embodiments, portions or all of the computer program can be loaded and / or installed onto the device 600 via the ROM 602 and / or the communication unit 609. When the computer program is loaded onto the RAM 603 and executed by the CPU 601, one or more acts of the method 300 described above can be performed.

[0058] The present disclosure can be a method, apparatus, system, and / or computer program product. Computer program products can include computer readable storage media having computer readable program instructions embodied therewith.

[0059] The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch cards or punched tape, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

[0060] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0061] Computer readable program instructions for carrying out operations of the present disclosure can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate array (FPGA), or programmable logic array (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

[0062] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0063] These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can include random access memory (RAM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), flash memory or other data storage device. When the computer readable program instructions are loaded into the computer and other programmable data processing apparatus, a series of operational steps are implemented that provide processes such that the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0064] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0065] The flow diagrams and the block diagrams in the drawings are presented to illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flow diagrams and the block diagrams can represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logic functions. In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flow diagrams, and combinations thereof, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and

[0066] Embodiments of the present disclosure have been described above, and the description is intended to be illustrative of the embodiments and not restrictive. Many modifications and variations of the described embodiments are possible and are within the scope of the disclosure. The selection of the terms to be used in the description is not intended to limit the scope of the embodiments described herein, but rather to best describe the principles of the embodiments in the context of the specific application or technical improvement offered by the embodiments.

Claims

1. A method for guaranteeing data consistency, comprising: writing data to a first temporary buffer located in a first processor; in response to the data being written to the first temporary buffer, sending the data to a second processor to update a copy of the data in the second processor; and in response to receiving an indication that the second processor has received the data, copying the data from the first temporary buffer to a first working buffer in the first processor, and wherein the method further comprises: writing the data to a temporary area on a storage disk shared by the first processor and the second processor; in response to the data being written to the temporary area, setting a flag associated with the temporary area to indicate that the data in the temporary area is valid; writing the data to a working area on the storage disk; and in response to the data being written to the working area, setting the flag to indicate that the data in the temporary area is invalid.

2. The method of claim 1, further comprising: in response to the data being copied to the first working buffer, releasing the first temporary buffer.

3. The method of claim 1, further comprising: in response to the flag being set to indicate that the data in the temporary area is valid, sending a first message containing the flag to the second processor.

4. The method of claim 3, wherein writing the data to a working area on the storage disk comprises: in response to receiving an acknowledgement from the second processor that the first message was received, writing the data to the working area.

5. The method of claim 1, further comprising: in response to the flag being set to indicate that the data in the temporary area is invalid, sending a second message containing the flag to the second processor.

6. A method for guaranteeing data consistency, comprising: in response to receiving data to be updated from a first processor, writing the data to a second temporary buffer located in a second processor; in response to the data being written to the second temporary buffer, sending an indication to the first processor that the second processor has received the data; and copying the data from the second temporary buffer to a second working buffer in the second processor, and wherein the method further comprises: in response to receiving a first message from the first processor indicating that the data was updated to a temporary area on a storage disk shared by the first processor and the second processor, obtaining a flag from the first message indicating that the data in the temporary area is valid; and sending a first acknowledgement to the first processor that the second processor has received the first message.

7. The method of claim 6, further comprising: in response to the data being copied to the second working buffer, releasing the second temporary buffer.

8. The method of claim 6, further comprising: ​ ​ in response to receiving a second message from the first processor indicating that the data was updated to a working region on the storage disk, obtaining the flag from the second message indicating that the data in the temporary region is invalid; and sending a second acknowledgement to the first processor that the second processor has received the second message.

9. The method of claim 6, further comprising: in response to determining that the first processor is unresponsive: writing the data to a temporary region on a storage disk shared by the first processor and the second processor; in response to the data being written to the temporary region, setting a flag associated with the temporary region to indicate that the data in the temporary region is valid; writing the data to a working region on the storage disk; and in response to the data being written to the working region, setting the flag to indicate that the data in the temporary region is invalid.

10. An apparatus for ensuring data consistency, comprising: at least one processing unit; at least one memory coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, the instructions, when executed by the at least one processing unit, cause the apparatus to: write data to a first temporary buffer in a first processor; in response to the data being written to the first temporary buffer, send the data to a second processor to update a copy of the data in the second processor; and in response to receiving an indication that the second processor has received the data, copy the data from the first temporary buffer to a first working buffer of the first processor, wherein the instructions, when executed by the at least one processing unit, further cause the apparatus to: write the data to a temporary region on a storage disk shared by the first processor and the second processor; in response to the data being written to the temporary region, set a flag associated with the temporary region to indicate that the data in the temporary region is valid; write the data to a working region on the storage disk; and in response to the data being written to the working region, set the flag to indicate that the data in the temporary region is invalid.

11. The apparatus of claim 10, wherein the instructions, when executed by the at least one processing unit, further cause the apparatus to: in response to the data being copied to the first working buffer, release the first temporary buffer.

12. The apparatus of claim 10, wherein the instructions, when executed by the at least one processing unit, further cause the apparatus to: in response to the flag being set to indicate that the data in the temporary region is valid, send a first message containing the flag to the second processor.

13. The apparatus of claim 12, wherein writing the data to a working region on the storage disk comprises: in response to receiving an acknowledgement from the second processor that the first message was received, writing the data to the working region.

14. The apparatus of claim 10, wherein the instructions, when executed by the at least one processing unit, further cause the apparatus to: in response to the flag being set to indicate that the data in the temporary region is invalid, send a second message containing the flag to the second processor.

15. An apparatus for ensuring data coherency, comprising: at least one processing unit; at least one memory coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, the instructions, when executed by the at least one processing unit, cause the apparatus to: in response to receiving data to be updated from a first processor, write the data to a second temporary buffer located in a second processor; in response to the data being written to the second temporary buffer, send an indication to the first processor that the data has been received by the second processor; and copy the data from the second temporary buffer into a second working buffer of the second processor, wherein the instructions, when executed by the at least one processing unit, further cause the apparatus to: in response to receiving a first message from the first processor indicating that the data is updated to a temporary region on a storage disk shared by the first processor and the second processor, obtain a flag from the first message indicating that the data in the temporary region is valid; and send a first acknowledgement to the first processor that the first message has been received by the second processor.

16. The apparatus of claim 15, wherein the instructions, when executed by the at least one processing unit, further cause the apparatus to: in response to the data being copied into the second working buffer, release the second temporary buffer.

17. The apparatus of claim 15, wherein the instructions, when executed by the at least one processing unit, further cause the apparatus to: in response to receiving a second message from the first processor indicating that the data is updated to a working region on the storage disk, obtain the flag from the second message indicating that the data in the temporary region is invalid; and send a second acknowledgement to the first processor that the second message has been received by the second processor.

18. The apparatus of claim 15, wherein the instructions, when executed by the at least one processing unit, further cause the apparatus to: in response to determining that the first processor is unresponsive: write the data to a temporary region on a storage disk shared by the first processor and the second processor; in response to the data being written to the temporary region, set a flag associated with the temporary region to indicate that the data in the temporary region is valid; write the data to a working region on the storage disk; and in response to the data being written to the working region, set the flag to indicate that the data in the temporary region is invalid.

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