Method and apparatus for facilitating fast booting using high-speed and low-speed non-volatile memories

Abstract

A method for booting a data processing system (DPS) involves, during a boot process of the DPS, using a preliminary boot code module from a slow non-volatile memory (NVM) in the DPS to load a master boot code module from a high-speed NVM in the DPS into a volatile random access memory (RAM) in the DPS, wherein the high-speed NVM supports a read speed that is faster than a maximum read speed of the slow NVM. The method further involves, during the boot process, after loading the master boot code module from the high-speed NVM into the RAM, using the master boot code module to boot the DPS to an operating system (OS). The method may also involve using the preliminary boot code module to automatically determine whether the master boot code module from the high-speed NVM has good integrity. Other embodiments are described and claimed.

Description

Technical Field

[0001] The present disclosure generally relates to techniques for booting a data processing system. In particular, the present disclosure relates to methods and apparatus for facilitating fast booting using high-speed non-volatile memory (NVM) and low-speed NVM. Background Art

[0002] A data processing system (DPS) may include hardware components and software components. The software components may include one or more applications, an operating system (OS), and firmware. The application may include control logic for performing work that is valuable to the user of the DPS. In such a DPS, the application runs on top of the OS, which runs at a lower logical level than the application (i.e., closer to the hardware) to provide an underlying environment or abstraction layer that makes it easier to create and execute applications. The firmware runs at an even lower logical level to provide an underlying environment or abstraction layer that makes it easier to create and execute the OS. For example, the firmware may establish a basic input / output system (BIOS), and the OS may use the BIOS to communicate with different hardware components within the DPS.

[0003] Typically, the OS and applications execute out of volatile random access memory (RAM). Some or all of the firmware may also execute out of RAM. However, because RAM is volatile, whenever the DPS is shut down, the environment for performing useful work essentially disappears. Therefore, whenever the DPS is started, the DPS must recreate the environment before useful work can be performed. For purposes of this disclosure, the operations used to prepare the DPS to execute the OS may be referred to as the "boot process." Similarly, the time that elapses during the boot process may be referred to as the "boot time." BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a block diagram of an example embodiment of a data processing system that uses a high-speed NVM and a relatively large, low-speed NVM to facilitate fast booting.

[0005] Figure 2 is a block diagram of an example embodiment of a data processing system that uses a high-speed NVM and a relatively small, low-speed NVM to facilitate fast booting.

[0006] Figure 3 A flow chart of an example embodiment of a process for facilitating fast boot using a high-speed NVM and a relatively large, low-speed NVM is presented.

[0007] Figure 4A and Figure 4B A flow chart of an example embodiment of a process for facilitating fast booting using a high-speed NVM and a relatively small, low-speed NVM is presented. DETAILED DESCRIPTION

[0008] As indicated above, when the DPS is started or reset, the DPS may need to perform a boot process before the DPS can be used for useful work. The control logic or firmware that performs or controls the boot process may be referred to as "system firmware," "system boot code," "platform boot code," or simply "boot code." The DPS may store the boot code in the NVM. As part of the process of preparing the computer to execute the OS, the boot code may discover and initialize hardware resources (e.g., RAM) in the computer. Before the boot code initializes the RAM, the processor in the DPS may execute the boot code using techniques such as execute-in-place (XIP) and cache-as-RAM as RAM. After the RAM is initialized, the processor may copy some or all of the boot code from the NVM to the RAM. The processor may then execute the boot code from the RAM to complete the boot process.

[0009] Part of this boot process may include discovering peripheral devices and loading peripheral firmware from these peripheral devices into RAM. For example, a peripheral device may store its peripheral firmware in a read-only memory (ROM). Therefore, for the purposes of this disclosure, peripheral firmware may generally be referred to as "option ROM firmware." Therefore, system firmware may use option ROM firmware. For the purposes of this disclosure, terms such as "system firmware," "system boot code," "platform boot code," and "boot code" should be understood to mean system firmware, and not include option ROM firmware or other types of peripheral firmware.

[0010] The time required to perform the boot process can be quite long. Therefore, to avoid delays caused by the boot process, a user may decide not to shut down his or her DPS in the first place. The energy consumed by the DPS when the DPS is powered on but not being used can be considered wasted energy. Fortunately, the DPS can be configured to enter a low power state in response to a predetermined period of inactivity or in response to a manual selection of a low power state. However, the low power state still consumes more energy than the off state. In addition, some energy consumption practices may violate energy ordinances promulgated by organizations such as the California Energy Commission.

[0011] Additionally, some data processing systems are used for purposes that cannot tolerate lengthy delays between power-up and useful work. For example, a DPS used in a motor vehicle or transportation industry may be required to transfer control to its OS in less than 700 milliseconds (ms).

[0012] In a typical DPS, the NVM used for boot code uses NOR flash memory to store data and uses a serial peripheral interface (SPI) for input and output. Therefore, the NVM is relatively slow. A significant portion of the boot time can therefore be attributed to reading the boot code from the NVM.

[0013] The present disclosure describes a DPS having at least two different types of NVMs: including a low-speed NVM and a high-speed NVM. In addition, the present disclosure describes a boot code that is divided into two or more different parts or modules, and at least one of these parts is stored in a high-speed NVM. Typically, when the DPS boots, the DPS does not read all of the boot code from the low-speed NVM, but reads at least some of the boot code from the high-speed NVM. In addition, before executing the boot code, the DPS may take steps to confirm the boot code from the high-speed NVM. Despite the additional operations for confirmation and for other actions associated with the use of more than one NVM, the overall boot time can be significantly reduced relative to a conventional DPS in which all boot codes are in a low-speed NVM. In addition, as described in more detail below, the hardware cost of the DPS according to the present disclosure can be reduced relative to a conventional DPS having a low-speed NVM that is large enough to retain all boot codes.

[0014] Figure 1 is a block diagram of an example embodiment of a DPS 20 that uses a high-speed NVM 32 and a low-speed NVM 36 to facilitate fast booting. Figure 1 In the embodiment, relative to Figure 2 In the embodiment of the low-speed NVM, the low-speed NVM 36 is larger.

[0015] As shown, the DPS 20 also includes at least one processor 22 that communicates with the following other hardware components: for example, a high-speed NVM 32, a low-speed NVM 36, a RAM 30, a network interface controller (NIC) 58, and a trusted platform module (TPM) 48. The processor 22 may include one or more levels of cache 24. The processor 22 may also be referred to as a "central processing unit" (CPU), and some embodiments may include multiple CPUs. The processor 22 may also be communicatively coupled to one or more non-volatile mass storage devices, such as a solid-state drive (SSD) or a hard disk drive (HDD) 38.

[0016] As indicated below, some types of NVMs are faster than other types of NVMs. For the purposes of this disclosure, the term "read speed" is used to describe how much data can be read from an NVM in a certain amount of time. Thus, the read speed may be expressed, for example, in units of megabytes per second (MB / s). The read speed may also be referred to as the "average read speed," "maximum read speed," or simply "speed." Additionally, an NVM that is capable of delivering a particular read speed may be referred to as "supporting" that speed. Thus, in a given embodiment, a high-speed NVM supports a higher read speed than a low-speed NVM. In other words, a high-speed NVM supports a read speed that is faster than the maximum supported read speed of the low-speed NVM. Or, more simply, a high-speed NVM has a higher read speed. For the purposes of this disclosure, the "maximum supported read speed" or "maximum read speed" of a NVM is the fastest average read speed that the NVM is capable of delivering.

[0017] exist Figure 1 and Figure 2 In an embodiment of the present invention, the low-speed NVM can use NOR flash memory to store data, and each low-speed NVM can use an interface with a bus width of no more than four lines or lines, wherein only two of these lines are used to input and output data. For example, the low-speed NVM can use SPI, which has only two data lines: a master output, slave input (MOSI) line and a master input, slave output (MISO) line. Using SPI operating at 75 megahertz (MHz), the low-speed NVM can have a read speed of about 9.38MB / s. However, other embodiments can use low-speed NVMs with different speeds. For example, one embodiment can use a low-speed NVM with a read speed of about 35MB / s, which uses an SPI operating at 280MHz. Other embodiments can use a low-speed NVM with a speed ranging from about 9MB / s to about 40MB / s.

[0018] High-speed NVM 32 can use horizontal and vertically arranged NAND memory cells to store data. In other words, high-speed NVM 32 can use one or more three-dimensional (3D) sets (or arrays) of memory cells to store data. In addition, high-speed NVM 32 can use fast NVM (NVMe) interface, serial AT attachment (ATA) interface, or any other suitable bus interface to input and output data. Serial ATA interface can also be referred to as "SATA interface". Therefore, high-speed NVM 32 may include an input / output (I / O) interface with multiple transmit lines and multiple receive lines.

[0019] exist Figure 1In the embodiment of the present invention, the high-speed NVM 32 has a read speed of about 1600 MB / s. However, other embodiments may use high-speed NVMs with different speeds. For example, one embodiment may use a high-speed NVM with a read speed of about 1000 MB / s, and other embodiments may use high-speed NVMs with speeds exceeding 1000 MB / s. Some embodiments may use a high-speed NVM such as that provided by Intel Corporation under the name “ Optane TM "Optine Memory" is a high-speed NVM such as those described by the name or trademark of "Optine Memory". Additional details about this memory technology can be found on the Internet at the following Global Resource Locator (URL): www.intel.com--content--www--us--en--architecture-and-technology--optane-memory.html. (To prevent the URLs from becoming clickable hyperlinks, the present disclosure replaces each forward slash character in each URL with the string "--"). In addition, as indicated at www.intel.com--content--www--us--en--architecture-and-technology--intel--optane-technology.html, the fabrication of the high-speed NVM may include "cutting a sub-microscopic layer of material into columns, each column containing a memory cell and a selector, and then connecting them with a novel cross-point structure of vertical lines." The memory technology used for the high-speed NVM may also be referred to using the name or trademark of "3D Crosspoint" or "3D XPoint". More details may be obtained from en.wikipedia.org --wiki--3D_XPoint and from other websites, such as www.businesswire.com--news--home--20150728005534--en--Intel-Micron-Product-Breakthrough-Memory-Technology. Thus, the high-speed NVM 32 may have an effective read speed that is approximately the same as a double data rate fourth generation synchronous dynamic RAM (DDR4 SDRAM) while having non-volatile characteristics. However, other embodiments may use a high-speed NVM referred to by other names or trademarks. Nonetheless, the high-speed NVM in each embodiment may use a different interface than the low-speed NVM. In addition, the high-speed NVM is faster than the low-speed NVM. For example, as indicated below, in some embodiments, the high-speed NVM may be more than 20 times faster than the low-speed NVM. In other embodiments, the high-speed NVM may be more than 150 times faster than the low-speed NVM.

[0020] The HDD 38 may use one or more disks to store data, and the HDD 38 may use an interface with no more than four data lines or wires. For example, the HDD 38 may use a SATA interface with two transmit lines and two receive lines. The OS 80 and one or more applications may be stored on the HDD 38. Similarly, if an SSD is included, the SSD may use the same type of interface as the HDD, for example, a SATA interface.

[0021] exist Figure 1 In the embodiment of the present invention, the manufacturer or supplier of DPS 20 has already installed the preliminary boot code module (PBM) 40 and the main boot code module (MBM) 42 into the low-speed NVM 36. Therefore, an instance of the main boot code module in the low-speed NVM can be referred to as a "low-speed main boot code module" or "low-speed MBM". Figure 3 As described in more detail, the preparatory boot code module 40 may then copy the low-speed MBM 42 to the protected area 34 of the high-speed NVM 32. Thus, an instance of a master boot code module in a high-speed NVM may be referred to as a "high-speed master boot code module" or "high-speed MBM". Figure 1 A high-speed MBM 43 in the high-speed NVM 32 is shown.

[0022] During a typical boot process, processor 22 may copy some or all of high-speed MBM 43 from high-speed NVM 32 to RAM 30 for execution, and processor 22 may copy some or all of OS 80 from HDD 38 to RAM 30 for execution, as shown by the boxes with dashed outlines in RAM 30. In addition, as described below with respect to Figure 3 Described in more detail, the preliminary boot code module 40 may (a) compute measurements 44 of the high-speed MBM 43, (b) retrieve previously saved measurements of the primary boot code module 42 from a trusted repository (e.g., TPM 48), and (c) use these measurements to determine whether the integrity of the high-speed MBM 43 has been maintained or whether the high-speed MBM 43 has been tampered with.

[0023] Figure 2 is a block diagram of an example embodiment of a DPS 120 that uses high-speed NVM 32 and low-speed NVM 136 to facilitate fast booting. Figure 2 In the embodiment of the present invention, DPS 120 may use some of the same types of components as DPS 20, as reflected by the matching reference numerals. Figure 2 In the embodiment, relative to Figure 1 In the embodiment of the invention, the low-speed NVM 36 is smaller than the low-speed NVM 136. Figure 2The embodiment includes a pre-boot code module 140, which is connected to Figure 1 For example, the preparatory boot code module 140 may include control logic for retrieving a fresh copy of the primary boot code module 42 from an external source (eg, the boot code server 90).

[0024] Therefore, in Figure 2 In an embodiment of the present invention, DPS 120 is part of a distributed data processing system (DDPS) 100. DPS 120 and boot code server 90 can communicate with each other using any suitable method or combination of methods, including via a wide area network (WAN) 110 (e.g., the Internet), via a local area network (LAN), etc. Boot code server 90 can be referred to as "remote" because it is external to DPS 120. Nevertheless, boot code server 90 and DPS 120 can be located in the same facility. For example, a DDPS may include a boot code server and hundreds of client devices, such as DPS 120 operating together in a data center. Alternatively, one or more of the client devices may be located at a great distance from the boot code server.

[0025] in addition, Figure 2 The embodiments also illustrate that the DPS 120 need not include a TPM, and the trusted MBM measurements 46 may instead be stored somewhere else, for example, in the low-speed NVM 136. For example, the pre-boot code module 140 may comply with the Unified Extensible Firmware Interface (UEFI) specification, and the pre-boot code module 140 may store the MBM measurements 46 in protected storage in the low-speed NVM 136. For example, the pre-boot code module 140 may use protected dedicated UEFI variables to store the MBM measurements 46 and other protected data items. Additionally, information about UEFI and protecting UEFI variables may be found in the UEFI specification, which may be found on the Internet at www.uefi.org--specifications, where version 2.6 may be available at www.uefi.org--sites--default--files--resources--UEFI%20Spec%202_6%20Errata%20A%20final.pdf.

[0026] Figure 3 A flow chart of an example embodiment of a process for facilitating fast booting using high-speed NVM 32 and relatively large low-speed NVM 36 is presented. Figure 3 The process and Figure 1 Corresponding to DPS20 in Figure 1 Low-speed NVM 36 in Figure 2 The low-speed NVM 136 in FIG. 1 is large because the low-speed NVM 136 is large enough to include a copy of the main boot code module, but the low-speed NVM 136 does not need to include a copy of the main boot code module.

[0027] DPS 20 may, for example, execute in response to being activated or reset. Figure 3 As shown at block 210, the process begins with the processor 22 starting the boot process using the preparatory boot code module 40. For example, the processor 22 may start executing the preparatory boot code module 40 using XIP, and then the processor 22 may transition to executing the preparatory boot code module 40 using a cache as RAM.

[0028] As shown at block 212, the pre-boot code module 40 may discover and initialize the RAM 30. For example, the pre-boot code module 40 may include a memory initialization reference code (MRC), and the pre-boot code module 40 may initialize the RAM 30 using the MRC. The pre-boot code module 40 may also perform early chipset initialization. For example, as shown at block 214, the pre-boot code module 40 may discover the TPM 48.

[0029] As shown at box 220, the preliminary boot code module 40 can then determine whether the DPS 20 has been booted before. If this is the first boot of the DPS 20, the preliminary boot code module 40 can take various steps to configure the DPS 20. For the purposes of this disclosure, these steps can be referred to as an "initial boot process" or a "configuration boot process." For example, as shown at box 222, the preliminary boot code module 40 can decompress the main boot code module 42 into the RAM 30, and then the preliminary boot code module 40 can measure the decompressed main boot code module, as shown at box 224. For example, the preliminary boot code module 40 can calculate a 32-byte hash of the image. As shown at box 226, the preliminary boot code module 40 can also save the decompressed main boot code module 42 to the high-speed NVM 32, thereby creating a high-speed MBM 43. In particular, as indicated above, the preliminary boot code module 40 can load the high-speed MBM 43 into the protected area 34. Additional details regarding techniques for preventing unauthorized access to the protected area 34 are provided below. Additionally, as shown at block 228, the provisioning boot code module 40 may complete the configuration boot process by saving the MBM measurements 46 to a trusted non-volatile storage repository. For example, the provisioning boot code module 40 may save the MBM measurements 46 to the TPM 48. Alternatively, the provisioning boot code module 40 may save the MBM measurements 46 to a proprietary non-volatile storage repository.

[0030] As shown at block 230, the preliminary boot code module 40 may then complete execution by transferring control to the image of the primary boot code module 42 in RAM 30. Figure 3 The process may end with master boot code module 42 performing any additional steps necessary to prepare DPS 20 to boot into OS 80.

[0031] However, referring again to block 220, if the pre-boot code module 40 determines that the DPS 20 is not booting for the first time, the pre-boot code module 40 may then determine whether the high-speed MBM 43 has been marked as bad, as shown at block 240 and described in more detail below. If the high-speed MBM 43 is not marked as bad, the pre-boot code module 40 may copy the high-speed MBM 43 from the high-speed NVM 32 to the RAM 30, as shown at block 242. As shown at block 244, the pre-boot code module 40 may then measure the copy of the high-speed MBM 43 in the RAM 30. This measurement may be referred to as the current MBM measurement. Alternatively, the pre-boot code module 40 may measure the high-speed MBM 43 as it is being read. In addition, as shown at block 246, the pre-boot code module 40 may retrieve the trusted MBM measurement 46 from the TPM 48. As shown at block 250, provisioning boot code module 40 may then use the current MBM measurements and trusted MBM measurements 46 to determine whether high speed MBM 43 has lost integrity. For example, the measurements may not match due to tampering, due to one or more failed memory cells, etc. If high speed MBM 43 has good integrity, provisioning boot code module 40 may then complete execution by transferring control to the image of high speed MBM 43 in RAM 30, as shown at block 252. Then Figure 3 The process may end with high-speed MBM 43 performing any additional steps necessary to prepare DPS 20 to boot to OS 80. For purposes of this disclosure, the steps performed by the preparatory boot code module when the high-speed MBM is not marked as bad and the high-speed MBM has good integrity may be referred to as a "regular boot process" or a "typical boot process."

[0032] However, referring again to box 250, if the pre-boot code module 40 determines that the high-speed MBM 43 has been damaged, the pre-boot code module 40 may mark the high-speed MBM 43 as bad, as shown at box 254. For the purposes of this disclosure, the operations for recovering from a damaged high-speed MBM may be collectively referred to as a "recovery boot process". The pre-boot code module 40 may use any suitable technique to mark the high-speed MBM 43 as bad. For example, the pre-boot code module 40 may use a special UEFI variable as a flag to notify the execution path when a reset occurs. As shown at box 256, the pre-boot code module 40 may then perform a reset operation, causing the process to return to box 210 via page connector A.

[0033] The preparatory boot code module 40 may then perform steps 210-220 and 240 as indicated above. However, now the preparatory boot code module 40 may determine at block 240 that the high-speed MBM 43 has been marked as bad. Therefore, the process may proceed to block 222, where the preparatory boot code module 40 obtains a fresh copy of the master boot code module 42 from the low-speed NVM 36. To complete the recovery boot process, the preparatory boot code module 40 may then use the master boot code module 42 to refresh the image in the high-speed NVM 32, as described above with respect to blocks 222-228. However, in some embodiments, during the recovery boot process, the preparatory boot code module may skip the step (224) for measuring the master boot code module and the step (228) for saving the measurement.

[0034] During a typical boot process in which a trusted copy of the master boot code module 42 is in the high-speed NVM 32, the DPS 20 can load the high-speed MBM 43 into RAM much faster than would be possible if all of the boot code had to come from the low-speed NVM 36. The following table shows some example approximate load times for four different systems, each of which has a 7MB large master boot code module (or an equivalent portion of a monolithic boot code module).

[0035] Read speed Loading time 9.375MB / s low-speed NVM 746ms 35MB / s low-speed NVM 200ms 1000MB / s high-speed NVM 7ms 1600MB / s high-speed NVM 4.3ms

[0036] Therefore, a high-speed NVM of 1000MB / s is faster than a low-speed NVM of 35MB / s. 28 times faster . And the high-speed NVM of 1600MB / s is faster than the low-speed NVM of 9.375MB / s. 173 times faster Therefore, the DPS of using a slow NVM with 35MB / s is 200ms In comparison, the DPS using 1000MB / s high-speed NVM can be 7msThe 7MB boot code is loaded within 10 seconds. And the DPS of the low-speed NVM is 9.375MB / s. 746ms In comparison, the DPS using 1600MB / s high-speed NVM can be 4.3ms Therefore, in the four examples shown above, the minimum DPS that can be saved is (200-7=) 193ms The maximum value is (746-4.3=) 741.7ms Different levels of relative improvement may be achieved in different embodiments.

[0037] The present disclosure may use terms such as "specific boot process", "single boot process", etc. Such terms are intended to refer to boot operations performed after the DPS is started or reset to initialize the boot process in order to boot to the OS. Figure 3 , for the first boot of the DPS, this particular boot process may start at block 210 and end at block 230. Similarly, a single boot process for a regular boot or a typical boot may start at block 210 and end at block 252. However, a single boot process may include intermediate reset and recovery operations. For example, a single boot process involving a damaged high-speed MBM may start at block 210, continue through block 256 back to block 210, and end at block 230.

[0038] Figure 4A and Figure 4B A flow chart of an example embodiment of a process for facilitating fast booting using high-speed NVM 32 and relatively small low-speed NVM 136 is presented. Figure 4A and Figure 4B The process and Figure 2 Corresponding to DPS120 in Figure 2 The low speed NVM 136 in Figure 1 The low-speed NVM 36 in the DPS 120 is small because the low-speed NVM 136 does not need to contain a copy of the main boot code module. Instead, as described in more detail below, when the DPS 120 needs a copy of the main boot code module, the DPS 120 obtains the copy from the high-speed NVM 32 or from a source other than the low-speed NVM 136.

[0039] DPS 120 may, for example, execute in response to being activated or reset. Figure 4A and Figure 4B As shown at block 310, the process begins with the processor 22 using the pre-boot code module 140 to start the boot process. Figure 3When performing operations such as those described above, the preparatory boot code module 140 may use techniques the same or similar to those described above with respect to the preparatory boot code module 40. For example, the processor 22 may begin executing the preparatory boot code module 140 using XIP, and then the processor 22 may transition to executing the preparatory boot code module 140 using the cache as RAM.

[0040] As shown at box 312, the pre-boot code module 140 can find the RAM 30 and initialize it. For example, the pre-boot code module 140 can include an MRC, which the pre-boot code module 140 uses to initialize the RAM 30. In addition, the pre-boot code module 140 can perform early chipset initialization. As shown at box 320, the pre-boot code module 140 can then determine whether the high-speed NVM 32 contains a master boot code module (e.g., high-speed MBM 43). If the master boot code module is missing from the high-speed NVM 32, the pre-boot code module can obtain the master boot code module from a trusted source, as shown at box 322. For example, the pre-boot code module 140 can obtain a copy of the master boot code module 42 from the boot code server 90. Alternatively, the pre-boot code module 140 can obtain the master boot code module from a flash drive connected to the DPS 120. For example, the DPS 120 can prompt the user to insert the flash drive with the master boot code module into a universal serial bus (USB) port of the DPS 120.

[0041] Sources such as flash drives and remote servers 90 may be deemed to be trusted with the aid of digital signatures or any other suitable technique. For example, the original equipment manufacturer (OEM) that assembles the DPS 120 may digitally sign the master boot code module 42 before it is saved to the remote server 90 or saved to the flash drive. Thus, when the preliminary boot code module 140 retrieves the master boot code module 42 from the remote server 90 or from the flash drive, the preliminary boot code module 140 may use the signature to verify that the master boot code module 42 is authentic.

[0042] Alternatively, the preparatory boot code module may obtain the master boot code module from any other suitable source. As shown at block 324, the preparatory boot code module 140 may then save a copy of the master boot code module to the protected area 43 in the high-speed NVM 32, thereby creating a high-speed MBM 43.

[0043] However, at block 320, if the provisioning boot code module 140 determines that the high-speed NVM 32 already contains the high-speed MBM 43, the provisioning boot code module 140 may then determine whether the high-speed MBM 43 has been marked as bad, as shown at block 330. If the high-speed MBM 43 has been marked as bad, the provisioning boot code module may obtain a recent copy of the main boot code module from a trusted source and save the copy to the high-speed NVM 32, as shown at blocks 322 and 324.

[0044] The process may then pass from block 324 to block 332, which depicts the preparatory boot code module 140 loading the high speed MBM 43 into the RAM 30, as shown at block 332. And as shown at block 334, the preparatory boot code module may then calculate a measurement 44 of the high speed MBM 43. This measurement may be referred to as a current MBM measurement.

[0045] As shown at block 340, the pre-boot code module 140 may then determine whether the DPS 120 has been booted before. If this is not the first boot of the DPS 120, the process may then pass through page connector A to Figure 4B If this is the first boot of the DPS 120, the pre-boot code module 140 may save the MBM measurements 46 to the slow NVM 136, as shown at block 350. The process may then pass through page connector B to Figure 4B After passing through Page Connector B due to a positive first boot determination, the pre-boot code module 140 may then complete execution by transferring control to the image of the high speed MBM 43 in RAM 30. Then, Figure 4B The process may end with high-speed MBM 43 performing any additional steps necessary to prepare DPS 120 to boot to OS 80 .

[0046] However, after passing through page connector A due to the negative first boot determination, the pre-boot code module 140 may then retrieve the trusted MBM measurement 46 from the low-speed NVM 136, as shown at block 342. As shown at block 360, the pre-boot code module 140 may then use the current MBM measurement and the trusted MBM measurement 46 to determine whether the high-speed MBM 43 has been corrupted. If the high-speed MBM 43 is not corrupted, the pre-boot code module 140 may then complete execution by transferring control to the image of the high-speed MBM 43 in RAM 30, as shown at block 362. Then, Figure 4B The process may end with high-speed MBM 43 performing any additional steps necessary to prepare DPS 20 to boot to OS 80.

[0047] However, referring again to block 360, if the pre-boot code module 140 determines that the high-speed MBM 43 has been damaged, the pre-boot code module 140 may mark the high-speed MBM 43 as bad, as shown at block 364. As shown at block 366, the pre-boot code module 140 may then perform a reset operation, causing the process to return to block 310 via page connector C.

[0048] The pre-boot code module 140 may then perform steps 310-320 and 330 as indicated above. However, at block 330, the pre-boot code module 40 will determine that the high-speed MBM 43 has been marked as bad. Therefore, the process will proceed to block 332, where the pre-boot code module 140 obtains a fresh copy of the main boot code module 42 from a trusted source, as indicated above.

[0049] In addition, as indicated above, the high-speed MBM can be stored in a protected area of ​​the high-speed NVM. For example, DPS20 and DPS120 may include technology for protecting the protected area 34 from unauthorized access. For example, DPS20 (and DPS120) may only allow access to the protected area 34 from a trusted execution environment (TEE). In addition, security technology may prevent software outside the TEE from accessing data in the TEE. The TEE may thus provide an isolated execution environment. In one embodiment, to create and utilize a TEE, a device may use a device that is manufactured by Intel Corporation under the name or trademark “ Software Guard Extensions" or In another embodiment, to create and utilize a TEE, a device may use technology provided by ARM Limited under the name or trademark “ARM TrustZone”. In other embodiments, a device may use alternative technology to create and utilize a TEE. Figure 1 and Figure 2 In the embodiment of the present invention, the protected area 34 is a dedicated, tamper-resistant portion of the high-speed NVM 32 that can only be accessed by software executing in the TEE of the platform. During the manufacturing process, the protected area 34 can be provisioned with appropriate security policies. In other embodiments, the DPS can use other techniques to protect the protected area of ​​the high-speed NVM from unauthorized access.

[0050] As has been described, the boot code for the DPS can be divided into a preliminary boot code module and a main boot code module, and the main boot code module can be stored in a high-speed NVM to facilitate a significantly faster boot process than the boot process of the DPS storing all the boot code in the low-speed NVM. In addition, compared to a motherboard that requires a larger low-speed NVM to accommodate all the boot code, it may be less expensive to produce a motherboard for a DPS that uses a high-speed NVM for booting. In other words, a motherboard for a DPS that uses a high-speed NVM for booting can benefit from a reduced bill of materials (BOM) in addition to reducing boot time.

[0051] In some embodiments, the high-speed MBM may allow the pre-OS firmware to replay audio streams, to present or publish graphical images, and to provide other advanced output capabilities during the initial boot of the DPS. The initial boot may also be referred to as a training boot. Data for advanced output capabilities may also be stored in the high-speed NVM. Such output capabilities may meet user interface requirements associated with certain applications, such as applications for autonomous vehicles and other vehicle systems.

[0052] Additionally, the DPS may achieve some or all of the advantages described herein while also achieving reduced energy consumption relative to a conventional DPS.

[0053] Based on the principles and example embodiments described and shown herein, it will be appreciated that the illustrated embodiments may be modified in arrangement and detail without departing from these principles. In addition, although expressions such as "embodiment," "one embodiment," "another embodiment," etc. are used herein, these phrases are generally intended to refer to embodiment possibilities and are not intended to limit the invention to specific embodiment configurations. As used herein, these phrases may reference the same embodiment or different embodiments, and these embodiments may be combined into other embodiments.

[0054] For example, a TPM can be added to Figure 2 and the control logic for obtaining the master boot code module from an external source may be added to Figure 1 In addition, Figure 3 Box 250 and Figure 4B Block 360 of 300 involves a determination of whether the high-speed MBM has been compromised. Such an operation may be used in embodiments with non-lockable high-speed NVM, for example, embodiments in which the high-speed NVM does not have protected regions. In other embodiments, other techniques may be used for tamper protection or detection in addition to or in lieu of the operations described above. For example, the DPS may include a method described by Intel Corporation under the name “ Platform Trust Technology (PTT)” and “ The Boot Guard technology may provide secure boot based on an authenticated code module (ACM). The ACM may perform one or more integrity checks to verify that a known and trusted firmware is booting the platform. Another embodiment may feature a high-speed NVM that may be locked to prevent tampering with the boot image. The prepared boot code module may therefore omit integrity checks.

[0055] In addition, the present disclosure may relate to instructions, functions, programs, data structures, applications, microcodes, configuration settings, and other types of data. As described above, when data is accessed by a machine or device, the machine or device may respond by performing tasks, defining abstract data types or low-level hardware contexts, and / or performing other operations. For example, data storage devices, RAM, and / or flash memories may include various instruction sets that perform various operations when executed. Such instruction sets may generally be referred to as software. As indicated above, the software used during the boot process may be referred to as firmware. Software stored in non-volatile memory may also be referred to as firmware. In addition, terms such as "program" and "module" may generally be used to cover a wide range of software structures, including applications, routines, drivers, subroutines, processes, and other types of software components. Any suitable operating environment and programming language (or a combination of operating environment and programming language) may be used to implement the software components described herein.

[0056] Alternative embodiments include machine-accessible media that encode instructions or control logic for performing the operations described herein. Such embodiments may also be referred to as program products. Such machine-accessible media may include, but are not limited to, tangible storage media such as disks, optical disks, RAM, ROM, etc., as well as processors, controllers, and other components including RAM, ROM, and / or other storage facilities. For purposes of this disclosure, the term "ROM" may be generally used to refer to non-volatile memory devices, such as erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash ROM, flash memory, etc.

[0057] It should also be understood that the hardware components and software components depicted herein represent reasonably self-contained so that each functional element can be designed, constructed, or updated substantially independently of other functional elements. In alternative embodiments, many components in the assembly can be implemented as hardware, software, or a combination of hardware and software, for providing the functions described and shown herein. In certain embodiments, some or all of the control logic for implementing the described operation can be implemented with hardware logic (e.g., as a part of an integrated circuit chip, a programmable gate array (PGA), an application specific integrated circuit (ASIC), etc.).

[0058] In addition, it should be understood that any particular software module may include more than one component. For example, a master boot code module may include two or more components, and these components may cooperate to complete the operation of the master boot code module, for example, booting to an OS.

[0059] Similarly, instructions for multiple components can be stored in a non-transitory machine-accessible medium. In at least one other embodiment, two or more non-transitory machine-accessible media can be used to store instructions for related components. For example, instructions for one component can be stored in one medium, and instructions for another component can be stored in another medium. Alternatively, a portion of the instructions for one component can be stored in one medium, and the remaining instructions in the instructions for the component (and instructions for other components) can be stored in one or more other media. Instructions can also be used in a distributed environment and can be stored locally and / or remotely for access by a single processor or multiple processor machines.

[0060] Similarly, the applications and / or other data described above as residing on a specific device in one example embodiment may reside on one or more other devices in other embodiments. Also, the computing operations described above as being performed on a specific device in one example embodiment may be performed by one or more other devices in other embodiments.

[0061] This teaching can be used to facilitate many different types of data processing systems. Example data processing systems may include, but are not limited to: system on chip (SOC), wearable device, handheld device, smart phone, phone, entertainment device (e.g., audio device, video device, audio / video device (e.g., TV and set-top box)), vehicle-mounted processing system, personal digital assistant (PDA), tablet computer, laptop computer, portable computer, personal computer (PC), workstation, server, client-server system, distributed computing system, supercomputer, high performance computing system, computing cluster, mainframe computer, minicomputer and other devices for processing or transmitting information. Therefore, unless otherwise expressly specified or required by context, references to any particular type of data processing system (e.g., PC) should be understood to also cover other types of data processing systems. In addition, unless otherwise expressly specified, components described as being coupled to each other, communicating with each other, responding to each other, etc. do not necessarily communicate continuously with each other, and are not necessarily directly coupled to each other. Similarly, when a component is described as receiving data from another component or sending data to another component, unless otherwise expressly specified, the data can be sent or received by one or more intermediate components. In addition, some components of the data processing system can be implemented as adapter cards with interfaces (e.g., connectors) for communicating with the bus. Alternatively, the device or component can be implemented as an embedded controller using the following components: for example, programmable or non-programmable logic devices or arrays, ASICs, embedded computers, smart cards, etc. For the purposes of this disclosure, the term "bus" includes pathways and point-to-point pathways that can be shared by more than two devices. In addition, for the purposes of this disclosure, a processor may also be referred to as a processing unit, a processing element, a CPU, etc.

[0062] In addition, although one or more example processes have been described with respect to specific operations performed in a specific sequence, many modifications may be applied to these processes to derive many alternative embodiments of the present invention. For example, alternative embodiments may include processes that use fewer operations than all disclosed operations, processes that use additional operations, and processes in which the individual operations disclosed herein are combined, subdivided, rearranged, or otherwise changed.

[0063] In view of the wide variety of useful arrangements that can be readily derived from the example embodiments described herein, this detailed description is intended to be illustrative only, and should not be taken as limiting the scope of coverage.

[0064] The following examples relate to further embodiments.

[0065] Example A1 is a DPS utilizing a technique for fast booting. The DPS includes a processor, a volatile RAM responsive to the processor, a low-speed NVM responsive to the processor, a high-speed NVM responsive to the processor, a preparatory boot code module stored in the low-speed NVM, and a main boot code module stored in the high-speed NVM. The high-speed NVM supports a read speed faster than the maximum read speed of the low-speed NVM. The preparatory boot code module, when executed by the processor, enables the DPS to load the main boot code module from the high-speed NVM into the RAM. The main boot code module, when executed by the processor, enables the DPS to boot to the OS.

[0066] Example A2 is a DPS according to Example A1, wherein the high-speed NVM supports an average read speed of at least 200 megabytes per second (MB / s), and the maximum read speed of the low-speed NVM is less than 200 MB / s.

[0067] Example A3 is a DPS according to Example A2, wherein the maximum read speed of the low-speed NVM is less than 40 MB / s.

[0068] Example A4 is a DPS according to Example A1, wherein the preparatory boot code module, when executed, enables the DPS to automatically determine whether the main boot code module from the high-speed NVM has good integrity before booting the DPS to the OS. Example A4 may also include any one or more features of Examples A2 to A3.

[0069] Example A5 is a DPS according to Example A4, further comprising a trusted MBM measurement. In addition, the operation of automatically determining whether the master boot code module from the high-speed NVM has good integrity includes (a) using the master boot code module from the high-speed NVM to calculate the current MBM measurement; (b) retrieving the trusted MBM measurement; and (c) determining whether the current MBM measurement matches the trusted MBM measurement.

[0070] Example A6 is a DPS according to Example A1, wherein the preparatory boot code module, when executed, enables the DPS to (a) automatically determine whether the master boot code module from the high-speed NVM has good integrity before booting the DPS to the OS; and (b) in response to determining that the master boot code module from the high-speed NVM does not have good integrity, automatically use the master boot code module from a storage device other than the high-speed NVM to boot the DPS to the OS. Example A4 may also include any one or more features of Examples A2 to A5.

[0071] Example A7 is a DPS according to Example A6, wherein the storage device other than the high-speed NVM includes a low-speed NVM in the DPS.

[0072] Example A8 is the DPS of Example A6, wherein the storage device other than the high-speed NVM includes an external storage device.

[0073] Example A9 is a DPS according to Example A1, wherein the preparatory boot code module, when executed, enables the DPS to (a) automatically determine whether the master boot code module from the high-speed NVM has good integrity using the preparatory boot code module before using the master boot code module to boot the DPS to the OS; (b) in response to determining that the master boot code module from the high-speed NVM does not have good integrity, automatically retrieve the master boot code module from a storage device other than the high-speed NVM; and (c) automatically replace the master boot code module in the high-speed NVM with the master boot code module from the storage device other than the high-speed NVM. Example A7 may also include any one or more of the features of Examples A2 to A8.

[0074] Example A10 is a DPS according to Example A9, wherein the preliminary boot code module, when executed, enables the DPS to decompress the boot code module from the storage device other than the high-speed NVM before automatically replacing the master boot code module in the high-speed NVM with the master boot code module from the storage device other than the high-speed NVM.

[0075] Example A11 is a DPS according to Example A1, wherein the preliminary boot code module, when executed, enables the DPS to save the master boot code module to a protected area of ​​the high-speed NVM during an initial boot process for the DPS. In addition, the operation of loading the master boot code module from the high-speed NVM into the RAM includes obtaining the master boot code module from the protected area of ​​the high-speed NVM. Example A9 may also include any one or more of the features of Examples A2 to A10.

[0076] Example A12 is a DPS according to Example A11, wherein the preliminary boot code module, when executed, enables the DPS to (a) calculate measurements of the main boot code module during the initial boot process; and (b) save the measurements of the main boot code module to a storage device other than the high-speed NVM during the initial boot process.

[0077] Example A13 is a DPS according to Example A1, wherein (a) the processor includes a cache, at least a portion of which is capable of operating as a cache as RAM; (b) the pre-boot code module includes a first portion for executing in place and a second portion for executing from the cache as RAM; and (c) the low-speed NVM includes a flash memory with SPI. Example A11 may also include the features of any one or more of Examples A2 to A12.

[0078] Example A14 is a DPS according to Example A1, wherein the preparatory boot code module includes an MRC; and the preparatory boot code module is configured to initialize the RAM using the MRC before loading the main boot code module from the high-speed NVM into the RAM. Example A12 may also include any one or more features of Examples A2 to A13.

[0079] Example B1 is a DPS utilizing a technique for fast booting. The DPS includes a processor, a volatile RAM responsive to the processor, a low-speed NVM responsive to the processor, a high-speed NVM responsive to the processor, and a preparatory boot code module stored in the low-speed NVM. In addition, the preparatory boot code module, when executed by the processor, enables the DPS to save the main boot code module in the high-speed NVM during the configuration boot process. In addition, the preparatory boot code module, when executed by the processor after the main boot code module is saved in the high-speed NVM, enables the DPS to load the main boot code module from the high-speed NVM into the RAM.

[0080] Example B2 is a DPS according to example B1, wherein the master boot code module, when executed, enables the DPS to boot to the OS.

[0081] Example B3 is a DPS according to example B1, wherein the preparatory boot code module, when executed, enables the DPS to automatically replace a bad primary boot code module in the high-speed NVM with a good primary boot code module during a recovery boot process. Example B3 may also include features of example B2.

[0082] Example C1 is a method for fast booting of a DPS. The method includes, during a boot process of the DPS, using a preliminary boot code module from a low-speed NVM in the DPS to load a master boot code module from a high-speed NVM in the DPS into a volatile RAM in the DPS, wherein the high-speed NVM supports a read speed faster than a maximum read speed of the low-speed NVM. The method also includes, during the boot process, after loading the master boot code module from the high-speed NVM into RAM, using the master boot code module to boot the DPS to the OS.

[0083] Example C2 is the method of Example C1, wherein the high-speed NVM supports an average read speed of at least 200 megabytes per second (MB / s), and the maximum read speed of the low-speed NVM is less than 200 MB / s.

[0084] Example C3 is the method of Example C2, wherein the maximum read speed of the low-speed NVM is less than 40 MB / s.

[0085] Example C4 is a method according to Example C1, further comprising, during the boot process, before using the main boot code module to boot the DPS to the OS, using the preliminary boot code module to automatically determine whether the main boot code module from the high-speed NVM has good integrity. Example C4 may also include any one or more features of Examples C2 to C3.

[0086] Example C5 is a method according to Example C4, wherein the operation of using a preliminary boot code module to automatically determine whether a main boot code module from a high-speed NVM has good integrity includes (a) calculating a current MBM measurement using the main boot code module from the high-speed NVM; (b) retrieving a trusted MBM measurement; and (c) determining whether the current MBM measurement matches the trusted MBM measurement.

[0087] Example C6 is a method according to Example C1, further comprising: (a) using a preliminary boot code module to automatically determine whether the master boot code module from the high-speed NVM has good integrity before using the master boot code module to boot the DPS to the OS; and (b) in response to determining that the master boot code module from the high-speed NVM does not have good integrity, automatically using a master boot code module from a storage device other than the high-speed NVM to boot the DPS to the OS. Example C4 may also include any one or more features of Examples C2 to C5.

[0088] Example C7 is the method of Example C6, wherein the storage device other than the high-speed NVM includes a low-speed NVM in the DPS.

[0089] Example C8 is the method of Example C6, wherein the storage device other than the high-speed NVM includes an external storage device.

[0090] Example C9 is a method according to Example C1, further comprising: (a) using a preliminary boot code module to automatically determine whether the master boot code module from the high-speed NVM has good integrity before using the master boot code module to boot the DPS to the OS; (b) in response to determining that the master boot code module from the high-speed NVM does not have good integrity, automatically retrieving the master boot code module from a storage device other than the high-speed NVM; and (c) automatically replacing the master boot code module in the high-speed NVM with the master boot code module from the storage device other than the high-speed NVM. Example C7 may also include any one or more of the features of Examples C2 to C8.

[0091] Example C10 is the method of Example C9, further comprising, before automatically replacing the master boot code module in the high-speed NVM with the master boot code module from the storage device other than the high-speed NVM, decompressing the boot code module from the storage device other than the high-speed NVM.

[0092] Example C11 is a method according to Example C1, further comprising (a) saving the master boot code module to a protected area of ​​the high-speed NVM during an initial boot process for the DPS. In addition, the operation of loading the master boot code module from the high-speed NVM into the RAM includes obtaining the master boot code module from the protected area of ​​the high-speed NVM. Example C9 may also include any one or more features of Examples C2 to C10.

[0093] Example C12 is a method according to Example C11, further comprising (a) calculating a measurement of a master boot code module during an initial boot process; and (b) saving the measurement of the master boot code module to a storage device other than the high-speed NVM during the initial boot process.

[0094] Example C13 is a method according to Example C1, wherein the first portion of the preparatory boot code module is executed in situ, the second portion of the preparatory boot code module is executed from a cache as RAM, and the low-speed NVM includes a flash memory with a serial peripheral interface (SPI). Example C9 may also include any one or more features of Examples C2 to C12.

[0095] Example C14 is a method according to Example C1, wherein the preparatory boot code module includes a memory initialization reference code (MRC), and before loading the main boot code module from the high-speed NVM into the RAM, the preparatory boot code module initializes the RAM using the MRC. Example C10 may also include any one or more features of Examples C2 to C13.

[0096] Example D is at least one machine accessible medium including computer instructions for fast booting a DPS. The computer instructions, in response to being executed in the DPS, enable the DPS to perform a method according to any one of Examples C1 to C14.

[0097] Example E is a DPS utilizing a technique for fast booting. The DPS includes a processing element, a volatile RAM responsive to the processing element, a low-speed NVM responsive to the processing element, a high-speed NVM responsive to the processing element, and computer instructions at least partially stored in the low-speed NVM. The computer instructions, when executed by the processing element, enable the DPS to perform a method according to any one of Examples C1 to C14.

[0098] Example F is a DPS utilizing a technique for fast booting. The DPS includes means for performing the method of any one of Examples C1 to C14.

Claims

1. A data processing system (DPS) utilizing a technique for fast booting, the DPS comprising: processor; a volatile random access memory (RAM) responsive to the processor; a low speed non-volatile memory (NVM) responsive to the processor; a high-speed NVM responsive to the processor, wherein the high-speed NVM supports a read speed faster than a maximum read speed of the low-speed NVM; Trusted MBM measurement; a preparatory boot code module stored in the low-speed NVM; and A master boot code module stored in the high-speed NVM; wherein the preliminary boot code module, when executed by the processor, enables the DPS to load the main boot code module from the high-speed NVM into the RAM; wherein the master boot code module, when executed by the processor in response to loading the master boot code module into the RAM, enables the DPS to boot into an operating system (OS); Wherein, when the preparatory boot code module is executed, the DPS is able to automatically determine whether the main boot code module from the high-speed NVM has good integrity before booting the DPS to the OS, wherein the operation of automatically determining whether the main boot code module from the high-speed NVM has good integrity includes: calculating a current MBM measurement indicative of contents of the master boot code module using the master boot code module from the high-speed NVM; retrieving the trusted MBM measurements; and determining whether the current MBIM measurement matches the trusted MBIM measurement; and wherein the preparatory boot code module, when executed, enables the DPS to determine whether the high-speed NVM supports the read speed that is faster than the maximum read speed of the low-speed NVM; In response to determining that the master boot code module from the high-speed NVM does not have good integrity, automatically retrieving a master boot code module from a storage device other than the high-speed NVM; and In response to determining that the high-speed NVM supports the read speed faster than the maximum read speed of the low-speed NVM, the master boot code module in the high-speed NVM is automatically replaced with the master boot code module from the storage device other than the high-speed NVM.

2. The DPS of claim 1, wherein: The high-speed NVM supports an average read speed of at least 200 megabytes per second (MB / s); and The maximum read speed of the low-speed NVM is less than 200 MB / s.

3. The DPS of claim 2, wherein: The maximum read speed of the low-speed NVM is less than 40 MB / s.

4. The DPS of claim 1, wherein: The pre-boot code module, when executed, enables the DPS to In response to determining that the master boot code module from the high-speed NVM does not have good integrity, automatically booting the DPS to the OS using the master boot code module from the storage device other than the high-speed NVM.

5. The DPS of claim 4, wherein: The storage device other than the high-speed NVM includes the low-speed NVM in the DPS.

6. The DPS of claim 4, wherein: The storage device other than the high-speed NVM includes an external storage device.

7. The DPS of claim 1, wherein: The processor includes a cache, at least a portion of which is operable as a cache serving as RAM; The pre-boot code module includes a first portion for executing in-place and a second portion for executing from the cache as RAM; and The low-speed NVM includes a flash memory having a serial peripheral interface (SPI).

8. The DPS of claim 1, wherein: The preparatory boot code module includes a memory initialization reference code (MRC); and The preliminary boot code module is configured to initialize the RAM using the MRC before loading the main boot code module from the high-speed NVM into the RAM.

9. A data processing system (DPS) utilizing a technique for fast booting, the DPS comprising: processor; a volatile random access memory (RAM) responsive to the processor; a low speed non-volatile memory (NVM) responsive to the processor; a high speed NVM responsive to the processor; as well as a preparatory boot code module stored in the low-speed NVM; wherein the pre-boot code module, when executed by the processor, enables the DPS to: (i) determine whether the high-speed NVM supports a read speed faster than a maximum read speed of the low-speed NVM; (ii) in response to determining that the high-speed NVM supports the read speed faster than the maximum read speed of the low-speed NVM, save a master boot code module in the high-speed NVM during a configuration boot process; (iii) calculate a trusted MBM measurement indicating contents of the master boot code module during the configuration boot process; and (iv) save the trusted MBM measurement during the configuration boot process; and The preliminary boot code module, when executed by the processor after the main boot code module is stored in the high-speed NVM, enables the DPS to load the main boot code module from the high-speed NVM into the RAM.

10. The DPS of claim 9, wherein: The master boot code module, when executed, enables the DPS to boot into an operating system (OS).

11. The DPS of claim 9, wherein: The preparatory boot code module, when executed, enables the DPS to automatically replace a bad primary boot code module in the high-speed NVM with a good primary boot code module during a recovery boot process.

12. A method for quickly booting a data processing system, the method comprising: During a boot process of a data processing system (DPS), loading a primary boot code module from a high-speed non-volatile memory (NVM) in the DPS into a volatile random access memory (RAM) in the DPS using a preliminary boot code module from a low-speed non-volatile memory (NVM) in the DPS, wherein the high-speed NVM supports a read speed faster than a maximum read speed of the low-speed NVM; during the boot process, using the preliminary boot code module to calculate a current MBM measurement indicative of contents of the primary boot code module loaded into the volatile RAM, retrieving a trusted MBM measurement, and determining whether the current MBM measurement matches the trusted MBM measurement; during the boot process, after loading the master boot code module from the high-speed NVM into the RAM and determining that the current MBM measurement matches the trusted MBM measurement, booting the DPS to an operating system (OS) using the master boot code module; During the boot process, after determining that the current MBM measurement does not match the trusted MBM measurement, determining using the preliminary boot code module whether the high-speed NVM supports the read speed faster than the maximum read speed of the low-speed NVM; and During the boot process, after determining that the high-speed NVM supports the read speed faster than the maximum read speed of the low-speed NVM, the preliminary boot code module is used to automatically replace the main boot code module in the high-speed NVM with the main boot code module from a storage device other than the high-speed NVM.

13. The method according to claim 12, wherein: The high-speed NVM supports an average read speed of at least 200 megabytes per second (MB / s); and The maximum read speed of the low-speed NVM is less than 200 MB / s.

14. The method according to claim 13, wherein: The maximum read speed of the low-speed NVM is less than 40 MB / s.

15. The method according to claim 12, further comprising: During the boot process, the preliminary boot code module is used to automatically determine whether the main boot code module from the high-speed NVM has good integrity before using the main boot code module to boot the DPS to the OS.

16. The method according to claim 12, further comprising: Before using the master boot code module to boot the DPS to the OS, using the preliminary boot code module to automatically determine whether the master boot code module from the high-speed NVM has good integrity; as well as In response to determining that the master boot code module from the high-speed NVM does not have good integrity, automatically booting the DPS to the OS using the master boot code module from the storage device other than the high-speed NVM.

17. The method according to claim 16, wherein: The storage device other than the high-speed NVM includes the low-speed NVM in the DPS.

18. The method according to claim 16, wherein: The storage device other than the high-speed NVM includes an external storage device.

19. The method according to claim 16, further comprising: Before automatically replacing the master boot code module in the high-speed NVM with the master boot code module from the storage device other than the high-speed NVM, the master boot code module from the storage device other than the high-speed NVM is decompressed.

20. The method of claim 12, further comprising: saving the master boot code module to a protected area of ​​the high-speed NVM during an initial boot process for the DPS; and The operation of loading the master boot code module from the high-speed NVM into the RAM includes obtaining the master boot code module from a protected area of ​​the high-speed NVM.

21. The method according to claim 20, further comprising: During the initial boot process, calculating the trusted MBM measurement, wherein the trusted MBM measurement indicates content of the master boot code module; and During the initial boot process, the trusted MBM measurements are saved to a storage device other than the high-speed NVM.

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