Neural network scheduling mechanism

Abstract

Disclosed is an apparatus for facilitating workload scheduling. The apparatus includes one or more clients, one or more processing units configured to process workloads received from the one or more clients, the one or more processing units comprising hardware resources and scheduling logic configured to schedule direct access to the hardware resources to the one or more clients to process the workloads.

Description

Technical Field

[0001] Embodiments relate generally to data processing, and more particularly to machine learning processing via general-purpose graphics processing units. Background Art

[0002] Current parallel graphics data processing includes systems and methods developed for performing specific operations on graphics data, such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors have used fixed-function compute units to process graphics data; however, recently, portions of graphics processors have become programmable, enabling such processors to support a wider variety of operations for processing vertex and fragment data.

[0003] To further improve performance, graphics processors typically implement processing techniques (e.g., pipelining) that attempt to process as much graphics data as possible in parallel across different parts of the graphics pipeline. Parallel graphics processors with a single instruction multiple thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In a SIMT architecture, multiple groups of parallel threads attempt to execute program instructions together synchronously as often as possible to improve processing efficiency. A general overview of the software and hardware for a SIMT architecture can be found in Shane Cook's CUDA Programming, Chapter 3, pages 37-51 (2013). BRIEF DESCRIPTION OF THE DRAWINGS

[0004] In order that the above-described features of the present embodiment can be understood in detail, the embodiments briefly summarized above may be described in more detail by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical embodiments and, therefore, should not be considered as limiting the scope thereof.

[0005] Figure 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein;

[0006] Figures 2A to 2D shows a parallel processor component according to an embodiment;

[0007] Figures 3A to 3B is a block diagram of a graphics multiprocessor according to an embodiment;

[0008] Figures 4A to 4F An exemplary architecture is shown in which multiple GPUs are communicatively coupled to multiple multi-core processors;

[0009] Figure 5 shows a graphics processing pipeline according to an embodiment;

[0010] Figure 6 A computing device employing a scheduling mechanism according to an embodiment is shown;

[0011] Figure 7A One embodiment of a system for performing direct scheduling of a neural network is shown;

[0012] Figure 7B Another embodiment of a system for performing direct scheduling of a neural network is shown;

[0013] Figure 7C An embodiment of a feature map and a relative offset table is shown;

[0014] Figure 8 shows a machine learning software stack according to an embodiment;

[0015] Figure 9 shows a highly parallel general purpose graphics processing unit according to an embodiment;

[0016] Figure 10 A multi-GPU computing system according to an embodiment is shown;

[0017] Figures 11A to 11B The layers of an exemplary deep neural network are shown;

[0018] Figure 12 An exemplary recurrent neural network is shown;

[0019] Figure 13 shows the training and deployment of deep neural networks;

[0020] Figure 14 is a block diagram illustrating distributed learning;

[0021] Figure 15 An exemplary inference system-on-chip (SOC) suitable for performing inference using a trained model is shown;

[0022] Figure 16 is a block diagram of a processing system according to an embodiment;

[0023] Figure 17 is a block diagram of a processor according to an embodiment;

[0024] Figure 18 is a block diagram of a graphics processor according to an embodiment;

[0025] Figure 19 is a block diagram of a graphics processing engine of a graphics processor according to some embodiments;

[0026] Figure 20 is a block diagram of a graphics processor provided by an additional embodiment;

[0027] Figure 21 Thread execution logic is shown, including an array of processing elements employed in some embodiments;

[0028] Figure 22 is a block diagram illustrating a graphics processor instruction format according to some embodiments;

[0029] Figure 23 is a block diagram of a graphics processor according to another embodiment;

[0030] FIG. 24A to FIG. 24B shows a graphics processor command format and command sequence according to some embodiments;

[0031] Figure 25 An exemplary graphics software architecture for a data processing system according to some embodiments is shown;

[0032] Figure 26 is a block diagram illustrating an IP core development system according to an embodiment;

[0033] Figure 27 is a block diagram illustrating an exemplary system-on-chip integrated circuit according to an embodiment;

[0034] Figure 28 is a block diagram illustrating an additional exemplary graphics processor; and

[0035] Figure 29 is a block diagram illustrating an additional exemplary graphics processor of a system-on-chip integrated circuit according to an embodiment. DETAILED DESCRIPTION

[0036] In some embodiments, a scheduling mechanism is disclosed for performing direct scheduling of pre-compiled neural network (NN) kernel client workloads. In such embodiments, the kernel application client is scheduled via a KMD (kernel mode driver). In further embodiments, irregular kernels received from the client can be processed. In such embodiments, a clustering unit clusters sparse kernels and facilitates processing. The clustering unit includes a relative address table implemented to indicate the location of kernel elements within memory. The kernel elements are multiplied with entries in a feature map.

[0037] In the following description, numerous specific details are set forth to provide a more comprehensive understanding. However, it will be apparent to those skilled in the art that the embodiments described herein may be practiced without one or more of these specific details. In other instances, well-known features are not described to avoid obscuring the details of the present embodiments.

[0038] Figure 11 is a block diagram illustrating a computer system 100 configured to implement one or more aspects of the embodiments described herein. Computing system 100 includes a processing subsystem 101 having one or more processors 102 and system memory 104, the one or more processors and the system memory communicating via an interconnect path that may include a memory hub 105. Memory hub 105 may be a separate component within a chipset assembly or integrated within one or more processors 102. Memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. I / O subsystem 111 includes an I / O hub 107, which enables computing system 100 to receive input from one or more input devices 108. Additionally, I / O hub 107 enables a display controller (which may be included in one or more processors 102) to provide output to one or more display devices 110A. In one embodiment, the one or more display devices 110A coupled to I / O hub 107 may include a local display device, an internal display device, or an embedded display device.

[0039] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112, which are coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standard-based communication link technologies or protocols (such as, but not limited to, PCI Express), or a vendor-specific communication interface or communication structure. In one embodiment, the one or more parallel processors 112 form a compute-centric parallel or vector processing system that includes a large number of processing cores and / or processing clusters such as integrated many-core (MIC) processors. In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one of one or more display devices 110A coupled via the I / O hub 107. The one or more parallel processors 112 can also include a display controller and display interface (not shown) to enable direct connection to one or more display devices 110B.

[0040] Within the I / O subsystem 111, a system storage unit 114 can be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. An I / O switch 116 can be used to provide an interface mechanism to enable connections between the I / O hub 107 and other components that can be integrated into the platform, such as a network adapter 118 and / or a wireless network adapter 119, as well as various other devices that can be added via one or more plug-in devices 120. The network adapter 118 can be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices that include one or more radio devices.

[0041] Computing system 100 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 107 . Figure 1 The communication paths interconnecting the various components can be implemented using any suitable protocol such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express), or (multiple) any other bus or point-to-point communication interface and / or protocol such as the NV-Link high-speed interconnect or interconnect protocols known in the art.

[0042] In one embodiment, one or more parallel processors 112 incorporate circuits optimized for graphics and video processing, including, for example, video output circuits, and the circuits constitute a graphics processing unit (GPU). In another embodiment, one or more parallel processors 112 incorporate circuits optimized for general-purpose processing while retaining the basic computing architecture described in more detail herein. In yet another embodiment, the components of the computing system 100 can be integrated with one or more other system elements on a single integrated circuit. For example, one or more parallel processors 112, memory hub 105, (multiple) processors 102, and I / O hub 107 can be integrated into a system-on-chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 can be integrated into a single package to form a system-in-package (SIP) configuration. In other embodiments, at least a portion of the components of the computing system 100 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules to form a modular computing system.

[0043] It should be understood that the computing system 100 shown herein is illustrative and that variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of processor(s) 102, and the number of parallel processor(s) 112, can be modified as needed. For example, in some embodiments, the system memory 104 is connected to the processor(s) 102 directly rather than through a bridge, while other devices communicate with the system memory 104 via the memory hub 105 and the processor(s) 102. In other alternative topologies, the parallel processor(s) 112 are connected to the I / O hub 107 or directly to one of the one or more processors 102 rather than to the memory hub 105. In other embodiments, the I / O hub 107 and the memory hub 105 can be integrated into a single chip. Some embodiments may include two or more groups of processor(s) 102 attached via multiple sockets, which may be coupled to two or more instances of the parallel processor(s) 112.

[0044] Some specific components shown herein are optional and may not be included in all implementations of computing system 100. For example, any number of plug-in cards or peripheral devices may be supported, or some components may be omitted. In addition, some architectures may use different terminology to describe the components associated with the computing system 100. Figure 1 For example, in some architectures, memory hub 105 may be referred to as a north bridge, while I / O hub 107 may be referred to as a south bridge.

[0045] Figure 2A A parallel processor 200 according to an embodiment is shown. The various components of the parallel processor 200 may be implemented using one or more integrated circuit devices such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). According to an embodiment, the parallel processor 200 shown is Figure 1 A variation of one or more parallel processors 112 is shown.

[0046] In one embodiment, parallel processor 200 includes a parallel processing unit (PPU) 202. The PPU includes an I / O unit 204 that enables communication with other devices, including other instances of PPU 202. I / O unit 204 can be directly connected to other devices. In one embodiment, I / O unit 204 connects to other devices via the use of a hub or switch interface, such as memory hub 105. The connection between memory hub 105 and I / O unit 204 forms communication link 113. Within PPU 202, I / O unit 204 is connected to a host interface 206 that receives commands related to performing processing operations and a memory crossbar switch 216 that receives commands related to performing memory operations.

[0047] When host interface 206 receives command buffers via I / O unit 204, host interface 206 can direct work operations for executing those commands to front end 208. In one embodiment, front end 208 is coupled to scheduler 210, which is configured to distribute commands or other work items to processing cluster array 212. In one embodiment, scheduler 210 ensures that processing cluster array 212 is properly configured and in a valid state before distributing tasks to processing clusters in processing cluster array 212.

[0048] Processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B, through cluster 214N). Each cluster 214A through 214N of processing cluster array 212 may execute a large number of concurrent threads. Scheduler 210 may use various scheduling and / or work distribution algorithms to distribute work to clusters 214A through 214N of processing cluster array 212, which may vary depending on the workload induced by each type of program or computation. Scheduling may be handled dynamically by scheduler 210 or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by processing cluster array 212.

[0049] In one embodiment, different clusters 214A through 214N of processing cluster array 212 may be assigned to process different types of programs or to perform different types of calculations.

[0050] Processing cluster array 212 can be configured to perform various types of parallel processing operations. In one embodiment, processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, processing cluster array 212 can include logic for performing processing tasks including filtering of video and / or audio data, and / or modeling operations including physics operations, as well as performing data transformations.

[0051] In one embodiment, processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where parallel processors 200 are configured to perform graphics processing operations, processing cluster array 212 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In addition, processing cluster array 212 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. Parallel processing units 202 may transfer data from system memory via I / O units 204 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 222) during processing and then written back to system memory.

[0052] In one embodiment, when parallel processing unit 202 is used to perform graphics processing, scheduler 210 can be configured to divide the processing workload into tasks of approximately equal size to better enable the distribution of graphics processing operations to multiple clusters 214A to 214N of processing cluster array 212. In some embodiments, portions of processing cluster array 212 can be configured to perform different types of processing. For example, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. Intermediate data generated by one or more of clusters 214A to 214N can be stored in a buffer to allow the intermediate data to be transferred between clusters 214A to 214N for further processing.

[0053] During operation, the processing cluster array 212 may receive processing tasks to be executed via the scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, a processing task may include data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and an index of commands (e.g., which program to execute) that define how the data is to be processed. The scheduler 210 may be configured to obtain an index corresponding to a task or may receive an index from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured to be in a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0054] Each of the one or more instances of parallel processing unit 202 can be coupled to parallel processor memory 222. Parallel processor memory 222 can be accessed via memory crossbar switch 216, which can receive memory requests from processing cluster array 212 and I / O unit 204. Memory crossbar switch 216 can access parallel processor memory 222 via memory interface 218. Memory interface 218 can include multiple partition units (e.g., partition unit 220A, partition unit 220B, through partition unit 220N), each of which can be coupled to a portion of parallel processor memory 222 (e.g., memory cells). In one implementation, the number of partition units 220A through 220N is configured to be equal to the number of memory cells, such that the first partition unit 220A has a corresponding first memory cell 224A, the second partition unit 220B has a corresponding memory cell 224B, and the Nth partition unit 220N has a corresponding Nth memory cell 224N. In other embodiments, the number of partition units 220A through 220N may not be equal to the number of memory devices.

[0055] In various embodiments, memory units 224A through 224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, memory units 224A through 224N may also include 3D stacked memory, including, but not limited to, high bandwidth memory (HBM). Those skilled in the art will appreciate that the specific implementation of memory units 224A through 224N may vary and may be selected from a variety of conventional designs. Render targets, such as frame buffers or texture maps, may be stored on memory units 224A through 224N, allowing partition units 220A through 220N to write to portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 222. In some embodiments, to support a unified memory design that utilizes system memory along with local cache memory, the local instance of parallel processor memory 222 may be excluded.

[0056] In one embodiment, any of the clusters 214A to 214N of the processing cluster array 212 can process data to be written to any of the memory units 224A to 224N within the parallel processor memory 222. The memory crossbar 216 can be configured to pass the output of each cluster 214A to 214N to any partition unit 220A to 220N or another cluster 214A to 214N, which can perform additional processing operations on the output. Each cluster 214A to 214N can communicate with a memory interface 218 via the memory crossbar 216 to perform read or write operations to various external memory devices. In one embodiment, the memory crossbar 216 can be connected to the memory interface 218 to communicate with the I / O unit 204 and to a local instance of the parallel processor memory 222, thereby enabling processing units within different processing clusters 214A to 214N to communicate with system memory or other memory that is not local to the parallel processing unit 202. In one embodiment, the memory crossbar 216 may use virtual channels to separate traffic flows between the clusters 214A through 214N and the partition units 220A through 220N.

[0057] Although a single instance of parallel processing unit 202 is shown within parallel processor 200, any number of instances of parallel processing unit 202 may be included. For example, multiple instances of parallel processing unit 202 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. Different instances of parallel processing unit 202 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor storage, and / or other configuration differences. For example, and in one embodiment, some instances of parallel processing unit 202 may include higher precision floating point units relative to other instances. Systems incorporating one or more instances of parallel processing unit 202 or parallel processor 200 may be implemented in a variety of configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0058] Figure 2B is a block diagram of the partition unit 220 according to an embodiment. In one embodiment, the partition unit 220 is Figure 2A2. As shown, partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and a ROP 226 (raster operation unit). L2 cache 221 is a read / write cache that is configured to execute load and store operations received from memory crossbar 216 and ROP 226. Read misses and urgent write-back requests are output by L2 cache 221 to frame buffer interface 225 for processing. Dirty updates can also be sent to the frame buffer via frame buffer interface 225 for opportunistic processing. In one embodiment, frame buffer interface 225 interacts with one of the memory units in parallel processor memory, such as memory units 224A to 224N of FIG. 2 (e.g., within parallel processor memory 222).

[0059] In graphics applications, ROP 226 is a processing unit that performs raster operations such as stenciling, z-testing, and blending. ROP 226 then outputs processed graphics data, which is stored in graphics memory. In some embodiments, ROP 226 includes compression logic for compressing z or color data written to memory and decompressing z or color data read from memory. In some embodiments, ROP 226 is included within each processing cluster (e.g., clusters 214A to 214N in FIG. 2 ) rather than within partition unit 220. In such embodiments, read and write requests for pixel data are transmitted through memory crossbar 216 rather than pixel fragment data.

[0060] The processed graphic data can be displayed on a display device such as Figure 1 to one of the one or more display devices 110, routed by the processor(s) 102 for further processing, or by Figure 2A One of the processing entities within parallel processor 200 is routed for further processing.

[0061] Figure 2C2 is a block diagram of a processing cluster 214 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 214A to 214N of Figure 2. The processing cluster 214 can be configured to execute multiple threads in parallel, where the term "thread" refers to an instance of a specific program executed on a specific input data set. In some embodiments, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, single instruction multiple thread (SIMT) technology is used to use a public instruction unit configured to issue instructions to a group of processing engines within each of the processing clusters to support the parallel execution of a large number of roughly synchronized threads. Unlike the SIMD execution mechanism in which all processing engines typically execute the same instruction, SIMT execution allows different threads to more easily follow the divergent execution path that passes through a given thread program. Those skilled in the art will understand that the SIMD processing mechanism represents a functional subset of the SIMT processing mechanism.

[0062] The operation of the processing cluster 214 can be controlled via a pipeline manager 232 that distributes processing tasks to the SIMT parallel processors. The pipeline manager 232 receives instructions from the scheduler 210 of FIG. 2 and manages the execution of those instructions via the graphics multiprocessor 234 and / or the texture unit 236. The illustrated graphics multiprocessor 234 is an illustrative example of a SIMT parallel processor. However, various types of SIMT parallel processors with different architectures can be included in the processing cluster 214. One or more instances of the graphics multiprocessor 234 can be included in the processing cluster 214. The graphics multiprocessor 234 can process data, and the data crossbar 240 can be used to distribute the processed data to one of multiple possible destinations, including other shading units. The pipeline manager 232 can facilitate the distribution of the processed data by specifying a destination for the data to be distributed via the data crossbar 240.

[0063] Each graphics multiprocessor 234 within a processing cluster 214 may include the same set of function execution logic (e.g., arithmetic logic unit, load-store unit, etc.). The function execution logic may be configured in a pipelined manner, where a new instruction may be issued before the previous instruction has completed. The function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and calculations of various algebraic functions. In one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0064] Instructions transmitted to the processing cluster 214 constitute threads. A group of threads executing on a set of parallel processing engines is a thread group. A thread group executes the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 234. A thread group can include fewer threads than the number of processing engines within the graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle in which the thread group is being processed. A thread group can also include more threads than the number of processing engines within the graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines within the graphics multiprocessor 234, processing can be performed on consecutive clock cycles. In one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 234.

[0065] In one embodiment, the graphics multiprocessor 234 includes internal cache memory for performing load and store operations. In one embodiment, the graphics multiprocessor 234 can forgo the internal cache and instead use cache memory (e.g., L1 cache 308) within the processing cluster 214. Each graphics multiprocessor 234 can also access an L2 cache within a partition unit (e.g., partition units 220A to 220N of FIG. 2 ) that is shared between all processing clusters 214 and can be used to pass data between threads. The graphics multiprocessor 234 can also access off-chip global memory, which can include one or more of the local parallel processor memory and / or system memory. Any memory external to the parallel processing unit 202 can be used as global memory. Embodiments in which the processing cluster 214 includes multiple instances of the graphics multiprocessor 234 can share common instructions and data that can be stored in the L1 cache 308.

[0066] Each processing cluster 214 may include an MMU 245 (memory management unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of the MMU 245 may reside within the memory interface 218 of FIG. 2 . The MMU 245 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (more commonly referred to as tiles) and, optionally, cache line indexes. The MMU 245 may include a translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 234 or L1 cache or processing cluster 214. Physical addresses are processed to distribute surface data access locality to achieve efficient request interleaving between partition units. The cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0067] In graphics and compute applications, the processing clusters 214 can be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown) or, in some embodiments, from an L1 cache within the graphics multiprocessor 234 and retrieved from an L2 cache, local parallel processor memory, or system memory as needed. Each graphics multiprocessor 234 outputs processed tasks to a data crossbar 240 to provide the processed tasks to another processing cluster 214 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 216. A preROP 242 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 234 and direct the data to ROP units, which can be located using partition units (e.g., partition units 220A through 220N of FIG. 2 ) as described herein. The preROP 242 unit optimizes color blending, organizes pixel color data, and performs address translation.

[0068] It should be understood that the core architecture described herein is illustrative and that variations and modifications are possible. Any number of processing units, such as graphics multiprocessor 234, texture unit 236, preROP 242, etc., may be included within processing cluster 214. Furthermore, while only one processing cluster 214 is shown, the parallel processing unit described herein may include any number of instances of processing cluster 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 cache, etc.

[0069] Figure 2D A graphics multiprocessor 234 is shown according to one embodiment. In such an embodiment, the graphics multiprocessor 234 is coupled to the pipeline manager 232 of the processing cluster 214. The graphics multiprocessor 234 has an execution pipeline that includes, but is not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0070] In one embodiment, the instruction cache 252 receives a stream of instructions to be executed from the pipeline manager 232. These instructions are cached in the instruction cache 252 and dispatched for execution by the instruction unit 254. The instruction unit 254 can dispatch instructions as thread groups (e.g., warps), with each thread of the thread group being assigned to a different execution unit within the GPGPU core 262. Instructions can access any of the local, shared, or global address spaces by specifying an address within the unified address space. The address mapping unit 256 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 266.

[0071] The register file 258 provides a set of registers for the functional units of the graphics multiprocessor 324. The register file 258 provides temporary storage for operands for the data paths of the functional units (e.g., the GPGPU core 262, the load / store unit 266) connected to the graphics multiprocessor 324. In one embodiment, the register file 258 is divided between each of the functional units so that each functional unit is allocated a dedicated portion of the register file 258. In one embodiment, the register file 258 is divided between the different warps being executed by the graphics multiprocessor 324.

[0072] The GPGPU cores 262 may each include a floating point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 324. Depending on the embodiment, the architecture of the GPGPU cores 262 may be similar or different. For example, and in one embodiment, the first portion of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while the second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 floating-point arithmetic standard or enable variable-precision floating-point arithmetic. In addition, the graphics multiprocessor 324 may also include one or more fixed-function or special-function units for performing specific functions such as copying rectangles or pixel blending operations. In one embodiment, one or more of the GPGPU cores may also include fixed-function or special-function logic.

[0073] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 324 to the register file 258 and the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to perform load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, so data transfer between the GPGPU core 262 and the register file 258 has very low latency. The shared memory 270 can be used to facilitate communication between threads executing on the functional units within the graphics multiprocessor 234. For example, the cache memory 272 can be used as a data cache to cache texture data communicated between the functional units and the texture unit 236. The shared memory 270 can also be used as a cached managed program. In addition to the automatically cached data stored in the cache memory 272, threads executing on the GPGPU core 262 can also programmatically store data in the shared memory.

[0074] Figures 3A to 3B Additional graphics multiprocessors are shown according to an embodiment. The graphics multiprocessors 325, 350 shown are Figure 2C The illustrated graphics multiprocessors 325, 350 may be configured as streaming multiprocessors (SMs) capable of executing a large number of execution threads simultaneously.

[0075] Figure 3A A graphics multiprocessor 325 is shown according to an additional embodiment. The graphics multiprocessor 325 includes Figure 2D The graphics multiprocessor 325 may include multiple additional instances of execution resource units of the graphics multiprocessor 234. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A-332B, register files 334A-334B, and texture unit(s) 344A-344B. The graphics multiprocessor 325 may also include multiple sets of graphics or compute execution units (e.g., GPGPU cores 336A-336B, GPGPU cores 337A-337B, GPGPU cores 338A-338B) and multiple sets of load / store units 340A-340B. In one embodiment, the execution resource units have a common instruction cache 330, texture and / or data cache memory 342, and shared memory 346. The various components may communicate via an interconnect fabric 327. In one embodiment, the interconnect fabric 327 includes one or more crossbar switches to enable communication between the various components of the graphics multiprocessor 325.

[0076] Figure 3B A graphics multiprocessor 350 is shown according to an additional embodiment. Figure 2D and Figure 3A As shown, the graphics processor includes multiple sets of execution resources 356A to 356D, each of which includes multiple instruction units, register files, GPGPU cores, and load-store units. The execution resources 356A to 356D can work with (multiple) texture units 360A to 360D to perform texture operations while sharing an instruction cache 354 and a shared memory 362. In one embodiment, the execution resources 356A to 356D can share multiple instances of the instruction cache 354 and the shared memory 362 as well as texture and / or data cache memories 358A to 358B. Various components can be connected to the graphics processor via the CPU. Figure 3A The interconnect structure 327 communicates with a similar interconnect structure 352 .

[0077] Those skilled in the art will understand that Figure 1 、 Figures 2A to 2D and Figures 3A to 3B The architecture described in the accompanying drawings is illustrative and does not limit the scope of the embodiments of the present invention. Therefore, the techniques described herein can be implemented on any appropriately configured processing unit, including but not limited to: one or more mobile application processors; one or more desktop or server central processing units (CPUs), including multi-core CPUs; one or more parallel processing units such as parallel processing unit 202 of FIG. 2; and one or more graphics processors or special-purpose processing units, without departing from the scope of the embodiments described herein.

[0078] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0079] Technologies for GPU to host processor interconnect

[0080] Figure 4AAn exemplary architecture is shown in which multiple GPUs 410 to 413 are communicatively coupled to multiple multi-core processors 405 to 406 via high-speed links 440 to 443 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, the high-speed links 440 to 443 support 4 GB / s, 30 GB / s, 80 GB / s, or higher communication throughput, depending on the implementation. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the underlying principles of the present invention are not limited to any particular communication protocol or throughput.

[0081] Furthermore, in one embodiment, two or more of the GPUs 410-413 are interconnected via high-speed links 444-445, which may be implemented using the same or different protocols / links as used for high-speed links 440-443. Similarly, two or more of the multi-core processors 405-406 may be connected via high-speed link 433, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, Figure 4A All communications between the various system components shown in can be accomplished using the same protocol / links (eg, through a common interconnect structure). However, as mentioned, the underlying principles of the invention are not limited to any particular type of interconnect technology.

[0082] In one embodiment, each multi-core processor 405-406 is communicatively coupled to processor memory 401-402 via memory interconnects 430-431, respectively, and each GPU 410-413 is communicatively coupled to GPU memory 420-423 via GPU memory interconnects 450-453, respectively. Memory interconnects 430-431 and 450-453 can utilize the same or different memory access technologies. By way of example and not limitation, processor memory 401-402 and GPU memory 420-423 can be volatile memory such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memory such as 3D XPoint or Nano-Ram. In one embodiment, a portion of the memory can be volatile memory, while another portion can be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0083] As described below, although the various processors 405-406 and GPUs 410-413 may each be physically coupled to a specific memory 401-402, 420-423, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed across all of the various physical memories. For example, the processor memories 401-402 may each include 64GB of system memory address space, and the GPU memories 420-423 may each include 32GB of system memory address space (resulting in a total of 256GB of addressable memory space in the described example).

[0084] Figure 4B 4 shows additional details of the interconnection between the multi-core processor 407 and the graphics acceleration module 446 according to one embodiment. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card coupled to the processor 407 via the high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0085] The processor 407 shown includes a plurality of cores 460A to 460D, each of which has a translation lookaside buffer 461A to 461D and one or more caches 462A to 462D. These cores may include various other components (e.g., instruction fetch units, branch prediction units, decoders, execution units, reorder buffers, etc.) for executing instructions and processing data not shown to avoid obscuring the basic principles of the present invention. Caches 462A to 462D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 426 may be included in the cache hierarchy and shared by each group of cores 460A to 460D. For example, one embodiment of the processor 407 includes 24 cores, each of which has its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 cache and the L3 cache is shared by two adjacent cores. The processor 407 and the graphics accelerator integrated module 446 are connected to the system memory 441 , which may include the processor memories 401 to 402 .

[0086] Coherence is maintained for data and instructions stored in the various caches 462A-462D, 456, and system memory 441 via inter-core communication via a coherence bus 464. For example, each cache may have associated cache coherence logic / circuitry to communicate via the coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented via the coherence bus 464 to snoop cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art, and to avoid obscuring the underlying principles of the present invention, they are not described in detail herein.

[0087] In one embodiment, the proxy circuit 425 communicatively couples the graphics acceleration module 446 to the coherence bus 464, thereby allowing the graphics acceleration module 446 to participate in the cache coherence protocol as a peer of the core. Specifically, the interface 435 provides connectivity to the proxy circuit 425 via a high-speed link 440 (e.g., a PCIe bus, NVLink, etc.), and the interface 437 connects the graphics acceleration module 446 to the link 440.

[0088] In one implementation, the accelerator integrated circuit 436 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 431, 432, 43N of the graphics acceleration module 446. The graphics processing engines 431, 432, 43N can each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, 43N can include different types of graphics processing engines such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a block image transfer engine within the GPU. In other words, the graphics acceleration module can be a GPU having multiple graphics processing engines 431, 432, 43N, or the graphics processing engines 431 to 432, 43N can be separate GPUs integrated on a common package, line card, or chip.

[0089] In one embodiment, the accelerator integrated circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions such as virtual-to-physical memory translation (also known as effective-to-real memory translation) and memory access protocols for accessing system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, cache 438 stores commands and data for efficient access by graphics processing engines 431 to 432, 43N. In one embodiment, data stored in cache 438 and graphics memory 433 to 434, 43N is kept consistent with core caches 462A to 462D, 456, and system memory 411. As mentioned, this can be accomplished via proxy circuitry 425, which participates in cache coherence mechanisms on behalf of cache 438 and memories 433 to 434, 43N (e.g., sending updates to cache 438 related to modifications / accesses of cache lines on processor caches 462A to 462D, 456 and receiving updates from cache 438).

[0090] A set of registers 445 stores context data for threads executed by graphics processing engines 431 to 432, 43N, and context management circuitry 448 manages thread contexts. For example, context management circuitry 448 can perform save and restore operations to save and restore the contexts of various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, upon context switching, context management circuitry 448 can store current register values ​​to a designated area in memory (e.g., identified by a context pointer). The context management circuitry can restore register values ​​upon returning to context. In one embodiment, interrupt management circuitry 447 receives and processes interrupts received from system devices.

[0091] In one implementation, the virtual / effective addresses from the graphics processing engine 431 are translated into real / physical addresses in the system memory 411 by the MMU 439. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator module 446 can be dedicated to a single application executing on the processor 407, or can be shared among multiple applications. In one embodiment, a virtual graphics execution environment is presented in which the resources of the graphics processing engines 431 to 432, 43N are shared with multiple applications or virtual machines (VMs). The resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0092] Thus, the accelerator integrated circuit acts as a bridge to the system for the graphics acceleration module 446 and provides address translation and system memory cache services. In addition, the accelerator integrated circuit 436 can provide virtualization facilities for the host processor to manage virtualization of the graphics processing engine, interrupts, and memory management.

[0093] Because the hardware resources of the graphics processing engines 431-432, 43N are explicitly mapped into the real address space seen by the host processor 407, any host processor can directly address these resources using effective address values. In one embodiment, one function of the accelerator integrated circuit 436 is the physical separation of the graphics processing engines 431-432, 43N so that they appear to the system as independent units.

[0094] As mentioned, in the illustrated embodiment, one or more graphics memories 433-434, 43M are coupled to each of the graphics processing engines 431-432, 43N, respectively. Graphics memories 433-434, 43M store instructions and data being processed by each of the graphics processing engines 431-432, 43N. Graphics memories 433-434, 43M can be volatile memory such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory such as 3D XPoint or Nano-Ram.

[0095] In one embodiment, to reduce data traffic on link 440, a biasing technique is used to ensure that the data stored in graphics memory 433 to 434, 43M is the data most frequently used by graphics processing engines 431 to 432, 43N and preferably not used (at least not frequently) by cores 460A to 460D. Similarly, the biasing mechanism attempts to keep data needed by the cores (and preferably not the graphics processing engines 431 to 432, 43N) within the caches 462A to 462D, 456 of the core and system memory 411.

[0096] Figure 4C Another embodiment is shown in which the accelerator integrated circuit 436 is integrated into the processor 407. In this embodiment, the graphics processing engines 431 to 432, 43N communicate directly with the accelerator integrated circuit 436 via the interface 437 and the interface 435 via the high-speed link 440 (which may also utilize any form of bus or interface protocol). The accelerator integrated circuit 436 can perform operations related to Figure 4B The same operations are described, but given their close proximity to the coherency bus 462 and caches 462A to 462D, 426, may operate at a higher throughput.

[0097] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The shared programming model can include a programming model controlled by the accelerator integrated circuit 436 and a programming model controlled by the graphics acceleration module 446.

[0098] In one embodiment of a dedicated process model, graphics processing engines 431 to 432, 43N are dedicated to a single application or process under a single operating system. A single application can funnel other application requests to graphics engines 431 to 432, 43N, thereby providing virtualization within a VM / partition.

[0099] In a dedicated process programming model, graphics processing engines 431 to 432, 43N can be shared by multiple VM / application partitions. This shared model requires a hypervisor, which virtualizes graphics processing engines 431 to 432, 43N to allow access by each operating system. In a single-partition system without a hypervisor, graphics processing engines 431 to 432, 43N are owned by the operating system. In both cases, the operating system can virtualize graphics processing engines 431 to 432, 43N to provide access to each process or application.

[0100] For the shared programming model, the graphics acceleration module 446 or the individual graphics processing engines 431 to 432, 43N use a process handle to select a process element. In one embodiment, process elements are stored in system memory 411 and can be addressed using the effective address to real address translation techniques described herein. The process handle can be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 431 to 432, 43N (i.e., calling system software to add a process element to the process element linked list). The lower 16 bits of the process handle can be the offset of the process element within the process element linked list.

[0101] Figure 4D An exemplary accelerator integrated slice 490 is shown. As used herein, a "slice" comprises a designated portion of the processing resources of an accelerator integrated circuit 436. An application effective address space 482 within system memory 411 stores process elements 483. In one embodiment, process elements 483 are stored in response to GPU calls 481 from applications 480 executing on processor 407. Process elements 483 contain the processing state of the corresponding application 480. A work descriptor (WD) 484 contained in process element 483 can be a single job requested by the application, or can contain a pointer to a job queue. In the latter case, WD 484 is a pointer to a job request queue in the application address space 482.

[0102] Graphics acceleration module 446 and / or individual graphics processing engines 431-432, 43N may be shared by all or some processes in the system. Embodiments of the present invention include an infrastructure for establishing processing state and sending WD 484 to graphics acceleration module 446 to start a job in a virtual environment.

[0103] In one implementation, a dedicated process programming model is specific to a particular implementation. In this model, a single process owns either the graphics acceleration module 446 or a separate graphics processing engine 431. Because the graphics acceleration module 446 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 436 to obtain the owned partition, and the operating system initializes the accelerator integrated circuit 436 to obtain the owned process when the graphics acceleration module 446 is allocated.

[0104] In operation, the WD fetch unit 491 in the accelerator integrated slice 490 fetches the next WD 484, which includes an indication of work to be performed by one of the graphics processing engines of the graphics acceleration module 446. As shown, data from the WD 484 can be stored in registers 445 and used by the MMU 439, the interrupt management circuit 447, and / or the context management circuit 446. For example, one embodiment of the MMU 439 includes a segment / page walk circuit for accessing the segment / page table 486 within the OS virtual address space 485. The interrupt management circuit 447 can process the interrupt event 492 received from the graphics acceleration module 446. When executing graphics operations, the effective address 493 generated by the graphics processing engines 431 to 432, 43N is converted into a real address by the MMU 439.

[0105] In one embodiment, the same set of registers 445 is replicated for each graphics processing engine 431 to 432, 43N, and / or graphics acceleration module 446, and can be initialized by a hypervisor or operating system. Each of these replicated registers can be included in an accelerator integration slice 490. Table 1 shows exemplary registers that can be initialized by a hypervisor.

[0106] Table 1 - Hypervisor Initialization Registers

[0107] 1 Slice Control Register 2 Real Address (RA) Dispatch Process Area Pointer 3 Authorization mask override register 4 Interrupt vector table entry offset 5 Interrupt vector table entry limit 6 Status Register 7 Logical partition ID 8 Real Address (RA) Manager Accelerator Utilizes Record Pointers 9 Storage Description Register

[0108] Example registers that may be initialized by the operating system are shown in Table 2.

[0109] Table 2 - Operating System Initialization Registers

[0110]

[0111]

[0112] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engine 431 to 432, 43N. The WD contains all the information needed by the graphics processing engine 431 to 432, 43N to complete its work, or the WD may be a pointer to a memory location where the application has set up a command queue for work to be completed.

[0113] Figure 4E 4. The embodiment of the sharing model includes a hypervisor real address space 498 in which a process element list 499 is stored. The hypervisor real address space 498 is accessible via a hypervisor 496 that virtualizes the graphics acceleration module engine of the operating system 495.

[0114] The shared programming model allows all or some processes from all or some partitions in the system to use the graphics acceleration module 446. There are two programming models where the graphics acceleration module 446 is shared by multiple processes and partitions: time-sliced ​​sharing and graphics direct sharing.

[0115] In this model, hypervisor 496 owns graphics acceleration module 446 and makes its functionality available to all operating systems 495. For graphics acceleration module 446 to support hypervisor 496 virtualization, it must adhere to the following requirements: 1) Application job requests must be autonomous (i.e., no state needs to be maintained between jobs), or graphics acceleration module 446 must provide a context save and restore mechanism. 2) Graphics acceleration module 446 guarantees that application job requests will complete within a specified amount of time, including any translation errors, or graphics acceleration module 446 provides the ability to preempt job processing. 3) When operating in a direct sharing programming model, fairness must be guaranteed for graphics acceleration module 446 within the process.

[0116] In one embodiment, for a shared model, application 480 is required to make an operating system 495 system call using a graphics acceleration module 446 type, a work descriptor (WD), an authorization mask register (AMR) value, and a context save / restore region pointer (CSRP). The graphics acceleration module 446 type describes the target acceleration function of the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446 and can take the following forms: a graphics acceleration module 446 command; an effective address pointer to a user-defined structure; an effective address pointer to a command queue; or any other data structure describing the work to be performed by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state for the current process. The value passed to the operating system is similar to the application setting the AMR. If the implementation of the accelerator integrated circuit 436 and graphics acceleration module 446 does not support the User Authorization Mask Override Register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. Before placing the AMR into the process element 483, the hypervisor 496 may optionally apply the current authorization mask override register (AMOR) value. In one embodiment, the CSRP is one of the registers 445 that contains the effective address of an area in the application address space 482 for the graphics acceleration module 446 to save and restore context state. This pointer is optional if state does not need to be saved between jobs or when a job is preempted. The context save / restore area may be plugged into system memory.

[0117] Upon receiving the system call, the operating system 495 can verify that the application 480 is registered and authorized to use the graphics acceleration module 446. The operating system 495 then calls the hypervisor 496 using the information shown in Table 3.

[0118] Table 3 - Parameters of the operating system calling the hypervisor

[0119] 1 Work Descriptor (WD) 2 Authorization Mask Register (AMR) value (may be masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0120] Upon receiving the hypervisor call, the hypervisor 496 may verify that the operating system 495 has registered and is authorized to use the graphics acceleration module 446. The hypervisor 496 then places the process element 483 into the process element linked list for the corresponding graphics acceleration module 446 type. The process element may contain the information shown in Table 4.

[0121] Table 4 - Process element information

[0122] 1 Work Descriptor (WD) 2 Authorization Mask Register (AMR) value (may be masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt vector table, derived from hypervisor call parameters 9 Status register (SR) value 10 Logical Partition ID (LPID) 11 Real Address (RA) Manager Accelerator Utilizes Record Pointers 12 Storage Descriptor Register (SDR)

[0123] In one embodiment, the hypervisor initializes the plurality of accelerator integrated slices 490 of registers 445 .

[0124] like Figure 4F As shown, one embodiment of the present invention employs a unified memory addressable via a common virtual memory address space for accessing physical processor memories 401-402 and GPU memories 420-423. In this implementation, operations executed on GPUs 410-413 utilize the same virtual / effective memory address space to access processor memories 401-402, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion is allocated to second processor memory 402, a third portion is allocated to GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 401-402 and GPU memories 420-423, allowing any processor or GPU to access any physical memory having a virtual address mapped to that memory.

[0125] In one embodiment, bias / coherency management circuitry 494A-494E within one or more of MMUs 439A-439E ensures cache coherency between the caches of the host processor (e.g., 405) and GPUs 410-413, as well as biasing techniques that indicate the physical memory where certain types of data should be stored. Figure 4F , multiple instances of bias / consistency management circuits 494A to 494E are shown, but bias / consistency circuits may also be implemented within an MMU of one or more host processors 405 and / or within an accelerator integrated circuit 436.

[0126] One embodiment allows GPU-attached memory 420-423 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, without the typical performance drawbacks associated with system-wide cache coherence. The ability to access GPU-attached memory 420-423 as system memory without incurring heavy cache coherence overhead provides a favorable operating environment for GPU offloading. This arrangement allows host processor 405 software to set operands and access computation results without the overhead of traditional I / O DMA data copies. These traditional copies involve driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are inefficient relative to simple memory accesses. At the same time, the ability to access GPU-attached memory 420-423 without cache coherence overhead can be critical to the execution time of offloaded computations. For example, in scenarios with a large amount of streaming write-to-memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 410-413. The efficiency of operand setup, result access, and GPU computation all play an important role in determining the effectiveness of GPU offloading.

[0127] In one implementation, the selection between GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which can be a page-granular structure consisting of 1 or 2 bits per GPU-attached memory page (i.e., controlled at the granularity of a memory page). The bias table can be implemented in the stolen memory range of one or more GPU-attached memories 420 to 423, with or without a bias cache in GPUs 410 to 413 (e.g., to cache frequently / recently used bias table entries). Alternatively, the entire bias table can be maintained within the GPU.

[0128] In one implementation, the bias table entry associated with each access to GPU-attached memory 420-423 is accessed before the GPU memory is actually accessed, resulting in the following operations. First, local requests from GPUs 410-413 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 420-423. Local requests from the GPU whose pages are found in the host bias are forwarded to processor 405 (e.g., over a high-speed link as described above). In one embodiment, requests from processor 405 that find the requested page in the host processor bias complete the request like a normal memory read. Alternatively, requests for GPU biased pages can be forwarded to GPUs 410-413. If the GPU is not currently using the page, the GPU can convert the page to the host processor bias.

[0129] The bias state of a page can be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, a hardware-only based mechanism.

[0130] One mechanism for changing the bias state employs an API call (e.g., OpenCL) that in turn calls the GPU device driver, which in turn sends a message (or queues a command descriptor) to the GPU, thereby directing the GPU to change the bias state and, for certain transitions, performs a cache flush operation in the host. The cache flush operation is required for transitions from host processor 405 bias to GPU bias, but not for the reverse transition.

[0131] In one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages uncacheable to host processor 405. To access these pages, processor 405 may request access from GPU 410, which may or may not grant access immediately, depending on the implementation. Therefore, to reduce communication between processor 405 and GPU 410, it is advantageous to ensure that GPU bias pages are pages required by the GPU but not by host processor 405, and vice versa.

[0132] Graphics processing pipeline

[0133] Figure 5 A graphics processing pipeline 500 according to an embodiment is shown. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included in a parallel processing subsystem as described herein, such as the parallel processor 200 of FIG. 2 . In one embodiment, the parallel processor is Figure 12 . As described herein, various parallel processing systems can implement the graphics processing pipeline 500 via one or more instances of a parallel processing unit (e.g., parallel processing unit 202 of FIG. 2 ). For example, a shader unit (e.g., graphics multiprocessor 234 of FIG. 3 ) can be configured to perform the functionality of one or more of a vertex processing unit 504, a tessellation control processing unit 508, a tessellation evaluation processing unit 512, a geometry processing unit 516, and a fragment / pixel processing unit 524. The functionality of the data assembler 502, primitive assemblers 506, 514, 518, tessellation unit 510, rasterizer 522, and raster operation unit 526 can also be performed by other processing engines within a processing cluster (e.g., processing cluster 214 of FIG. 3 ) and corresponding partition units (e.g., partition units 220A through 220N of FIG. 2 ). The graphics processing pipeline 500 can also be implemented using one or more dedicated processing units for a particular function. In one embodiment, one or more portions of graphics processing pipeline 500 may be executed by parallel processing logic within a general-purpose processor (e.g., a CPU). In one embodiment, one or more portions of graphics processing pipeline 500 may access on-chip memory (e.g., parallel processor memory 222 shown in FIG. 2 ) via memory interface 528, which may be an example of memory interface 218 of FIG. 2 .

[0134] In one embodiment, the data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. The data assembler 502 then outputs the vertex data, including vertex attributes, to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes vertex shader programs, thereby lighting and transforming the vertex data as specified by the vertex shader programs. The vertex processing unit 504 reads data stored in cache, local, or system memory for processing vertex data and can be programmed to transform vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0135] A first instance of primitive assembler 506 receives vertex attributes from vertex processing unit 50. Primitive assembler 506 reads the stored vertex attributes as needed and constructs graphics primitives for processing by tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc. as supported by various graphics processing application programming interfaces (APIs).

[0136] The tessellation control processing unit 508 treats the input vertices as control points of a geometry patch. These control points are transformed from an input representation of the patch (e.g., a basis for the patch) into a representation suitable for surface estimation by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 may also calculate tessellation factors for the edges of the geometry patch. The tessellation factors apply to individual edges and quantify the view-dependent level of detail associated with the edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and tessellate the patch into a plurality of geometric primitives, such as lines, triangles, or quadrilaterals, which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the tessellated patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitive.

[0137] A second instance of primitive assembler 514 receives vertex attributes from tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphics primitives for processing by geometry processing unit 516. Geometry processing unit 516 is a programmable execution unit that executes geometry shader programs to transform graphics primitives received from primitive assembler 514 as specified by the geometry shader programs. In one embodiment, geometry processing unit 516 is programmed to tessellate a graphics primitive into one or more new graphics primitives and calculate parameters for rasterizing the new graphics primitives.

[0138] In some embodiments, the geometry processing unit 516 may add or remove elements from the geometry stream. The geometry processing unit 516 outputs parameters and vertices specifying new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphics primitives for processing by the viewport scaling, picking, and clipping unit 520. The geometry processing unit 516 reads data stored in parallel processor memory or system memory to process the geometry data. The viewport scaling, picking, and clipping unit 520 performs clipping, picking, and viewport scaling and outputs the processed graphics primitives to the rasterizer 522. The rasterizer 522 may perform depth picking and other depth-based optimizations. The rasterizer 522 also scan converts the new graphics primitives to generate fragments and outputs these fragments and associated coverage data to the fragment segment / pixel processing unit 524. The rasterizer 522 scan converts the new graphics primitives and outputs the fragments and coverage data to the fragment / pixel processing unit 524.

[0139] The fragment / pixel processing unit 524 is a programmable execution unit configured to execute a fragment shader program or a pixel shader program. The fragment / pixel processing unit 524 transforms the fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 524 can be programmed to perform operations including, but not limited to, texture mapping, shading, blending, texture correction, and perspective correction to produce shaded fragments or pixels that are output to the raster operation unit 526. The fragment / pixel processing unit 524 can read data stored in parallel processor memory or system memory for use in processing fragment data. The fragment or pixel shader program can be configured to shade at a sample, pixel, tile, or other granularity based on the sampling rate configured for the processing unit.

[0140] The raster operation unit 526 is a processing unit that performs raster operations including but not limited to stenciling, z-testing, blending, etc., and outputs pixel data as processed graphics data for storage in graphics memory (e.g., as Figure 1 22 in parallel processor memory 222 for display on one or more display devices 110 or further processing by one or more processors 102 or one of parallel processor(s) 112. In some embodiments, raster operation unit 526 is configured to compress z or color data written to memory and decompress z or color data read from memory.

[0141] Figure 6 An embodiment of a computing device 600 employing a scheduling mechanism that enables direct scheduling of neural network (NN) clients is shown. The computing device 600 (e.g., a smart wearable device, a virtual reality (VR) device, a head-mounted display (HMD), a mobile computer, an Internet of Things (IoT) device, a laptop computer, a desktop computer, a server computer, etc.) can be connected to a computing device 600. Figure 1 The data processing system 100 is the same as that of FIG. 1 , and therefore for the sake of brevity, clarity, and ease of understanding, the above references Figure 1-5 Many of the details described are not further discussed or repeated below. As shown, in one embodiment, computing device 600 is shown hosting a scheduling mechanism (or scheduler) 610.

[0142] As shown, in one embodiment, scheduler 610 may be hosted by GPU 614. However, in other embodiments, scheduler 610 may be hosted by, or part of, firmware of graphics driver 616. In yet another embodiment, scheduler 610 may be hosted by, or part of firmware of central processing unit (“CPU” or “application processor”) 612. For the sake of brevity, clarity, and ease of understanding, throughout the remainder of this document, scheduler 610 may be discussed as part of graphics driver 616; however, embodiments are not limited in this regard.

[0143] In yet another embodiment, the scheduler 610 may be hosted as software or firmware logic by the operating system 606. In yet further embodiments, the scheduler 610 may be partially and simultaneously hosted by multiple components of the computing device 600, such as one or more of the graphics driver 1216, the GPU 614, the GPU firmware, the CPU 612, the CPU firmware, the operating system 606, and / or the like. It is contemplated that the scheduler 610 or one or more of its components may be implemented as hardware, software, and / or firmware.

[0144] Throughout this document, the term "user" may be referred to interchangeably as a "viewer," "observer," "person," "individual," "end-user," and / or the like. It should be noted that throughout this document, terms like "graphics domain" may be referred to interchangeably with "graphics processing unit," "graphics processor," or simply "GPU," and similarly, "GPU domain" or "host domain" may be referred to interchangeably with "computer processing unit," "application processor," or simply "CPU."

[0145] The computing device 600 may include any number and type of communication devices, such as large-scale computing systems (e.g., server computers, desktop computers, etc.), and may further include set-top boxes (e.g., Internet-based cable TV set-top boxes, etc.), devices based on the Global Positioning System (GPS), etc. The computing device 600 may include mobile computing devices used as communication devices, such as cellular phones including smartphones, personal digital assistants (PDAs), tablet computers, laptop computers, e-readers, smart TVs, TV platforms, wearable devices (e.g., glasses, watches, bracelets, smart cards, jewelry, articles of clothing, etc.), media players, etc. For example, in one embodiment, the computing device 600 may include a mobile computing device that utilizes a computer platform hosting an integrated circuit (“IC”), such as a system on a chip (“SoC” or “SOC”), integrating various hardware and / or software components of the computing device 600 on a single chip.

[0146] As shown, in one embodiment, the computing device 600 may include any number and types of hardware and / or software components, such as, but not limited to, a GPU 614, a graphics driver (also referred to as a "GPU driver," "graphics driver logic," "driver logic," a user-mode driver (UMD), UMD, user-mode driver framework (UMDF), UMDF, or simply "driver") 616, a CPU 612, memory 608, network devices, drivers, etc., and input / output (I / O) sources 604 such as a touch screen, touch panel, touchpad, a virtual or conventional keyboard, a virtual or conventional mouse, ports, connectors, etc.

[0147] The computing device 600 may include an operating system (OS) 606 that serves as an interface between the hardware and / or physical resources of the computing device 600 and a user. It is contemplated that the CPU 612 may include one or more processors, such as Figure 1 (multiple) processors 102, and GPU 614 may include one or more graphics processors (or multiple processors).

[0148] It is worth noting that throughout this document, terms like "node," "computing node," "server," "server device," "cloud computer," "cloud server," "cloud server computer," "machine," "host," "device," "computing device," "computer," "computing system," etc. are used interchangeably. It should be further noted that throughout this document, terms like "application," "software application," "program," "software program," "package," "software software package," etc. are used interchangeably. Likewise, throughout this document, terms like "job," "input," "request," "message," etc. are used interchangeably.

[0149] It can be imagined and as reference Figure 1-5 As further described, some of the processes of the graphics pipeline described above are implemented in software, while others are implemented in hardware. The graphics pipeline can be implemented in a graphics coprocessor design, wherein the CPU 612 is designed to work with a GPU 614, which can be included in or co-located with the CPU 612. In one embodiment, the GPU 614 can employ any number and type of conventional software and hardware logic for performing conventional functions related to graphics rendering, as well as novel software and hardware logic for executing any number and type of instructions.

[0150] As mentioned above, the memory 608 may include random access memory (RAM) containing an application database having object information. Figure 1 The memory hub 105 of the CPU 612 can access data in the RAM and forward it to the GPU 614 for graphics pipeline processing. The RAM may include double data rate RAM (DDR RAM), extended data output RAM (EDO RAM), etc. The CPU 612 interacts with the hardware graphics pipeline to share graphics pipeline functions.

[0151] The processed data is stored in a buffer in the hardware graphics pipeline, and state information is stored in memory 608. The resulting image is then passed to an I / O source 604, such as a display component for displaying the image. It is contemplated that the display device can be of various types, such as a cathode ray tube (CRT), a thin film transistor (TFT), a liquid crystal display (LCD), an organic light emitting diode (OLED) array, etc., for displaying information to a user.

[0152] The memory 608 includes a pre-allocated buffer (e.g., frame buffer) area; however, it should be understood by those skilled in the art that the embodiments are not limited thereto and any memory accessible to the lower level graphics pipeline may be used. The computing device 600 may further include a memory device such as the one in FIG. Figure 1 The input / output (I / O) control hub (ICH) 107 mentioned in the figure can serve as one or more I / O sources 604, etc.

[0153] CPU 612 may include one or more processors for executing instructions to perform whatever software routines the computing system implements. Instructions often involve some type of operation performed on data. Both data and instructions may be stored in system memory 608 and any associated caches. Caches are typically designed to have lower latency than system memory 608; for example, caches may be integrated onto the same silicon chip(s) as the processor(s), and / or caches may be constructed with faster static RAM (SRAM) cells, while system memory 608 may be constructed with slower dynamic RAM (DRAM) cells. By tending to store more frequently used instructions and data in cache rather than in system memory 608, the overall performance efficiency of computing device 600 is improved. It is contemplated that in some embodiments, GPU 614 may exist as part of CPU 612 (e.g., part of the physical CPU package), in which case memory 608 may be shared by CPU 612 and GPU 614 or kept separate.

[0154] The system memory 608 may be made available to other components within the computing device 600. For example, in a software program implementation, any data (e.g., input graphics data) received to the computing device 600 from various interfaces (e.g., keyboard and mouse, printer port, local area network (LAN) port, modem port, etc.) or any data retrieved from the internal storage elements (e.g., hard drive) of the computing device 600 is often temporarily queued in the system memory 608 before being operated on by one or more processors. Similarly, data that the software program determines should be sent from the computing device 600 to an external entity through one of the computing system interfaces or should be stored in an internal storage element is often temporarily queued in the system memory 608 before it is sent or stored.

[0155] Further, for example, the ICH may be used to ensure that such data is properly transferred between system memory 608 and its appropriate corresponding computing system interface (and internal storage devices, if the computing system is so designed) and may have a bidirectional point-to-point link between itself and the observed I / O sources / devices 604. Similarly, the MCH may be used to manage multiple competing requests for access to system memory 608 between the CPU 612 and GPU 614, interfaces and internal storage elements, which may occur closely in time with each other.

[0156] I / O sources 604 may include one or more I / O devices implemented to transfer data to and / or from computing device 600 (e.g., a network adapter); or, for large-scale non-volatile storage, to transfer data within computing device 1100 (e.g., a hard drive). User input devices including alphanumeric and other keys may be used to transfer information and command selections to GPU 614. Another type of user input device is a cursor control (such as a mouse, trackball, touch screen, touchpad, or cursor direction keys) for transferring direction information and command selections to GPU 614 and for controlling cursor movement on a display device. The camera and microphone array of computing device 600 may be used to observe gestures, record audio and video, and receive and transmit visual and audio commands.

[0157] The computing device 600 may further include network interface(s) for providing access to networks such as a LAN, a wide area network (WAN), a metropolitan area network (MAN), a personal area network (PAN), Bluetooth, a cloud network, a mobile network (e.g., third generation (3G), fourth generation (4G), etc.), an intranet, the Internet, etc. The network interface(s) may include, for example, a wireless network interface having an antenna (which may represent one or more antennas). The network interface(s) may also include, for example, a wired network interface for communicating with a remote device via a network cable, which may be, for example, an Ethernet cable, a coaxial cable, a fiber optic cable, a serial cable, or a parallel cable.

[0158] The network interface(s) may provide access to a LAN, for example, by conforming to the IEEE 802.11b and / or IEEE 802.11g standards, and / or the wireless network interface may provide access to a personal area network, for example, by conforming to the Bluetooth standard. Other wireless network interfaces and / or protocols may also be supported, including previous and subsequent versions of the standards. In addition to or in lieu of communicating via the wireless LAN standard, the network interface(s) may also provide wireless communication using, for example, a time division multiple access (TDMA) protocol, a global system for mobile communications (GSM) protocol, a code division multiple access (CDMA) protocol, and / or any other type of wireless communication protocol.

[0159] The network interface(s) may include one or more communication interfaces, such as a modem, a network interface card, or other well-known interface devices, such as those used to couple to an Ethernet, token ring, or other type of physical wired or wireless attachment designed to provide, for example, a communication link supporting a LAN or WAN. In this way, the computer system may be coupled to multiple peripheral devices, clients, control planes, consoles, or servers via a conventional network infrastructure, including, for example, an intranet or the Internet.

[0160] It should be understood that for some implementations, it may be preferred to have a system with fewer or more equipment than the examples described above. Therefore, depending on numerous factors such as price constraints, performance requirements, technological improvements or other situations, the configuration of computing device 600 may be different between implementations. The example of electronic device or computer system 600 may include, but is not limited to, mobile device, personal digital assistant, mobile computing device, smart phone, cellular phone, handheld device, one-way pager, two-way pager, messaging device, computer, personal computer (PC), desktop computer, laptop computer, notebook computer, handheld computer, tablet computer, server, server array or server farm (server farm), web server, network server, internet server, workstation, minicomputer, mainframe computer (main frame computer), supercomputer, network appliance (appliance), web appliance, distributed computing system, multiprocessor system, processor-based system, consumer electronics, programmable consumer electronics, television, digital television, set-top box, wireless access point, base station, subscriber station, mobile subscriber center, radio network controller, router, hub, gateway, bridge, switch, machine or combination thereof.

[0161] Embodiments may be implemented as any one or a combination of the following: one or more microchips or integrated circuits interconnected using a motherboard, hardwired logic, software stored by a memory device and executed by a microprocessor, firmware, an application specific integrated circuit (ASIC), and / or a field programmable gate array (FPGA). The term "logic" may include, by way of example, software, hardware, and / or a combination of software and hardware.

[0162] Embodiments may be provided, for example, as a computer program product that may include one or more machine-readable media having machine-executable instructions stored thereon that, when executed by one or more machines such as a computer, a network of computers, or other electronic devices, may cause the one or more machines to perform operations according to the embodiments described herein. Machine-readable media may include, but are not limited to, floppy disks, optical disks, CD-ROMs (compact disk-read only memory), and magneto-optical disks, ROMs, RAMs, EPROMs (erasable programmable read-only memory), EEPROMs (electrically erasable programmable read-only memory), magnetic or optical cards, flash memory, or any other type of medium / machine-readable medium suitable for storing machine-executable instructions.

[0163] Furthermore, embodiments may be downloaded as a computer program product, wherein the program may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) via a communications link (e.g., a modem and / or a network connection) by one or more data signals embodied in and / or modulated by a carrier wave or other propagation medium.

[0164] In one embodiment, GPU 614 workloads submitted by clients are scheduled via a scheduler. In such an embodiment, GPU 614 clients submit workloads via driver 616 and are scheduled based on their priority. Depending on the priority, GPU 614 hardware resources may need to be preempted and the current program pointer stored in order to obtain high priority workloads for its execution queue.

[0165] According to one embodiment, the GPU 614 hardware can be implemented in convolutional neural network (CNN) computations by applying a convolution mathematical operation to a filter to produce an output of the filter. Convolution is a specialized mathematical operation performed by two functions to produce a third function that is a modified version of one of the two original functions. In convolutional network terminology, the first function of the convolution can be called the input, and the second function can be called the convolution kernel. The output can be called a feature map. For example, the input to a convolutional layer can be a multidimensional data array that defines the various color components of the input image. The convolution kernel can be a multidimensional array of parameters, where the parameters are adapted through the training process of the neural network.

[0166] In one embodiment, GPU 614 includes a scheduler 610 for scheduling application clients also via a KMD (kernel mode driver) (e.g., a KMD client). Thus, clients have full and uninterrupted access to all GPU 614 hardware components without waiting and can reference any available memory address. Thus, scheduler 610 can perform direct scheduling of workloads received from direct clients for execution at GPU 614 hardware resources.

[0167] In further embodiments, application clients include clients based on precompiled kernels. Thus, NN clients can precompile compute kernels, submit workloads, and run the precompiled kernels for the workloads. Directly scheduled client workloads are executed with fast turnaround times and low end-to-end execution latency. Based on the workload inputs and the precompiled kernels, GPU 614 can execute those workloads with zero tolerance and high priority.

[0168] Figure 7A An embodiment of a system for direct scheduling is shown. Figure 7A As shown in , client 710 can schedule graphics workloads to scheduler GPU 614 via driver 616 and scheduler 712. Further, pre-compiled NN kernels 720 can schedule workloads directly to GPU 614 via scheduler 610. In such an embodiment, scheduler 610 provides access to GPU 614 hardware resources to pre-compiled NN kernel clients 720 based on priority and submitting client type.

[0169] In a further embodiment, the pre-compiled NN kernel client 720 registers with the graphics driver 616 upon initialization and receives function pointers for submission directly to the GPU 614. In yet a further embodiment, each client 720 includes an input interface (or sensor input) to the GPU 614 that allows the GPU 614 to execute the client workload based on the pre-compiled kernel for the corresponding input. In such an embodiment, the GPU 614 includes a runtime algorithm based on the input from the client 720.

[0170] Figure 7B Another embodiment of a direct scheduling system is shown. In this embodiment, the NN learning module 750 operates as a pre-compiled NN kernel client that provides direct access to the GPU 614 hardware resources via the scheduler 610. In addition, regular clients are provided access to the GPU 614 resources via the graphics driver 616 and the scheduler 712.

[0171] As discussed above, the scheduling mechanism 610 provides direct access to the GPU 614 to execute workloads received from machine learning and NN clients that are optimized based on input and kernels, rather than queuing the workload at the OS level and then going through the driver and traditional scheduler to the GPU 614. However, the kernels received may have sparse elements. Specifically, the supported kernel sizes may not be conventional (e.g., nxn or nxn with several spans).

[0172] According to one embodiment, GPU 614 includes a gathering unit 615 to gather (or irregular convolution) kernels. In one embodiment, kernel 760 can be received from client 720. In this embodiment, gathering unit 770 establishes a relative address table that lists the non-zero numbers in the convolution kernel. In such an embodiment, an offset table is implemented to pick non-zero numbers during processing of the kernel. The implementation of the offset table provides a non-fixed computation time that is linear with respect to the non-zero numbers in the kernel. In a further embodiment, the number of non-zero elements in the kernel can be varied. In order to balance the convolution kernel size and computational requirements, the irregular convolution kernel can be trained with a 0-1 mask to produce a trainable result.

[0173] Figure 7C An embodiment of a feature map of an irregular 2D convolution kernel and a relative address table 785 is shown, which records how the kernel is recorded in the memory. For example, table 785 shows that the data element D0 is stored at location (0,0) in the memory. In one embodiment, the irregular convolution kernel is N-dimensional. For an N-dimensional irregular kernel, the entries in the table can be expressed as:

[0174] "(kernel index 0, kernel index 1, ... kernel index N-1 )data"

[0175] To use an irregular convolution kernel, the feature map 780 data is read and multiplied with the kernel data. To speed up irregular convolution, a specially designed finite state machine (FSM) can be designed. In one embodiment, the FSM includes the following irregular convolution primitive: Irregular_convolution(kernel_base, kernel_items_N, kernel_dimention, feature_base, [list_of_feature_dimention_width]), where kernel_base is the kernel base address; kernel_items_N is the number of non-zero items in the kernel; kernel_dimention is the dimension of the kernel, the total number of KernelIndexs; feature_base is the feature map base address; and [list_of_feature_dimention_width] is the feature width in each dimension, and the list length should be equal to the kernel dimension. As a result of the FSM calculation, the appropriate sequence of non-zero elements is achieved.

[0176] Machine Learning Overview

[0177] Machine learning algorithms are algorithms that can learn based on a set of data. Embodiments of machine learning algorithms can be designed to model high-level abstractions within a dataset. For example, image recognition algorithms can be used to determine which of several categories a given input belongs to; regression algorithms can output a numerical value given an input; and pattern recognition algorithms can be used to generate translated text or perform text-to-speech and / or speech recognition.

[0178] One example type of machine learning algorithm is a neural network. There are many types of neural networks; a simple type of neural network is a feedforward network. A feedforward network can be implemented as an acyclic graph in which nodes are arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer, separated by at least one hidden layer. The hidden layer transforms the input received by the input layer into a representation useful for generating the output in the output layer. The network nodes are fully connected to the nodes in the adjacent layers via edges, but there are no edges between the nodes within each layer. Data received at the nodes of the input layer of the feedforward network is propagated (i.e., "fed forward") to the nodes of the output layer via an activation function, which calculates the state of the nodes in each successive layer of the network based on coefficients ("weights"), which are respectively associated with each of the edges connecting these layers. Depending on the specific model represented by the algorithm being executed, the output from the neural network algorithm can take various forms.

[0179] Before a machine learning algorithm can be used to model a specific problem, the algorithm is trained using a training data set. Training a neural network involves: selecting a network topology; using a set of training data representing the problem being modeled by the network; and adjusting weights until the network model behaves with minimal error for all instances of the training data set. For example, during a supervised learning training process for a neural network, the output generated by the network in response to an input representing an instance in the training data set is compared to the "correct" labeled output for the instance; an error signal representing the difference between the output and the labeled output is calculated; and as the error signal is propagated back through the layers of the network, the weights associated with the connections are adjusted to minimize the error. The network is considered "trained" when the error for each output generated from an instance of the training data set is minimized.

[0180] The accuracy of a machine learning algorithm can be greatly affected by the quality of the dataset used to train it. The training process can be computationally intensive and can require a significant amount of time on conventional general-purpose processors. Consequently, many types of machine learning algorithms are trained using parallel processing hardware. This is particularly useful for optimizing the training of neural networks, as the calculations performed when adjusting the coefficients in a neural network are naturally suited to parallel implementation. In particular, many machine learning algorithms and software applications have been adapted to use parallel processing hardware within general-purpose graphics processing devices.

[0181] Figure 8 800 is a generalized diagram of a machine learning software stack. A machine learning application 802 can be configured to train a neural network using a training dataset or to implement machine intelligence using a trained deep neural network. The machine learning application 802 can include training and inference functionality for the neural network and / or specialized software that can be used to train the neural network prior to deployment. The machine learning application 802 can implement any type of machine intelligence, including, but not limited to, image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

[0182] Hardware acceleration for machine learning applications 802 can be implemented via a machine learning framework 804. The machine learning framework 804 can provide a library of machine learning primitives. Machine learning primitives are the basic operations typically performed by machine learning algorithms. Without the machine learning framework 804, developers of machine learning algorithms would be required to create and optimize the main computational logic associated with the machine learning algorithm, and then re-optimize the computational logic when new parallel processors are developed. Instead, machine learning applications can be configured to use the primitives provided by the machine learning framework 804 to perform the necessary calculations. Exemplary primitives include tensor convolutions, activation functions, and pooling, which are computational operations performed when training convolutional neural networks (CNNs). The machine learning framework 804 can also provide primitives for implementing basic linear algebra subroutines, such as matrix and vector operations, performed by many machine learning algorithms.

[0183] The machine learning framework 804 can process input data received from the machine learning application 802 and generate appropriate input to the computation framework 806. The computation framework 806 can abstract the underlying instructions provided to the GPGPU driver 808 to enable the machine learning framework 804 to utilize hardware acceleration via the GPGPU hardware 810 without requiring the machine learning framework 804 to be intimately familiar with the architecture of the GPGPU hardware 810. In addition, the computation framework 806 can implement hardware acceleration for the machine learning framework 804 across multiple types and generations of GPGPU hardware 810.

[0184] GPGPU machine learning acceleration

[0185] Figure 9 A highly parallel general-purpose graphics processing unit 900 is shown in accordance with an embodiment. In one embodiment, the general-purpose processing unit (GPGPU) 900 can be configured to be particularly efficient in processing the type of computational workload associated with training deep neural networks. Additionally, the GPGPU 900 can be directly linked to other instances of the GPGPU to create a multi-GPU cluster, thereby improving the training speed of particularly deep neural networks.

[0186] GPGPU 900 includes a host interface 902 for connecting to a host processor. In one embodiment, host interface 902 is a PCI Express interface. However, the host interface may also be a vendor-specific communication interface or communication fabric. GPGPU 900 receives commands from the host processor and uses a global scheduler 904 to distribute the execution threads associated with those commands to a set of compute clusters 906A to 906H. Computing clusters 906A to 906H share a cache memory 908. Cache memory 908 can act as a high-level cache within the cache memory within compute clusters 906A to 906H.

[0187] GPGPU 900 includes memory 914A-914B coupled to compute clusters 906A-906H via a set of memory controllers 912A-912B. In various embodiments, memory 914A-914B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory (GRAM), such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, memory units 224A-224N may also include 3D stacked memory, including, but not limited to, high bandwidth memory (HBM).

[0188] In one embodiment, each computing cluster GPLAB06A-H includes a set of graphics multiprocessors, such as Figure 4A The graphics multiprocessor 400 of the compute cluster includes multiple types of integer and floating-point logic units that can perform computational operations at a range of precisions, including precisions suitable for machine learning computations. For example, and in one embodiment, at least a subset of the floating-point units of each of the compute clusters 906A through 906H can be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units can be configured to perform 64-bit floating-point operations.

[0189] Multiple instances of GPGPU 900 can be configured to operate as a computing cluster. The communication mechanisms used by the computing cluster for synchronization and data exchange vary across embodiments. In one embodiment, multiple instances of GPGPU 900 communicate via a host interface 902. In one embodiment, GPGPU 900 includes an I / O hub 908 that couples GPGPU 900 to a GPU link 910, which enables direct connections to other instances of the GPGPU. In one embodiment, GPU link 910 is coupled to a dedicated GPU-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 900. In one embodiment, GPU link 910 is coupled to a high-speed interconnect for transmitting and receiving data to and from other GPGPUs or parallel processors. In one embodiment, multiple instances of GPGPU 900 are located in separate data processing systems and communicate via a network device accessible via host interface 902. In one embodiment, GPU link 910 can also be configured to enable connection to a host processor in addition to or as an alternative to host interface 902.

[0190] While the illustrated configuration of GPGPU 900 can be configured to train neural networks, one embodiment provides an alternative configuration of GPGPU 900 that can be configured for deployment within a high-performance or low-power inference platform. In the inference configuration, GPGPU 900 includes fewer compute clusters 906A-906H relative to the training configuration. Additionally, the memory technology associated with memories 914A-914B can differ between the inference and training configurations. In one embodiment, the inference configuration of GPGPU 900 can support inference-specific instructions. For example, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which are commonly used during inference operations for deployed neural networks.

[0191] Figure 10 A multi-GPU computing system 1000 according to an embodiment is shown. The multi-GPU computing system 1000 may include a processor 1002 coupled to a plurality of GPGPUs 1006A to D via a host interface switch 1004. In one embodiment, the host interface switch 1004 is a PCI Express switch device that couples the processor 1002 to a PCI Express bus, through which the processor 1002 can communicate with the set of GPGPUs 1006A to D. Each of the plurality of GPGPUs 1006A to 1006D may be a Figure 9GPGPU 900. GPGPUs 1006A to D may be interconnected via a set of high-speed point-to-point GPU-GPU links 1016. The high-speed GPU-GPU links may be connected via dedicated GPU links (e.g., Figure 9 1006D. A P2P GPU link 1016 enables direct communication between each of GPGPUs 1006A through 1006D without requiring communication via a host interface bus to which processor 1002 is connected. While GPU-GPU traffic is directed to the P2P GPU link, the host interface bus can still be used for system memory access or communication with other instances of multi-GPU computing system 1000 (e.g., via one or more network devices). While GPGPUs 1006A through 1006D are connected to processor 1002 via host interface switch 1004 in the illustrated embodiment, in one embodiment, processor 1002 includes direct support for P2P GPU link 1016 and can connect directly to GPGPUs 1006A through 1006D.

[0192] Machine Learning Neural Network Implementation

[0193] The computing architecture provided by the embodiments described herein can be configured to perform these types of parallel processing that are particularly well-suited for training and deploying neural networks for machine learning. A neural network can be generalized as a network of functions with graph relationships. As is well known in the art, there are many types of neural network implementations used in machine learning. One exemplary type of neural network is a feedforward network as previously described.

[0194] A second exemplary type of neural network is a convolutional neural network (CNN). A CNN is a specialized feedforward neural network used to process data with a known, grid-like topology (e.g., image data). CNNs are therefore commonly used in computer vision and image recognition applications, but they can also be used for other types of pattern recognition, such as speech and language processing. The nodes in the input layer of a CNN are organized into a set of "filters" (feature detectors inspired by the receptive fields found in the retina), and the output of each set of filters is propagated to nodes in successive layers of the network. The calculations used in a CNN involve applying a mathematical operation called convolution to each filter to produce the output of the filter. Convolution is a specialized mathematical operation performed by two functions to produce a third function that is a modified version of one of the two original functions. In convolutional network terminology, the first function involved in the convolution can be called the input, while the second function can be called the convolution kernel. The output can be called a feature map. For example, the input to a convolutional layer can be a multidimensional data array that defines the various color components of the input image. The convolution kernel can be a multidimensional parameter array, where the parameters are adapted through a training process for the neural network.

[0195] Recurrent neural networks (RNNs) are a type of feedforward neural network that includes feedback connections between layers. RNNs enable modeling of sequence data by sharing parameter data across different parts of the neural network. The architecture of RNNs includes loops. These loops represent the effect of the current value of a variable on its own value at future times, as at least a portion of the output data from the RNN is used as feedback for processing subsequent inputs in the sequence. This feature makes RNNs particularly useful for language processing due to the mutable nature of language data, which can be composed.

[0196] The figures described below present exemplary feedforward, CNN, and RNN networks, and describe the general process for training and deploying each of those types of networks, respectively. It will be understood that these descriptions are exemplary and non-limiting with respect to any specific embodiment described herein, and that the concepts presented can generally be applied to deep neural networks and machine learning techniques in general.

[0197] The exemplary neural network described above can be used to perform deep learning. Deep learning is machine learning performed using deep neural networks. In contrast to shallow neural networks that include only a single hidden layer, deep neural networks used in deep learning are artificial neural networks composed of multiple hidden layers. Deeper neural networks are generally more computationally intensive to train. However, the additional hidden layers of the network enable multi-step pattern recognition, which results in reduced output error compared to shallow machine learning techniques.

[0198] The deep neural networks used in deep learning typically include a front-end network for performing feature recognition coupled to a back-end network representing a mathematical model that can perform operations (e.g., object classification, speech recognition, etc.) based on the feature representations provided to the model. Deep learning enables machine learning to be performed without the need to perform manual feature engineering for the model. Instead, deep neural networks can learn features based on statistical structures or correlations within the input data. The learned features can be provided to a mathematical model that can map the detected features to an output. The mathematical model used by the network is typically dedicated to a specific task to be performed, and different models will be used to perform different tasks.

[0199] Once a neural network is structured, a learning model can be applied to the network to train it to perform a specific task. The learning model describes how to adjust the weights within the model to reduce the network's output error. Backpropagation of error is a common method for training neural networks. An input vector is presented to the network for processing. The network's output is compared to the desired output using a loss function, and an error value is calculated for each neuron in the output layer. These error values ​​are then propagated backward until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then learn from those errors using an algorithm (such as stochastic gradient descent) to update the weights of the neural network.

[0200] Figure 11A and 11B Shows an example convolutional neural network. Figure 11A Show the various layers in CNN. Figure 11A As shown in , an exemplary CNN for modeling image processing can receive an input 1102 that describes the red, green, and blue (RGB) components of an input image. The input 1102 can be processed by multiple convolutional layers (e.g., convolutional layer 1104, convolutional layer 1106). Optionally, the outputs from the multiple convolutional layers can be processed by a set of fully connected layers 1108. The neurons in the fully connected layers have full connections to all activation functions in the previous layer, as previously described for feedforward networks. The outputs from the fully connected layers 1108 can be used to generate output results from the network. Matrix multiplication can be used instead of convolution to calculate the activation functions within the fully connected layers 1108. Not all CNN implementations use fully connected layers 1108. For example, in some implementations, the convolutional layers 1106 can generate the output of the CNN.

[0201] The convolutional layers are sparsely connected, which is different from the traditional neural network configuration found in the fully connected layer 1108. Traditional neural network layers are fully connected so that every output unit interacts with every input unit. However, the convolutional layers are sparsely connected because the output of the convolution of the receptive field (rather than the corresponding state value of each node in the receptive field) is input to the nodes of the subsequent layer, as shown. The kernel associated with the convolutional layer performs a convolution operation, the output of which is sent to the next layer. The dimensionality reduction performed within the convolutional layer is one aspect that enables CNNs to scale to process large images.

[0202] Figure 11B An exemplary computational stage within a convolutional layer of a CNN is shown. Input 1112 to a convolutional layer of the CNN can be processed in three stages within convolutional layer 1114. These three stages can include a convolution stage 1116, a detector stage 1118, and a pooling stage 1120. Convolutional layer 1114 can then output data to a subsequent convolutional layer. The last convolutional layer of the network can generate output feature map data or provide input to a fully connected layer, for example, to generate a classification value for the input to the CNN.

[0203] Several convolutions are performed in parallel in the convolution stage 1116 to produce a set of linear activation functions. The convolution stage 1116 may include an affine transformation, which is any transformation that can be specified as a linear transformation plus a translation. Affine transformations include rotations, translations, scaling, and combinations of these transformations. The convolution stage calculates the output of a function connected to a specific region in the input (e.g., a neuron), which can be determined as a local region associated with the neuron. The neuron calculates the dot product between the neuron's weight and the region in the local input (to which the neuron is connected). The output from the convolution stage 1116 defines a set of linear activation functions that are processed by successive stages of the convolution layer 1114.

[0204] The linear activation function may be processed by the detector stage 1118. In the detector stage 1118, each linear activation function is processed by a nonlinear activation function. Nonlinear activation functions increase the nonlinear nature of the overall network without affecting the receptive field of the convolutional layers. Several types of nonlinear activation functions may be used. One specific type is the rectified linear unit (ReLU), which uses an activation function defined as f(x) = max(0, x), such that the activation function is thresholded to zero.

[0205] The pooling stage 1120 uses a pooling function that replaces the output of the convolutional layer 1106 with a summary statistic of nearby outputs. The pooling function can be used to introduce translation invariance into the neural network so that a slight translation to the input does not change the pooled output. The invariance of local translation can be useful when the presence of features in the input data is more important than the precise location of the features. Various types of pooling functions can be used during the pooling stage 1120, including maximum pooling, average pooling, and L2 norm pooling. In addition, some CNN implementations do not include a pooling stage. Instead, such implementations use an additional convolution stage with an increased stride relative to the previous convolution stage.

[0206] The output from the convolutional layer 1114 may then be processed by the next layer 1122. The next layer 1122 may be an additional convolutional layer or one of the fully connected layers 1108. For example, Figure 11A The first convolutional layer 1104 can output to the second convolutional layer 1106, and the second convolutional layer can output to the first layer in the fully connected layer 1108.

[0207] Figure 12 An exemplary recurrent neural network 1200 is shown. In a recurrent neural network (RNN), the network's previous state influences the output of the network's current state. RNNs can be built in a variety of ways using a variety of functions. The use of RNNs generally revolves around using mathematical models to predict the future based on previous input sequences. For example, RNNs can be used to perform statistical language modeling to predict upcoming words given a previous word sequence. The shown RNN 1200 can be described as having the following: an input layer 1202, which receives an input vector; a hidden layer 1204, which implements a recursive function; a feedback mechanism 1205, which implements a 'memory' of previous states; and an output layer 1206, which outputs a result. RNN 1200 operates based on time steps. The state of the RNN at a given time step is influenced by the previous time step via the feedback mechanism 1205. For a given time step, the state of the hidden layer 1204 is defined by the previous state and the input at the current time step. The initial input (x1) at the first time step can be processed by the hidden layer 1204. The second input (x2) can be processed by the hidden layer 1204 using the state information determined during the processing of the initial input (x1). The given state can be calculated as s t =f(Ux t +Ws t-1), where U and W are parameter matrices. The function is typically nonlinear, such as a variant of the hyperbolic tangent function (Tanh) or a correction function f(x) = max(0, x). However, the specific mathematical function used in hidden layer 1204 may vary depending on the specific implementation details of RNN 1200.

[0208] In addition to the basic CNN and RNN networks described, variations of those networks can also be implemented. An example RNN variant is the long short-term memory (LSTM) RNN. LSTM RNNs are able to learn long-term dependencies that may be necessary to process longer language sequences. A variant of CNN is the convolutional deep belief network, which has a structure similar to a CNN and is trained in a manner similar to a deep belief network. A deep belief network (DBN) is a generative neural network composed of multiple layers of stochastic (random) variables. A DBN can be trained layer by layer using greedy unsupervised learning. The learned weights of the DBN can then be used to provide a pre-trained neural network by determining a set of optimal initial weights for the neural network.

[0209] Figure 13 Demonstrates the training and deployment of a deep neural network. Once a given network has been structured for a task, the neural network is trained using a training dataset 1302. Various training frameworks 1304 have been developed to enable hardware acceleration of the training process. For example, Figure 8 The machine learning framework 804 can be configured as a training framework 1304. The training framework 604 can be hooked up to an untrained neural network 1306 and enable the untrained neural network to be trained using the parallel processing resources described herein to generate a trained neural network 1308.

[0210] To start the training process, initial weights can be chosen randomly or by pre-training with a deep belief network. The training cycle is then performed in a supervised or unsupervised manner.

[0211] Supervised learning is a learning method in which training is performed as an arbitration operation, such as when the training dataset 1302 includes inputs paired with expected outputs for those inputs, or when the training dataset includes inputs with known outputs and the outputs of the neural network are manually graded. The network processes the inputs and compares the resulting outputs to a set of expected or desired outputs. Errors are then backpropagated through the system. The training framework 1304 can be adjusted to adjust the weights of the untrained neural network 1306. The training framework 1304 can provide tools for monitoring the extent to which the untrained neural network 1306 is converging to a model suitable for generating the correct answer based on the known input data. The training process occurs iteratively as the network's weights are adjusted to improve the outputs generated by the neural network. The training process can continue until the neural network reaches a statistically expected accuracy associated with the trained neural network 1308. The trained neural network 1308 can then be deployed to implement any number of machine learning operations.

[0212] Unsupervised learning is a learning method in which a network attempts to train itself using unlabeled data. Therefore, for unsupervised learning, the training data set 1302 will include input data without any associated output data. The untrained neural network 1306 can learn groupings within the unlabeled inputs and can determine how individual inputs relate to the overall data set. Unsupervised training can be used to generate self-organizing maps, which are a type of trained neural network 1307 that can perform operations useful in data dimensionality reduction. Unsupervised training can also be used to perform anomaly detection, which allows for the identification of data points in the input data set that deviate from the normal pattern of the data.

[0213] Variations of supervised and unsupervised training can also be employed. Semi-supervised learning is a technique in which the training dataset 1302 includes a mixture of labeled and unlabeled data from the same distribution. Incremental learning is a variant of supervised learning in which input data is continuously used to further train the model. Incremental learning enables a trained neural network 1308 to adapt to new data 1312 without forgetting the knowledge embedded in the network during initial training.

[0214] The training process for particularly deep neural networks, whether supervised or unsupervised, can be too computationally intensive for a single compute node. The training process can be accelerated by using a distributed network of compute nodes rather than a single compute node.

[0215] Figure 14is a block diagram illustrating distributed learning. Distributed learning is a training model that uses multiple distributed computing nodes to perform supervised or unsupervised training of a neural network. The distributed computing nodes can each include one or more host processors and one or more general processing nodes, such as Figure 9 900. As shown, distributed learning can perform model parallelism 1402, data parallelism 1404, or a combination of model and data parallelism 1404.

[0216] In model parallelism 1402, different computing nodes in a distributed system can perform training computations for different parts of a single network. For example, each layer of a neural network can be trained by a different processing node of the distributed system. Benefits of model parallelism include the ability to scale to extremely large models. Splitting the computations associated with different layers of a neural network enables training of very large neural networks, where the weights for all layers will not fit into the memory of a single computing node. In some instances, model parallelism can be particularly useful in performing unsupervised training of large neural networks.

[0217] In data parallelization 1404, different nodes of the distributed network have complete instances of the model, and each node receives a different portion of the data. The results from the different nodes are then combined. Although different methods for data parallelization are possible, data parallel training methods all require a technique for combining the results and synchronizing the model parameters between each node. Exemplary methods for combining data include parameter averaging and update-based data parallelization. Parameter averaging trains each node on a subset of the training data and sets global parameters (e.g., weights, biases) to the average value of the parameters from each node. Parameter averaging uses a central parameter server that maintains parameter data. Update-based data parallelism is similar to parameter averaging, except that updates to the model are passed instead of passing parameters from the node to the parameter server. In addition, update-based data parallelism can be performed in a decentralized manner, where updates are compressed and passed between nodes.

[0218] For example, combined model and data parallelism 1406 can be implemented in a distributed system where each compute node includes multiple GPUs. Each node can have a complete instance of the model, with separate GPUs within each node used to train different parts of the model.

[0219] Distributed training has increased overhead relative to training on a single machine. However, the parallel processors and GPGPUs described herein can each implement various techniques to reduce the overhead of distributed training, including techniques for enabling high-bandwidth GPU-GPU data transfer and accelerated remote data synchronization.

[0220] Example Machine Learning Applications

[0221] Machine learning can be applied to solve a variety of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. Applications of computer vision range from reproducing human visual capabilities (e.g., recognizing faces) to creating new categories of visual capabilities. For example, a computer vision application can be configured to identify sound waves from vibrations induced in objects visible in a video. Parallel processor-accelerated machine learning enables the use of significantly larger training data sets than were previously feasible to train computer vision applications, and enables the deployment of inference systems using low-power parallel processors.

[0222] Parallel processor-accelerated machine learning has autonomous driving applications, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on datasets that define appropriate responses to specific training inputs. The parallel processors described herein can enable rapid training of increasingly complex neural networks for autonomous driving solutions and enable the deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0223] Deep neural networks accelerated by parallel processors have enabled machine learning methods for automatic speech recognition (ASR). ASR involves creating a function that computes the most likely speech sequence given a sequence of input sounds. Accelerated machine learning using deep neural networks has replaced the hidden Markov models (HMMs) and Gaussian mixture models (GMMs) previously used for ASR.

[0224] Parallel processor-accelerated machine learning can also be used to accelerate natural language processing. Automatic learning programs can use statistical inference algorithms to generate models that are robust to erroneous or unfamiliar inputs. Exemplary natural language processor applications include automatic machine translation between human languages.

[0225] Parallel processing platforms for machine learning can be divided into training platforms and deployment platforms. Training platforms are typically highly parallel and include optimizations for accelerating multi-GPU single-node training and multi-node multi-GPU training. Exemplary parallel processors suitable for training include highly parallel general-purpose graphics processing units and multi-GPU computing systems. In contrast, deployed machine learning platforms typically include low-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0226] Figure 15 An exemplary inference system-on-chip (SOC) 1500 suitable for performing inference using a trained model is shown. The SOC 1500 can integrate multiple processing components, including a media processor 1502, a vision processor 1504, a GPGPU 1506, and a multi-core processor 1508. The SOC 1500 can further include on-chip memory 1505, which can implement a shared on-chip data pool accessible by each of the processing components. The processing components can be optimized for low-power operation to enable deployment to a variety of machine learning platforms (including autonomous vehicles and autonomous robots). For example, an implementation of the SOC 1500 can be used as part of a main control system for an autonomous vehicle. In the case where the SOC 1500 is configured for use in an autonomous vehicle, the SOC is designed and configured to comply with the relevant functional safety standards of the deployment jurisdiction.

[0227] During operation, the media processor 1502 and the vision processor 1504 can work in concert to accelerate computer vision operations. The media processor 1502 can enable low-latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video stream can be written to a buffer in the on-chip memory 1505. The vision processor 1504 can then parse the decoded video and perform preliminary processing operations on the frames of the decoded video in preparation for processing the frames using the trained image recognition model. For example, the vision processor 1504 can accelerate convolution operations for CNN (for performing image recognition on high-resolution video data), while the back-end model calculations are performed by the GPGPU 1506.

[0228] The multi-core processor 1508 may include control logic to facilitate sequencing and synchronization of data transfers and shared memory operations performed by the media processor 1502 and the vision processor 1504. The multi-core processor 1508 may also serve as an application processor for executing software applications that can utilize the inference computing capabilities of the GPGPU 1506. For example, at least a portion of navigation and driving logic may be implemented in software executing on the multi-core processor 1508. Such software may directly issue computational workloads to the GPGPU 1506, or may issue computational workloads to the multi-core processor 1508, which may offload at least a portion of those operations to the GPGPU 1506.

[0229] GPGPU 1506 may include a compute cluster, such as a low-power configuration of compute clusters 906A through 906H within a highly parallel general-purpose graphics processing unit 700. The compute cluster within GPGPU 1506 may support instructions that are explicitly optimized for performing inference computations on trained neural networks. For example, GPGPU 1506 may support instructions for performing low-precision computations (e.g., 8-bit and 4-bit integer vector operations).

[0230] Additional Exemplary Graphics Processing Systems

[0231] Details of the embodiments described above may be included in the graphics processing systems and apparatus described below. Figures 16 to 29 The graphics processing systems and devices of exemplify alternative systems and graphics processing hardware that can implement any and all of the techniques described above.

[0232] Additional Exemplary Graphics Processing System Overview

[0233] Figure 16 16 is a block diagram of a processing system 1600 according to an embodiment. In various embodiments, system 1600 includes one or more processors 1602 and one or more graphics processors 1608, and can be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 1602 or processor cores 1607. In one embodiment, system 1600 is a processing platform incorporated into a system-on-chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device.

[0234] Embodiments of system 1600 may include or be incorporated into a server-based game platform, a game console, including a game and media console, a mobile game console, a handheld game console, or an online game console. In some embodiments, system 1600 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. Data processing system 1600 may also include a wearable device (such as a smart watch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device), be coupled to the wearable device, or be integrated into the wearable device. In some embodiments, data processing system 1600 is a television or set-top box device having one or more processors 1602 and a graphical interface generated by one or more graphics processors 1608.

[0235] In some embodiments, one or more processors 1602 each include one or more processor cores 1607 for processing instructions that, when executed, perform operations of the system and user software. In some embodiments, each processor core in the one or more processor cores 1607 is configured to process a specific instruction set 1609. In some embodiments, the instruction set 1609 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). Multiple processor cores 1607 can each process different instruction sets 1609, which may include instructions for facilitating emulation of other instruction sets. The processor cores 1607 may also include other processing devices, such as a digital signal processor (DSP).

[0236] In some embodiments, the processor 1602 includes a cache memory 1604. Depending on the architecture, the processor 1602 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among the components of the processor 1602. In some embodiments, the processor 1602 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which may be shared among the processor cores 1607 using known cache coherence techniques. Additionally, a register file 1606 is included in the processor 1602, which may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of the processor 1602.

[0237] In some embodiments, processor 1602 is coupled to a processor bus 1610, which is used to transmit communication signals, such as address, data, or control signals, between processor 1602 and other components within system 1600. In one embodiment, system 1600 uses an exemplary 'hub' system architecture, including a memory controller hub 1616 and an input / output (I / O) controller hub 1630. Memory controller hub 1616 facilitates communication between memory devices and other components of system 1600, while I / O controller hub (ICH) 1630 provides connectivity to I / O devices via a local I / O bus. In one embodiment, the logic of memory controller hub 1616 is integrated within the processor.

[0238] Memory device 1620 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device with suitable properties for use as processing memory. In one embodiment, memory device 1620 may operate as system memory for system 1600 to store data 1622 and instructions 1621 for use when one or more processors 1602 execute applications or processes. Memory controller hub 1616 is also coupled to an optional external graphics processor 1612, which may communicate with one or more graphics processors 1608 in processor 1602 to perform graphics and media operations.

[0239] In some embodiments, ICH 1630 connects peripheral components to memory devices 1620 and processor 1602 via a high-speed I / O bus. I / O peripherals include, but are not limited to, an audio controller 1646, a firmware interface 1628, a wireless transceiver 1626 (e.g., Wi-Fi, Bluetooth), a data storage device 1624 (e.g., a hard drive, flash memory, etc.), and a legacy I / O controller 1640 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 1642 connect multiple input devices, such as a keyboard and mouse 1644 combination. A network controller 1634 may also be coupled to ICH 1630. In some embodiments, a high-performance network controller (not shown) is coupled to processor bus 1610. It should be understood that the illustrated system 1600 is exemplary and non-limiting, as other types of data processing systems configured in different ways may also be used. For example, I / O controller hub 1630 may be integrated within one or more processors 1602 , or memory controller hub 1616 and I / O controller hub 1630 may be integrated within a discrete external graphics processor, such as external graphics processor 1612 .

[0240] Figure 17 is a block diagram of an embodiment of a processor 1700 having one or more processor cores 1702A through 1702N, an integrated memory controller 1714 , and an integrated graphics processor 1708 . Figure 17 Those elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. Processor 1700 may include additional cores up to and including additional core 1702N represented by a dashed box. Processor cores 1702A through 1702N each include one or more internal cache units 1704A through 1704N. In some embodiments, each processor core may also have access to one or more shared cache units 1706.

[0241] Internal cache units 1704A to 1704N and shared cache unit 1706 represent a cache memory hierarchy within processor 1700. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache is classified as LLC before external memory. In some embodiments, cache coherence logic maintains coherence between each cache unit 1706 and 1704A to 1704N.

[0242] In some embodiments, the processor 1700 may further include a set of one or more bus controller units 1716 and a system agent core 1710. The one or more bus controller units 1716 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express). The system agent core 1710 provides management functions for various processor components. In some embodiments, the system agent core 1710 includes one or more integrated memory controllers 1714 for managing access to various external memory devices (not shown).

[0243] In some embodiments, one or more of the processor cores 1702A through 1702N include support for simultaneous multithreading. In such embodiments, the system agent core 1710 includes components for coordinating and operating the cores 1702A through 1702N during multithreaded processing. Additionally, the system agent core 1710 may include a power control unit (PCU) that includes logic and components for regulating the power state of the processor cores 1702A through 1702N and the graphics processor 1708.

[0244] In some embodiments, processor 1700 also includes a graphics processor 1708 for performing graphics processing operations. In some embodiments, graphics processor 1708 is coupled to a shared cache unit 1706 and a system agent core 1710, which includes one or more integrated memory controllers 1714. In some embodiments, a display controller 1711 is coupled to graphics processor 1708 to drive graphics processor output to one or more coupled displays. In some embodiments, display controller 1711 can be a separate module coupled to the graphics processor via at least one interconnect, or can be integrated within graphics processor 1708 or system agent core 1710.

[0245] In some embodiments, a ring-based interconnect 1712 is used to couple the internal components of the processor 1700. However, alternative interconnects may be used, such as point-to-point interconnects, switched interconnects, or other technologies, including those well known in the art. In some embodiments, the graphics processor 1708 is coupled to the ring interconnect 1712 via an I / O link 1713.

[0246] Exemplary I / O links 1713 represent at least one of a variety of I / O interconnects, including package I / O interconnects, that facilitate communication between various processor components and high-performance embedded memory modules 1718 (e.g., eDRAM modules). In some embodiments, each of processor cores 1702A through 1702N and graphics processor 1708 utilize embedded memory modules 1718 as a shared last-level cache.

[0247] In some embodiments, processor cores 1702A to 1702N are homogeneous cores that execute the same instruction set architecture. In another embodiment, processor cores 1702A to 1702N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of processor cores 1702A to 1702N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, processor cores 1702A to 1702N are homogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In addition, processor 1700 can be implemented on one or more chips or as a SoC integrated circuit having the components shown in addition to other components.

[0248] Figure 181 is a block diagram of a graphics processor 1800, which may be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates with memory via a mapped I / O interface to registers on the graphics processor and using commands placed in processor memory. In some embodiments, graphics processor 1800 includes a memory interface 1814 for accessing memory. Memory interface 1814 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0249] In some embodiments, the graphics processor 1800 also includes a display controller 1802 for driving display output data to a display device 1820. The display controller 1802 includes hardware for one or more overlapping planes of the display and a composition of multiple layers of video or user interface elements. In some embodiments, the graphics processor 1800 includes a video codec engine 1806 for encoding, decoding, or transcoding media to, from, or between one or more media coding formats, including but not limited to: Moving Picture Experts Group (MPEG) (such as MPEG-2), Advanced Video Coding (AVC) format (such as H.264 / MPEG-4 AVC), and Society of Motion Picture & Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) format (such as JPEG and Motion JPEG (MJPEG) format).

[0250] In some embodiments, graphics processor 1800 includes a block image transfer (BLIT) engine 1804 for performing two-dimensional (2D) rasterizer operations, including, for example, bit-boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 1810. In some embodiments, GPE 1810 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0251] In some embodiments, GPE 1810 includes a 3D pipeline 1812 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that operate on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 1812 includes programmable and fixed functional elements that perform various tasks within components and / or spawned execution threads to 3D / media subsystem 1815. While 3D pipeline 1812 can be used to perform media operations, embodiments of GPE 1810 also include a media pipeline 1816 specifically for performing media operations, such as video post-processing and image enhancement.

[0252] In some embodiments, media pipeline 1816 includes fixed-function or programmable logic units to perform one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, instead of, or on behalf of, video codec engine 1806. In some embodiments, media pipeline 1816 also includes a thread generation unit to generate threads for execution on 3D / media subsystem 1815. The generated threads perform computations for media operations on one or more graphics execution units included in 3D / media subsystem 1815.

[0253] In some embodiments, 3D / media subsystem 1815 includes logic for executing threads generated by 3D pipeline 1812 and media pipeline 1816. In one embodiment, the pipelines send thread execution requests to 3D / media subsystem 1815, which includes thread dispatch logic for arbitrating and dispatching each request to available thread execution resources. Execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, 3D / media subsystem 1815 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) to share data between threads and to store output data.

[0254] Graphics processing engine

[0255] Figure 19 is a block diagram of a graphics processing engine 1910 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 1910 is Figure 18 A version of the GPE 1810 is shown. Figure 19 Elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. Figure 18 1910. The 3D pipeline 1812 and the media pipeline 1816 of the GPE 1910 are shown in FIG. 1910. The media pipeline 1816 is optional in some embodiments of the GPE 1910 and may not be explicitly included within the GPE 1910. For example, and in at least one embodiment, separate media and / or graphics processors are coupled to the GPE 1910.

[0256] In some embodiments, GPE 1910 is coupled to or includes a command streamer 1903, which provides a command stream to 3D pipeline 1812 and / or media pipeline 1816. In some embodiments, command streamer 1903 is coupled to a memory, which may be system memory or one or more of internal cache memory and shared cache memory. In some embodiments, command streamer 1903 receives commands from memory and sends these commands to 3D pipeline 1812 and / or media pipeline 1816. The commands are instructions retrieved from a ring buffer storing commands for 3D pipeline 1812 and media pipeline 1816. In one embodiment, the ring buffer may also include a batch command buffer that stores multiple batches of commands. Commands for 3D pipeline 1812 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for 3D pipeline 1812 and / or image data and memory objects for media pipeline 1816. The 3D pipeline 1812 and the media pipeline 1816 process the commands by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to the execution unit array 1914 .

[0257] In various embodiments, the 3D pipeline 1812 can execute one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 1914. The graphics core array 1914 provides a unified block of execution resources. The multi-purpose execution logic (e.g., execution units) within the graphics core array 1914 includes support for various 3D API shader languages ​​and can execute multiple simultaneous execution threads associated with multiple shaders.

[0258] In some embodiments, graphics core array 1914 also includes execution logic for performing media functions such as video and / or image processing. In one embodiment, in addition to graphics processing operations, the execution unit also includes general logic that can be programmed to perform parallel general computing operations. The general logic can be used with Figure 16 (multiple) processor cores 1607 or Figure 17 The general logic within cores 1702A to 1702N performs processing operations in parallel or in combination.

[0259] Output data generated by threads executing on graphics core array 1914 can be output to memory in unified return buffer (URB) 1918. URB 1918 can store data for multiple threads. In some embodiments, URB 1918 can be used to send data between different threads executing on graphics core array 1914. In some embodiments, URB 1918 can also be used for synchronization between threads on the graphics core array and fixed-function logic within shared function logic 1920.

[0260] In some embodiments, graphics core array 1914 is scalable such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of GPE 1910. In one embodiment, execution resources are dynamically scalable such that execution resources can be enabled or disabled as needed.

[0261] Graphics core array 1914 is coupled to shared function logic 1920, which includes a number of resources shared between the graphics cores in the graphics core array. Shared functions within shared function logic 1920 are hardware logic units that provide specialized, supplemental functionality to graphics core array 1914. In various embodiments, shared function logic 1920 includes, but is not limited to, sampler 1921, math 1922, and inter-thread communication (ITC) 1923 logic. Additionally, some embodiments implement one or more caches 1925 within shared function logic 1920. Shared functions are implemented when the demand for a given specialized function is insufficient to be included within graphics core array 1914. Instead, a single instance of the specialized function is implemented as a separate entity within shared function logic 1920 and shared among the execution resources within graphics core array 1914. The exact set of functions shared between and included within graphics core array 1914 varies between embodiments.

[0262] Figure 20 is a block diagram of another embodiment of a graphics processor 2000 . Figure 20 Those elements having the same reference numbers (or names) as elements in any other figures herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0263] In some embodiments, graphics processor 2000 includes ring interconnect 2002, pipeline front end 2004, media engine 2037, and graphics cores 2080A through 2080N. In some embodiments, ring interconnect 2002 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of multiple processors integrated into a multi-core processing system.

[0264] In some embodiments, the graphics processor 2000 receives batches of commands via a ring interconnect 2002. The incoming commands are interpreted by a command streamer 2003 in a pipeline front end 2004. In some embodiments, the graphics processor 2000 includes scalable execution logic for performing 3D geometry processing and media processing via graphics core(s) 2080A through 2080N. For 3D geometry processing commands, the command streamer 2003 supplies the commands to a geometry pipeline 2036. For at least some media processing commands, the command streamer 2003 supplies the commands to a video front end 2034, which is coupled to a media engine 2037. In some embodiments, the media engine 2037 includes a video quality engine (VQE) 2030 for video and image post-processing and a multi-format encoding / decoding (MFX) 2033 engine for providing hardware-accelerated media data encoding and decoding. In some embodiments, the geometry pipeline 2036 and the media engine 2037 each generate execution threads for thread execution resources provided by at least one graphics core 2080A.

[0265] In some embodiments, the graphics processor 2000 includes scalable thread execution resource representation module cores 2080A to 2080N (sometimes referred to as core slices), each of which has multiple sub-cores 2050A to 550N and 2060A to 2060N (sometimes referred to as core sub-slices). In some embodiments, the graphics processor 2000 can have any number of graphics cores 2080A to 2080N. In some embodiments, the graphics processor 2000 includes a graphics core 2080A having at least a first sub-core 2050A and a second sub-core 2060A. In other embodiments, the graphics processor is a low-power processor having a single sub-core (e.g., 2050A). In some embodiments, the graphics processor 2000 includes multiple graphics cores 2080A to 2080N, each of which includes a group of first sub-cores 2050A to 2050N and a group of second sub-cores 2060A to 2060N. Each sub-core in the set of first sub-cores 2050A to 2050N includes at least a first set of execution units 2052A to 2052N and a media / texture sampler 2054A to 2054N. Each sub-core in the set of second sub-cores 2060A to 2060N includes at least a second set of execution units 2062A to 2062N and a sampler 2064A to 2064N. In some embodiments, each sub-core 2050A to 2050N, 2060A to 2060N shares a set of shared resources 2070A to 2070N. In some embodiments, the shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0266] Execution Unit

[0267] Figure 21 Thread execution logic 2100 is shown, comprising an array of processing elements employed in some embodiments of a GPE. Figure 21 Those elements having the same reference numbers (or names) as elements in any other figures herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0268] In some embodiments, thread execution logic 2100 includes a shader processor 2102, a thread dispatcher 2104, an instruction cache 2106, a scalable execution unit array including a plurality of execution units 2108A through 2108N, a sampler 2110, a data cache 2112, and a data port 2114. In one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., execution units 2108A, 2108B, 2108C, 2108D, through any one of 2108N-1 and 2108N) based on the computational demands of the workload. In one embodiment, the included components are interconnected via an interconnect structure that links each of the components. In some embodiments, thread execution logic 2100 includes one or more connections to a memory (e.g., system memory or cache memory) through the instruction cache 2106, the data port 2114, the sampler 2110, and one or more of the execution unit arrays 2108A through 2108N. In some embodiments, each execution unit (e.g., 2108A) is an independently programmable general-purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 2108A to 2108N is scalable to include any number of individual execution units.

[0269] In some embodiments, execution units 2108A to 2108N are primarily used to execute shader programs. Shader processor 2102 can process various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 2104. In one embodiment, thread dispatcher includes logic for arbitrating thread initiation requests from graphics and media pipelines and instantiating the requested threads on one or more execution units 2108A to 2108N. For example, the geometry pipeline (e.g., Figure 20 2036) can dispatch vertex processing, tessellation or geometry processing threads to thread execution logic 2100 ( Figure 21In some embodiments, the thread dispatcher 2104 may also process runtime thread generation requests from executing shader programs.

[0270] In some embodiments, execution units 2108A to 2108N support an instruction set (including native support for many standard 3D graphics shader instructions) that enables shader programs from graphics libraries (e.g., Direct3D and OpenGL) to be executed with minimal conversion. These execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., compute and media shaders). Each of execution units 2108A to 2108N is capable of executing multi-issue single instruction multiple data (SIMD), and multi-threaded operations enable an efficient execution environment in the face of high-latency memory accesses. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. For pipelines with integer, single-precision floating-point and double-precision floating-point operations, SIMD branching functions, logical operations, transcendental operations, and other miscellaneous operations, execution is multiple issues per clock. When waiting for data from memory or one of the shared functions, dependency logic within execution units 2108A through 2108N causes the waiting thread to sleep until the requested data has returned. While the waiting thread is sleeping, hardware resources may be dedicated to processing other threads. For example, during the delay associated with vertex shader operations, the execution unit may execute operations of a pixel shader, a fragment shader, or another type of shader program that includes a different vertex shader.

[0271] Each execution unit in execution units 2108A through 2108N operates on an array of data elements. The number of data elements is the "execution size," or the number of lanes of an instruction. An execution lane is a logical unit that performs data element access, masking, and flow control within an instruction. The number of lanes may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) for a particular graphics processor. In some embodiments, execution units 2108A through 2108N support integer and floating point data types.

[0272] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as compressed data types, and the execution unit will process various elements based on the data size of the element. For example, when operating on a 256-bit wide vector, the 256-bit vector is stored in a register, and the execution unit operates on the vector as four separate 64-bit compressed data elements (data elements of quadruple word length (QW) size), eight separate 32-bit compressed data elements (data elements of double word length (DW) size), sixteen separate 16-bit compressed data elements (data elements of word length (W) size), or thirty-two separate 8-bit data elements (data elements of byte (B) size). However, different vector widths and register sizes are possible.

[0273] One or more internal instruction caches (e.g., 2106) are included in the thread execution logic 2100 to cache thread instructions for the execution unit. In some embodiments, one or more data caches (e.g., 2112) are included to cache thread data during thread execution. In some embodiments, a sampler 2110 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 2110 includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to the execution unit.

[0274] During execution, the graphics and media pipeline sends a thread initiation request to the thread execution logic 2100 via the thread generation and dispatch logic. Once a set of geometric objects has been processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 2102 is called to further calculate output information and cause the results to be written to the output surface (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, the pixel shader or fragment shader calculates the value of each vertex attribute, which is interpolated across the rasterized object. In some embodiments, the pixel processor logic within the shader processor 2102 then executes the pixel or fragment shader program supplied by the application programming interface (API). To execute the shader program, the shader processor 2102 dispatches the thread to the execution unit (e.g., 2108A) via the thread dispatcher 2104. In some embodiments, the pixel shader 2102 uses the texture sampling logic in the sampler 2110 to access texture data in the texture map stored in the memory. Arithmetic operations on texture data and input geometry data compute pixel color data for each geometry fragment, or discard one or more pixels without further processing.

[0275] In some embodiments, the data port 2114 provides a memory access mechanism for the thread execution logic 2100 to output processed data to memory for processing on the graphics processor output pipeline. In some embodiments, the data port 2114 includes or is coupled to one or more cache memories (e.g., data cache 2112) to cache data via the data port for memory access.

[0276] Figure 22 2 is a block diagram illustrating a graphics processor instruction format 2200 according to some embodiments. In one or more embodiments, the graphics processor execution unit supports an instruction set having instructions in multiple formats. Solid-line boxes illustrate components that are typically included in execution unit instructions, while dashed lines include optional components or components that are included only in a subset of instructions. In some embodiments, the instruction format 2200 described and illustrated are macroinstructions because they are instructions supplied to the execution unit, as opposed to micro-operations generated from instruction decoding (once the instruction is processed).

[0277] In some embodiments, the graphics processor execution unit natively supports instructions in 128-bit instruction format 2210. A 64-bit compact instruction format 2230 may be used for some instructions based on the selected instruction, multiple instruction options, and the number of operands. While the native 128-bit instruction format 2210 provides access to all instruction options, some options and operations are restricted to the 64-bit format 2230. The native instructions available in the 64-bit format 2230 vary depending on the embodiment. In some embodiments, instructions are partially compressed using a set of index values ​​in the index field 2213. The execution unit hardware references a set of compression tables based on the index values ​​and uses the compression table output to reconstruct the native instruction in 128-bit instruction format 2210.

[0278] For each format, the instruction opcode 2212 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a synchronous add operation across each color channel, and the color channel represents a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, the instruction control field 2214 enables control of certain execution options, such as channel selection (e.g., prediction) and data channel sorting (e.g., mixing). For instructions using the 128-bit instruction format 2210, the execution size field 2216 limits the number of data channels to be executed in parallel. In some embodiments, the execution size field 2216 is not available for the 64-bit compact instruction format 2230.

[0279] Some execution unit instructions have up to three operands, including two source operands (src0 2220, src1 2222) and a destination 2218. In some embodiments, the execution unit supports dual-destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., src2 2224), where the instruction opcode 2212 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value passed with the instruction.

[0280] In some embodiments, the 128-bit instruction format 2210 includes an access / address mode field 2226. The access / address mode information specifies, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is provided directly by bits in the instruction.

[0281] In some embodiments, the 128-bit instruction format 2210 includes an access / address mode field 2226 that specifies the address mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, wherein the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in the first mode, the instruction may use byte-aligned addressing for source operands and destination operands, and when in the second mode, the instruction may use 16-byte aligned addressing for all source operands and destination operands.

[0282] In one embodiment, the address mode portion of the access / address mode field 2226 determines whether the instruction uses direct or indirect addressing. When direct register addressing mode is used, bits in the instruction directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0283] In some embodiments, instructions are grouped based on the opcode 2212 bit field to simplify opcode decoding 2240. For 8-bit opcodes, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is exemplary only. In some embodiments, the move and logic opcode group 2242 includes data move and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 2242 shares the five most significant bits (MSBs), wherein the move (mov) instruction adopts the form of 0000xxxxb, while the logic instruction adopts the form of 0001xxxxb. The flow control instruction group 2244 (e.g., call (call), jump (jmp)) includes instructions using the form of 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 2246 includes a mixture of instructions, including synchronization instructions (e.g., wait (wait), send (send)) using the form of 0011xxxxb (e.g., 0x30). The parallel math instruction group 2248 includes component-wise arithmetic instructions (e.g., add, mul) in the form of 0100xxxxb (e.g., 0x40). The parallel math group 2248 performs arithmetic operations in parallel across data lanes. The vector math group 2250 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic operations on vector operands, such as dot products.

[0284] Graphics pipeline

[0285] Figure 23 is a block diagram of another embodiment of a graphics processor 2300 . Figure 23 Those elements having the same reference numbers (or names) as elements in any other figures herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0286] In some embodiments, graphics processor 2300 includes a graphics pipeline 2320, a media pipeline 2330, a display engine 2340, thread execution logic 2350, and a render output pipeline 2370. In some embodiments, graphics processor 2300 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or by commands issued to graphics processor 2300 via ring interconnect 2302. In some embodiments, ring interconnect 2302 couples graphics processor 2300 to other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnect 2302 are interpreted by command stream converter 2303, which supplies instructions to individual components of graphics pipeline 2320 or media pipeline 2330.

[0287] In some embodiments, command stream converter 2303 directs the operation of vertex fetcher 2305, which reads vertex data from memory and executes vertex processing commands provided by command stream converter 2303. In some embodiments, vertex fetcher 2305 provides vertex data to vertex shader 2307, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, vertex fetcher 2305 and vertex shader 2307 execute vertex processing instructions by dispatching execution threads to execution units 2352A and 2352B via thread dispatcher 2331.

[0288] In some embodiments, execution units 2352A-2352B are vector processor arrays with instruction sets for performing graphics and media operations. In some embodiments, execution units 2352A-2352B have an attached L1 cache 2351, which is dedicated to each array or shared between arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0289] In some embodiments, the graphics pipeline 2320 includes a tessellation component for performing hardware-accelerated tessellation of 3D objects. In some embodiments, the programmable hull shader 811 configures the tessellation operations. The programmable domain shader 817 provides back-end evaluation of the tessellation output. The tessellator 2313 operates under the direction of the hull shader 2311 and contains dedicated logic for generating a detailed set of geometric objects based on a coarse geometric model that is provided as input to the graphics pipeline 2320. In some embodiments, the tessellation components (e.g., hull shader 2311, tessellator 2313, domain shader 2317) can be bypassed if tessellation is not used.

[0290] In some embodiments, the complete geometric object can be processed by the geometry shader 2319 via one or more threads dispatched to the execution units 2352A-2352B, or can proceed directly to the clipper 2329. In some embodiments, the geometry shader operates on entire geometric objects (rather than vertices or vertex patches as in previous stages of the graphics pipeline). If tessellation is disabled, the geometry shader 2319 receives input from the vertex shader 2307. In some embodiments, the geometry shader 2319 can be programmed by the geometry shader program to perform geometry tessellation when the tessellation unit is disabled.

[0291] Before rasterization, the clipper 2329 processes the vertex data. The clipper 2329 can be a fixed-function clipper or a programmable clipper with clipping and geometry shader functionality. In some embodiments, the rasterizer and depth test component 2373 in the render output pipeline 2370 dispatches a pixel shader to convert the geometric objects into their per-pixel representations. In some embodiments, the pixel shader logic is included in the thread execution logic 2350. In some embodiments, the application can bypass the rasterizer and depth test component 2373 and access the unrasterized vertex data via the outflow unit 2323.

[0292] The graphics processor 2300 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be passed between the main components of the graphics processor. In some embodiments, execution units 2352A-2352B and associated cache(s) 2351, texture and media samplers 2354, and texture / sampler cache 2358 are interconnected via data ports 2356 to perform memory accesses and communicate with the processor's rendering output pipeline components. In some embodiments, samplers 2354, caches 2351, 2358, and execution units 2352A-2352B each have a separate memory access path.

[0293] In some embodiments, the rendering output pipeline 2370 includes a rasterizer and depth test component 2373, which converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit for performing fixed-function triangle and line rasterization. Associated rendering caches 2378 and depth caches 2379 are also available in some embodiments. Pixel operation components 2377 perform pixel-based operations on data, but in some instances, pixel operations associated with 2D operations (e.g., using mixed bit block image transfer) are performed by the 2D engine 2341 or replaced by overlapping display planes at display time by the display controller 2343. In some embodiments, a shared L3 cache 2375 can be used for all graphics components, thereby allowing data to be shared without using main system memory.

[0294] In some embodiments, the graphics processor media pipeline 2330 includes a media engine 2337 and a video front end 2334. In some embodiments, the video front end 2334 receives pipeline commands from the command stream converter 2303. In some embodiments, the media pipeline 2330 includes a separate command stream converter. In some embodiments, the video front end 2334 processes the media commands before sending them to the media engine 2337. In some embodiments, the media engine 2337 includes a thread generation function for generating threads for dispatching to the thread execution logic 2350 via the thread dispatcher 2331.

[0295] In some embodiments, the graphics processor 2300 includes a display engine 2340. In some embodiments, the display engine 2340 is external to the processor 2300 and is coupled to the graphics processor via the ring interconnect 2302, or some other interconnect bus or mechanism. In some embodiments, the display engine 2340 includes a 2D engine 2341 and a display controller 2343. In some embodiments, the display engine 2340 includes dedicated logic capable of operating independently of the 3D pipeline. In some embodiments, the display controller 2343 is coupled to a display device (not shown), which can be a system-integrated display device (such as in a laptop computer) or an external display device attached via a display device connector.

[0296] In certain embodiments, graphics pipeline 2320 and media pipeline 2330 can be configured to perform operations based on multiple graphics and media programming interfaces and are not dedicated to any application programming interface (API). In certain embodiments, the driver software of the graphics processing unit converts the API dispatch dedicated to specific graphics or media library into a command that can be processed by the graphics processing unit. In certain embodiments, support is provided for all open graphics libraries (OpenGL), open computing language (OpenCL) and / or Vulkan graphics and computing APIs from Khronos Group. In certain embodiments, support can also be provided for Microsoft's Direct3D library. In certain embodiments, the combination of these libraries can be supported. Support can also be provided for open source computer vision library (OpenCV). If the mapping from the pipeline of future API to the pipeline of graphics processing unit can be made, the future API with compatible 3D pipeline will also be supported.

[0297] Graphics pipeline programming

[0298] Figure 24A is a block diagram illustrating a graphics processor command format 2400 according to some embodiments. Figure 24B is a block diagram illustrating a graphics processor command sequence 2410 according to an embodiment. Figure 24A Solid-line boxes in show components that are typically included in a graphics command, while dashed lines include components that are optional or included only in a subset of the graphics commands. Figure 24A The exemplary graphics processor command format 2400 includes a data field for identifying the target client 2402 of the command, a command operation code (opcode) 2404, and associated data for the command 2406. Some commands also include a sub-opcode 2405 and a command size 2408.

[0299] In some embodiments, client 2402 defines a client unit of a graphics device that processes command data. In some embodiments, a graphics processor command parser examines the client field of each command to adjust further processing of the command and routes the command data to the appropriate client unit. In some embodiments, a graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing the command. Once a command is received by a client unit, the client unit reads the opcode 2404 and sub-opcode 2405 (if any) to determine the operation to be performed. The client unit uses the information in the data field 2406 to execute the command. For some commands, it is desired to explicitly define the size of the command using a command size 2408. In some embodiments, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some embodiments, commands are aligned via multiples of double word length.

[0300] Figure 24B The flowchart in FIG. 24 illustrates an exemplary graphics processor command sequence 2410. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses a version of the illustrated command sequence to initiate, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for exemplary purposes only, as embodiments are not limited to these specific commands or command sequences. Furthermore, the commands may be issued as a batch of commands in a command sequence such that the graphics processor processes the command sequence at least partially simultaneously.

[0301] In some embodiments, graphics processor command sequence 2410 may begin with a pipeline flush command 2412 to cause any active graphics pipeline to complete currently pending commands for that pipeline. In some embodiments, 3D pipeline 2422 and media pipeline 2424 are not operating simultaneously. A pipeline flush is performed to allow the active graphics pipeline to complete any pending commands. In response to a pipeline flush, the command parser for the graphics processor will halt command processing until the active drawing engine completes pending operations and invalidates the associated read cache. Optionally, any data marked as 'dirty' in the render cache may be flushed to memory. In some embodiments, pipeline flush command 2412 may be used for pipeline synchronization or before placing the graphics processor into a low-power state.

[0302] In some embodiments, pipeline select command 2413 is used when a command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, pipeline select command 2413 is only required once per execution context before issuing pipeline commands, unless the context is issuing commands for both pipelines. In some embodiments, pipeline flush command 2412 is required immediately prior to a pipeline switch via pipeline select command 2413.

[0303] In some embodiments, pipeline control commands 2414 configure the graphics pipeline for operation and are used to program 3D pipeline 2422 and media pipeline 2424. In some embodiments, pipeline control commands 2414 configure the pipeline state of the active pipeline. In one embodiment, pipeline control commands 2414 are used for pipeline synchronization and for flushing data from one or more cache memories within the active pipeline before processing a batch of commands.

[0304] In some embodiments, return buffer status commands 2416 are used to configure a set of return buffers for the corresponding pipeline to write data to. Some pipeline operations require allocating, selecting, or configuring one or more return buffers to which the operation writes intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, return buffer status 2416 includes selecting the size and number of return buffers to use for the set of pipeline operations.

[0305] The remaining commands in the command sequence differ based on the active pipeline for operation. Based on pipeline decision 2420 , the command sequence is tailored for either the 3D pipeline 2422 starting at 3D pipeline state 2430 or the media pipeline 2424 starting at media pipeline state 2440 .

[0306] The commands for the 3D pipeline state 2430 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables to be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API in use. In some embodiments, the 3D pipeline state 2430 commands can also selectively disable or bypass specific pipeline elements if those elements are not to be used.

[0307] In some embodiments, the 3D primitive 2432 command is used to submit 3D primitives to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive 2432 command are forwarded to the vertex acquisition function in the graphics pipeline. The vertex acquisition function uses the 3D primitive 2432 command data to generate multiple vertex data structures. The vertex data structures are stored in one or more return buffers. In some embodiments, the 3D primitive 2432 command is used to perform vertex operations on the 3D primitives via the vertex shader. To process the vertex shader, the 3D pipeline 2422 dispatches the shader execution thread to the graphics processor execution unit.

[0308] In some embodiments, the 3D pipeline 2422 is triggered via an execute 2434 command or event. In some embodiments, a register write triggers command execution. In some embodiments, execution is triggered via a 'go' or 'kick' command in a command sequence. In one embodiment, pipeline synchronization commands are used to trigger command execution in order to flush the command sequence through the graphics pipeline. The 3D pipeline performs geometry processing on the 3D primitives. Once the operation is completed, the generated geometric objects are rasterized and the pixel engine shades the generated pixels. These operations may also include additional commands for controlling pixel shading and pixel backend operations.

[0309] In some embodiments, when performing media operations, the graphics processor command sequence 2410 follows the media pipeline 2424 path. Generally, the specific purpose and manner of programming the media pipeline 2424 depends on the media or computational operation to be performed. During the media decoding process, specific media decoding operations can be offloaded to the media pipeline. In some embodiments, the media pipeline can also be bypassed and the media decoding can be performed in whole or in part using resources provided by one or more general-purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processor unit (GPGPU) operations, wherein the graphics processor is used to perform SIMD vector operations using compute shader programs that are not explicitly related to rendering graphics primitives.

[0310] In some embodiments, the media pipeline 2424 is configured in a similar manner to the 3D pipeline 2422. A set of commands for configuring the media pipeline state 2440 is dispatched or placed into the command queue before the media object commands 2442. In some embodiments, the media pipeline state commands 2440 include data for configuring the media pipeline elements that will be used to process the media objects. This includes data for configuring the video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some embodiments, the media pipeline state commands 2440 also support the use of one or more pointers to "indirect" state elements that contain a batch of state settings.

[0311] In some embodiments, media object commands 2442 supply a pointer to a media object for processing by the media pipeline. The media object includes a memory buffer that contains video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object commands 2442. Once the pipeline state is configured and media object commands 2442 are queued, media pipeline 2424 is triggered via an execute 2444 command or an equivalent execution event (e.g., a register write). The output from media pipeline 2424 can then be post-processed by operations provided by 3D pipeline 2422 or media pipeline 2424. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0312] Graphics software architecture

[0313] Figure 25 An exemplary graphics software architecture for a data processing system 2500 according to some embodiments is shown. In some embodiments, the software architecture includes a 3D graphics application 2510, an operating system 2520, and at least one processor 2530. In some embodiments, processor 2530 includes a graphics processor 2532 and one or more general-purpose processor cores 2534. Graphics application 2510 and operating system 2520 each execute in system memory 2550 of the data processing system.

[0314] In some embodiments, the 3D graphics application 2510 includes one or more shader programs that include shader instructions 2512. The shader language instructions may be in a high-level shader language, such as High-Level Shader Language (HLSL) or OpenGL Shader Language (GLSL). The application also includes executable instructions 2514 in a machine language suitable for execution by the general-purpose processor core 2534. The application also includes graphics objects 2516 defined by vertex data.

[0315] In some embodiments, operating system 2520 is from Microsoft Corporation Operating system, dedicated UNIX operating system, or open source UNIX operating system using Linux kernel variant. Operating system 2520 can support graphics API 2522, such as Direct3D API, OpenGL API or Vulkan API. When Direct3D API is in use, operating system 2520 uses front-end shader compiler 2524 to compile any shader instruction 2512 in HLSL into a lower-level shader language. The compilation can be just-in-time (JIT) compilation, or the application can execute shader precompilation. In some embodiments, in the process of compiling 3D graphics application 2510, high-level shaders are compiled into low-level shaders. In some embodiments, shader instructions 2512 are provided in an intermediate form, such as a version of the standard portable intermediate representation (SPIR) used by Vulkan API.

[0316] In some embodiments, the user-mode graphics driver 2526 includes a back-end shader compiler 2527 that converts shader instructions 2512 into hardware-specific representations. When using the OpenGL API, shader instructions 2512 in the GLSL high-level language are passed to the user-mode graphics driver 2526 for compilation. In some embodiments, the user-mode graphics driver 2526 uses operating system kernel-mode functions 2528 to communicate with the kernel-mode graphics driver 2529. In some embodiments, the kernel-mode graphics driver 2529 communicates with the graphics processor 2532 to dispatch commands and instructions.

[0317] IP core implementation

[0318] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit, such as a processor. For example, a machine-readable medium may include instructions representing the various logic within the processor. When read by a machine, the instructions may cause the machine to manufacture logic for performing the techniques described herein. This type of representation (referred to as an "IP core") is a reusable unit of logic for an integrated circuit that can be stored on a tangible, machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be supplied to each consumer or manufacturing facility that loads the hardware model on a manufacturing machine that manufactures the integrated circuit. The integrated circuit may be manufactured so that the circuit performs the operations described in association with any of the embodiments described herein.

[0319] Figure 262 is a block diagram illustrating an IP core development system 2600 that can be used to manufacture integrated circuits to perform operations according to an embodiment. The IP core development system 2600 can be used to generate modular, reusable designs that can be incorporated into larger designs or used to build entire integrated circuits (e.g., SoC integrated circuits). A design facility 2630 can generate a software simulation 2610 of the IP core design using a high-level programming language (e.g., C / C++). The software simulation 2610 can be used to design, test, and verify the behavior of the IP core using a simulation model 2612. The simulation model 2612 can include functional, behavioral, and / or timing simulations. A register transfer level (RTL) design 2615 can then be created or synthesized from the simulation model 2612. The RTL design 2615 is an abstraction of the behavior of the integrated circuit (including associated logic executed using the modeled digital signals) that models the flow of digital signals between hardware registers. In addition to the RTL design 2615, lower-level designs at the logic or transistor levels can also be created, designed, or synthesized. Consequently, the specific details of the initial design and simulation can vary.

[0320] The RTL design 2615 or an equivalent solution can be further synthesized by the design facility into a hardware model 2620, which can be in hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to verify the IP core design. Non-volatile memory 2640 (e.g., a hard disk, flash memory, or any non-volatile storage medium) can be used to store the IP core design for delivery to a third-party manufacturing facility 2665. Alternatively, the IP core design can be transmitted (e.g., via the Internet) via a wired connection 2650 or a wireless connection 2660. The manufacturing facility 2665 can then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit can be configured to perform operations according to at least one embodiment described herein.

[0321] Exemplary System-on-Chip Integrated Circuit

[0322] Figures 27 to 29 An exemplary integrated circuit and related graphics processor that can be manufactured using one or more IP cores according to various embodiments described herein are shown. In addition to what is shown, other logic and circuits may also be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0323] Figure 2727 is a block diagram illustrating an exemplary system-on-chip integrated circuit 2700 that can be manufactured using one or more IP cores according to an embodiment. The exemplary integrated circuit 2700 includes one or more application processors 2705 (e.g., CPUs), at least one graphics processor 2710, and may also include an image processor 2715 and / or a video processor 2720, any of which can be modular IP cores from the same or multiple different design facilities. The integrated circuit 2700 includes peripheral or bus logic, including a USB controller 2725, a UART controller 2730, an SPI / SDIO controller 2735, and an I / O controller. 2 S / I 2 The integrated circuit may also include a display device 2745 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 2750 and a Mobile Industry Processor Interface (MIPI) display interface 2755. Storage may be provided by a flash memory subsystem 2760 (including flash memory and a flash memory controller). A memory interface may be provided via a memory controller 2765 to access SDRAM or SRAM memory devices. Some integrated circuits may also include an embedded security engine 2770.

[0324] Figure 28 is a block diagram illustrating an exemplary graphics processor 2810 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores according to an embodiment. The graphics processor 2810 may be Figure 27 The graphics processor 2810 includes a vertex processor 2805 and one or more fragment processors 2815A to 2815N (e.g., 2815A, 2815B, 2815C, 2815D, up to 2815N-1 and 2815N). The graphics processor 2810 can execute different shader programs via separate logic, such that the vertex processor 2805 is optimized to perform the operations of the vertex shader program, while the one or more fragment processors 2815A to 2815N perform fragment (e.g., pixel) shading operations for the fragment or pixel shader program. The vertex processor 2805 executes the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. The fragment processor(s) 2815A to 2815N use the primitives and vertex data generated by the vertex processor 2805 to generate a frame buffer for display on the display device. In one embodiment, the fragment processor(s) 2815A through 2815N are optimized to execute fragment shader programs provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0325] In addition, the graphics processor 2810 also includes one or more memory management units (MMUs) 2820A-2820B, one or more caches 2825A-2825B, and (multiple) circuit interconnects 2830A-2830B. The one or more MMUs 2820A-2820B provide virtual-to-physical address mappings for the integrated circuit 2810, including for the vertex processor 2805 and / or one or more fragment processors 2815A-2815N, which can reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in the one or more caches 2825A-2825B. In one embodiment, the one or more MMUs 2825A-2825B can communicate with other MMUs within the system, including with Figure 27 The graphics processor 2810 may be synchronized with one or more MMUs associated with one or more application processors 2705, image processor 2715, and / or video processor 2720 so that each processor 2705 to 2720 may participate in a shared or unified virtual memory system. In accordance with an embodiment, one or more circuit interconnects 2830A to 2830B may enable the graphics processor 2810 to interact with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0326] Figure 29 is a block diagram illustrating an additional exemplary graphics processor 2910 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores in accordance with an embodiment. The graphics processor 2910 may be Figure 27 A variant of the graphics processor 2710. The graphics processor 2910 includes Figure 28 One or more MMUs 2820A-2820B, caches 2825A-2825B, and circuit interconnects 2830A-2830B of integrated circuit 2800.

[0327] The graphics processor 2910 includes one or more shader cores 2915A to 2915N (e.g., 2915A, 2915B, 2915C, 2915D, 2915E, 2915F, all the way to 2915N-1 and 2915N), which provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code, to implement vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present may vary in embodiments and implementations. In addition, the graphics processor 2910 also includes an inter-core task manager 2905, which acts as a thread dispatcher for dispatching execution threads to the one or more shader cores 2915A to 2915N and a tiling unit 2918 for accelerating tiling operations for tile-based rendering, in which rendering operations of a scene are subdivided in image space, for example to exploit local spatial coherence within the scene or to optimize the use of internal caches.

[0328] Some embodiments relate to Example 1, which includes an apparatus for facilitating work scheduling, the apparatus comprising one or more clients, one or more processing units for processing a workload received from the one or more clients, the one or more processing units comprising hardware resources and scheduling logic for scheduling access to the hardware resources to the one or more clients to process the workload.

[0329] Example 2 includes the subject matter of Example 1, wherein the one or more clients each comprise a precompiled neural network (NN) kernel client.

[0330] Example 3 includes the subject matter of Examples 1 and 2, wherein the scheduling logic schedules access to each of the precompiled NN kernel clients via a kernel mode driver (KMD).

[0331] Example 4 includes the subject matter of Examples 1-3, characterized in that the scheduling logic provides access to the hardware resources to each of the precompiled NN kernel clients based on priority and submitting client type.

[0332] Example 5 includes the subject matter of Examples 1-4, further comprising driver logic that accesses the one or more processing units, wherein each of the precompiled NN kernel clients is registered at the driver logic.

[0333] Example 6 includes the subject matter of Examples 1-5, characterized in that each of the precompiled NN kernel clients receives a function pointer to enable direct access to the hardware resources.

[0334] Example 7 includes the subject matter of Examples 1-6, characterized in that each of the precompiled NN kernel clients includes an input interface to the one or more processing units.

[0335] Example 8 includes the subject matter of Examples 1-7, further comprising aggregation logic to aggregate sparse kernel elements.

[0336] Example 9 includes the subject matter of Examples 1-8, further comprising a memory, wherein the aggregation logic comprises a relative address table to indicate a location of the kernel element within the memory.

[0337] Example 10 includes the subject matter of Examples 1-9, further comprising a memory, wherein the kernel elements are multiplied with entries in the feature map.

[0338] Some embodiments relate to Example 11, which includes a method for facilitating workload scheduling, the method comprising receiving a request for access to hardware resources of a processing unit from one or more clients, and scheduling access to the hardware resources to a first client among the one or more clients to process the workload.

[0339] Example 12 includes the subject matter of Example 11, characterized in that the first client comprises a pre-compiled neural network (NN) kernel client.

[0340] Example 13 includes the subject matter of Examples 11 and 12, wherein access to the first client is dispatched via a kernel mode driver (KMD).

[0341] Example 14 includes the subject matter of Examples 11-13, wherein access is provided to the first client based on priority and submitting client type.

[0342] Example 15 includes the subject matter of Examples 11-14, further comprising registering the first client with driver logic associated with the processing unit.

[0343] Some embodiments relate to Example 16, which includes at least one computer-readable medium having instructions that, when executed by one or more processors, cause the processor to: receive a request from one or more clients to access hardware resources of a processing unit, and schedule direct access of the hardware resources to a first client of the one or more clients to process the workload.

[0344] Example 17 includes the subject matter of Example 16, characterized in that the first client comprises a pre-compiled neural network (NN) kernel client.

[0345] Example 18 includes the subject matter of Example 16 and Example 17, wherein access to the first client is scheduled via a kernel mode driver (KMD).

[0346] Example 19 includes the subject matter of Examples 16-18, wherein access is provided to the first client based on priority and submitting client type.

[0347] Example 20 includes the subject matter of Examples 16-19, with instructions that, when executed by the one or more processors, further cause the processor to register the first client with driver logic associated with the processing unit.

[0348] Some embodiments relate to Example 21, which includes at least one computer-readable medium having instructions that, when executed by one or more processors, cause the processors to perform the method as claimed in any one of claims 11-15.

[0349] Some embodiments relate to Example 22, which includes a system comprising mechanisms for implementing or performing the method as claimed in any one of claims 11-15.

[0350] Some embodiments relate to Example 23, which includes an apparatus comprising means for performing the method as claimed in any one of the claims or Examples 11-15.

[0351] Some embodiments relate to Example 24, which includes a computing device arranged to implement or perform a method as claimed in any one of the claims or Examples 11-15.

[0352] Some embodiments relate to Example 25, which includes a communication device arranged to implement or perform a method as claimed in any one of the claims or Examples 11-15.

[0353] The foregoing description and accompanying drawings should be regarded as illustrative rather than restrictive. Those skilled in the art will appreciate that various modifications and changes may be made to the embodiments described herein without departing from the broader spirit and scope of the invention as set forth in the appended claims.

Claims

1. An apparatus for facilitating workload scheduling, the apparatus comprising: One or more clients, including pre-compiled neural network (NN) kernel clients and other clients; One or more processing units, the one or more processing units configured to process workloads received from the one or more clients, the one or more processing units comprising: Hardware resources; Scheduling logic for scheduling direct access to the hardware resources to the precompiled NN kernel client via a kernel mode driver KMD based on priority and submitting client type to process the workload; and Aggregation logic comprising a relative address table for indicating memory locations of non-zero data values ​​of convolution kernels received from the precompiled NN kernel client, the aggregation logic for aggregating the non-zero data values ​​of the convolution kernels and bypassing zero data values ​​of the convolution kernels during processing of the convolution kernels, Access to the hardware resources is provided to the other clients via a driver and a scheduler.

2. The apparatus of claim 1 , further comprising driver logic that accesses the one or more processing units, wherein each of the precompiled NN kernel clients is registered at the driver logic.

3. The device according to claim 2, wherein Each of the precompiled NN kernel clients receives function pointers to enable direct access to the hardware resources.

4. The device according to claim 2, wherein Each of the precompiled NN kernel clients includes an input interface to the one or more processing units.

5. The apparatus of claim 1, further comprising a memory, wherein The kernel elements are multiplied by the entries in the feature map.

6. A method for facilitating workload scheduling, the method comprising: Receiving requests from one or more clients to access hardware resources of a processing unit, the one or more clients including pre-compiled neural network (NN) kernel clients and other clients; dispatching, via a kernel mode driver (KMD), direct access to the hardware resources to the precompiled NN kernel client based on priority and submitting client type to process the workload; as well as During processing of a convolution kernel received from the precompiled NN kernel client, aggregating non-zero data values ​​of the convolution kernel while bypassing zero data values ​​of the convolution kernel via aggregation logic of the processing unit, the aggregation logic including a relative address table indicating memory locations of the non-zero data values ​​of the convolution kernel, Access to the hardware resources is provided to the other clients via a driver and a scheduler.

7. The method of claim 6, further comprising registering each of the precompiled NN kernel clients with driver logic associated with the processing unit.

8. At least one computer-readable medium having instructions which, when executed by one or more processors, cause the processors to perform the method as claimed in claim 6 or 7.

9. A system comprising means for implementing or executing the method as claimed in claim 6 or 7.

10. An apparatus comprising means for performing the method as claimed in claim 6 or 7.

11. A computing device arranged to implement or perform a method as claimed in claim 6 or 7.

12. A communication device arranged to implement or perform the method as claimed in claim 6 or 7.

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