Encoding 3D rendered images by labeling objects

Abstract

Image information is often transmitted from one electronic device to another. Such information is typically encoded and / or compressed to reduce the bandwidth required for transmission and / or to reduce the time necessary for transmission. Embodiments are directed to marking objects or primitives with attribute tags to facilitate the encoding process. Other embodiments are directed to codecs running on hardware and / or software.

Description

Technical Field

[0001] Embodiments relate generally to encoding, and more particularly, to encoding 3D rendered images by labeling objects. Background Art

[0002] Image information is often transmitted from one electronic device to another. Such information is typically encoded and / or compressed to reduce the bandwidth required for the transmission and / or to reduce the time necessary for the transmission. Labeling objects / primitives with attributes generated by a 3D engine can enhance this process and eliminate certain time / power consuming steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Various advantages of the embodiments will become apparent to those skilled in the art by reading the following specification and appended claims, and by referring to the following drawings, in which:

[0004] Figure 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein;

[0005] Figures 2A-2D illustrates a parallel processor assembly according to an embodiment;

[0006] Figure 3A-3B is a block diagram of a graphics multiprocessor according to an embodiment;

[0007] Figures 4A-4F illustrates an exemplary architecture in which multiple GPUs are communicatively coupled to multiple multi-core processors;

[0008] Figure 5 illustrates a graphics processing pipeline according to an embodiment;

[0009] Fig. 6A is an example of a block diagram showing marking moving or static attributes to eliminate motion estimation steps;

[0010] Figure 6B is an example of a block diagram further illustrating marking moving or static attributes to eliminate motion estimation steps;

[0011] Figure 7 is an example of a flow chart showing the steps of marking moving or static attributes to eliminate motion estimation;

[0012] Fig. 8A and 8B is an example of a block diagram illustrating labeling pixel depth attributes;

[0013] Figure 8C is an example of a flow chart illustrating labeling pixel depth attributes;

[0014] FIG. 9A is an example of a block diagram illustrating a related technique for encoding pixel frame data using a media encoder pipeline;

[0015] Fig. 9B is an example of a block diagram illustrating a 3D pipeline for encoding video data directly into JPEG-DCT (Joint Photographic Experts Group - Discrete Cosine Transform) according to one embodiment;

[0016] Fig. 9C It is a graphic Fig. 9B An example of a flowchart shown in;

[0017] Fig. 10A is an example of a block diagram illustrating a software tracking system that indicates when a codec is programmed into an FPGA (field programmable gate array);

[0018] Fig. 10B It is a graphic Fig. 10A An example of a flowchart shown in;

[0019] Fig.11 is a block diagram of an example of a display having localized backlight capability according to an embodiment;

[0020] Fig. 12A is a block diagram of an example of a data processing apparatus according to an embodiment;

[0021] Fig. 12B is an illustration of an example of distance determination according to an embodiment;

[0022] Fig.13 is a block diagram of an example of a layered display architecture according to an embodiment;

[0023] Fig.14 is a block diagram of an example of a display architecture including a plurality of display units according to an embodiment;

[0024] Fig.15 is a block diagram of an example of a cloud-assisted media delivery architecture according to an embodiment;

[0025] Figure 16-18 is a block diagram of an example of an overview of a data processing system according to an embodiment;

[0026] Fig.19 is a block diagram of an example of a graphics processing engine according to an embodiment;

[0027] Figure 20-22 is a block diagram of an example of an execution unit according to an embodiment;

[0028] Fig.23 is a block diagram of an example of a graphics pipeline according to an embodiment;

[0029] Figures 24A-24Bis a block diagram of an example of graphics pipeline programming according to an embodiment;

[0030] Fig.25 is a block diagram of an example of a graphics software architecture according to an embodiment;

[0031] Fig.26 is a block diagram of an example of an intellectual property (IP) core development system according to an embodiment;

[0032] Fig. 27 is a block diagram of an example of a system on chip integrated circuit according to an embodiment. DETAILED DESCRIPTION

[0033] In the following description, a large number of specific details are set forth to provide a more comprehensive understanding of the present invention. However, it will be appreciated by those skilled in the art that the present invention may be implemented without one or more of these specific details. In other examples, well-known features are not described in order to avoid confusing the present invention.

[0034] System Overview

[0035] Figure 1 1 is a block diagram illustrating a computing system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 and a system memory 104, the one or more processors 102 communicating with the system memory 104 via an interconnect path that may include a memory hub 105. The memory hub 105 may be a separate component within a chipset assembly, or may be integrated within the one or more processors 102. The memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107, which may enable the computing system 100 to receive input from one or more input devices 108. Additionally, the I / O hub 107 may enable a display controller, which may be included in the one or more processors 102, to provide output to one or more display devices 110A. In one embodiment, the one or more display devices 110A coupled to the I / O hub 107 may include local, internal, or embedded display devices.

[0036] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112, which are coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standard-based communication link technologies or protocols (such as, but not limited to, the PCI Express bus), or can be a vendor-specific communication interface or communication structure. In one embodiment, the one or more parallel processors 112 form a computationally focused parallel or vector processing system that includes a large number of processing cores and / or processing clusters (such as, an integrated many-core (MIC) processor). In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one of the one or more display devices 110A coupled via the I / O hub 107. The one or more parallel processors 112 may also include a display controller and display interface (not shown) to enable direct connection to one or more display devices 110B.

[0037] Within the I / O subsystem 111, a system storage unit 114 may be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. An I / O switch 116 may be used to provide an interface mechanism to enable connection between the I / O hub 107 and other components, such as a network adapter 118 and / or a wireless network adapter 119 that may be integrated into the platform, as well as various other devices that may be added via one or more plug-in devices 120. The network adapter 118 may be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 may include one or more of the following: Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless radios.

[0038] The computing system 100 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and the like, which may also be connected to the I / O hub 107. Figure 1 The communication paths interconnecting the various components in the system may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI Express bus) or any other bus or point-to-point communication interface and / or protocol (such as, NV-Link high-speed interconnect, or interconnect protocols known in the art).

[0039] In one embodiment, the one or more parallel processors 112 incorporate circuits optimized for graphics and video processing (including, for example, video output circuits) and constitute a graphics processing unit (GPU). In another embodiment, the one or more parallel processors 112 incorporate circuits optimized for general-purpose processing while maintaining the underlying computing architecture described in more detail herein. In yet another embodiment, the components of the computing system 100 may be integrated on a single integrated circuit along with one or more other system elements. For example, the one or more parallel processors 112, the memory hub 105, the processor 102, and the I / O hub 107 may be integrated into a system-on-chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 may be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules into a modular computing system.

[0040] It will be appreciated that the computing system 100 shown herein is illustrative and that variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of processor(s) 102, and the number of parallel processor(s) 112, may be modified as desired. For example, in some embodiments, the system memory 104 is connected to the processor(s) 102 directly rather than through a bridge, while other devices communicate with the processor(s) 102 and the system memory 104 via the memory hub 105. In other alternative topologies, the parallel processor(s) 112 are connected to the I / O hub 107 or directly to one of the processor(s) 102, rather than to the memory hub 105. In other embodiments, the I / O hub 107 and the memory hub 105 may be integrated into a single chip. Some embodiments may include two or more groups of processors 102 attached via multiple sockets, which may be coupled to two or more instances of the parallel processor(s) 112.

[0041] Some of the specific components shown herein are optional and may not be included in all implementations of computing system 100. For example, any number of plug-in cards or peripherals may be supported, or some components may be eliminated. In addition, some architectures may be different from those described above. Figure 1 Different terminology is used for components that are similar to those shown in FIG. 1. For example, in some architectures, memory hub 105 may be referred to as a north bridge, while I / O hub 107 may be referred to as a south bridge.

[0042] Figure 2A200 according to an embodiment. The various components of the parallel processor 200 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). According to an embodiment, the parallel processor 200 shown is Figure 1 A variation of one or more parallel processors 112 is shown in FIG.

[0043] In one embodiment, the parallel processor 200 includes a parallel processing unit 202. The parallel processing unit includes an I / O unit 204, which is capable of communicating with other devices (including other instances of the parallel processing unit 202). The I / O unit 204 can be directly connected to other devices. In one embodiment, the I / O unit 204 is connected to other devices via the use of a hub or switch interface (such as, a memory hub 105). The connection between the memory hub 105 and the I / O unit 204 forms a communication link 113. Within the parallel processing unit 202, the I / O unit 204 is connected to a host interface 206 and a memory crossbar 216, wherein the host interface 206 receives commands for performing processing operations and the memory crossbar 216 receives commands for performing memory operations.

[0044] When the host interface 206 receives the command buffer via the I / O unit 204, the host interface 206 can direct the work operations for executing those commands to the front end 208. In one embodiment, the front end 208 is coupled with a scheduler 210, which is configured to distribute commands or other work items to the processing cluster array 212. In one embodiment, the scheduler 210 ensures that the processing cluster array 212 is properly configured and in a valid state before the tasks are distributed to the processing clusters of the processing cluster array 212. In one embodiment, the scheduler 210 is implemented via firmware logic executed on a microcontroller. The microcontroller-implemented scheduler 210 can be configured to perform complex scheduling and work distribution operations at coarse and fine granularity, thereby enabling context switching and rapid preemption of threads executed on the processing array 212. In one embodiment, the host software can verify that the workload is scheduled on the processing array 212 via one of a plurality of graphics processing doorbells. The workload may then be automatically distributed across the processing array 212 by the scheduler 210 logic within the scheduler microcontroller.

[0045] Processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B, up to cluster 214N). Each cluster 214A-214N of processing cluster array 212 may execute a large number of concurrent threads. Scheduler 210 may use various scheduling and / or work distribution algorithms to assign work to clusters 214A-214N of processing cluster array 212, which may vary depending on the workload generated for each type of program or calculation. Scheduling may be handled dynamically by scheduler 210, or may be assisted in part by compiler logic during compilation of program logic configured for execution by processing cluster array 212. In one embodiment, different clusters 214A-214N of processing cluster array 212 may be assigned to process different types of programs, or to perform different types of calculations.

[0046] Processing cluster array 212 may be configured to perform various types of parallel processing operations. In one embodiment, processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, processing cluster array 212 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations (including physics operations), and performing data transformations.

[0047] In one embodiment, processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where parallel processor 200 is configured to perform graphics processing operations, processing cluster array 212 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, and tessellation logic and other vertex processing logic. In addition, processing cluster array 212 may be configured to execute graphics processing related shader programs, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. Parallel processing unit 202 may transfer data from system memory via I / O unit 204 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 222) during processing and then written back to system memory.

[0048] In one embodiment, when parallel processing unit 202 is used to perform graphics processing, scheduler 210 can be configured to divide the processing workload into tasks of approximately equal size to better enable the distribution of graphics processing operations to multiple clusters 214A-214N in processing cluster array 212. In some embodiments, portions of processing cluster array 212 can be configured to perform different types of processing. For example, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations to produce a rendered image for display. Intermediate data generated by one or more of clusters 214A-214N can be stored in a buffer to allow the intermediate data to be transferred between clusters 214A-214N for further processing.

[0049] During operation, the processing cluster array 212 may receive processing tasks to be performed via the scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, the processing tasks may include commands and state parameters defining how data is to be processed (e.g., what program is to be executed) and indices of the data to be processed (e.g., surface (patch) data, primitive data, vertex data, and / or pixel data). The scheduler 210 may be configured to extract the index corresponding to the task, or may receive the index from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured to a valid state before initiating a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.).

[0050] Each of the one or more instances of the parallel processing unit 202 may be coupled to a parallel processor memory 222. The parallel processor memory 222 may be accessed via a memory crossbar 216, which may receive memory requests from the processing cluster array 212 and the I / O unit 204. The memory crossbar 216 may access the parallel processor memory 222 via a memory interface 218. The memory interface 218 may include a plurality of partition units (e.g., partition unit 220A, partition unit 220B, up to partition unit 220N), which may each be coupled to a portion (e.g., memory unit) of the parallel processor memory 222. In one implementation, the number of partition units 220A-220N is configured to be equal to the number of memory units, such that the first partition unit 220A has a corresponding first memory unit 224A, the second partition unit 220B has a corresponding memory unit 224B, and the Nth partition unit 220N has a corresponding Nth memory unit 224N. In other embodiments, the number of partition units 220A-220N may not be equal to the number of memory devices.

[0051] In various embodiments, the memory units 224A-224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, the memory units 224A-224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will recognize that the specific implementation of the memory units 224A-224N may vary and may be selected from one of various conventional designs. Rendering targets (such as frame buffers or texture maps) may be stored across the memory units 224A-224N, allowing the partition units 220A-220N to write portions of each rendering target in parallel to efficiently use the available bandwidth of the parallel processor memory 222. In some embodiments, local instances of the parallel processor memory 222 may be excluded to facilitate the unified memory design of the system memory to be utilized in conjunction with the local cache memory.

[0052] In one embodiment, any of the clusters 214A-214N of the processing cluster array 212 can process data to be written to any of the memory units 224A-224N within the parallel processor memory 222. The memory crossbar 216 can be configured to transfer the output of each cluster 214A-214N to any partition unit 220A-220N or another cluster 214A-214N, which can perform additional processing operations on the output. Each cluster 214A-214N can communicate with a memory interface 218 through the memory crossbar 216 to read from or write to various external memory devices. In one embodiment, the memory crossbar 216 has a connection to the memory interface 218 to communicate with the I / O unit 204, as well as a connection to a local instance of the parallel processor memory 222, thereby enabling processing units within different processing clusters 214A-214N to communicate with system memory or other memory that is not local to the parallel processing unit 202. In one embodiment, the memory crossbar switch 216 may use virtual channels to separate traffic flows between the clusters 214A-214N and the partition units 220A-220N.

[0053] Although a single instance of parallel processing unit 202 is shown in parallel processor 200, any number of instances of parallel processing unit 202 may be included. For example, multiple instances of parallel processing unit 202 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. Different instances of parallel processing unit 202 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example and in one embodiment, some instances of parallel processing unit 202 may include higher precision floating point units relative to other instances. Systems that incorporate one or more instances of parallel processing unit 202 or parallel processor 200 may be implemented in a variety of configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0054] Figure 2B is a block diagram of a partition unit 220 according to an embodiment. In one embodiment, the partition unit 220 is Figure 2A2 is an example of one of the partition units 220A-220N of the processor. As shown, the partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and an ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache that is configured to perform load and store operations received from the memory crossbar switch 216 and the ROP 226. Read misses and urgent write-back requests are output by the L2 cache 221 to the frame buffer interface 225 for processing. Updates may also be sent to the frame buffer via the frame buffer interface 225 for processing. In one embodiment, the frame buffer interface 225 interfaces with one of the memory units in the parallel processor memory, such as the memory units 224A-224N of FIG. 2 (e.g., within the parallel processor memory 222).

[0055] In graphics applications, ROP 226 is a processing unit that performs raster operations such as stencil, z-test, blending, and the like. ROP 226 then outputs processed graphics data that is stored in graphics memory. In some embodiments, ROP 226 includes compression logic that compresses depth or color data written to memory and decompresses depth or color data read from memory. The compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. The type of compression performed by ROP 226 can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on depth and color data on a tile-by-tile basis.

[0056] In some embodiments, ROP 226 is included within each processing cluster (e.g., clusters 214A-214N of FIG. 2 ) rather than within partition unit 220. In such embodiments, read and write requests for pixel data rather than pixel fragment data are transmitted through memory crossbar 216. The processed graphics data may be displayed on a display device (e.g., Figure 1 100), is routed for further processing by the processor(s) 102, or is routed for processing by the processor(s) 102. Figure 2A One of the processing entities within parallel processor 200 further processes.

[0057] Figure 2C2 is a block diagram of a processing cluster 214 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 214A-214N of FIG. 2. The processing cluster 214 can be configured to execute many threads in parallel, wherein the term "thread" refers to an instance of a specific program executed on a specific set of input data. In some embodiments, without providing multiple independent instruction units, a single instruction multiple data (SIMD) instruction issuance technique is used to support the parallel execution of a large number of threads. In other embodiments, a common instruction unit configured to issue instructions to a group of processing engines within each of the processing clusters is used, and a single instruction multiple thread (SIMT) technique is used to support the parallel execution of a large number of generally synchronized threads. Unlike the SIMD execution regime (wherein all processing engines generally execute the same instruction), SIMT execution allows different threads to more easily follow divergent execution paths through a given thread program. It will be understood by those skilled in the art that the SIMD processing regime represents a functional subset of the SIMT processing regime.

[0058] The operation of the processing cluster 214 can be controlled via a pipeline manager 232, which distributes processing tasks to SIMT parallel processors. The pipeline manager 232 receives instructions from the scheduler 210 of Figure 2, and manages the execution of those instructions via a graphics multiprocessor 234 and / or a texture unit 236. The illustrated graphics multiprocessor 234 is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors of different architectures may be included in the processing cluster 214. One or more instances of the graphics multiprocessor 234 may be included in the processing cluster 214. The graphics multiprocessor 234 may process data, and the data crossbar 240 may be used to distribute the processed data to one of a plurality of possible destinations (including other shader units). The pipeline manager 232 may facilitate the distribution of processed data by specifying a destination for the processed data to be distributed via the data crossbar 240.

[0059] Each graphics multiprocessor 234 within a processing cluster 214 may include the same set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). The function execution logic may be configured in a pipelined manner in which a new instruction may be issued before a previous instruction is completed. The function execution logic supports a wide variety of operations, including integer and floating point arithmetic, comparison operations, Boolean operations, bit shifts, and calculation of various algebraic functions. In one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0060] The instructions transmitted to the processing cluster 214 constitute threads. A group of threads executed across a group of parallel processing engines is a thread group. A thread group executes the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 234. A thread group can include fewer threads than the number of processing engines within the graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines can be idle during the cycle in which the thread group is being processed. A thread group can also include more threads than the number of processing engines within the graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines within the graphics multiprocessor 234, processing can be performed on consecutive clock cycles. In one embodiment, multiple thread groups can be executed concurrently on the graphics multiprocessor 234.

[0061] In one embodiment, the graphics multiprocessor 234 includes an internal cache memory for performing load and store operations. In one embodiment, the graphics multiprocessor 234 can abandon the internal cache and use the cache memory (e.g., L1 cache 308) within the processing cluster 214. Each graphics multiprocessor 234 also has access to the L2 cache within the partition unit (e.g., partition unit 220A-220N of Figure 2) that can be used to transfer data between threads and shared among all processing clusters 214. The graphics multiprocessor 234 can also access off-chip global memory, which can include one or more of the local parallel processor memory and / or system memory. Any memory outside the parallel processing unit 202 can be used as global memory. Embodiments (wherein the processing cluster 214 includes multiple instances of the graphics multiprocessor 234) can share common instructions and data, which can be stored in the L1 cache 308.

[0062] Each processing cluster 214 may include an MMU 245 (memory management unit) configured to map virtual addresses into physical addresses. In other embodiments, one or more instances of the MMU 245 may reside within the memory interface 218 of FIG. 2 . The MMU 245 includes: a set of page table entries (PTEs) for mapping the virtual addresses of tiles (more on tiling) to their physical addresses; and optionally a cache line index. The MMU 245 may include an address translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 234 or L1 cache or processing cluster 214. Physical addresses are processed to distribute surface data access locality, thereby allowing efficient request interleaving among partition units. The cache line index can be used to determine whether a request for a cache line is a hit or a miss.

[0063] In graphics and computing applications, the processing clusters 214 may be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown) or in some embodiments from an L1 cache within the graphics multiprocessor 234, and the texture data is retrieved from an L2 cache, a local parallel processor memory, or a system memory, as needed. Each graphics multiprocessor 234 outputs a processed task to a data crossbar 240 to provide the processed task to another processing cluster 214 for further processing or to store the processed task in an L2 cache, a local parallel processor memory, or a system memory via a memory crossbar 216. A preROP 242 (e.g., a pre-raster operation unit) is configured to receive data from the graphics multiprocessor 234, direct the data to a ROP unit, which may be located with a partition unit (e.g., partition units 220A-220N of FIG. 2 ) as described herein. The preROP 242 unit may perform optimizations for color blending, organize pixel color data, and perform address translations.

[0064] It will be appreciated that the core architecture described herein is illustrative and that variations and modifications are possible. Any number of processing units (e.g., graphics multiprocessor 234, texture unit 236, preROP 242, etc.) may be included within processing cluster 214. Furthermore, while only one processing cluster 214 is shown, a parallel processing unit as described herein may include any number of instances of processing cluster 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0065] Figure 2D A graphics multiprocessor 234 is shown according to one embodiment. In such embodiments, the graphics multiprocessor 234 is coupled to the pipeline manager 232 of the processing cluster 214. The graphics multiprocessor 234 has an execution pipeline that includes, but is not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0066] In one embodiment, the instruction cache 252 receives a stream of instructions to be executed from the pipeline manager 232. The instructions are cached in the instruction cache 252 and dispatched by the instruction unit 254 for execution. The instruction unit 254 can dispatch instructions into thread groups (e.g., warps), where each thread of the thread group is assigned to a different execution unit within the GPGPU core 262. Instructions can access any of the local, shared, or global address spaces by specifying an address within the unified address space. The address mapping unit 256 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 266.

[0067] The register file 258 provides a set of registers for the functional units of the graphics multiprocessor 324. The register file 258 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 262, load / store unit 266) connected to the graphics multiprocessor 324. In one embodiment, the register file 258 is divided between each of the functional units so that each functional unit is allocated a dedicated portion of the register file 258. In one embodiment, the register file 258 is divided between different warps executed by the graphics multiprocessor 324.

[0068] The GPGPU cores 262 may each include a floating point unit (FPU) and / or an integer arithmetic logic unit (ALU), which are used to execute instructions of the graphics multiprocessor 324. Depending on the embodiment, the GPGPU cores 262 may be similar in architecture, or may be different in architecture. For example and in one embodiment, the first part of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while the second part of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic, or may be capable of variable-precision floating-point arithmetic. The graphics multiprocessor 324 may additionally include one or more fixed-function or special-function units to perform specific functions (such as copying rectangles or pixel blending operations). In one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0069] In one embodiment, the GPGPU core 262 includes SIMD logic capable of executing a single instruction to multiple sets of data. In one embodiment, the GPGPU core 262 can physically execute SIMD4, SIMD8 and SIMD16 instructions, and logically execute SIMD1, SIMD2 and SIMD32 instructions. SIMD instructions for the GPGPU core can be generated by the shader compiler at compile time, or can be automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. Multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example and in one embodiment, eight SIMT threads performing the same or similar operation can be executed in parallel via a single SIMD8 logic unit.

[0070] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 234 to the register file 258 and to the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to implement load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, so that data transfer between the GPGPU core 262 and the register file 258 is very low latency. The shared memory 270 can be used to implement communication between threads executed on the functional units within the graphics multiprocessor 234. The cache memory 272 can be used as, for example, a data cache to cache texture data communicated between the functional units and the texture unit 236. The shared memory 270 can also be used as a program-managed cache (cached). Threads executing on the GPGPU core 262 can programmatically store data in the shared memory in addition to the automatically cached data stored in the cache memory 272.

[0071] Figure 3A-3B Additional graphics multiprocessors are shown according to an embodiment. The graphics multiprocessors 325, 350 shown are Figure 2C The illustrated graphics multiprocessors 325, 350 may be configured as streaming multiprocessors (SMs) capable of executing a large number of execution threads simultaneously.

[0072] Figure 3A A graphics multiprocessor 325 is shown according to an additional embodiment. The graphics multiprocessor 325 includes Figure 2DThe graphics multiprocessor 325 may include multiple additional instances of the execution resource unit of the graphics multiprocessor 234. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A-332B, register files 334A-334B, and texture units 344A-344B. The graphics multiprocessor 325 also includes multiple groups of graphics or compute execution units (e.g., GPGPU cores 336A-336B, GPGPU cores 337A-337B, GPGPU cores 338A-338B) and multiple groups of load / store units 340A-340B. In one embodiment, the execution resource unit has a common instruction cache 330, texture and / or data cache memory 342, and shared memory 346.

[0073] Various components may communicate via interconnect structure 327. In one embodiment, interconnect structure 327 includes one or more crossbar switches to enable communication between various components of graphics multiprocessor 325. In one embodiment, interconnect structure 327 is a separate high-speed network fabric layer on which each component of graphics multiprocessor 325 is stacked. Components of graphics multiprocessor 325 communicate with remote components via interconnect structure 327. For example, GPGPU cores 336A-336B, 337A-337B, and 3378A-338B may each communicate with shared memory 346 via interconnect structure 327. Interconnect structure 327 may arbitrate communications within graphics multiprocessor 325 to ensure fair bandwidth allocation between components.

[0074] Figure 3B A graphics multiprocessor 350 according to an additional embodiment is shown. The graphics processor includes multiple sets of execution resources 356A-356D, wherein each set of execution resources includes multiple instruction units, register files, GPGPU cores, and load storage units, such as Figure 2D and Figure 3A . Execution resources 356A-356D may work in concert with texture units 360A-360D for texture operations while sharing instruction cache 354 and shared memory 362. In one embodiment, execution resources 356A-356D may share instruction cache 354 and shared memory 362, as well as multiple instances of texture and / or data cache memory 358A-358B. The various components may be communicated via a communication protocol similar to Figure 3A The interconnect structure 327 and the interconnect structure 352 communicate with each other.

[0075] Those skilled in the art will understand that Figure 1 , 2AThe architectures described in Figures 2-2D and 3A-3B are illustrative and non-limiting with respect to the scope of the present embodiments. Thus, without departing from the scope of the embodiments described herein, the techniques described herein may be implemented on any properly configured processing unit, including but not limited to one or more mobile application processors, one or more desktop or server central processing units (CPUs) (including multi-core CPUs), one or more parallel processing units (such as parallel processing unit 202 of Figure 2), and one or more graphics processors or special purpose processing units.

[0076] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the manner in which the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuits / logic to efficiently process these commands / instructions.

[0077] Technologies for GPU to host processor interconnect

[0078] Figure 4A An exemplary architecture is shown in which multiple GPUs 410-413 are communicatively coupled to multiple multi-core processors 405-406 via high-speed links 440-443 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, the high-speed links 440-443 support 4GB / s, 30GB / s, 80GB / s, or higher communication throughputs, depending on the implementation. Various interconnect protocols may be used, including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. However, the underlying principles of the invention are not limited to any particular communication protocol or throughput.

[0079] Additionally, in one embodiment, two or more of the GPUs 410-413 are interconnected via high-speed links 444-445, which may be implemented using the same or different protocols / links as used for high-speed links 440-443. Similarly, two or more of the multi-core processors 405-406 may be connected via high-speed link 433, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, Figure 4A All communications between the various system components shown in can be achieved using the same protocol / links (eg, through a common interconnect structure). However, as mentioned, the underlying principles of the invention are not limited to any particular type of interconnect technology.

[0080] In one embodiment, each multi-core processor 405-406 is communicatively coupled to processor memory 401-402 via memory interconnects 430-431, respectively, and each GPU 410-413 is communicatively coupled to GPU memory 420-423 via GPU memory interconnects 450-453, respectively. Memory interconnects 430-431 and 450-453 may utilize the same or different memory access technologies. By way of example and not limitation, processor memory 401-402 and GPU memory 420-423 may be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memory, such as 3DXPoint or Nano-Ram. In one embodiment, a portion of the memory may be volatile memory, and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0081] As described below, although the various processors 405-406 and GPUs 410-413 may be physically coupled to specific memories 401-402, 420-423, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed across all of the various physical memories. For example, the processor memories 401-402 may each include 64GB of system memory address space, and the GPU memories 420-423 may each include 32GB of system memory address space (yielding a total of 256GB of addressable memory in this example).

[0082] Figure 4B Additional details are shown for the interconnection between the multi-core processor 407 and the graphics acceleration module 446 according to one embodiment. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card that is coupled to the processor 407 via the high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0083] The processor 407 shown includes multiple cores 460A-460D, each of which has a translation lookaside buffer 461A-461D and one or more caches 462A-462D. The core may include various other components (e.g., instruction fetch unit, branch prediction unit, decoder, execution unit, reorder buffer, etc.) for executing instructions and processing data, which are not shown to avoid confusing the underlying principles of the present invention. Caches 462A-462D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 426 may be included in the cache hierarchy and shared by multiple groups of cores 460A-460D. For example, one embodiment of the processor 407 includes 24 cores, each of which has its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, one of the L2 and L3 caches is shared by two adjacent cores. The processor 407 and the graphics accelerator integrated module 446 are connected to the system memory 441, which may include the processor memories 401-402.

[0084] Coherence is maintained for data and instructions stored in the various caches 462A-462D, 456, and the system memory 441 via inter-core communications over the coherence bus 464. For example, each cache may have cache coherence logic / circuitry associated therewith to communicate over the coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented over the coherence bus 464 to snoop cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art and will not be described in detail herein to avoid obscuring the underlying principles of the present invention.

[0085] In one embodiment, the proxy circuit 425 communicatively couples the graphics acceleration module 446 to the coherence bus 464, thereby allowing the graphics acceleration module 446 to participate in the cache coherence protocol as a peer of the core. Specifically, the interface 435 provides connectivity to the proxy circuit 425 through a high-speed link 440 (e.g., a PCIe bus, NVLink, etc.), and the interface 437 connects the graphics acceleration module 446 to the link 440.

[0086] In one implementation, the accelerator integrated circuit 436 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 431, 432, N of the graphics acceleration module 446. The graphics processing engines 431, 432, N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, N may include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a bit block transfer (blit) engine. In other words, the graphics acceleration module may be a GPU with multiple graphics processing engines 431-432, N, or the graphics processing engines 431-432, N may be individual GPUs integrated on a common package, line card, or chip.

[0087] In one embodiment, the accelerator integrated circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions, such as virtual to physical memory translation (also known as effective to real memory translation) and memory access protocols for accessing the system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In one implementation, the cache 438 stores commands and data for efficient access by the graphics processing engines 431-432, N. In one embodiment, the data stored in the cache 438 and the graphics memory 433-434, N is kept consistent with the core caches 462A-462D, 456 and the system memory 411. As mentioned, this may be accomplished via proxy circuitry 425, which participates in cache coherence mechanisms on behalf of cache 438 and memories 433-434, N (e.g., sending updates to cache 438 (related to modifications / accesses of cache lines on processor caches 462A-462D, 456), and receiving updates from cache 438).

[0088] A set of registers 445 stores context data for threads executed by the graphics processing engines 431-432, N, and context management circuitry 448 manages thread contexts. For example, context management circuitry 448 may perform save and restore operations during context switching to save and restore contexts of various threads (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, upon context switching, context management circuitry 448 may store current register values ​​to a designated area in memory (e.g., identified by a context pointer). It may then restore the register values ​​upon returning to the context. In one embodiment, interrupt management circuitry 447 receives and processes interrupts received from system devices.

[0089] In one implementation, the virtual / effective addresses from the graphics processing engine 431 are translated into real / physical addresses in the system memory 411 by the MMU 439. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator module 446 may be dedicated to a single application executed on the processor 407, or may be shared between multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 431-432, N are shared with multiple applications or virtual machines (VMs). The resources may be subdivided into "slices" that are allocated to different VMs and / or applications (based on the processing requirements and priorities associated with the VMs and / or applications).

[0090] Thus, the accelerator integrated circuit acts as a bridge to the system for the graphics acceleration module 446 and provides address translation and system memory cache services. In addition, the accelerator integrated circuit 436 can provide virtualization facilities for the host processor to manage interrupts, memory management, and virtualization of the graphics processing engine.

[0091] Since the hardware resources of the graphics processing engines 431-432, N are explicitly mapped to the real address space seen by the host processor 407, any host processor can directly address these resources using effective address values. In one embodiment, one function of the accelerator integrated circuit 436 is the physical separation of the graphics processing engines 431-432, N so that they appear to the system as independent units.

[0092] As mentioned, in the illustrated embodiment, one or more graphics memories 433-434, M are respectively coupled to each of the graphics processing engines 431-432, N. The graphics memories 433-434, M store instructions and data being processed by each of the graphics processing engines 431-432, N. The graphics memories 433-434, M may be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory, such as 3D XPoint or Nano-Ram.

[0093] In one embodiment, to reduce data traffic on link 440, biasing techniques are used to ensure that data stored in graphics memory 433-434, M is data that will be used most frequently by graphics processing engines 431-432, N and preferably not used (at least not frequently) by cores 460A-460D. Similarly, the biasing mechanism attempts to keep data needed by a core (and preferably not graphics processing engines 431-432, N) within system memory 411 and the core's cache 462A-462D, 456.

[0094] Figure 4C Another embodiment is shown in which an accelerator integrated circuit 436 is integrated within the processor 407. In this embodiment, the graphics processing engines 431-432, N communicate directly to the accelerator integrated circuit 436 via the interface 437 and the interface 435 (again, which may utilize any form of bus or interface protocol) through the high-speed link 440. The accelerator integrated circuit 436 may execute the same instructions as those for the graphics processing engines 431-432, N. Figure 4B The same operations as those described, but at potentially higher throughput given their close proximity to the coherency bus 462 and caches 462A-462D, 426.

[0095] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The latter may include a programming model controlled by the accelerator integrated circuit 436 and a programming model controlled by the graphics acceleration module 446.

[0096] In one embodiment of a dedicated process model, the graphics processing engines 431-432, N are dedicated to a single application or process under a single operating system. A single application can funnel other application requests to the graphics engines 431-432, N, thereby providing virtualization within a VM / partition.

[0097] In a dedicated process programming model, graphics processing engines 431-432, N can be shared by multiple VM / application partitions. The shared model requires a hypervisor to virtualize graphics processing engines 431-432, N to allow access by each operating system. For a single partition system without a hypervisor, graphics processing engines 431-432, N are owned by the operating system. In both cases, the operating system can virtualize graphics processing engines 431-432, N to provide access to each process or application.

[0098] For the shared programming model, the graphics acceleration module 446 or the individual graphics processing engines 431-432, N use a process handle to select a process element. In one embodiment, the process element is stored in the system memory 411 and is addressable using the effective address to real address conversion technology described herein. The process handle can be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 431-432, N (that is, calling the system software to add the process element to the process element linked list). The lower 16 bits of the process handle can be the offset of the process element within the process element linked list.

[0099] Figure 4D An exemplary accelerator integrated slice 490 is shown. As used herein, a "slice" includes a specified portion of the processing resources of the accelerator integrated circuit 436. The application effective address space 482 within the system memory 411 stores process elements 483. In one embodiment, the process element 483 is stored in response to a GPU call (invocation) 481 from an application 480 executed on the processor 407. The process element 483 contains the process state for the corresponding application 480. The work descriptor (WD) 484 contained in the process element 483 can be a single job requested by the application, or can contain a pointer to a job queue. In the latter case, WD 484 is a pointer to a job request queue in the address space 482 of the application.

[0100] Graphics acceleration module 446 and / or individual graphics processing engines 431-432, N may be shared by all processes or a subset of processes in the system. Embodiments of the present invention include infrastructure for setting up process state and sending WD 484 to graphics acceleration module 446 to start a job in a virtualized environment.

[0101] In one implementation, the dedicated process programming model is implementation specific. In this model, a single process owns the graphics acceleration module 446 or individual graphics processing engine 431. Since the graphics acceleration module 446 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 436 for the owning partition, and the operating system initializes the accelerator integrated circuit 436 for the owning process (when assigning the graphics acceleration module 446).

[0102] In operation, the WD extraction unit 491 in the accelerator integrated slice 490 extracts the next WD 484, which includes an indication of the work to be completed by one of the graphics processing engines of the graphics acceleration module 446. The data from the WD 484 can be stored in the register 445 and used by the MMU 439, the interrupt management circuit 447 and / or the context management circuit 446 as shown. For example, one embodiment of the MMU 439 includes a segment / page walk circuit for accessing the segment / page table 486 within the OS virtual address space 485. The interrupt management circuit 447 can handle the interrupt event 492 received from the graphics acceleration module 446. When performing graphics operations, the effective address 493 generated by the graphics processing engine 431-432, N is converted into a real address by the MMU 439.

[0103] In one embodiment, the same set of registers 445 is replicated for each graphics processing engine 431-432, N, and / or graphics acceleration module 446, and can be initialized by a hypervisor or operating system. Each of these replicated registers can be included in an accelerator integrated slice 490. Example registers that can be initialized by a hypervisor are shown in Table 1.

[0104] Table 1 - Registers initialized by the hypervisor

[0105] 1 Slice Control Register 2 Real address (RA) dispatched process area pointer 3 Permission Mask Override Register 4 Interrupt vector table entry offset 5 Interrupt Vector Table Entry Limits 6 Status Register 7 Logical Partition ID 8 Real Address (RA) Hypervisor Accelerator Utilizing Record Pointers 9 Storage Description Register

[0106] Example registers that may be initialized by the operating system are shown in Table 2.

[0107] Table 2 - Registers initialized by the operating system

[0108] 1 Process and thread identities 2 Effective Address (EA) context save / restore pointer 3 Virtual Address (VA) Accelerator Utilizes Record Pointers 4 Virtual Address (VA) Segment Table Pointer 5 Permission masking 6 Job Descriptor

[0109] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engine 431-432, N. It contains all the information required by the graphics processing engine 431-432, N to complete its work, or it may be a pointer to a memory location of a command queue where the application has set up work to be done.

[0110] Figure 4E Additional details for one embodiment of the sharing model are shown. This embodiment includes a hypervisor real address space 498 in which a process element list 499 is stored. The hypervisor real address space 498 is accessible via a hypervisor 496 that virtualizes a graphics acceleration module engine for an operating system 495.

[0111] The shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 446. There are two programming models where the graphics acceleration module 446 is shared by multiple processes and partitions: time-slice shared and graphics directed shared.

[0112] In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. In order for the graphics acceleration module 446 to support virtualization by the hypervisor 496, the graphics acceleration module 446 may comply with the following requirements: 1) The application's job requests must be autonomous (that is, there is no need to maintain state between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) The application's job requests are guaranteed to be completed within a specified amount of time by the graphics acceleration module 446 (including any translation failures), or the graphics acceleration module 446 provides the ability to preempt the processing of jobs. 3) When operating in a directed sharing programming model, the graphics acceleration module 446 must ensure fairness between processes.

[0113] In one embodiment, for the shared model, the application 480 is required to make an operating system 495 system call with a graphics acceleration module 446 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). The graphics acceleration module 446 type describes the targeted acceleration function for the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446 and can take the form of a graphics acceleration module 446 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure used to describe the work to be completed by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state to be used for the current process. The value passed to the operating system is similar to the application of setting the AMR. If the accelerator integrated circuit 436 and the graphics acceleration module 446 implementation do not support the user authority mask override register (UAMOR), the operating system can apply the current UAMOR value to the AMR value (before passing the AMR in the hypervisor call). Optionally, the hypervisor 496 may apply the current privilege mask overwrite register (AMOR) value (before placing the AMR into the process element 483). In one embodiment, the CSRP is one of the registers 445 that contains the effective address of an area in the application's address space 482 for the graphics acceleration module 446 to save and restore context state. This pointer is optional if state is not required to be saved between jobs or when a job is preempted. The context save / restore area may be pinned system memory.

[0114] Upon receiving the system call, the operating system 495 may verify that the application 480 has been registered and has been given permission to use the graphics acceleration module 446. The operating system 495 then calls the hypervisor 496 with the information shown in Table 3.

[0115] Table 3 – OS to Hypervisor call parameters

[0116] 1 Job Descriptor (WD) 2 Authority Mask Register (AMR) value (potentially masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0117] Upon receiving the hypervisor call, the hypervisor 496 verifies that the operating system 495 has registered and has been given permission to use the graphics acceleration module 446. The hypervisor 496 then places the process element 483 into a linked list of process elements for the corresponding type of graphics acceleration module 446. The process element may include the information shown in Table 4.

[0118] Table 4 - Process element information

[0119] 1 Job Descriptor (WD) 2 Authority Mask Register (AMR) value (potentially masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt vector table derived from hypervisor call parameters 9 Status Register (SR) Value 10 Logical Partition ID (LPID) 11 Real Address (RA) Hypervisor Accelerator Utilizing Record Pointers 12 Storage Device Descriptor Register (SDR)

[0120] In one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 490 registers 445 .

[0121] like Figure 4F As shown in , one embodiment of the present invention employs a unified memory addressable via a common virtual memory address space, which is used to access physical processor memory 401-402 and GPU memory 420-423. In this implementation, operations executed on GPU 410-413 utilize the same virtual / effective memory address space to access processor memory 401-402 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion is allocated to second processor memory 402, a third portion is allocated to GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thereby distributed across each of processor memory 401-402 and GPU memory 420-423, thereby allowing any processor or GPU to access any physical memory (using a virtual address mapped to that memory).

[0122] In one embodiment, bias / coherency management circuits 494A-494E within one or more of MMUs 439A-439E ensure cache coherency between the caches of the host processor (e.g., 405) and GPUs 410-413 and implement biasing techniques that indicate physical memory where certain types of data should be stored. Figure 4FMultiple instances of bias / consistency management circuits 494A- 494E are shown in , but bias / consistency circuits may be implemented within an MMU of one or more host processors 405 and / or within an accelerator integrated circuit 436 .

[0123] One embodiment allows the use of shared virtual memory (SVM) technology to access GPU-attached memory 420-423 and map it as part of system memory without experiencing the typical performance drawbacks associated with full system cache coherence. The ability of GPU-attached memory 420-423 to be accessed as system memory without heavy cache coherence overhead provides a beneficial operating environment for GPU offloading. This arrangement allows the host processor 405 software to set operands and access calculation results without the overhead of traditional I / O DMA data copying. Such traditional copies involve driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, which are all inefficient relative to simple memory accesses. At the same time, the ability to access GPU-attached memory 420-423 without cache coherence overhead can be critical to the execution time of offloaded calculations. In the case of substantial streaming write memory business, for example, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 410-413. The efficiency of operand setup, the efficiency of result access, and the efficiency of GPU calculation all play a role in determining the effectiveness of GPU offloading.

[0124] In one implementation, the selection between GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table may be used, which may be a page granular structure comprising 1 or 2 bits per GPU attached memory page (i.e., controlled at the granularity of a memory page). The bias table may be implemented in a stolen memory range of one or more GPU attached memories 420-423, with or without a bias cache in the GPUs 410-413 (e.g., to cache frequently / recently used entries of the bias table). Alternatively, the entire bias table may be maintained within the GPU.

[0125] In one implementation, the bias table entry associated with each access to the GPU-attached memory 420-423 is accessed before the GPU memory is actually accessed, thereby causing the following operations. First, local requests from GPUs 410-413 to find their pages in the GPU bias are forwarded directly to the corresponding GPU memory 420-423. Local requests from the GPU to find their pages in the host bias are forwarded to the processor 405 (e.g., via a high-speed link as discussed above). In one embodiment, the request from the processor 405 to find the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, the request for a page of the GPU bias can be forwarded to the GPU 410-413. Then, if the GPU is not currently using the page, the GPU can transfer the page to the host processor bias.

[0126] The bias state of a page may be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of situations, a purely hardware-based mechanism.

[0127] One mechanism for changing the bias state employs an API call (e.g., OpenCL) which in turn calls the GPU's device driver, which in turn sends a message (or enqueues a command descriptor) to the GPU, instructing it to change the bias state and perform a cache flushing operation in the host for some transitions. The cache flushing operation is required for transitions from host processor 405 bias to GPU bias, but not for the reverse transition.

[0128] In one embodiment, cache coherency is maintained by temporarily rendering GPU biased pages that are not cacheable by host processor 405. To access these pages, processor 405 may request access from GPU 410, which may or may not immediately grant access (depending on the implementation). Therefore, to reduce communication between processor 405 and GPU 410, it is advantageous to ensure that GPU biased pages are those pages that are required by the GPU but not by host processor 405 (and vice versa).

[0129] Graphics processing pipeline

[0130] Figure 5 2. A graphics processing pipeline 500 is shown according to an embodiment. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included in a parallel processing subsystem as described herein (such as the parallel processor 200 of FIG. 2), which in one embodiment is Figure 12 . Various parallel processing systems may implement the graphics processing pipeline 500 via one or more instances of a parallel processing unit (e.g., parallel processing unit 202 of FIG. 2 ) as described herein. For example, a shader unit (e.g., graphics multiprocessor 234 of FIG. 3 ) may be configured to perform the functions of one or more of a vertex processing unit 504, a tessellation control processing unit 508, a tessellation evaluation processing unit 512, a geometry processing unit 516, and a fragment / pixel processing unit 524. The functions of the data assembler 502, primitive assemblers 506, 514, 518, tessellation unit 510, rasterizer 522, and raster operation unit 526 may also be performed by other processing engines within a processing cluster (e.g., processing cluster 214 of FIG. 3 ) and corresponding partition units (e.g., partition units 220A-220N of FIG. 2 ). The graphics processing pipeline 500 may also be implemented using dedicated processing units for one or more functions. In one embodiment, one or more portions of the graphics processing pipeline 500 may be executed by parallel processing logic within a general purpose processor (e.g., a CPU). In one embodiment, one or more portions of the graphics processing pipeline 500 may access on-chip memory (e.g., such as parallel processor memory 222 in FIG. 2 ) via a memory interface 528, which may be an example of the memory interface 218 of FIG. 2 .

[0131] In one embodiment, the data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. The data assembler 502 then outputs the vertex data including vertex attributes to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes the vertex shader program, lighting and transforming the vertex data as specified by the vertex shader program. The vertex processing unit 504 reads data stored in cache, local or system memory for use in processing vertex data, and the vertex processing unit 504 can be programmed to transform the vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0132] A first instance of primitive assembler 506 receives vertex attributes from vertex processing unit 504. Primitive assembler 506 reads the stored vertex attributes as needed and builds graphics primitives for processing by tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc. as supported by various graphics processing application programming interfaces (APIs).

[0133] The tessellation control processing unit 508 treats the input vertices as control points for the geometric patch. The control points are transformed from the input representation from the patch (e.g., the basis of the patch) to a representation suitable for use in surface evaluation by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 can also calculate tessellation factors for the edges of the geometric patch. The tessellation factors are applied to a single edge and quantize the view-dependent detail level associated with the edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and tessellate the patch into a plurality of geometric primitives such as lines, triangles, or quadrilateral primitives, which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the subdivided patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitive.

[0134] A second instance of primitive assembler 514 receives vertex attributes from tessellation evaluation processing unit 512 (which reads stored vertex attributes as needed) and builds graphics primitives for processing by geometry processing unit 516. Geometry processing unit 516 is a programmable execution unit that executes geometry shader programs to transform graphics primitives received from primitive assembler 514 as specified by the geometry shader programs. In one embodiment, geometry processing unit 516 is programmed to subdivide the graphics primitive into one or more new graphics primitives and to compute parameters for rasterizing the new graphics primitives.

[0135] In some embodiments, the geometry processing unit 516 may add or delete elements in the geometry stream. The geometry processing unit 516 outputs parameters and vertices specifying new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs the graphics primitives for processing by the viewport scaling, picking, and clipping unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or the system memory for use in processing the geometry data. The viewport scaling, picking, and clipping unit 520 performs clipping, picking, and viewport scaling, and outputs the processed graphics primitives to the rasterizer 522.

[0136] The rasterizer 522 can perform depth sorting and other depth-based optimizations. The rasterizer 522 also performs scan conversion on new graphics primitives to generate fragments, and outputs those fragments and associated coverage data to the fragment / pixel processing unit 524. The fragment / pixel processing unit 524 is a programmable execution unit configured to execute a fragment shader program or a pixel shader program. The fragment / pixel processing unit 524 transforms the fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 524 can be programmed to perform the following operations to generate shaded fragments or pixels output to the raster operation unit 526, including but not limited to texture mapping, shading, blending, texture correction, and perspective correction. The fragment / pixel processing unit 524 can read data stored in a parallel processor memory or system memory for use in processing fragment data. The fragment or pixel shader program can be configured to shade with samples, pixels, tiles, or other granularity (depending on the sampling rate configured for the processing unit).

[0137] Raster operations unit 526 is a processing unit that performs raster operations including, but not limited to, stenciling, z-testing, blending, and the like, and outputs pixel data as processed graphics data for storage in graphics memory (e.g., parallel processor memory 222 in FIG. 2 and / or as Figure 1 The raster operations unit 526 may be configured to compress the z or color data written to the memory and to decompress the z or color data read from the memory.

[0138] Encoding 3D rendered images by marking moving objects

[0139] Image information is often transmitted from one electronic device to another. Such information is typically encoded and / or compressed to reduce the bandwidth required for the transmission and / or to reduce the time necessary for the transmission. In some configurations, information about the difference between a current picture and a previous picture may be transmitted, and the device receiving the image information may then, for example, decode and / or decompress the information (e.g., by using the previous picture and the difference to generate the current picture) and provide the image to a viewing device.

[0140] One of the main elements of many video encoding / compression schemes is motion estimation. A video sequence consists of a series of frames. Motion estimation techniques exploit the temporal redundancy between adjacent frames to achieve compression by selecting a certain frame as a reference and predicting subsequent frames from the reference.

[0141] As implied by the name, motion estimation is an estimate and is therefore not completely accurate. In addition, motion estimation algorithms can consume a lot of computing power and time. In some instances, it can be advantageous if motion estimation can be skipped or eliminated from the process.

[0142] Reference now Fig. 6A , showing a block diagram for encoding a 3D (three-dimensional) rendered image from a 3D engine (such as used in gaming scenarios), which "marks" objects that move from frame to frame and allows motion estimation to be eliminated prior to encoding.

[0143] 3D engine 602 outputs digital stream 601, where primitives are marked as static versus moving. 3D engine can be used in gaming applications. Video stream 601 is then sent down 3D pipeline 604, where various operations such as vertex fetch (VFE) 606, vertex shading (VS) 608, rasterization 610, and pixel shading (PS) 612 are performed. This is just a partial list of various functional blocks that can be found in 3D pipeline 604, and there may be other or alternatives known to those skilled in the art. The output of the 3D pipeline can then go to encoder 614. Rasterizer 610 can mark individual pixels 620 as moving or static.

[0144] refer to Figure 6B , this tag can be simply an attribute 622 associated with a specific pixel 620. In the memory buffer 630, the frame pixel surface can store the pixels to be displayed, and the metadata surface 634 can store all the corresponding motion tags. From there, the data in the memory can go to the encoder 614, where the encoder 614 can use the tags 634 to determine which pixels actually moved and which pixels did not move (i.e., skip motion estimation). Knowing the actual motion, as opposed to estimated motion, can be much more accurate and efficient, and can therefore result in more accurate compression rates, bandwidth savings, and a better gaming / viewing experience.

[0145] Reference now Figure 7, a flow chart for encoding a 3D rendered image from a 3D engine (such as used in a gaming situation) is shown, which "marks" objects that move from frame to frame and allows motion estimation to be eliminated before encoding. The illustrated process can be implemented as one or more modules in a set of logic instructions, which are stored in a non-transitory machine or computer readable storage medium (such as random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc.), in configurable logic (such as, for example, a programmable logic array (PLA), a field programmable gate array (FPGA), a complex programmable logic device (CPLD)), in fixed functionality hardware logic using circuit technology (such as, for example, application specific integrated circuit (ASIC), complementary metal oxide semiconductor (CMOS), or transistor-transistor logic (TTL) technology, or any combination thereof).

[0146] After start 700, it may be known whether the video stream is from a 3D engine or some other source 702. Since the 3D engine may be generating motion, it may have motion data available and already know which objects are changing in the x, y, z directions. Other video sources, such as cameras, or some streaming video data may not have motion data available and will likely use normal motion estimation techniques.

[0147] At block 704, the 3D engine may mark the primitive as static or mobile. The primitive and marking may then be processed by the 3D pipeline at 706. The rasterizer may use the primitive information to add attributes to each pixel, thereby marking it as static or mobile. The pixel and attribute markings continue through the remainder of the pipeline 708. At 710, the memory stores the pixel data on the frame surface to be displayed. Similarly, at 712 the markings may be stored on the metadata surface mapped to the pixel frame surface. At 714, the encoder may use the markings to determine which pixels from the previous frame actually moved and which did not move, and completely skip the often expensive motion estimation step. The data may then be more efficiently compressed and sent over the link to be displayed 716.

[0148] Encoding 3D rendered images: The 3D pipeline sends depth information (pixels) to the encoder

[0149] Reference now Fig. 8A , a 3D engine 802 is shown, wherein the 3D engine 802 receives viewport data 803 (e.g., user eye tracking information) in addition to object movement information. In simplified terms, the illustrated 3D engine 802 determines the user's position in the virtual room and / or what the user is looking at. Fig. 8AAs shown in , a 3D engine 802 outputs a digital stream 801 in which primitives are marked as static versus moving. The 3D engine may be used in gaming applications. The video stream 801 is then sent down to a 3D pipeline 804 where various operations such as vertex fetch (VFE) 806, vertex shading (VS) 808, rasterization 810, and pixel shading (PS) 812 are performed. This is only a partial list of the various functional blocks that may be found in the 3D pipeline 804, and there may be other or alternatives known to those skilled in the art. The output of the 3D pipeline may then go to an encoder 814. The rasterizer 810 may mark individual pixels 820 as foreground or background (i.e., depth).

[0150] refer to Figure 8B , this depth tag can be simply an attribute 822 associated with a specific pixel 820. In the memory buffer 830, the frame pixel surface can store the pixels to be displayed, and the metadata surface 834 can store all the corresponding depth tags. From there, the data in memory can go to the encoder 814, where the encoder 814 can use the tags 834 to determine which pixels are in the foreground and which pixels are in the background. Based on this depth information, different encoding / compression schemes can be used for the foreground and background, with the foreground generally being higher quality to save bandwidth and allow for a better gaming / viewing experience.

[0151] Reference now Figure 8C , a flow chart for encoding a 3D rendered image from a 3D engine (such as used in a gaming situation) is shown, which "tags" objects as foreground or background based on the current viewport. The illustrated process can be implemented as one or more modules in a set of logical instructions stored in a non-transitory machine or computer readable storage medium (such as RAM, ROM, PROM, firmware, flash memory, etc.), in configurable logic (such as, for example, PLA, FPGA, CPLD), in fixed functional hardware logic using circuit technology (such as, for example, ASIC, CMOS or TTL technology, or any combination thereof). After starting 850, it may be known whether the video stream is from the 3D engine or some other source 852, because the 3D engine may know the viewport location while other video sources may not.

[0152] At box 854, the 3D engine can mark the primitive as foreground or background. The primitive and mark can then be processed by the 3D pipeline at 856. The rasterizer can use the primitive information to add attributes to each pixel, thereby marking it as foreground or background. The pixel and attribute marking continues through the remainder of the pipeline 858. At 860, the memory stores the pixel data on the frame surface to be displayed. Similarly, at 862, the mark can be stored on the metadata surface mapped to the pixel frame surface. At 864, the encoder can use the mark to determine which pixels are foreground and background and can encode / compress the foreground picture with a higher quality than the background pixels, thereby saving a lot of bandwidth. The data compressed more efficiently is sent through the link to be displayed 866.

[0153] Apply DCT (Discrete Cosine Transform) 3D color compression

[0154] Referring to FIG. 9A , there is shown a 3D pipeline 904 similar to the 3D pipeline 604 already discussed ( Fig. 6A ) and 804 ( Fig. 8A ). The details are not repeated here to avoid redundancy. As previously discussed, data from pipeline 904 may be stored in pixel frame memory 906. 3D pipeline 904 typically performs pixel color compression on the data before the pixel data is stored in memory 906. Thereafter, the data may be read out to media encoder pipeline 908. However, media encoder pipeline 908 includes a decompression module 910 to decompress the pixel data prior to compression module 912 (e.g., DCT) to reuse any of a number of suitable compression schemes suitable for transmission to a user over the Internet or other link.

[0155] refer to Fig. 9B As previously discussed, the 3D pipeline 904 already has motion information available to it (e.g., whether an object has moved or was static for the previous frame) as well as depth information. Therefore, the 3D pipeline 904 may have enough information to convert the pixel data directly into JPEG-DCT and Z compression. JPEG-DCT stands for Joint Photographic Experts Group-Discrete Cosine Transform, which is suitable for direct transmission to users over the Internet. Therefore, in situations where JPEG-DCT or Z compression (depth compression) is desired, embodiments advantageously eliminate the media encoder pipeline 908 and the power and time penalties associated with it.

[0156] Reference now Fig. 9C, a flow chart of a 3D pipeline and a picture frame memory is shown, which can transmit appropriately compressed / encoded data over the Internet without the need for a separate media encoder pipeline. The illustrated process can be implemented as one or more modules in a set of logical instructions, which are stored in a non-transitory machine or computer readable storage medium (such as RAM, ROM, PROM, firmware, flash memory, etc.), stored in a configurable logic (such as, for example, PLA, FPGA, CPLD), stored in a fixed functional hardware logic using circuit technology (such as, for example, ASIC, CMOS or TTL technology, or any combination thereof). After starting 950, it can be determined in box 952 whether JPEG-DCT or Z compression is suitable for the current media. If not, it will proceed as normal. More specifically, in the illustrated box 954, the 3D pipeline will perform picture color compression, where box 956 can then send the pixels to the pixel frame memory. The illustrated box 958 then sends the data to the media pipeline, where it can be decompressed and encoded / compressed again into a suitable format for transmission over the Internet or other network.

[0157] On the other hand, if the media is determined to be suitable for JPEG-DCT or Z compression at block 952, the 3D pipeline may determine motion and / or depth data for the pixel at block 960. Illustrated block 962 directly performs JPEG-DCT or Z compression before sending the data to a pixel frame store at block 964 for transmission to a client / user over the Internet or a suitable link.

[0158] Workload distribution via FPGA / ASIC

[0159] According to embodiments of the present invention, workloads may be optimized between ASICs (Application Specific Integrated Circuits), SW (Software), and FPGAs (Field Programmable Gate Arrays) in large computing facilities. Thus, for example, if a large online retailer or Internet entertainment company streams movies and shows over the Internet, the entity may maintain a very large server farm that continually changes the way video is encoded and / or sent (e.g., changes in encryption, compression, how colors are mapped, etc.). The things that are changing may not yet be implemented in hardware (e.g., central processing unit / CPU, graphics processing unit / GPU). Therefore, new algorithms may be implemented in software.

[0160] Unfortunately, software is usually the least preferred option because it is often slower and more power intensive than a codec running on ASIC or FPGA hardware. Fig. 10A , there is a diagram of a workload distribution scheme according to one embodiment. You can get a scheduler 1000 into which a large number of video streams 1002 are being requested.

[0161] Thus, there may be numerous video streams at any given time, and this may be constant while the system is running, with each stream having a requested codec. There may be multiple ASICs programmed to run multiple different codecs 1-N 1002, there may also be multiple FPGAs programmed to run multiple different codecs 1-M 1004. The illustrated scheduler 1000 will schedule the flows according to the algorithm and preferably to the appropriate codec on the ASIC 1002 or FPGA 1004. If the codec has not been implemented in the ASIC 1002 or programmed into the FPGA 1004, it may be executed in software invoked by the CPU / GPU. In this case, the software tracking module 1006 collects statistics about the number of times a particular codec is used, how long it runs, etc. Once a threshold has been met (e.g., the number of times a codec has been used in a given time period), it may be determined that the codec should be programmed into the FPGA (designated herein as FPGA M+1 )1008.

[0162] By continuing to refer Fig. 10A and 10B , a flow chart starting at block 1050 is shown, which illustrates the above system. In block 1052, the scheduler 1000 schedules the video stream for a specific codec available on an ASIC or FPGA. If not available, block 1052 may schedule the codec to be executed via software. In decision block 1054, it is determined whether software is used. In block 1056, statistics about each codec call are compiled. In block 1058, once the threshold for a specific codec has been reached, a decision is made to implement the specific codec in FPGA 1008.

[0163] Display Technology

[0164] Now go to Fig.11, a performance-enhanced computing system 1100 is shown. In the illustrated example, the processor 1110 is coupled to a display 1120. The processor 1110 may generally generate an image to be displayed on an LCD panel 1150 of the display 1120. In one example, the processor 1110 includes a communication interface, such as, for example, a video graphics array (VGA), a display port (DP) interface, an embedded display port (eDP) interface, a high-definition multimedia interface (HDMI), a digital visual interface (DVI), and the like. The processor 1110 may be a graphics processor (e.g., a graphics processing unit / GPU) that processes graphics data and generates an image (e.g., a video frame, a still image) displayed on the LCD panel 1150. Moreover, the processor 1110 may include one or more image processing pipelines that generate pixel data. The image processing pipeline may conform to the OPENGL architecture or other suitable architectures. In addition, the processor 1110 may be connected to a host processor (e.g., a central processing unit / CPU), wherein the host processor executes one or more device drivers that control the processor 1110 and / or interact with it.

[0165] The illustrated display 1120 includes a timing controller (TCON) 1130 that can individually address different pixels in the LCD panel 1150 and update each individual pixel in the LCD panel 1150 per refresh cycle. In this regard, the LCD panel 1150 can include a plurality of liquid crystal elements, such as, for example, liquid crystals and integrated color filters. Each pixel of the LCD panel 1150 can include a group of three liquid crystal elements having red, green, and blue color filters, respectively. The LCD panel 1150 can arrange these pixels in a two-dimensional (2D) array, which is controlled via a row driver 1152 and a column driver 1154 to update the image being displayed by the LCD panel 1150. Thus, the TCON 1130 can drive the row driver 1152 and the column driver 1154 to address specific pixels of the LCD panel 1150. The TCON 1130 can also adjust the voltage provided to the liquid crystal element in the pixel to change the light intensity that penetrates each of the three liquid crystal elements, and thus change the color of the pixel displayed on the surface of the LCD panel 1150.

[0166] The backlight 1160 may include a plurality of light emitting elements, such as, for example, light emitting diodes (LEDs), arranged at the edges of the LCD panel 1150. Accordingly, the light generated by the LEDs may be dispersed by a diffuser (not shown) through the LCD panel 1150. In another example, the LEDs are arranged in a 2D array directly behind the LCD panel 1150, in a configuration sometimes referred to as direct backlighting because each LED disperses light through one or more corresponding pixels of the LCD panel 1150 positioned in front of the LED. The light emitting elements may also include compact fluorescent lamps (CFLs) arranged along one or more edges of the LCD panel 1150. To eliminate multiple edges, the combination of edges may be modified to achieve selective illumination of an area, where fewer lighting elements than a full set of lighting elements are used with less power.

[0167] The light emitting element may also include one or more sheets of electroluminescent material placed behind the LCD panel 1150. In such cases, light from the surface of the sheet may be dispersed through the pixels of the LCD panel 1150. In addition, the sheet may be divided into multiple regions, such as, for example, one divided into four. In one example, each region is individually controlled to illuminate only a portion of the LCD panel 1150. Other backlight solutions may also be used.

[0168] The illustrated display 1120 also includes a backlight controller (BLC) 1140 that provides voltage to the light-emitting elements of the backlight 1160. For example, the BLC 1140 may include a pulse width modulation (PWM) driver (not shown) to generate a PWM signal that activates at least some of the light-emitting elements of the backlight 1160. The duty cycle and frequency of the PWM signal may cause the light generated by the light-emitting elements to dim. For example, a 100% duty cycle may correspond to a light-emitting element being fully powered on, and a 0% duty cycle may correspond to a light-emitting element being fully powered off. Thus, intermediate duty cycles (e.g., 25%, 50%) typically cause the light-emitting elements to be turned on within a portion of the cycle period that is proportional to the percentage of the duty cycle. The cycle period may be fast enough so that the flickering of the light-emitting elements is not noticeable to the human eye. In addition, the impact on the user may be that the degree of light emitted by the backlight 1160 is lower than when the backlight 1160 is fully activated. The BLC 1140 may be separate from or incorporated into the TCON 1130.

[0169] Alternatively, an emissive display system may be used, where LCD panel 1150 would be replaced by an emissive display panel (eg, organic light emitting diode / OLED), backlight 1160 would be omitted, and pixel color and brightness could be modulated directly using row and column drivers 1152 and 1154, respectively.

[0170] Display resolution based on distance

[0171] Fig. 12A A situation is shown in which a user 1218 interacts with a data processing device 1200 that includes a display unit 1228. The display processing device 1200 may include, for example, a notebook computer, a desktop computer, a tablet computer, a convertible tablet, a mobile Internet device (MID), a personal digital assistant (PDA), a wearable device (e.g., a head mounted display / HMD), a media player, etc. or any combination thereof. The illustrated data processing device 1200 includes a processor 1224 (e.g., an embedded controller, a microcontroller, a host processor, a graphics processor) coupled to a memory 1222, which may include storage locations addressable by the processor 1224. As will be discussed in more detail, the distance sensor 1210 may enable a distance-based display resolution for the display unit 1228.

[0172] The illustrated memory 1222 contains display data 1226 to be rendered on the display unit 1228. In one example, the processor 1224 performs data conversion on the display data 1226 before presenting the display data 1226 on the display unit 1228. The post-processing engine 1214 may be executed on the processor 1224 to receive the display data 1226 and the output of the distance sensor 1210. The post-processing engine 1214 may modify the display data 1226 to enhance the readability of the screen content on the display unit 1228, reduce power consumption in the data processing device 1200, etc., or any combination thereof.

[0173] In addition to the operating system 1212 and the applications 1220, the illustrated memory 1222 stores a display resolution setting 1216. The display resolution setting 1216 may specify a number of pixels of the display data 1226 to be presented on the display unit 1228 along the length dimension and the width dimension. If the display data 1226 generated by the application 1220 is not compatible with the format of the display unit 1228, the processor 1224 may configure the scale of the display data 1226 to match the format of the display unit 1228. In this regard, the display resolution setting 1216 may be associated with and / or incorporated into configuration data defining other settings for the display unit 1228. Furthermore, the display resolution setting 1216 may be defined in terms of unit distance or area (e.g., pixels per inch / PPI) or other suitable parameters.

[0174] The application 1220 can generate a user interface, where the user 1218 can interact with the user interface to select a display resolution setting 1216 from one or more options provided through the user interface, enter the display resolution setting 1216 as a requested value, etc. Thus, the display data 1226 can be resized to fit the display resolution setting 1216 before being rendered on the display unit 1228.

[0175] The distance sensor 1210 may track the distance between the user 1218 and the display unit 1228, wherein the distance sensing may be triggered by a physical button associated with the data processing device 1200 / display unit 1228, by a user interface provided by the application 1220 and / or the loading of the operating system 1220, etc. For example, during booting of the data processing device 1200, the operating system 1212 may perform an automatic process for triggering distance sensing in the background or foreground. The distance sensing may be performed periodically or continuously.

[0176] Fig. 12B An example of a distance sensing scenario is shown. In the illustrated example, the distance sensor 1210 uses a transceiver 1208 to transmit an electromagnetic beam 1202 in the direction of a user 1218. Thus, the transceiver 1202 may be located at a data processing device 1200 ( Fig. 12A ). Electromagnetic beam 1202 may impact user 1218 and be reflected / scattered from user 1218 as return electromagnetic beam 1204. Return electromagnetic beam 1204 may be processed by processor 1224 ( Fig. 12A ) and / or post-processing engine 1214 ( Fig. 12A ) analysis to determine whether the user 1218 and the display unit 1228 ( Fig. 12A ) between the two images 1206. The distance 1206 can be used to adjust the display resolution setting 1216.

[0177] Display Layer

[0178] Now go to Fig.13 , a display system 1300 is shown in which cascaded display layers 1361, 1362, and 1363 are used to achieve spatial / temporal super-resolution in a display assembly 1360. In the illustrated example, the processor 1310 provides initial graphics data 1334 (e.g., video frames, still images) to the system 1300 via a bus 1320. The cascaded display program 1331 can be stored in a memory 1330, where the cascaded display program 1331 can be part of a display driver associated with the display assembly 1360. The illustrated memory 1330 also includes the initial graphics data 1334 and the factorized graphics data 1335. In one example, the cascaded display program 1331 includes a temporal factorization component 1332 and a spatial factorization component 1333. The temporal factorization component 1332 can perform temporal factorization calculations, and the spatial factorization component can perform spatial factorization calculations. The cascaded display program 1331 may derive factorized graphics data 1335 for presentation on each display layer 1361 , 1362 , and 1363 based on the user configuration and the initial graphics data 1334 .

[0179] Display assembly 1360 may be implemented as an LCD (liquid crystal display) such as used in head mounted display (HMD) applications. More specifically, display assembly 1360 may include a stack of LCD panels, an interface board, lens attachments, and the like. Each panel may, for example, operate at a native resolution of 1280x800 pixels and at a 60 Hz refresh rate. Other native resolutions, refresh rates, display panel technologies, and / or layer configurations may be used.

[0180] Multiple display units

[0181] Fig.14 A graphical display system 1400 is shown that includes a set of display units 1430 (1430a-1430n) that are generally operable to output a widescreen (e.g., panoramic) presentation 1440 that includes coordinated content in a cohesive and structured topology. In the illustrated example, a data processing device 1418 includes a processor 1415 that applies a logic function 1424 to hardware profile data 1402 received from the set of display units 1430 over a network 1420. When the hardware profile data is not found to match a set of settings in a hardware profile lookup table 1412, the application of the logic function 1424 to the hardware profile data 1402 may create a set of automatic topology settings 1406. The illustrated set of automatic topology settings 1406 is transmitted from the display processing device 1418 to the display units 1430 over the network 1420.

[0182] The processor 1415 may execute and run the logic function 1424 upon receiving the logic function 1424 from the display driver 1410. In this regard, the display driver 1410 may include an automatic topology module 1408 that automatically configures and constructs the topology of the display unit 1432 to create the presentation 1440. In one example, the display driver 1410 is a set of instructions that, when executed by the processor 1415, causes the data processing device 1418 to communicate with the display unit 1430, a video card, etc., and perform an automatic topology generation operation.

[0183] Data processing device 1418 may include, for example, a server, a desktop computer, a notebook computer, a tablet computer, a convertible tablet, a MID, a PDA, a wearable device, a media player, and the like. Thus, display processing device 1418 may include hardware control module 1416, storage device 1414, random access memory (RAM, not shown), a controller card including one or more video controller cards, and the like. In one example, display unit 1430 is a flat panel display (e.g., liquid crystal, active matrix, plasma, etc.), HMD, video projection device, and the like that coordinate with each other to produce presentation 1440. In addition, presentation 1440 may be generated based on media files stored in storage device 1414, where the media files may include, for example, movies, video clips, animations, advertisements, and the like, or any combination thereof.

[0184] The term "topology" may be considered as the number, scaling, shape, and / or other configuration parameters of the first display unit 1430a, the second display unit 1430b, the third display unit 1430n, and the like. Accordingly, the topology of the display unit 1430 may enable the presentation 1440 to be visually consistent, such that the individual portions of the presentation 1440 are proportional to and compatible with the original dimensions and extent of the media being played through the display unit 1430. Thus, the topology may constitute geometric properties and / or spatial relationships that are not affected by continuous changes in the size or shape of the content rendered in the presentation 1440. In one example, the automatic topology module 1408 includes a timing module 1426, a control module 1428, a signal monitor module 1432, and a signal display module 1434. The timing module 1426 may designate a specific display unit in the set of display units 1430 as a sample display unit. In such a case, the timing module 1426 may designate the remaining display units 1430 as additional display units. In one example, the timing module 1426 can automatically set the form factor to be compatible with the hardware profile data 1402 , where the presentation 1440 is automatically initiated by a sequence of graphic signals 1422 .

[0185] In one example, the control module 1428 modifies the set of automatic topology settings 1406. In addition, the signal monitor module 1432 can automatically monitor the sequence graphic signal 1422 and trigger the storage device 1414 to associate the set of automatic topology settings 1406 with the hardware profile lookup table 1412. Moreover, the signal monitor module 1432 can automatically detect changes in the set of display units 1430 according to a set of change criteria and automatically generate a new topology profile corresponding to the changes in the set of display units 1430. Thus, the new topology profile can be applied to the set of display units 1430. If the sequence graphic signal 1422 fails to meet a set of criteria, the signal monitor module 1432 can also trigger the signal display module 1434 to reapply the set of automatic topology settings 1406. If the hardware profile data 1402 does not support the automatic topology display of the sequence graphic signal 1422, the data processing device 1418 can report an error and record the error in the error log 1413.

[0186] Cloud-assisted media delivery

[0187] Now go to Fig.15 , the cloud gaming system 1500 includes a client 1540 coupled to a server 1520 via a network 1510. The client 1540 may generally be a consumer of graphics (e.g., games, virtual reality / VR, augmented reality / AR) content stored, processed, and rendered on the server 1520. The illustrated server 1520 (which may be scalable) has the capacity to provide graphics content to multiple clients simultaneously (e.g., by utilizing parallel and shared processing and rendering resources). In one example, the scalability of the server 1520 is limited by the capacity of the network 1510. Accordingly, there may be a certain threshold number of clients above which the service to all clients may be degraded.

[0188] In one embodiment, server 1520 includes a graphics processor (e.g., GPU) 1530, a host processor (e.g., CPU) 1524, and a network interface card (NIC) 1522. NIC 1522 can receive requests for graphics content from clients 1540. The request from client 1540 can cause the graphics content to be retrieved from memory via an application executed on host processor 1524. Host processor 1524 can perform high-level operations, such as, for example, determining the position, collision, and motion of objects in a given scene. Based on the high-level operations, host processor 1524 can generate rendering commands, which can be combined with scene data and executed by graphics processor 1530. The rendering commands can cause graphics processor 1530 to define scene geometry, shading, lighting, motion, textures, camera parameters, etc. for a scene to be rendered via client 1540.

[0189] More specifically, the illustrated graphics processor 1530 includes a graphics renderer 1532 that executes rendering procedures according to rendering commands generated by the host processor 1524. The output of the graphics renderer 1532 may be a raw video frame stream that is provided to a frame capturer 1534. The illustrated frame capturer 1534 is coupled to an encoder 1536, which may compress / format the raw video stream for transmission over the network 1510. The encoder 1536 may use a variety of video compression algorithms, such as, for example, the H.246 standard from the International Telecommunication Union Telecommunication Standardization Sector (ITUT), the MPEG4 Advanced Video Coding (AVC) standard from the International Organization for Standardization / International Electrotechnical Commission (ISO / IEC), and the like.

[0190] The illustrated client 1540 (which may be a desktop computer, notebook computer, tablet computer, convertible tablet, wearable device, MID, PDA, media player, etc.) includes a NIC 1542 for receiving a transmitted video stream from the server 1520. The NIC 1522 may include the base and physical layers of the software layer for the network interface in the client 1540 to facilitate communication over the network 1510. The client 1540 may also include a decoder 1544 that employs the same formatting / compression scheme of the encoder 1536. Thus, the decompressed video stream may be provided from the decoder 1544 to a video renderer 1546. The illustrated video renderer 1546 is coupled to a display 1548 that visually presents graphical content.

[0191] As already noted, the graphical content may include gaming content. In this regard, the client 1540 may perform real-time interactive streaming, which involves collecting user input from the input device 1550 and delivering the user input to the server 1520 via the network 1510. This real-time interactive component of cloud gaming may pose challenges with respect to latency.

[0192] Additional System Overview Examples

[0193] Fig.16 16 is a block diagram of a processing system 1600 according to an embodiment. In various embodiments, the system 1600 includes one or more processors 1602 and one or more graphics processors 1608, and may be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 1602 or processor cores 1607. In one embodiment, the system 1600 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in a mobile device, a handheld device, or an embedded device.

[0194] Embodiments of system 1600 may include or be incorporated into: a server-based gaming platform, a gaming console (including gaming and media consoles, mobile gaming consoles, handheld gaming consoles, or online gaming consoles). In some embodiments, system 1600 is a mobile phone, a smart phone, a tablet computing device, or a mobile Internet device. Data processing system 1600 may also include, be coupled to, or be integrated into: a wearable device, such as a smart watch wearable device, a smart glasses (eyewear) device, an augmented reality device, or a virtual reality device. In some embodiments, data processing system 1600 is a television or set-top box device having one or more processors 1602 and a graphical interface generated by one or more graphics processors 1608.

[0195] In some embodiments, one or more processors 1602 each include one or more processor cores 1607 for processing instructions, which when executed perform operations for system and user software. In some embodiments, each of the one or more processor cores 1607 is configured to process a specific instruction set 1609. In some embodiments, the instruction set 1609 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). Multiple processor cores 1607 can each process different instruction sets 1609, which may include instructions for facilitating emulation of other instruction sets. The processor core 1607 may also include other processing devices, such as a digital signal processor (DSP).

[0196] In some embodiments, the processor 1602 includes a cache memory 1604. Depending on the architecture, the processor 1602 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of the processor 1602. In some embodiments, the processor 1602 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which may be shared among the processor core 1607 using known cache coherence techniques. A register file 1606 is additionally included in the processor 1602, and the register file may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of the processor 1602.

[0197] In some embodiments, processor 1602 is coupled to processor bus 1610 to transmit communication signals (such as address, data or control signals) between processor 1602 and other components in system 1600. In one embodiment, system 1600 uses an exemplary 'hub' system architecture, including a memory controller hub 1616 and an input output (I / O) controller hub 1630. Memory controller hub 1616 facilitates communication between memory devices and other components of system 1600, while I / O controller hub (ICH) 1630 provides connections to I / O devices via a local I / O bus. In one embodiment, the logic of memory controller hub 1616 is integrated within the processor.

[0198] The memory device 1620 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device having suitable properties to act as a process memory. In one embodiment, the memory device 1620 may operate as a system memory for the system 1600 to store data 1622 and instructions 1621 for use when the one or more processors 1602 execute applications or processes. The memory controller hub 1616 is also coupled to an optional external graphics processor 1612, which may communicate with one or more graphics processors 1608 in the processor 1602 to perform graphics and media operations.

[0199] In some embodiments, the ICH 1630 enables peripherals to connect to the memory device 1620 and the processor 1602 via a high-speed I / O bus. The I / O peripherals include, but are not limited to, an audio controller 1646, a firmware interface 1628, a wireless transceiver 1626 (e.g., Wi-Fi, Bluetooth), a data storage device 1624 (e.g., a hard drive, flash memory, etc.), and a legacy I / O controller 1640 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 1642 connect input devices (such as a keyboard and mouse 1644 combination). A network controller 1634 may also be coupled to the ICH 1630. In some embodiments, a high-performance network controller (not shown) is coupled to the processor bus 1610. It will be appreciated that the system 1600 shown is exemplary and not limiting, as other types of data processing systems configured in different ways may also be used. For example, the I / O controller hub 1630 may be integrated within the one or more processors 1602 , or the memory controller hub 1616 and the I / O controller hub 1630 may be integrated within a discrete external graphics processor, such as the external graphics processor 1612 .

[0200] Fig.17 is a block diagram of an embodiment of a processor 1700 having one or more processor cores 1702A- 1702N, an integrated memory controller 1714 , and an integrated graphics processor 1708 . Fig.17 Those elements with the same reference numbers (or names) as those of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto. Processor 1700 may include additional cores up to and including additional core 1702N represented by a dashed box. Each of processor cores 1702A-1702N includes one or more internal cache units 1704A-1704N. In some embodiments, each processor core is also capable of accessing one or more shared cache units 1706.

[0201] Internal cache units 1704A-1704N and shared cache unit 1706 represent a cache memory hierarchy within processor 1700. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared intermediate level caches (such as level 2 (L2), level 3 (L3), level 4 (L4), or other level caches), where the highest level cache in front of external memory is classified as LLC. In some embodiments, cache coherence logic maintains coherence between the various cache units 1706 and 1704A-1704N.

[0202] In some embodiments, the processor 1700 may also include a set of one or more bus controller units 1716 and a system agent core 1710. The one or more bus controller units 1716 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express buses). The system agent core 1710 provides management functionality for various processor components. In some embodiments, the system agent core 1710 includes one or more integrated memory controllers 1714 to manage access to various external memory devices (not shown).

[0203] In some embodiments, one or more of the processor cores 1702A-1702N include support for simultaneous multithreading. In such embodiments, the system agent core 1710 includes components for coordinating and operating the cores 1702A-1702N during multithreaded processing. The system agent core 1710 may additionally include a power control unit (PCU) that includes logic and components for regulating the power state of the processor cores 1702A-1702N and the graphics processor 1708.

[0204] In some embodiments, the processor 1700 additionally includes a graphics processor 1708 for performing graphics processing operations. In some embodiments, the graphics processor 1708 is coupled to a set of shared cache units 1706 and a system agent core 1710 (including one or more integrated memory controllers 1714). In some embodiments, a display controller 1711 is coupled to the graphics processor 1708 to drive the graphics processor output to one or more coupled displays. In some embodiments, the display controller 1711 can be a separate module coupled to the graphics processor via at least one interconnect, or can be integrated within the graphics processor 1708 or the system agent core 1710.

[0205] In some embodiments, a ring-based interconnect unit 1712 is used to couple the internal components of the processor 1700. However, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies, including those well known in the art. In some embodiments, the graphics processor 1708 is coupled to the ring interconnect 1712 via an I / O link 1713.

[0206] Exemplary I / O links 1713 represent at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 1718, such as an eDRAM module. In some embodiments, each of processor cores 1702-1702N and graphics processor 1708 use embedded memory module 1718 as a shared last-level cache.

[0207] In some embodiments, processor cores 1702A-1702N are homogeneous cores that execute the same instruction set architecture. In another embodiment, processor cores 1702A-1702N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of processor cores 1702A-N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, processor cores 1702A-1702N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively higher power consumption are coupled with one or more power cores with lower power consumption. In addition, processor 1700 can be implemented on one or more chips or as a SoC integrated circuit having the components shown in addition to other components.

[0208] Fig.181 is a block diagram of a graphics processor 1800, which may be a discrete graphics processing unit, or may be a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates via a mapped I / O interface to registers on the graphics processor and using commands placed in processor memory. In some embodiments, the graphics processor 1800 includes a memory interface 1814 for accessing memory. The memory interface 1814 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0209] In some embodiments, the graphics processor 1800 also includes a display controller 1802 for driving display output data to a display device 1820. The display controller 1802 includes hardware for composing multiple layers of video or user interface elements and one or more overlapping planes for a display. In some embodiments, the graphics processor 1800 includes a video codec engine 1806 for encoding, decoding, or transcoding media to, from, or between one or more media encoding formats, including, but not limited to, Moving Picture Experts Group (MPEG) formats (such as MPEG-2), Advanced Video Coding (AVC) formats (such as H.264 / MPEG-4 AVC), and Society of Motion Picture & Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) formats (such as JPEG, and Motion JPEG (MJPEG) formats).

[0210] In some embodiments, graphics processor 1800 includes a block image transfer (BLIT) engine 1804 for performing two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 1810. In some embodiments, graphics processing engine 1810 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0211] In some embodiments, GPE 1810 includes a 3D pipeline 1812 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 1812 contains programmable and fixed function elements that perform various tasks within the element and / or generate execution threads to 3D / media subsystem 1815. Although 3D pipeline 1812 can be used to perform media operations, embodiments of GPE 1810 also include a media pipeline 1816 that is specifically used to perform media operations, such as video post-processing and image enhancement.

[0212] In some embodiments, the media pipeline 1816 includes fixed-function or programmable logic units for performing one or more specialized media operations (such as video decoding acceleration, video deinterlacing, and video encoding acceleration) instead of or on behalf of the video codec engine 1806. In some embodiments, the media pipeline 1816 additionally includes a thread generation unit to generate threads for execution on the 3D / media subsystem 1815. The generated threads perform calculations for the media operations on one or more graphics execution units included in the 3D / media subsystem 1815.

[0213] In some embodiments, the 3D / media subsystem 1815 includes logic for executing threads generated by the 3D pipeline 1812 and the media pipeline 1816. In one embodiment, the pipeline sends thread execution requests to the 3D / media subsystem 1815, which includes thread dispatch logic for arbitrating and dispatching various requests for available thread execution resources. The execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, the 3D / media subsystem 1815 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) to share data between threads and store output data.

[0214] 3D / Media Processing

[0215] Fig.19 is a block diagram of a graphics processing engine 1910 of a graphics processor according to some embodiments. In one embodiment, GPE 1910 is Fig.18 The version of GPE 1810 shown in . Fig.19 Elements in FIG. 1 having the same reference number (or name) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto.

[0216] In some embodiments, the GPE 1910 is coupled to a command streamer 1903 that transmits command streams to the GPE 3D and media pipelines 1912, 1916. In some embodiments, the command streamer 1903 is coupled to a memory, which may be a system memory, or may be one or more of an internal cache memory and a shared cache memory. In some embodiments, the command streamer 1903 receives commands from the memory and sends the commands to the 3D pipeline 1912 and / or the media pipeline 1916. The commands are instructions extracted from a ring buffer storing commands for the 3D pipeline 1912 and the media pipeline 1916. In one embodiment, the ring buffer may additionally include a batch command buffer storing multiple batches of multiple commands. The 3D pipeline 1912 and the media pipeline 1916 process the commands by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to the execution unit array 1914. In some embodiments, execution unit array 1914 is scalable such that the array includes a variable number of execution units based on the target power and performance level of GPE 1910 .

[0217] In some embodiments, sampling engine 1930 is coupled to memory (e.g., cache memory or system memory) and execution unit array 1914. In some embodiments, sampling engine 1930 provides a memory access mechanism for execution unit array 1914 that allows execution array 1914 to read graphics and media data from memory. In some embodiments, sampling engine 1930 includes logic for performing specialized image sampling operations for media.

[0218] In some embodiments, the specialized media sampling logic in the sampling engine 1930 includes a denoising / de-interlacing module 1932, a motion estimation module 1934, and an image scaling and filtering module 1936. In some embodiments, the denoising / de-interlacing module 1932 includes logic for performing one or more of a denoising or de-interlacing algorithm on the decoded video data. The de-interlacing logic combines alternating fields of interlaced video content into a single frame of video. The denoising logic reduces or removes data noise from the video and image data. In some embodiments, the denoising logic and de-interlacing logic are motion adaptive and use spatial or temporal filtering based on the amount of motion detected in the video data. In some embodiments, the denoising / de-interlacing module 1932 includes specialized motion detection logic (e.g., within the motion estimation engine 1934).

[0219] In some embodiments, the motion estimation engine 1934 provides hardware acceleration for video operations by performing video acceleration functions (such as motion vector estimation and prediction) on video data. The motion estimation engine determines motion vectors that describe transformations of image data between consecutive video frames. In some embodiments, the graphics processor media codec uses the video motion estimation engine 1934 to perform operations on macroblock-level video that otherwise may be too computationally intensive to perform using a general-purpose processor. In some embodiments, the motion estimation engine 1934 may be generally available to the graphics processor component to assist in video decoding and processing functions that are sensitive or adaptive to the direction or magnitude of motion within the video data.

[0220] In some embodiments, the image scaling and filtering module 1936 performs image processing operations to enhance the visual quality of the generated images and videos. In some embodiments, the scaling and filtering module 1936 processes the image and video data during a sampling operation before providing the data to the execution unit array 1914.

[0221] In some embodiments, GPE 1910 includes a data port 1944 that provides an additional mechanism for enabling the graphics subsystem to access memory. In some embodiments, data port 1944 facilitates memory access for operations including render target writes, constant buffer reads, scratch memory space reads / writes, and media surface accesses. In some embodiments, data port 1944 includes a cache memory space for caching accesses to memory. The cache memory can be a single data cache, or separated into multiple caches (e.g., render buffer cache, constant buffer cache, etc.) for multiple subsystems that access memory via the data port. In some embodiments, threads executing on execution units in execution unit array 1914 communicate with the data port by exchanging messages via a data distribution interconnect that couples each subsystem of GPE 1910.

[0222] Execution Unit

[0223] Fig. 20 is a block diagram of another embodiment of a graphics processor 2000 . Fig. 20 Elements in FIG. 1 having the same reference number (or name) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto.

[0224] In some embodiments, graphics processor 2000 includes ring interconnect 2002, pipeline front end 2004, media engine 2037, and graphics cores 2080A-2080N. In some embodiments, ring interconnect 2002 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of many processors integrated into a multi-core processing system.

[0225] In some embodiments, the graphics processor 2000 receives batches of commands via the ring interconnect 2002. The incoming commands are interpreted by the command streamer 2003 in the pipeline front end 2004. In some embodiments, the graphics processor 2000 includes scalable execution logic for performing 3D geometry processing and media processing via the graphics cores 2080A-2080N. For 3D geometry processing commands, the command streamer 2003 supplies the commands to the geometry pipeline 2036. For at least some media processing commands, the command streamer 2003 supplies the commands to the video front end 2034, which is coupled to the media engine 2037. In some embodiments, the media engine 2037 includes a video quality engine (VQE) 2030 for video and image post-processing and a multi-format encoding / decoding (MFX) 2033 engine for providing hardware accelerated media data encoding and decoding. In some embodiments, the geometry pipeline 2036 and the media engine 2037 each generate an execution thread, which is used for thread execution resources provided by at least one graphics core 2080A.

[0226] In some embodiments, the graphics processor 2000 includes scalable thread execution resources featuring modular cores 2080A-2080N (sometimes referred to as core slices), each modular core having multiple sub-cores 2050A-2050N, 2060A-2060N (sometimes referred to as core sub-slices). In some embodiments, the graphics processor 2000 can have any number of graphics cores 2080A to 2080N. In some embodiments, the graphics processor 2000 includes a graphics core 2080A, which has at least a first sub-core 2050A and a second sub-core 2060A. In other embodiments, the graphics processor is a low-power processor with a single sub-core (e.g., 2050A). In some embodiments, the graphics processor 2000 includes multiple graphics cores 2080A-2080N, each graphics core including a group of first sub-cores 2050A-2050N and a group of second sub-cores 2060A-2060N. Each of the group of first sub-cores 2050A-2050N includes at least a first group of execution units 2052A-2052N and a media / texture sampler 2054A-2054N. Each of the group of second sub-cores 2060A-2060N includes at least a second group of execution units 2062A-2062N and a sampler 2064A-2064N. In some embodiments, each sub-core 2050A-2050N, 2060A-2060N shares a group of shared resources 2070A-2070N. In some embodiments, these shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0227] Fig.21 Thread execution logic 2100 is shown, including an array of processing elements employed in some embodiments of a GPE. Fig.21 Those elements in FIG. 1 having the same reference numbers (or names) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto.

[0228] In some embodiments, the thread execution logic 2100 includes a pixel shader 2102, a thread dispatcher 2104, an instruction cache 2106, a scalable execution unit array (including multiple execution units 2108A-2108N), a sampler 2110, a data cache 2112, and a data port 2114. In one embodiment, these included components are interconnected via an interconnect structure that links to each of these components. In some embodiments, the thread execution logic 2100 includes one or more connections to a memory (such as a system memory or a cache memory) through one or more of the instruction cache 2106, the data port 2114, the sampler 2110, and the execution unit array 2108A-2108N. In some embodiments, each execution unit (e.g., 2108A) is an individual vector processor that is capable of executing multiple simultaneous threads and processing multiple data elements in parallel for each thread. In some embodiments, the execution unit array 2108A-2108N includes any number of individual execution units.

[0229] In some embodiments, execution unit arrays 2108A-2108N are primarily used to execute "shader" programs. In some embodiments, the execution units in arrays 2108A-2108N execute an instruction set that includes native support for many standard 3D graphics shader instructions, so that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with minimal conversion. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., compute and media shaders).

[0230] Each execution unit in the execution unit array 2108A-2108N operates on an array of data elements. The number of data elements is the "execution size" or the number of lanes for the instruction. An execution lane is a logical unit used for execution of flow control, data element access, and masking within an instruction. The number of lanes may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) for a particular graphics processor. In some embodiments, the execution units 2108A-2108N support integer and floating point data types.

[0231] The execution unit instruction set includes single instruction multiple data (SIMD) instructions. Various data elements can be stored in registers as compact data types, and the execution unit will process various elements based on the data size of the element. For example, when operating on a 256-bit wide vector, the 256-bit vector is stored in a register, and the execution unit operates on the vector as four separate 64-bit compact data elements (data elements of quadruple word length (QW) size), eight separate 32-bit compact data elements (data elements of double word length (DW) size), sixteen separate 16-bit compact data elements (data elements of word length (W) size), or thirty-two separate 8-bit data elements (data elements of byte (B) size). However, different vector widths and register sizes are possible.

[0232] One or more internal instruction caches (e.g., 2106) are included in the thread execution logic 2100 to cache thread instructions for the execution unit. In some embodiments, one or more data caches (e.g., 2112) are included to cache thread data during thread execution. In some embodiments, a sampler 2110 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 2110 includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to the execution unit.

[0233] During execution, the graphics pipeline and the media pipeline send thread initiation requests to the thread execution logic 2100 via the thread generation and dispatch logic. In some embodiments, the thread execution logic 2100 includes a local thread dispatcher 2104 that arbitrates thread initiation requests from the graphics pipeline and the media pipeline and instantiates the requested threads on one or more execution units 2108A-2108N. For example, the geometry pipeline (e.g., Fig. 20 2036) dispatches vertex processing, tessellation or geometry processing threads to thread execution logic 2100 ( Fig.21 ). In some embodiments, thread dispatcher 2104 may also process runtime thread generation requests from executing shader programs.

[0234] Once the group of geometric objects has been processed and rasterized into pixel data, the pixel shader 2102 is called to further calculate output information and cause the results to be written to the output surface (e.g., color buffer, depth buffer, template buffer, etc.). In some embodiments, the pixel shader 2102 calculates the values ​​of various vertex attributes, which are interpolated across the rasterized objects. In some embodiments, the pixel shader 2102 then executes a pixel shader program supplied by an application programming interface (API). To execute the pixel shader program, the pixel shader 2102 dispatches threads to execution units (e.g., 2108A) via a thread dispatcher 2104. In some embodiments, the pixel shader 2102 uses texture sampling logic in a sampler 2110 to access texture data in a texture map stored in memory. Arithmetic operations performed on the texture data and the input geometric data calculate pixel color data for each geometric fragment, or discard one or more pixels for further processing.

[0235] In some embodiments, data port 2114 provides a memory access mechanism for thread execution logic 2100 to output processed data to memory for processing on the graphics processor output pipeline. In some embodiments, data port 2114 includes or is coupled to one or more cache memories (e.g., data cache 2112) to cache data for memory access via the data port.

[0236] Fig. 22 is a block diagram illustrating a graphics processor instruction format 2200 according to some embodiments. In one or more embodiments, a graphics processor execution unit supports an instruction set having instructions in multiple formats. Solid line boxes show components that are typically included in an execution unit instruction, while dashed lines include components that are optional or included only in a subset of instructions. In some embodiments, the instruction format 2200 described and illustrated are macroinstructions in that they are instructions supplied to the execution unit, as opposed to micro-operations derived from instruction decoding (once the instruction is processed).

[0237] In some embodiments, the graphics processor execution unit natively supports instructions in 128-bit format 2210. A 64-bit compact instruction format 2230 is available for some instructions based on the selected instruction, instruction options, and the number of operands. Native 128-bit format 2210 provides access to all instruction options, while some options and operations are restricted to 64-bit format 2230. The native instructions available in 64-bit format 2230 vary according to the embodiment. In some embodiments, instructions are partially compacted using a set of index values ​​in index field 2213. The execution unit hardware references a set of compact tables based on these index values, and uses the compact table output to reconstruct native instructions in 128-bit format 2210.

[0238] For each format, the instruction opcode 2212 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an addition instruction, the execution unit performs a simultaneous addition operation across each color channel representing a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, the instruction control field 2214 enables control of certain execution options such as channel selection (e.g., prediction) and data channel ordering (e.g., swizzling). For 128-bit instructions 2210, the execution size field 2216 limits the number of data channels that will be executed in parallel. In some embodiments, the execution size field 2216 is not available for use in the 64-bit compact instruction format 2230.

[0239] Some execution unit instructions have up to three operands, including two source operands src0 2220, src1 2222, and one destination 2218. In some embodiments, the execution unit supports dual destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 2224), where the instruction opcode 2212 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value passed by the instruction.

[0240] In some embodiments, the 128-bit instruction format 2210 includes access / addressing mode information 2226, which specifies, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is provided directly by bits in the instruction 2210.

[0241] In some embodiments, the 128-bit instruction format 2210 includes an access / addressing mode field 2226, which specifies an addressing mode and / or access mode for the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including 16-byte aligned access modes and 1-byte aligned access modes, wherein the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, the instruction 2210 may use byte-aligned addressing for source operands and destination operands, and when in a second mode, the instruction 2210 may use 16-byte aligned addressing for all source operands and destination operands.

[0242] In one embodiment, the addressing mode portion of the access / addressing mode field 2226 determines whether the instruction will use direct addressing or indirect addressing. When direct register addressing mode is used, the bits in the instruction 2210 directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands can be calculated based on the address immediate field and the address register value in the instruction.

[0243] In some embodiments, instructions are grouped based on the opcode 2212 bit field to simplify opcode decoding 2240. For 8-bit opcodes, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is only an example. In some embodiments, the move and logic opcode group 2242 includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 2242 shares five most significant bits (MSBs), wherein the move (mov) instruction adopts the form of 0000xxxxb, and the logic instruction adopts the form of 0001xxxxb. The flow control instruction group 2244 (e.g., call, jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 2246 includes a mixture of instructions, which includes synchronization instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). The parallel math instruction group 2248 includes component-wise arithmetic instructions (e.g., add, multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel math group 2248 performs arithmetic operations in parallel across data lanes. The vector math group 2250 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic such as dot production calculations on vector operands.

[0244] Graphics Pipeline

[0245] Fig.23 is a block diagram of another embodiment of a graphics processor 2300 . Fig.23 Elements in FIG. 1 having the same reference number (or name) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto.

[0246] In some embodiments, the graphics processor 2300 includes a graphics pipeline 2320, a media pipeline 2330, a display engine 2340, a thread execution logic 2350, and a rendering output pipeline 2370. In some embodiments, the graphics processor 2300 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or by commands issued to the graphics processor 2300 via the ring interconnect 2302. In some embodiments, the ring interconnect 2302 couples the graphics processor 2300 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 2302 are interpreted by a command stream transmitter 2303, which supplies instructions to individual components of the graphics pipeline 2320 or the media pipeline 2330.

[0247] In some embodiments, the command streamer 2303 directs the operation of the vertex extractor 2305, which reads vertex data from memory and executes vertex processing commands provided by the command streamer 2303. In some embodiments, the vertex extractor 2305 provides the vertex data to the vertex shader 2307, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, the vertex extractor 2305 and the vertex shader 2307 execute the vertex processing instructions by dispatching execution threads to the execution units 2352A, 2352B via the thread dispatcher 2331.

[0248] In some embodiments, execution units 2352A, 2352B are arrays of vector processors with instruction sets for performing graphics and media operations. In some embodiments, execution units 2352A, 2352B have an attached L1 cache 2351 specific for each array or shared between arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0249] In some embodiments, the graphics pipeline 2320 includes a tessellation component for performing hardware accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 2311 configures the tessellation operation. A programmable domain shader 2317 provides back-end evaluation of the tessellation output. The tessellation 2313 operates at the direction of the hull shader 2311 and contains dedicated logic for generating a set of detailed geometric objects based on a coarse geometric model that is provided as input to the graphics pipeline 2320. In some embodiments, if tessellation is not used, the tessellation components 2311, 2313, 2317 can be bypassed.

[0250] In some embodiments, the complete geometric object may be processed by the geometry shader 2319 via one or more threads dispatched to the execution units 2352A, 2352B, or may proceed directly to the clipper 2329. In some embodiments, the geometry shader operates on entire geometric objects (rather than patches or vertices of vertices as in previous stages of the graphics pipeline). If tessellation is disabled, the geometry shader 2319 receives input from the vertex shader 2307. In some embodiments, if the tessellation unit is disabled, the geometry shader 2319 may be programmed by a geometry shader program to perform geometry tessellation.

[0251] Prior to rasterization, the clipper 2329 processes the vertex data. The clipper 2329 can be a fixed function clipper or a programmable clipper with clipping and geometry shader functions. In some embodiments, a rasterizer 2373 (e.g., a depth test component) in the render output pipeline 2370 dispatches a pixel shader to convert geometric objects into their pixel-by-pixel representations. In some embodiments, the pixel shader logic is included in the thread execution logic 2350. In some embodiments, the application can bypass the rasterizer 2373 and access the unrasterized vertex data via the streaming out unit 2323.

[0252] The graphics processor 2300 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be passed among the major components of the processor. In some embodiments, the execution units 2352A, 2352B and associated cache(s) 2351, texture and media samplers 2354, and texture / sampler cache 2358 are interconnected via data ports 2356 to perform memory accesses and communicate with the processor's rendering output pipeline components. In some embodiments, the samplers 2354, caches 2351, 2358, and execution units 2352A, 2352B each have separate memory access paths.

[0253] In some embodiments, the render output pipeline 2370 includes a rasterizer 2373 that converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit for performing fixed-function triangle and line rasterization. An associated render cache 2378 and depth cache 2379 are also available in some embodiments. The pixel operation component 2377 performs pixel-based operations on data, although in some examples, pixel operations associated with 2D operations (e.g., bit block images are transmitted using blending) are performed by the 2D engine 2341, or replaced by a display controller 2343 using overlapping display planes at display time. In some embodiments, a shared L3 cache 2375 can be used for all graphics components, allowing data to be shared without using main system memory.

[0254] In some embodiments, the graphics processor media pipeline 2330 includes a media engine 2337 and a video front end 2334. In some embodiments, the video front end 2334 receives pipeline commands from the command streamer 2303. In some embodiments, the media pipeline 2330 includes a separate command streamer. In some embodiments, the video front end 2334 processes the media commands before sending them to the media engine 2337. In some embodiments, the media engine 2337 includes thread generation functionality for generating threads for dispatching to the thread execution logic 2350 via the thread dispatcher 2331.

[0255] In some embodiments, the graphics processor 2300 includes a display engine 2340. In some embodiments, the display engine 2340 is external to the processor 2300 and is coupled to the graphics processor via the ring interconnect 2302, or some other interconnect bus or structure. In some embodiments, the display engine 2340 includes a 2D engine 2341 and a display controller 2343. In some embodiments, the display engine 2340 includes dedicated logic that can operate independently of the 3D pipeline. In some embodiments, the display controller 2343 is coupled to a display device (not shown), which can be a system integrated display device (such as in a laptop computer), or can be an external display device attached via a display device connector.

[0256] In some embodiments, the graphics pipeline 2320 and the media pipeline 2330 can be configured to perform operations based on multiple graphics and media programming interfaces, and are not specific to any one application programming interface (API). In some embodiments, the driver software for the graphics processor converts API calls specific to a specific graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL) and Open Computing Language (OpenCL) from the Khronos Group, the Direct 3D library from Microsoft, or support can be provided for both OpenGL and D3D. Support can also be provided for the open source computer vision library (OpenCV). If a mapping from the pipeline of a future API to the pipeline of a graphics processor can be performed, future APIs with compatible 3D pipelines will also be supported.

[0257] Graphics Pipeline Programming

[0258] Fig.24A is a block diagram of a graphics processor command format 2400 according to some embodiments. Fig. 24B is a block diagram of a graphics processor command sequence 2410 according to an embodiment. Fig.24A The solid-line boxes in show components that are generally included in a graphics command, while the dashed lines include components that are optional or included only in a subset of the graphics commands. Fig.24A The exemplary graphics processor command format 2400 includes a data field for identifying the target client 2402 of the command, a command operation code (opcode) 2404, and associated data for the command 2406. In some commands, a sub-opcode 2405 and a command size 2408 are also included.

[0259] In some embodiments, client 2402 specifies a client unit of a graphics device that processes command data. In some embodiments, a graphics processor command parser checks the client field of each command to adjust further processing of the command and routes the command data to an appropriate client unit. In some embodiments, a graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once a command is received by a client unit, the client unit reads an opcode 2404 and (if present) a sub-opcode 2405 to determine the operation to be performed. The client unit uses the information in data field 2406 to execute the command. For some commands, an explicit command size 2408 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands in the command based on the command opcode. In some embodiments, the commands are aligned via multiples of a double word length.

[0260] Fig. 24B An exemplary graphics processor command sequence 2410 is shown in the flowchart of FIG. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses a version of the command sequence shown to set up, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for exemplary purposes only, as embodiments are not limited to these particular commands or this command sequence. In addition, the commands may be issued as a batch of commands in a command sequence so that the graphics processor will process the command sequence in an at least partially simultaneous manner.

[0261] In some embodiments, the graphics processor command sequence 2410 may begin with a pipeline dump clear command 2412 to cause any active graphics pipeline to complete currently pending commands for the pipeline. In some embodiments, the 3D pipeline 2422 and the media pipeline 2424 do not operate simultaneously. The pipeline dump clear is performed to cause the active graphics pipeline to complete any pending commands. In response to the pipeline dump clear, the command parser for the graphics processor will suspend command processing until the active drawing engine completes pending operations and the associated read cache is invalidated. Optionally, any data marked as 'dirty' in the rendering cache can be dumped to memory. In some embodiments, the pipeline dump clear command 2412 can be used for pipeline synchronization or before placing the graphics processor in a low power state.

[0262] In some embodiments, when a command sequence requires the graphics processor to explicitly switch between pipelines, a pipeline select command 2413 is used. In some embodiments, a pipeline select command 2413 is only required once within an execution context before issuing pipeline commands unless the context is to issue commands for both pipelines. In some embodiments, a pipeline flush command 2412 is required immediately prior to a pipeline switch via a pipeline select command 2413.

[0263] In some embodiments, pipeline control commands 2414 configure the graphics pipeline for operation and are used to program 3D pipeline 2422 and media pipeline 2424. In some embodiments, pipeline control commands 2414 configure the pipeline state for the active pipeline. In one embodiment, pipeline control commands 2414 are used for pipeline synchronization and for clearing data from one or more cache memories within the active pipeline before processing a batch of commands.

[0264] In some embodiments, a set of return buffers for the corresponding pipeline to write data is configured using return buffer state commands 2416. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers into which these operations write intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, return buffer state 2416 includes selecting the size and number of return buffers to use for a set of pipeline operations.

[0265] The remaining commands in the command sequence differ based on the active pipeline for operation. Based on pipeline determination 2420 , the command sequence is tailored for either a 3D pipeline 2422 , which starts at 3D pipeline state 2430 , or a media pipeline 2424 , which starts at media pipeline state 2440 .

[0266] The commands for 3D pipeline state 2430 include 3D state setting commands for the following: vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that will be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API in use. In some embodiments, the 3D pipeline state 2430 commands can also selectively disable or bypass certain pipeline elements (if those elements will not be used).

[0267] In some embodiments, 3D primitive 2432 commands are used to submit 3D primitives processed by 3D pipeline. Commands and associated parameters passed to the graphics processor via 3D primitive 2432 are forwarded to the vertex extraction function in the graphics pipeline. The vertex extraction function uses 3D primitive 2432 command data to generate vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, 3D primitive 2432 commands are used to perform vertex operations on 3D primitives via vertex shaders. In order to process vertex shaders, 3D pipeline 2422 dispatches shader execution threads to graphics processor execution units.

[0268] In some embodiments, the 3D pipeline 2422 is triggered via an execution 2434 command or event. In some embodiments, a register write triggers the command execution. In some embodiments, the execution is triggered via a 'go' or 'kick' command in a command sequence. In one embodiment, the command execution is triggered using a pipeline synchronization command to dump and clear the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for 3D primitives. Once the operation is completed, the resulting geometric object is rasterized, and the pixel engine colors the resulting pixels. Additional commands for controlling pixel shading and pixel backend operations may also be included for those operations.

[0269] In some embodiments, when performing media operations, the graphics processor command sequence 2410 follows the media pipeline 2424 path. Generally, the manner and specific use of programming for the media pipeline 2424 depends on the media or computing operation to be performed. During media decoding, specific media decoding operations can be offloaded to the media pipeline. In some embodiments, the media pipeline can also be bypassed and media decoding can be performed in whole or in part (using resources provided by one or more general processing cores). In one embodiment, the media pipeline also includes elements for general purpose graphics processor unit (GPGPU) operations, wherein the graphics processor is used to perform SIMD vector operations using compute shader programs that are not explicitly related to the rendering of graphics primitives.

[0270] In some embodiments, the media pipeline 2424 is configured in a similar manner to the 3D pipeline 2422. A set of media pipeline state commands 2440 are dispatched or placed into a command queue before the media object commands 2442. In some embodiments, the media pipeline state commands 2440 include data for configuring the media pipeline elements that will be used to process the media objects. This includes data (such as encoding or decoding formats) for configuring the video decoding and video encoding logic within the media pipeline. In some embodiments, the media pipeline state commands 2440 also support the use of one or more pointers to an "indirect" state element that contains a batch of state settings.

[0271] In some embodiments, media object commands 2442 supply pointers to media objects for processing by the media pipeline. The media object includes a memory buffer containing video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object commands 2442. Once the pipeline states are configured and media object commands 2442 are queued, the media pipeline 2424 is triggered via an execute command 2444 or an equivalent execution event (e.g., a register write). The output from the media pipeline 2424 can then be post-processed by operations provided by the 3D pipeline 2422 or the media pipeline 2424. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0272] Graphics software architecture

[0273] Fig.25 An exemplary graphics software architecture for data processing system 2500 is shown in accordance with some embodiments. In some embodiments, the software architecture includes 3D graphics application 2510, operating system 2520, and at least one processor 2530. In some embodiments, processor 2530 includes graphics processor 2532 and one or more general purpose processor cores 2534. Graphics application 2510 and operating system 2520 are each executed in system memory 2550 of the data processing system.

[0274] In some embodiments, the 3D graphics application 2510 includes one or more shader programs, which include shader instructions 2512. The shader language instructions can be in a high-level shader language, such as a high-level shader language (HLSL) or an OpenGL shader language (GLSL). The application also includes executable instructions 2514 in a machine language suitable for execution by a general-purpose processor core 2534. The application also includes graphics objects 2516 defined by vertex data.

[0275] In some embodiments, the operating system 2520 is a Microsoft® Windows® operating system from Microsoft Corporation, a proprietary UNIX-like operating system, or an open source UNIX-like operating system (using a variation of the Linux kernel). When the Direct3D API is in use, the operating system 2520 uses a front-end shader compiler 2524 to compile any shader instructions 2512 using HLSL into a lower-order shader language. The compilation can be a just-in-time (JIT) compilation, or the application can execute shader precompilation. In some embodiments, during the compilation of the 3D graphics application 2510, high-order shaders are compiled into low-order shaders.

[0276] In some embodiments, the user mode graphics driver 2526 includes a backend shader compiler 2527 that converts shader instructions 2512 into hardware specific representations. When the OpenGL API is in use, shader instructions 2512 in the GLSL high-level language are passed to the user mode graphics driver 2526 for compilation. In some embodiments, the user mode graphics driver 2526 uses the operating system kernel mode function 2528 to communicate with the kernel mode graphics driver 2529. In some embodiments, the kernel mode graphics driver 2529 communicates with the graphics processor 2532 to dispatch commands and instructions.

[0277] IP Core Implementation

[0278] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit such as a processor. For example, a machine-readable medium may include instructions representing various logic within a processor. When read by a machine, the instructions may cause the machine to manufacture logic for performing the techniques described herein. Such representations (referred to as "IP cores") are reusable units of logic for an integrated circuit that may be stored on a tangible, machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be supplied to various consumers or manufacturing facilities that load the hardware model on a manufacturing machine that manufactures the integrated circuit. The integrated circuit may be manufactured so that the circuit performs the operations described in association with any of the embodiments described herein.

[0279] Fig.26 26 is a block diagram showing an IP core development system 2600 according to an embodiment, which can be used to manufacture an integrated circuit to perform an operation. The IP core development system 2600 can be used to generate a modular, reusable design that can be incorporated into a larger design or used to build an entire integrated circuit (e.g., a SOC integrated circuit). The design facility 2630 can generate a software simulation 2610 for the IP core design using a high-level programming language (e.g., C / C++). The software simulation 2610 can be used to design, test, and verify the behavior of the IP core. A register transfer level (RTL) design can then be created or synthesized according to the simulation model 2600. The RTL design 2615 is an abstraction of the behavior of an integrated circuit (including associated logic executed using the modeled digital signals) that models the flow of digital signals between hardware registers. In addition to the RTL design 2615, a lower level design at the logic level or transistor level can also be created, designed, or synthesized. Therefore, the specific details of the initial design and simulation can vary.

[0280] The RTL design 2615 or equivalent may be further synthesized by the design facility into a hardware model 2620, which may be in a hardware description language (HDL) or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design may be stored using a non-volatile memory 2640 (e.g., a hard disk, a flash memory, or any non-volatile storage medium) for delivery to a third-party manufacturing facility 2665. Alternatively, the IP core design may be transmitted (e.g., via the Internet) via a wired connection 2650 or a wireless connection 2660. The manufacturing facility 2665 may then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit may be configured to perform operations according to at least one embodiment described herein.

[0281] Fig. 27 2700, which can be manufactured using one or more IP cores. The exemplary integrated circuit includes one or more application processors 2705 (e.g., CPUs), at least one graphics processor 2710, and may additionally include an image processor 2715 and / or a video processor 2720, any of which may be modular IP cores from the same or multiple different design facilities. The integrated circuit includes peripherals or bus logic, including a USB controller 2725, a UART controller 2730, an SPI / SDIO controller 2735, an I 2 S / I 2 C controller 2740. In addition, the integrated circuit may include a display device 2745, which is coupled to one or more of a high-definition multimedia interface (HDMI) controller 2750 and a mobile industry processor interface (MIPI) display interface 2755. Storage may be provided by a flash memory subsystem 2760 (including flash memory and a flash memory controller). A memory interface may be provided via a memory controller 2765 for accessing SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 2770.

[0282] Additionally, other logic and circuitry may be included in the processor of integrated circuit 2700 , including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores.

[0283] The present invention provides a set of technical solutions, as follows:

[0284] 1. A device comprising:

[0285] A 3D engine, for generating a video stream and marking graphics elements in the video stream as static or moving;

[0286] A 3D pipeline, for processing the video stream;

[0287] a rasterizer associated with the 3D pipeline to mark individual pixels with attribute tags indicating static or moving;

[0288] a frame buffer memory for storing the pixels in a frame and a corresponding attribute memory for storing the attribute flags; and

[0289] An encoder configured to use the attribute flag to omit motion estimation.

[0290] 2. The device as described in technical solution 1 further comprises:

[0291] A pixel shader is used for outputting the pixel and attribute tags to a memory.

[0292] 3. A method comprising:

[0293] Generate video stream;

[0294] Marking graphics elements in the video stream as static or moving;

[0295] Processing the video stream through a 3D pipeline;

[0296] labeling individual pixels with attribute tags indicating static or moving;

[0297] storing the pixel in a frame memory and storing the corresponding attribute tag in a corresponding tag memory; and

[0298] The pixels in the frame memory are encoded using the attribute flag to omit motion estimation.

[0299] 4. As described in Technical Solution 3, the video stream is generated using a 3D engine.

[0300] 5. A method as described in technical solution 3, wherein the rasterizer in the 3D pipeline marks individual pixels with attribute tags indicating static or moving.

[0301] 6. A method comprising:

[0302] Generate video stream;

[0303] Marking a picture element in the video stream as background or foreground;

[0304] Processing the video stream through a 3D pipeline;

[0305] Labeling individual pixels with attribute tags indicating background or foreground;

[0306] storing the pixel in a frame memory and storing the corresponding attribute tag in a corresponding tag memory; and

[0307] The pixels in the frame memory are encoded using the attribute flag to select a type of encoding.

[0308] 7. As described in Technical Solution 6, the video stream is generated using a 3D engine.

[0309] 8. A method as described in technical solution 6, wherein the rasterizer in the 3D pipeline marks individual pixels with an attribute tag indicating background or foreground.

[0310] 9. A method as described in Technical Solution 6, wherein foreground pixels are encoded with higher quality.

[0311] 10. A device comprising:

[0312] A 3D engine, used for generating a video stream and marking graphics elements in the video stream as background or foreground;

[0313] A 3D pipeline, for processing the video stream;

[0314] a rasterizer associated with the 3D pipeline for marking individual pixels with an attribute tag indicating background or foreground;

[0315] a frame buffer memory and a corresponding attribute memory, the frame buffer memory being used to store the pixels in a frame, and the corresponding attribute memory being used to store the attribute flags; and

[0316] The encoder is used to select the type of encoding using the attribute tag.

[0317] 11. The device as described in technical solution 10 further comprises:

[0318] A pixel shader is used for outputting the pixel and attribute tags to a memory.

[0319] 12. A device as described in technical solution 10, wherein foreground pixels are encoded with higher quality.

[0320] 13. A method comprising:

[0321] Generate video stream;

[0322] Correlating motion and depth data for individual pixels;

[0323] Processing the video stream through a 3D pipeline;

[0324] A Joint Photographic Experts Group - Discrete Cosine Transform (JPEG-DCT) is performed within the 3D pipeline.

[0325] 14. The method as described in Technical Solution 13 further includes storing the pixels to be sent via the network in a frame memory.

[0326] 15. As described in technical solution 13, the video stream is generated using a 3D engine.

[0327] 16. A method as described in technical solution 13, wherein the network is the Internet.

[0328] 17. A device comprising:

[0329] 3D engine, used to generate video stream;

[0330] a 3D pipeline for processing the video stream and associating motion data and depth data for individual pixels;

[0331] The 3D pipeline is configured to perform a Joint Photographic Experts Group-Discrete Cosine Transform (JPEG-DCT) on the stream.

[0332] 18. The device as described in technical solution 17 further includes a frame buffer, which stores the pixels before transmitting them through the network.

[0333] 19. A system comprising:

[0334] computer;

[0335] at least one application specific integrated circuit (ASIC) communicatively coupled to the computer to execute a first codec;

[0336] at least one field programmable gate array (FPGA) communicatively coupled to the computer to execute a second codec;

[0337] at least one software program for running on said computer to execute a third codec;

[0338] a scheduler for scheduling a plurality of video streams to be processed by the ASIC, the FPGA, or the software program; and

[0339] A tracker is used to track the number of times the software program is scheduled to execute the third codec and, when a threshold is reached, to indicate that the at least one FPGA and another FPGA should be programmed with the third codec.

[0340] 20. The system as described in technical solution 19 further includes multiple ASICs and multiple FPGAs, each for executing multiple encoders and decoders.

[0341] 21. At least one computer readable medium having stored thereon instructions which, when executed by a processor, cause the processor to:

[0342] Generate video stream;

[0343] Marking a picture element in the video stream as background or foreground;

[0344] Processing the video stream through a 3D pipeline;

[0345] Labeling individual pixels with attribute tags indicating background or foreground;

[0346] storing the pixel in a frame memory and storing the corresponding attribute tag in a corresponding tag memory; and

[0347] The pixels in the frame memory are encoded using the attribute flag to select a type of encoding.

[0348] 22. In the computer-readable medium as described in technical solution 21, a 3D engine is used to generate the video stream.

[0349] 23. A computer-readable medium as described in technical solution 21, wherein the rasterizer in the 3D pipeline marks individual pixels with an attribute tag indicating background or foreground.

[0350] 24. A computer-readable medium as described in technical solution 21, wherein foreground pixels are encoded with higher quality.

[0351] 25. A computer-readable medium as described in technical solution 21, wherein background pixels are encoded with lower quality.

[0352] Additional notes and examples:

[0353] Example 1 may include a device for encoding video to omit motion estimation, comprising: a 3D engine for generating a video stream and marking primitives in the video stream as static or moving; a 3D pipeline for processing the video stream; a rasterizer associated with the 3D pipeline to mark individual pixels with attribute tags indicating static or moving; a frame buffer memory and a corresponding attribute memory, wherein the frame buffer memory is used to store pixels in a frame, and the corresponding attribute memory is used to store the attribute tags; and an encoder for using the attribute tags to omit motion estimation.

[0354] Example 2 may include an apparatus as described in Example 1, further comprising a pixel shader for outputting the pixel and the attribute tag to a memory.

[0355] Example 3 may include a method for encoding video to omit motion estimation, comprising: generating a video stream; marking primitives in the video stream as static or moving; processing the video stream through a 3D pipeline; marking individual pixels with attribute tags indicating static or moving; storing the pixels in a frame memory and storing corresponding attribute tags in a corresponding tag memory; and encoding the pixels in the frame memory using the attribute tags to omit motion estimation.

[0356] Example 4 may include the method as described in Example 3, wherein generating the video stream is performed using a 3D engine.

[0357] Example 5 may include the method as described in Example 3, wherein a rasterizer in the 3D pipeline tags individual pixels with an attribute tag indicating static or moving.

[0358] Example 6 may include at least one computer-readable medium having instructions stored thereon that, when executed by a processor, cause the processor to perform Examples 3-5.

[0359] Example 7 may include a system for encoding video to omit motion estimation, comprising: a component for generating a video stream; a component for marking primitives in the video stream as static or moving; a component for processing the video stream through a 3D pipeline; a component for marking individual pixels with an attribute tag indicating static or moving; a component for storing pixels in a frame memory and storing corresponding attribute tags in a corresponding tag memory; and a component for encoding pixels in the frame memory using the attribute tags to omit motion estimation.

[0360] Example 8 may include the system as described in Example 7, wherein the component for generating the video stream is implemented using a 3D engine.

[0361] Example 9 may include a method for encoding a foreground with a higher quality than a background, comprising: generating a video stream; marking graphics elements in the video stream as background or foreground; processing the video stream through a 3D pipeline; marking individual pixels with attribute tags indicating background or foreground; storing the pixels in a frame memory and storing corresponding attribute tags in a corresponding tag memory; and encoding the pixels in the frame memory using the attribute tags to select a type of encoding.

[0362] Example 10 may include the method as described in Example 9, further comprising generating the video stream using a 3D engine.

[0363] Example 11 may include the method as described in Example 9, wherein a rasterizer in the 3D pipeline tags individual pixels with an attribute tag indicating background or foreground.

[0364] Example 12 may include a method as described in Example 9, wherein foreground pixels are encoded with a higher quality.

[0365] Example 13 may include at least one computer-readable medium having instructions stored thereon that, when executed by a processor, cause the processor to perform Examples 9-12.

[0366] Example 14 may include a system for encoding a foreground with a higher quality than a background, comprising: a component for generating a video stream; a component for marking graphics elements in the video stream as background or foreground; a component for processing the video stream through a 3D pipeline; a component for marking individual pixels with attribute tags indicating background or foreground; a component for storing pixels in a frame memory and storing corresponding attribute tags in a corresponding tag memory; and a component for encoding pixels in the frame memory using the attribute tags to select a type of encoding.

[0367] Example 15 may include the system as described in Example 14, wherein the component for generating the video stream is implemented using a 3D engine.

[0368] Example 16 may include the system as described in Example 14, wherein a rasterizer in the 3D pipeline tags individual pixels with an attribute tag indicating background or foreground.

[0369] Example 17 may include a system as described in Example 14, further comprising a component for encoding foreground pixels with higher quality.

[0370] Example 18 may include a device for encoding a foreground with a higher quality than a background, comprising: a 3D engine for generating a video stream and marking graphics elements in the video stream as background or foreground; a 3D pipeline for processing the video stream; a rasterizer associated with the 3D pipeline for marking individual pixels with attribute tags indicating background or foreground; a frame buffer memory and a corresponding attribute memory, wherein the frame buffer memory is used to store pixels in a frame, and the corresponding attribute memory is used to store the attribute tags; and an encoder for using the attribute tags to select a type of encoding.

[0371] Example 19 may include the apparatus as described in Example 18, further comprising a pixel shader for outputting the pixel and the attribute tag to a memory.

[0372] Example 20 may include an apparatus as described in Example 18, wherein the foreground pixels are encoded with a higher quality.

[0373] Example 21 may include a method for eliminating a media pipeline, comprising: generating a video stream; associating motion data and depth data for individual pixels; processing the video stream through a 3D pipeline; performing a Joint Photographic Experts Group-Discrete Cosine Transform (JPEG-DCT) within the 3D pipeline, the JPEG-DCT being typically performed in the media pipeline.

[0374] Example 22 may include the method as described in Example 21, further comprising storing pixels to be sent over the network in a frame memory.

[0375] Example 23 may include the method as described in Example 21, wherein generating the video stream is performed using a 3D engine.

[0376] Example 24 may include the method as described in Example 21, wherein the network is the Internet.

[0377] Example 25 may include at least one computer-readable medium having instructions stored thereon that, when executed by a processor, cause the processor to perform Examples 21-24.

[0378] Example 26 may include a system for eliminating a media pipeline, comprising: a component for generating a video stream; a component for associating motion data and depth data for individual pixels; a component for processing the video stream through a 3D pipeline; and a component for performing a Joint Photographic Experts Group-Discrete Cosine Transform (JPEG-DCT) within the 3D pipeline, the JPEG-DCT being typically performed in the media pipeline.

[0379] Example 27 may include the system as described in Example 26, further comprising a component for storing pixels to be sent over the network in a frame memory.

[0380] Example 28 may include the system as described in Example 26, wherein the component for generating the video stream is implemented using a 3D engine.

[0381] Example 29 may include the system as described in Example 26, wherein the network is the Internet.

[0382] Example 30 may include an apparatus for eliminating a media pipeline, comprising: a 3D engine for generating a video stream; a 3D pipeline for processing the video stream and associating motion data and depth data for individual pixels, wherein the 3D pipeline is used to perform a Joint Photographic Experts Group-Discrete Cosine Transform (JPEG-DCT) on the stream.

[0383] Example 31 may include an apparatus as described in Example 30, further comprising a frame buffer that stores the pixels before transmitting over the network.

[0384] Example 32 may include a system for scheduling video streams for codec processing, comprising: a computer; at least one application specific integrated circuit (ASIC) communicatively coupled to the computer to execute a first codec; at least one field programmable gate array (FPGA) communicatively coupled to the computer to execute a second codec; at least one software program for running on the computer to execute a third codec; a scheduler for scheduling multiple video streams to be processed by the ASIC, the FPGA, or the software program; and a tracker for tracking the number of times the software program is scheduled to execute the third codec, and when a threshold is reached, the tracker is used to indicate that the at least one FPGA and another FPGA should be programmed with the third codec.

[0385] Example 33 may include the system as described in Example 32, further comprising a plurality of ASICs and a plurality of FPGAs each for executing a plurality of codecs.

[0386] Example 34 may include a method for scheduling video streams for codec processing, comprising: providing a computer; providing at least one application specific integrated circuit (ASIC) communicatively coupled to the computer to execute a first codec; providing at least one field programmable gate array (FPGA) communicatively coupled to the computer to execute a second codec; providing at least one software program for running on the computer to execute a third codec; providing a scheduler for scheduling multiple video streams to be processed by the ASIC, the FPGA, or the software program; and providing a tracker for tracking the number of times the software program is scheduled to execute the third codec, and when a threshold is reached, the tracker is used to indicate that the at least one FPGA and another FPGA should be programmed with the third codec.

[0387] Example 35 may include the method system as described in Example 34, further comprising providing a plurality of ASICs and a plurality of FPGAs each for executing a plurality of codecs.

[0388] Example 36 may include at least one computer-readable medium having instructions stored thereon that, when executed by a processor, cause the processor to perform Examples 34-35.

[0389] The term "coupled" may be used herein to refer to any type of relationship (direct or indirect) between the components in question, and may apply to electrical, mechanical, fluid, optical, electromagnetic, electromechanical or other connections. Furthermore, the terms "first," "second," etc. may be used herein merely to facilitate discussion, and do not convey a particular temporal or chronological importance unless otherwise indicated. Additionally, it is understood that the indefinite article "a" or "an" conveys the meaning of "one or more" or "at least one."

[0390] As used in this application and in the claims, a list of items linked by the term "one or more of" may mean any combination of the listed items. For example, the phrase "one or more of A, B, or C" may mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0391] The embodiments have been described above with reference to specific embodiments. However, it will be appreciated by those skilled in the art that various modifications and changes may be made thereto without departing from the broader spirit and scope of the embodiments as set forth in the appended claims. The foregoing description and drawings are therefore to be considered in an illustrative rather than a restrictive sense.

Claims

1. An apparatus for encoding a video so as to omit motion estimation, comprising: A 3D engine, for generating a video stream and marking graphics elements in the video stream as static or moving; A 3D pipeline, for processing the video stream; a rasterizer associated with the 3D pipeline to mark individual pixels with attribute tags indicating static or moving; a frame buffer memory and a corresponding attribute memory, the frame buffer memory being used to store the pixels in a frame, the corresponding attribute memory being used to store the attribute flags; as well as An encoder configured to use the attribute flag to omit motion estimation.

2. The apparatus as claimed in claim 1, further comprising: A pixel shader is used for outputting the pixel and attribute tags to a memory.

3. A method for encoding a video so as to omit motion estimation, comprising: Generate video stream; Marking graphics elements in the video stream as static or moving; Processing the video stream through a 3D pipeline; labeling individual pixels with attribute tags indicating static or moving; storing the pixel in a frame memory and storing the corresponding attribute tag in a corresponding tag memory; as well as The pixels in the frame memory are encoded using the attribute flag to omit motion estimation.

4. The method as claimed in claim 3, wherein the generation of the video stream is accomplished by using a 3D engine.

5. The method of claim 3, wherein a rasterizer in the 3D pipeline tags individual pixels with an attribute tag indicating static or moving.

6. A computer-readable medium having instructions stored thereon, which, when executed by a computing device, cause the computing device to perform the method according to any one of claims 3 to 5.

7. A system for encoding video so as to omit motion estimation, comprising: Components for generating video streams; A component for marking a picture element in the video stream as static or moving; A component for processing the video stream through a 3D pipeline; A component for marking individual pixels with an attribute tag indicating static or moving; A component for storing the pixels in a frame memory and storing corresponding attribute tags in a corresponding tag memory; as well as Components for encoding the pixels in the frame memory using the attribute flag to omit motion estimation.

8. The system as claimed in claim 7, wherein the component for generating the video stream is implemented using a 3D engine.

9. A method for encoding a foreground with a higher quality than a background, comprising: Generate video stream; Marking a picture element in the video stream as background or foreground; Processing the video stream through a 3D pipeline; Labeling individual pixels with attribute tags indicating background or foreground; storing the pixel in a frame memory and storing a corresponding attribute tag indicating background or foreground in a corresponding tag memory; as well as The pixels in the frame memory are encoded using the attribute tag indicating background or foreground to select the type of encoding, wherein the picture elements in the video stream are marked as static or moving and individual pixels are marked with the attribute tag indicating static or moving and the attribute tag indicating static or moving is stored in a corresponding tag memory.

10. The method of claim 9, further comprising generating the video stream using a 3D engine.

11. The method of claim 9, wherein a rasterizer in the 3D pipeline tags individual pixels with an attribute tag indicating background or foreground.

12. A method as claimed in claim 9, wherein foreground pixels are encoded with higher quality.

13. A computer-readable medium having instructions stored thereon, which, when executed by a computing device, cause the computing device to perform the method according to any one of claims 9 to 12.

14. A system for encoding a foreground with a higher quality than a background, comprising: Components for generating video streams; A component for marking a picture element in the video stream as background or foreground; A component for processing the video stream through a 3D pipeline; A component for labeling individual pixels with an attribute tag indicating background or foreground; A component for storing the pixel in a frame memory and storing a corresponding attribute tag indicating background or foreground in a corresponding tag memory; as well as means for encoding said pixels in said frame memory using said attribute flag indicating background or foreground to select a type of encoding, The picture elements in the video stream are marked as static or moving, and individual pixels are marked with attribute tags indicating static or moving, and the attribute tags indicating static or moving are stored in a corresponding tag memory.

15. The system as claimed in claim 14, wherein the component for generating the video stream is implemented using a 3D engine.

16. The system of claim 14, wherein a rasterizer in the 3D pipeline tags individual pixels with an attribute tag indicating background or foreground.

17. The system of claim 16, further comprising a component for encoding foreground pixels at a higher quality.

18. An apparatus for encoding a foreground with a higher quality than a background, comprising: A 3D engine, used for generating a video stream and marking graphics elements in the video stream as background or foreground; A 3D pipeline, for processing the video stream; a rasterizer associated with the 3D pipeline for marking individual pixels with an attribute tag indicating background or foreground; a frame buffer memory and a corresponding attribute memory, the frame buffer memory being used to store the pixels in a frame, and the corresponding attribute memory being used to store the attribute flag indicating background or foreground; as well as an encoder for selecting a type of encoding using the attribute tag indicating background or foreground, The picture elements in the video stream are marked as static or moving and individual pixels are marked with attribute tags indicating static or moving and the attribute tags indicating static or moving are stored in a corresponding tag memory.

19. The apparatus of claim 18, further comprising: A pixel shader is used for outputting the pixel and attribute tags to a memory.

20. The apparatus of claim 18, wherein foreground pixels are encoded with a higher quality.

21. A method for eliminating a media pipeline, comprising: Generate video stream; associating motion data and depth data for individual pixels, wherein the motion data is obtained by marking primitives in the video stream as static or moving and marking individual pixels with an attribute tag indicating static or moving, and wherein the depth data is obtained by marking primitives in the video stream as background or foreground and marking individual pixels with an attribute tag indicating background or foreground; Processing the video stream through a 3D pipeline; A Joint Photographic Experts Group-Discrete Cosine Transform JPEG-DCT is performed within the 3D pipeline, which is usually performed in a media pipeline.

22. The method as claimed in claim 21, wherein generating the video stream is performed using a 3D engine.

23. A computer-readable medium having instructions stored thereon, which, when executed by a computing device, cause the computing device to perform the method according to any one of claims 21-22.

24. A system for eliminating media pipelines, comprising: Components for generating video streams; Components for associating motion data and depth data for individual pixels, wherein the motion data is obtained by marking primitives in the video stream as static or moving and marking individual pixels with attribute tags indicating static or moving, and wherein the depth data is obtained by marking primitives in the video stream as background or foreground and marking individual pixels with attribute tags indicating background or foreground; A component for processing the video stream through a 3D pipeline; Components for performing a Joint Photographic Experts Group - Discrete Cosine Transform JPEG-DCT within the 3D pipeline, the JPEG-DCT being typically performed in a media pipeline.

25. The system as claimed in claim 24, wherein the component for generating the video stream is implemented using a 3D engine.

26. An apparatus for eliminating a media pipeline, comprising: 3D engine, used to generate video stream; a 3D pipeline for processing the video stream and associating motion data and depth data for each pixel, wherein the motion data is obtained by marking primitives in the video stream as static or moving and marking individual pixels with an attribute tag indicating static or moving, and wherein the depth data is obtained by marking primitives in the video stream as background or foreground and marking individual pixels with an attribute tag indicating background or foreground; The 3D pipeline is used to perform Joint Photographic Experts Group-Discrete Cosine Transform JPEG-DCT on the video stream.

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