Programmable coarse-grained and sparse matrix computation hardware with advanced scheduling

Abstract

Programmable coarse-grained and sparse matrix computing hardware with advanced scheduling is provided. One embodiment provides a computing device that performs machine learning operations, the computing device including a decoding unit to decode a single instruction into decoded instructions that cause the computing device to perform complex machine learning computing operations.

Description

Technical Field

[0001] Embodiments relate generally to data processing and more particularly to data processing via a general purpose graphics processing unit. Background Art

[0002] Current parallel graphics data processing includes systems and methods developed to perform specific operations on graphics data, such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors have used fixed-function compute units to process graphics data; however, recently, portions of graphics processors have become programmable, enabling such processors to support a wider variety of operations for processing vertex and fragment data.

[0003] To further improve performance, graphics processors typically implement processing techniques (such as pipelining) that attempt to process as much graphics data in parallel as possible throughout different parts of the graphics pipeline. Parallel graphics processors with a single instruction multiple thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In a SIMT architecture, multiple groups of parallel threads attempt to execute program instructions together synchronously as often as possible to improve processing efficiency. A general overview of software and hardware for a SIMT architecture can be found in Shane Cook's CUDA Programming, Chapter 3, pages 37-51 (2013) and / or Nicholas Wilt's CUDA Handbook, A Comprehensive Guide to GPU Programming, Sections 2.6.2 to 3.1.2 (June 2013). BRIEF DESCRIPTION OF THE DRAWINGS

[0004] In order to be able to understand the features of the present invention in detail, a more particular description of the present invention may be had by reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments and are therefore not to be considered as limiting the scope of all embodiments.

[0005] Figure 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein;

[0006] Figures 2A-2D illustrates a parallel processor component according to an embodiment;

[0007] Figure 3A-3B is a block diagram of a graphics multiprocessor according to an embodiment;

[0008] Figures 4A-4F illustrates an exemplary architecture in which multiple GPUs are communicatively coupled to multiple multi-core processors;

[0009] Figure 5 illustrates a graphics processing pipeline according to an embodiment;

[0010] Figure 6 illustrates a machine learning software stack according to an embodiment;

[0011] Figure 7 illustrates a highly parallel general purpose graphics processing unit according to an embodiment;

[0012] Figure 8 illustrates a multi-GPU computing system according to an embodiment;

[0013] Figures 9A-9B illustrates the layers of an exemplary deep neural network;

[0014] Fig.10 An exemplary recurrent neural network is illustrated;

[0015] Fig.11 Illustrate the training and deployment of deep neural networks;

[0016] Fig.12 is a block diagram illustrating distributed learning;

[0017] Fig.13 illustrates an exemplary system-on-chip (SOC) for performing inference suitable for performing inference using a trained model;

[0018] Fig.14 is a block diagram of a data processing system according to an embodiment;

[0019] Fig.15A illustrates details of machine learning instructions and acquisition units according to an embodiment;

[0020] Fig. 15B illustrates details of a machine learning scheduler controller according to an embodiment;

[0021] Fig.16 illustrates an exemplary convolution operation according to an embodiment;

[0022] Fig.17 is a flow chart of logic for performing coarse-grained scheduling of machine learning operations of a computational pipeline according to an embodiment;

[0023] Fig.18 is a block diagram illustrating a hybrid memory computing system according to an embodiment;

[0024] Figures 19A-19Bis a flow chart illustrating logic for performing near data computing operations via embodiments described herein;

[0025] Fig. 20 illustrates exemplary multiply-add logic within the embodiments described herein;

[0026] Fig.21 illustrates a sparse computing accelerator architecture according to one embodiment;

[0027] Fig. 22 illustrates an additional sparse computing architecture for sparse matrix operations according to an embodiment;

[0028] Figures 23A-23B is a flow chart illustrating logic 2300, 2310 for performing sparse computing operations within a GPGPU provided by embodiments described herein;

[0029] Fig.24 is a block diagram of a processing system according to an embodiment;

[0030] Fig.25 is a block diagram of a processor according to an embodiment;

[0031] Fig.26 is a block diagram of a graphics processor according to an embodiment;

[0032] Fig. 27 is a block diagram of a graphics processing engine of a graphics processor according to some embodiments;

[0033] Fig.28 is a block diagram of a graphics processor provided by an additional embodiment;

[0034] Fig.29 illustrates thread execution logic including an array of processing elements employed in some embodiments;

[0035] Fig.30 is a block diagram illustrating a graphics processor instruction format according to some embodiments;

[0036] Fig.31 is a block diagram of a graphics processor according to another embodiment;

[0037] Figures 32A-32B illustrates a graphics processor command format and command sequence according to some embodiments;

[0038] Fig.33 illustrates an exemplary graphics software architecture for a data processing system according to some embodiments;

[0039] Fig.34 is a block diagram illustrating an IP core development system according to an embodiment;

[0040] Fig.35 is a block diagram illustrating an exemplary system-on-chip integrated circuit according to an embodiment;

[0041] Fig.36 is a block diagram illustrating an additional graphics processor according to an embodiment; and

[0042] Fig.37 is a block diagram illustrating an additional exemplary graphics processor of a system-on-chip integrated circuit according to an embodiment. DETAILED DESCRIPTION

[0043] In some embodiments, a graphics processing unit (GPU) is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuits / logic to efficiently process these commands / instructions.

[0044] In the following description, many specific details are set forth to provide a more thorough understanding. However, it should be understood by those skilled in the art that the embodiments described herein may be practiced without one or more of these specific details. In other instances, well-known features are not described to avoid obscuring the details of the embodiments of the present invention.

[0045] System Overview

[0046] Figure 11 is a block diagram illustrating a computing system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 and a system memory 104, the one or more processors and the system memory communicating via an interconnect path, which may include a memory hub 105. The memory hub 105 may be a separate component within a chipset component, or may be integrated within the one or more processors 102. The memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107, which may enable the computing system 100 to receive input from one or more input devices 108. In addition, the I / O hub 107 may enable a display controller (which may be included in the one or more processors 102) to provide output to one or more display devices 110A. In one embodiment, the one or more display devices 110A coupled to the I / O hub 107 may include a local display device, an internal display device, or an embedded display device.

[0047] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112, which are coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standard-based communication link technologies or protocols (such as but not limited to PCI Express), or can be a vendor-specific communication interface or communication structure. In one embodiment, the one or more parallel processors 112 form a computing-centric parallel or vector processing system that includes a large number of processing cores and / or processing clusters, such as an integrated many-core (MIC) processor. In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one of one or more display devices 110A coupled via the I / O hub 107. The one or more parallel processors 112 may also include a display controller and display interface (not shown) to enable direct connection to one or more display devices 110B.

[0048] Within the I / O subsystem 111, a system storage unit 114 may be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. An I / O switch 116 may be used to provide an interface mechanism to enable connection between the I / O hub 107 and other components that may be integrated into the platform, such as a network adapter 118 and / or a wireless network adapter 119, as well as various other devices that may be added via one or more plug-in devices 120. The network adapter 118 may be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0049] Computing system 100 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 107. Figure 1 The communication paths interconnecting the various components may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express) or any other bus or point-to-point communication interface(s) and / or protocol (such as the NV-Link high-speed interconnect or an interconnect protocol known in the art).

[0050] In one embodiment, one or more parallel processors 112 incorporate circuits optimized for graphics and video processing, including, for example, video output circuits, and the circuits constitute a graphics processing unit (GPU). In another embodiment, one or more parallel processors 112 incorporate circuits optimized for general-purpose processing while retaining the basic computing architecture described in more detail herein. In yet another embodiment, the components of the computing system 100 may be integrated with one or more other system elements on a single integrated circuit. For example, one or more parallel processors 112, a memory hub 105, (multiple) processors 102, and an I / O hub 107 may be integrated into a system-on-chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 may be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computing system.

[0051] It should be understood that the computing system 100 shown herein is illustrative and variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of (multiple) processors 102, and the number of (multiple) parallel processors 112, can be modified as needed. For example, in some embodiments, the system memory 104 is directly connected to the (multiple) processors 102 rather than through a bridge, and other devices communicate with the system memory 104 via the memory hub 105 and the (multiple) processors 102. In other alternative topologies, the (multiple) parallel processors 112 are connected to the I / O hub 107 or directly to one of the one or more processors 102, rather than to the memory hub 105. In other embodiments, the I / O hub 107 and the memory hub 105 can be integrated into a single chip. Some embodiments may include two or more groups of (multiple) processors 102 attached via multiple sockets, which can be coupled to two or more instances of (multiple) parallel processors 112.

[0052] Some specific components shown herein are optional and may not be included in all implementations of computing system 100. For example, any number of plug-in cards or peripherals may be supported, or some components may be omitted. In addition, some architectures may use Figure 1 For example, memory hub 105 may be referred to as a north bridge in some architectures, while I / O hub 107 may be referred to as a south bridge.

[0053] Figure 2A The parallel processor 200 according to an embodiment is illustrated. The various components of the parallel processor 200 may be implemented using one or more integrated circuit devices such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). According to an embodiment, the illustrated parallel processor 200 is Figure 1 A variation of one or more parallel processors 112 is shown.

[0054] In one embodiment, parallel processor 200 includes parallel processing unit 202. The parallel processing unit includes an I / O unit 204 that enables communication with other devices including other instances of parallel processing unit 202. I / O unit 204 can be directly connected to other devices. In one embodiment, I / O unit 204 is connected to other devices via the use of a hub or switch interface such as memory hub 105. The connection between memory hub 105 and I / O unit 204 forms communication link 113. Within parallel processing unit 202, I / O unit 204 is connected to host interface 206 and memory cross switch 216, wherein host interface 206 receives commands related to performing processing operations and memory cross switch 216 receives commands related to performing memory operations.

[0055] When the host interface 206 receives the command buffer via the I / O unit 204, the host interface 206 may direct the work operations for executing those commands to the front end 208. In one embodiment, the front end 208 is coupled with a scheduler 210, which is configured to distribute commands or other work items to the processing cluster array 212. In one embodiment, the scheduler 210 ensures that the processing cluster array 212 is properly configured and is in a valid state before distributing tasks to the processing clusters of the processing cluster array 212. In one embodiment, the scheduler 210 is implemented via firmware logic executed on a microcontroller. The microcontroller-implemented scheduler 210 may be configured to perform complex scheduling and work distribution operations at coarse and fine granularity, thereby enabling rapid preemption and context switching of threads executing on the processing array 212. In one embodiment, the host software may prove the workload for scheduling on the processing array 212 via one of a plurality of graphics processing doorbells. The workload may then be automatically distributed across the processing array 212 by the scheduler 210 logic within the scheduler microcontroller.

[0056] Processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B, up to cluster 214N). Each cluster 214A to 214N of processing cluster array 212 may execute a large number of concurrent threads. Scheduler 210 may use various scheduling and / or work distribution algorithms to allocate work to clusters 214A to 214N of processing cluster array 212, which may vary depending on the workload caused by each type of program or calculation. Scheduling may be handled dynamically by scheduler 210, or may be partially assisted by compiler logic in the process of compiling program logic configured to be executed by processing cluster array 212. In one embodiment, different clusters 214A to 214N of processing cluster array 212 may be allocated to process different types of programs or to perform different types of calculations.

[0057] Processing cluster array 212 may be configured to perform various types of parallel processing operations. In one embodiment, processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, processing cluster array 212 may include logic for performing processing tasks including: filtering of video and / or audio data; performing modeling operations, including physics operations; and performing data transformations.

[0058] In one embodiment, processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where parallel processor 200 is configured to perform graphics processing operations, processing cluster array 212 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations and tessellation logic and other vertex processing logic. In addition, processing cluster array 212 may be configured to execute shader programs associated with graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. Parallel processing unit 202 may transfer data from system memory via I / O unit 204 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 222) during processing and then written back to system memory.

[0059] In one embodiment, when parallel processing unit 202 is used to perform graphics processing, scheduler 210 can be configured to divide the processing workload into tasks of approximately equal size to better enable the distribution of graphics processing operations to multiple clusters 214A to 214N of processing cluster array 212. In some embodiments, portions of processing cluster array 212 can be configured to perform different types of processing. For example, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations to produce a rendered image for display. Intermediate data generated by one or more of clusters 214A to 214N can be stored in a buffer to allow the intermediate data to be transferred between clusters 214A to 214N for further processing.

[0060] During operation, the processing cluster array 212 may receive processing tasks to be executed via the scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, a processing task may include an index of data to be processed (e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, and state parameters and commands (e.g., which program to execute) that define how the data is to be processed). The scheduler 210 may be configured to obtain an index corresponding to a task or may receive an index from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured to a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0061] Each of the one or more instances of the parallel processing unit 202 may be coupled to a parallel processor memory 222. The parallel processor memory 222 may be accessed via a memory crossbar 216, which may receive memory requests from the processing cluster array 212 and the I / O unit 204. The memory crossbar 216 may access the parallel processor memory 222 via a memory interface 218. The memory interface 218 may include a plurality of partition units (e.g., partition unit 220A, partition unit 220B, up to partition unit 220N), which may each be coupled to a portion (e.g., memory unit) of the parallel processor memory 222. In one implementation, the number of partition units 220A to 220N is configured to be equal to the number of memory units, such that the first partition unit 220A has a corresponding first memory unit 224A, the second partition unit 220B has a corresponding memory unit 224B, and the Nth partition unit 220N has a corresponding Nth memory unit 224N. In other embodiments, the number of partition units 220A to 220N may not be equal to the number of memory devices.

[0062] In various embodiments, the memory units 224A to 224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, the memory units 224A to 224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will appreciate that the specific implementation of the memory units 224A to 224N may vary and may be selected from one of a variety of conventional designs. Rendering targets such as frame buffers or texture maps may be stored on the memory units 224A to 224N, allowing the partition units 220A to 220N to write to portions of each rendering target in parallel to efficiently use the available bandwidth of the parallel processor memory 222. In some embodiments, in order to support a unified memory design that utilizes system memory together with local cache memory, the local instance of the parallel processor memory 222 may be excluded.

[0063] In one embodiment, any of the clusters 214A to 214N of the processing cluster array 212 can process data to be written to any of the memory units 224A to 224N within the parallel processor memory 222. The memory crossbar 216 can be configured to transmit the output of each cluster 214A to 214N to any partition unit 220A to 220N or another cluster 214A to 214N, which can perform additional processing operations on the output. Each cluster 214A to 214N can communicate with the memory interface 218 through the memory crossbar 216 to perform read or write operations on various external memory devices. In one embodiment, the memory crossbar 216 can be connected to the memory interface 218 to communicate with the I / O unit 204, and can be connected to the local instance of the parallel processor memory 222, so that the processing units within different processing clusters 214A to 214N can communicate with the system memory or other memory that is not local to the parallel processing unit 202. In one embodiment, the memory crossbar switch 216 may use virtual channels to separate traffic flows between the clusters 214A to 214N and the partition units 220A to 220N.

[0064] Although a single instance of parallel processing unit 202 is illustrated as being within parallel processor 200, any number of instances of parallel processing unit 202 may also be included. For example, multiple instances of parallel processing unit 202 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. Different instances of parallel processing unit 202 may also be configured to interoperate even if different instances have different numbers of processing cores, different local parallel processor storage amounts, and / or other configuration differences. For example, and in one embodiment, some instances of parallel processing unit 202 may include higher precision floating point units relative to other instances. Systems incorporating one or more instances of parallel processing unit 202 or parallel processor 200 may be implemented in various configurations and form factors, including but not limited to desktop computers, laptop computers or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0065] Figure 2B is a block diagram of a partition unit 220 according to an embodiment. In one embodiment, the partition unit 220 is Figure 2A 2 is an example of one of the partition units 220A to 220N. As shown, the partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and an ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache that is configured to perform load and store operations received from the memory crossbar switch 216 and the ROP 226. Read misses and urgent write-back requests are output by the L2 cache 221 to the frame buffer interface 225 for processing. Updates may also be sent to the frame buffer via the frame buffer interface 225 for processing. In one embodiment, the frame buffer interface 225 is connected to an interface with one of the memory units in the parallel processor memory, such as the memory units 224A to 224N of FIG. 2 (e.g., within the parallel processor memory 222).

[0066] In graphics applications, ROP 226 is a processing unit that performs raster operations such as stencil, z-test, blending, etc. ROP 226 then outputs processed graphics data, which is stored in graphics memory. In some embodiments, ROP 226 includes compression logic that compresses depth or color data written to memory and decompresses depth or color data read from memory. The compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. The type of compression performed by ROP 226 can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on depth and color data on a per-tile basis.

[0067] In some embodiments, ROP 226 is included within each processing cluster (e.g., clusters 214A to 214N of FIG. 2 ) rather than within partition unit 220. In such embodiments, read and write requests for pixel data are transmitted through memory crossbar 216 rather than pixel fragment data. The processed graphics data may be displayed on a display device such as a Figure 1 100 ), routed by processor(s) 102 for further processing, or by Figure 2A One of the processing entities within parallel processor 200 is routed for further processing.

[0068] Figure 2C 2 is a block diagram of a processing cluster 214 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 214A to 214N of FIG. 2. The processing cluster 214 can be configured to execute many threads in parallel, where the term "thread" refers to an instance of a specific program executed on a specific input data set. In some embodiments, a single instruction multiple data (SIMD) instruction issuance technique is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, a single instruction multiple thread (SIMT) technique is used to support the parallel execution of a large number of roughly synchronized threads using a common instruction unit configured to issue instructions to a group of processing engines within each of the processing clusters. Unlike the SIMD execution mechanism in which all processing engines generally execute the same instructions, SIMT execution allows different threads to more easily follow the divergent execution path through a given thread program. It will be appreciated by those skilled in the art that the SIMD processing mechanism represents a functional subset of the SIMT processing mechanism.

[0069] The operation of the processing cluster 214 can be controlled via a pipeline manager 232 that distributes processing tasks to the SIMT parallel processors. The pipeline manager 232 receives instructions from the scheduler 210 of Figure 2 and manages the execution of those instructions via the graphics multiprocessor 234 and / or the texture unit 236. The illustrated graphics multiprocessor 234 is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors of different architectures can be included in the processing cluster 214. One or more instances of the graphics multiprocessor 234 can be included in the processing cluster 214. The graphics multiprocessor 234 can process data, and the data crossbar 240 can be used to distribute the processed data to one of multiple possible destinations including other shader units. The pipeline manager 232 can promote the distribution of processed data by specifying a destination for the processed data to be distributed via the data crossbar 240.

[0070] Each graphics multiprocessor 234 within a processing cluster 214 may include the same set of function execution logic (e.g., arithmetic logic units, load store units, etc.). The function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions are completed. The function execution logic supports a variety of operations, including integer and floating point arithmetic, comparison operations, Boolean operations, bit shifts, and calculation of various algebraic functions. In one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may exist.

[0071] The instructions transmitted to the processing cluster 214 constitute threads. A group of threads executed on a group of parallel processing engines is a thread group. The thread group executes the same program on different input data. Each thread in the thread group can be assigned to a different processing engine in the graphics multiprocessor 234. The thread group can include fewer threads than the number of processing engines in the graphics multiprocessor 234. When the thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle of processing the thread group. The thread group can also include more threads than the number of processing engines in the graphics multiprocessor 234. When the thread group includes more threads than the number of processing engines in the graphics multiprocessor 234, processing can be performed on consecutive clock cycles. In one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 234.

[0072] In one embodiment, the graphics multiprocessor 234 includes an internal cache memory for performing load and store operations. In one embodiment, the graphics multiprocessor 234 can abandon the internal cache and use cache memory (e.g., L1 cache 308) within the processing cluster 214. Each graphics multiprocessor 234 can also access the L2 cache within the partition unit (e.g., partition units 220A to 220N of Figure 2) shared between all processing clusters 214, and can be used to transfer data between threads. The graphics multiprocessor 234 can also access off-chip global memory, which can include one or more of the local parallel processor memory and / or system memory. Any memory external to the parallel processing unit 202 can be used as global memory. In which the processing cluster 214 includes multiple instances of the graphics multiprocessor 234, embodiments can share common instructions and data that can be stored in the L1 cache 308.

[0073] Each processing cluster 214 may include an MMU 245 (memory management unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of the MMU 245 may reside within the memory interface 218 of FIG. 2 . The MMU 245 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (more referred to as blocking) and optionally cache line indexes. The MMU 245 may include an address translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 234 or L1 cache or processing cluster 214. Physical addresses are processed to distribute surface data access locality to achieve efficient request interleaving between partition units. The cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0074] In graphics and computing applications, the processing clusters 214 can be configured so that each graphics multiprocessor 234 is coupled to a texture unit 236 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. The texture data is read from an internal texture L1 cache (not shown) or in some embodiments from an L1 cache within the graphics multiprocessor 234, and is retrieved from an L2 cache, a local parallel processor memory, or a system memory as needed. Each graphics multiprocessor 234 outputs a processed task to a data crossbar 240 to provide the processed task to another processing cluster 214 for further processing or to store the processed task in an L2 cache, a local parallel processor memory, or a system memory via a memory crossbar 216. The preROP 242 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 234, direct the data to the ROP units, which can be located with partition units (e.g., partition units 220A to 220N of FIG. 2) as described herein. The preROP 242 unit optimizes color blending, organizes pixel color data, and performs address translation.

[0075] It should be understood that the core architecture described herein is illustrative and variations and modifications are possible. Any number of processing units, such as graphics multiprocessor 234, texture unit 236, preROP 242, etc., may be included in processing cluster 214. In addition, although only one processing cluster 214 is shown, the parallel processing unit described herein may include any number of instances of processing cluster 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0076] Figure 2DA graphics multiprocessor 234 is shown according to one embodiment. In such an embodiment, the graphics multiprocessor 234 is coupled to the pipeline manager 232 of the processing cluster 214. The graphics multiprocessor 234 has an execution pipeline that includes, but is not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0077] In one embodiment, the instruction cache 252 receives a stream of instructions to be executed from the pipeline manager 232. These instructions are cached in the instruction cache 252 and dispatched for execution by the instruction unit 254. The instruction unit 254 can dispatch instructions as thread groups (e.g., warps), where each thread of the thread group is assigned to a different execution unit within the GPGPU core 262. Instructions can access any of the local, shared, or global address spaces by specifying an address within the unified address space. The address mapping unit 256 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 266.

[0078] The register file 258 provides a set of registers for the functional units of the graphics multiprocessor 324. The register file 258 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 262, load / store unit 266) connected to the graphics multiprocessor 324. In one embodiment, the register file 258 is divided between each of the functional units so that each functional unit is assigned a dedicated portion of the register file 258. In one embodiment, the register file 258 is divided between the different warps being executed by the graphics multiprocessor 324.

[0079] The GPGPU cores 262 may each include a floating point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 324. Depending on the embodiment, the architecture of the GPGPU cores 262 may be similar, or may be different. For example, and in one embodiment, the first portion of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while the second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 floating-point arithmetic standard or enable variable-precision floating-point arithmetic. In addition, the graphics multiprocessor 324 may also include one or more fixed-function or special-function units for performing specific functions such as copying rectangles or pixel blending operations. In one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0080] In one embodiment, GPGPU core 262 includes SIMD logic, and the SIMD logic can execute a single instruction on multiple data sets. In one embodiment, GPGPU core 262 can physically execute SIMD4, SIMD8 and SIMD16 instructions and logically execute SIMD1, SIMD2 and SIMD32 instructions. SIMD instructions for GPGPU core can be generated by a shader compiler at compile time or automatically generated when executing a program written and compiled for single program multiple data (SPMD) or SIMT architecture. Multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example and in one embodiment, eight SIMT threads performing the same or similar operation can be executed in parallel via a single SIMD8 logic unit.

[0081] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 324 to the register file 258 and the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to implement load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, so data transfer between the GPGPU core 262 and the register file 258 has very low latency. The shared memory 270 can be used to implement communication between threads executed on the functional units within the graphics multiprocessor 234. For example, the cache memory 272 can be used as a data cache to cache texture data communicated between the functional units and the texture unit 236. The shared memory 270 can also be used as a cached managed program. In addition to the automatically cached data stored in the cache memory 272, threads executing on the GPGPU core 262 can also programmatically store data in the shared memory.

[0082] FIG. 3A to FIG. 3B Additional graphics multiprocessors are illustrated according to an embodiment. The illustrated graphics multiprocessors 325, 350 are Figure 2C The illustrated graphics multiprocessors 325, 350 may be configured as streaming multiprocessors (SMs) capable of executing a large number of execution threads simultaneously.

[0083] Figure 3A A graphics multiprocessor 325 is shown according to an additional embodiment. The graphics multiprocessor 325 includes Figure 2D The graphics multiprocessor 325 may include multiple additional instances of execution resource units of the graphics multiprocessor 234. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A to 332B, register files 334A to 334B, and (multiple) texture units 344A to 344B. The graphics multiprocessor 325 also includes multiple groups of graphics or compute execution units (e.g., GPGPU cores 336A to 336B, GPGPU cores 337A to 337B, GPGPU cores 338A to 338B) and multiple groups of load / store units 340A to 340B. In one embodiment, the execution resource units have a common instruction cache 330, texture and / or data cache memory 342, and shared memory 346.

[0084] The various components may communicate via the interconnect structure 327. In one embodiment, the interconnect structure 327 includes one or more crossbar switches to enable communication between the various components of the graphics multiprocessor 325. In one embodiment, the interconnect structure 327 is a separate high-speed network fabric layer on which each component of the graphics multiprocessor 325 is stacked. The components of the graphics multiprocessor 325 communicate with remote components via the interconnect structure 327. For example, the GPGPU cores 336A-336B, 337A-337B, and 3378A-338B may each communicate with the shared memory 346 via the interconnect structure 327. The interconnect structure 327 may arbitrate communications within the graphics multiprocessor 325 to ensure fair bandwidth allocation between components.

[0085] Figure 3B A graphics multiprocessor 350 is shown according to an additional embodiment. Figure 2D and Figure 3A As shown, the graphics processor includes multiple groups of execution resources 356A to 356D, each of which includes multiple instruction units, register files, GPGPU cores, and load storage units. The execution resources 356A to 356D can work with (multiple) texture units 360A to 360D to perform texture operations while sharing the instruction cache 354 and shared memory 362. In one embodiment, the execution resources 356A to 356D can share the instruction cache 354 and shared memory 362 and multiple instances of texture and / or data cache memory 358A to 358B. The various components can be connected via Figure 3A The interconnect structure 327 communicates with a similar interconnect structure 352 .

[0086] Those skilled in the art will understand that Figure 1 , FIG. 2A to FIG. 2D and FIG. 3A to FIG. 3B The architecture described in is illustrative and does not limit the scope of the embodiments of the present invention. Therefore, the techniques described herein can be implemented on any appropriately configured processing unit, including but not limited to: one or more mobile application processors; one or more desktop computer or server central processing units (CPUs), including multi-core CPUs; one or more parallel processing units, such as Figure 2A and one or more graphics processors or special purpose processing units without departing from the scope of the embodiments described herein.

[0087] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuits / logic to efficiently process these commands / instructions.

[0088] Technologies for GPU to host processor interconnect

[0089] Figure 4A An exemplary architecture is illustrated in which multiple GPUs 410 to 413 are communicatively coupled to multiple multi-core processors 405 to 406 via high-speed links 440 to 443 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, the high-speed links 440 to 443 support 4 GB / s, 30 GB / s, 80 GB / s, or higher communication throughput, depending on the implementation. Various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the underlying principles of the invention are not limited to any particular communication protocol or throughput.

[0090] Furthermore, in one embodiment, two or more of the GPUs 410 to 413 are interconnected via high-speed links 444 to 445, which may be implemented using the same or different protocols / links as used for high-speed links 440 to 443. Similarly, two or more of the multi-core processors 405 to 406 may be connected via high-speed link 433, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, Figure 4A All communications between the various system components shown in can be accomplished using the same protocol / links (eg, through a common interconnect structure). However, as mentioned, the underlying principles of the invention are not limited to any particular type of interconnect technology.

[0091] In one embodiment, each multi-core processor 405-406 is communicatively coupled to a processor memory 401-402 via a memory interconnect 430-431, respectively, and each GPU 410-413 is communicatively coupled to a GPU memory 420-423 via a GPU memory interconnect 450-453, respectively. The memory interconnects 430-431 and 450-453 may utilize the same or different memory access technologies. As an example and not by way of limitation, the processor memory 401-402 and the GPU memory 420-423 may be a volatile memory such as a dynamic random access memory (DRAM) (including stacked DRAM), a graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or a high bandwidth memory (HBM), and / or may be a non-volatile memory such as a 3D XPoint or Nano-RAM. In one embodiment, a portion of the memory may be a volatile memory and another portion may be a non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0092] As described below, although the various processors 405-406 and GPUs 410-413 may each be physically coupled to a specific memory 401-402, 420-423, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed among all the various physical memories. For example, the processor memories 401-402 may each include 64GB of system memory address space, and the GPU memories 420-423 may each include 32GB of system memory address space (resulting in a total of 256GB of addressable storage space in this example).

[0093] Figure 4B Additional details of the interconnection between the multi-core processor 407 and the graphics acceleration module 446 according to one embodiment are illustrated. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card coupled to the processor 407 via the high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0094] The illustrated processor 407 includes a plurality of cores 460A to 460D, each of which has a translation lookaside buffer 461A to 461D and one or more caches 462A to 462D. These cores may include various other components (e.g., instruction fetch units, branch prediction units, decoders, execution units, reorder buffers, etc.) for executing instructions and processing data not shown to avoid obscuring the basic principles of the present invention. Caches 462A to 462D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 426 may be included in the cache hierarchy and shared by each group of cores 460A to 460D. For example, one embodiment of the processor 407 includes 24 cores, each of which has its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 cache and the L3 cache is shared by two adjacent cores. The processor 407 and the graphics accelerator integrated module 446 are connected to the system memory 441 , which may include the processor memories 401 to 402 .

[0095] Coherence is maintained for data and instructions stored in the various caches 462A-462D, 456, and the system memory 441 via inter-core communications over the coherence bus 464. For example, each cache may have cache coherence logic / circuitry associated therewith to communicate over the coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented over the coherence bus 464 to snoop on cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art and will not be described in detail herein to avoid obscuring the underlying principles of the present invention.

[0096] In one embodiment, the proxy circuit 425 communicatively couples the graphics acceleration module 446 to the coherence bus 464, thereby allowing the graphics acceleration module 446 to participate in the cache coherence protocol as a peer of the core. Specifically, the interface 435 provides connectivity to the proxy circuit 425 via a high-speed link 440 (e.g., a PCIe bus, NVLink, etc.), and the interface 437 connects the graphics acceleration module 446 to the link 440.

[0097] In one implementation, the accelerator integrated circuit 436 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 431, 432, 43N of the graphics acceleration module 446. The graphics processing engines 431, 432, 43N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, 43N may include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a block image transfer engine. In other words, the graphics acceleration module may be a GPU having multiple graphics processing engines 431 to 432, 43N, or the graphics processing engines 431 to 432, 43N may be separate GPUs integrated on a common package, line card, or chip.

[0098] In one embodiment, the accelerator integrated circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions such as virtual to physical memory translation (also known as effective to real memory translation) and a memory access protocol for accessing the system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In one implementation, the cache 438 stores commands and data for efficient access by the graphics processing engines 431 to 432, 43N. In one embodiment, the data stored in the cache 438 and the graphics memory 433 to 434, 43N is kept consistent with the core caches 462A to 462D, 456 and the system memory 411. As mentioned, this may be accomplished via proxy circuitry 425, which participates in cache coherence mechanisms on behalf of cache 438 and memories 433 to 434, 43N (e.g., sending updates to cache 438 related to modifications / accesses of cache lines on processor caches 462A to 462D, 456 and receiving updates from cache 438).

[0099] A set of registers 445 stores context data for threads executed by the graphics processing engines 431 to 432, 43N, and a context management circuit 448 manages thread contexts. For example, the context management circuit 448 may perform save and restore operations to save and restore contexts of various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, upon context switching, the context management circuit 448 may store current register values ​​to a designated area in memory (e.g., identified by a context pointer). The context management circuit may then restore the register values ​​upon returning to context. In one embodiment, the interrupt management circuit 447 receives and processes interrupts received from system devices.

[0100] In one implementation, the virtual / effective address from the graphics processing engine 431 is converted to an actual / physical address in the system memory 411 by the MMU 439. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator module 446 can be dedicated to a single application executed on the processor 407, or can be shared between multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 431 to 432, 43N are shared with multiple applications or virtual machines (VMs). Resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0101] Thus, the accelerator integrated circuit acts as a bridge to the system of graphics acceleration modules 446 and provides address translation and system memory cache services. In addition, the accelerator integrated circuit 436 can provide virtualization facilities for the host processor to manage virtualization of the graphics processing engine, interrupts, and memory management.

[0102] Because the hardware resources of the graphics processing engines 431-432, 43N are explicitly mapped to the actual address space seen by the host processor 407, any host processor can directly address these resources using effective address values. In one embodiment, one function of the accelerator integrated circuit 436 is the physical separation of the graphics processing engines 431-432, 43N so that they appear on the system as independent units.

[0103] As mentioned, in the illustrated embodiment, one or more graphics memories 433 to 434, 43M are coupled to each of the graphics processing engines 431 to 432, 43N, respectively. The graphics memories 433 to 434, 43M store instructions and data being processed by each of the graphics processing engines 431 to 432, 43N. The graphics memories 433 to 434, 43M may be volatile memories such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories such as 3D XPoint or Nano-Ram.

[0104] In one embodiment, in order to reduce data traffic on link 440, biasing techniques are used to ensure that the data stored in graphics memory 433 to 434, 43M is the data most frequently used by graphics processing engines 431 to 432, 43N and preferably not used (at least not frequently) by cores 460A to 460D. Similarly, the biasing mechanism attempts to keep data needed by the core (and preferably not the graphics processing engines 431 to 432, 43N) within the caches 462A to 462D, 456 of the core and system memory 411.

[0105] Figure 4C Another embodiment is shown in which an accelerator integrated circuit 436 is integrated within the processor 407. In this embodiment, the graphics processing engines 431 to 432, 43N communicate directly with the accelerator integrated circuit 436 via the interface 437 and the interface 435 through the high-speed link 440 (which may also utilize any form of bus or interface protocol). The accelerator integrated circuit 436 can perform operations related to Figure 4B The operations are the same as those described, but given their close proximity to the coherency bus 462 and caches 462A to 462D, 426, the operations may be performed at a higher throughput.

[0106] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The shared programming model may include a programming model controlled by accelerator integrated circuit 436 and a programming model controlled by graphics acceleration module 446.

[0107] In one embodiment of a dedicated process model, graphics processing engines 431 to 432, 43N are dedicated to a single application or process under a single operating system. A single application can funnel other application requests to graphics engines 431 to 432, 43N, thereby providing virtualization within a VM / partition.

[0108] In a dedicated process programming model, graphics processing engines 431 to 432, 43N can be shared by multiple VM / application partitions. The shared model requires a hypervisor to virtualize graphics processing engines 431 to 432, 43N to allow access by each operating system. For a single partition system without a hypervisor, graphics processing engines 431 to 432, 43N are owned by the operating system. In both cases, the operating system can virtualize graphics processing engines 431 to 432, 43N to provide access to each process or application.

[0109] For the shared programming model, the graphics acceleration module 446 or the individual graphics processing engines 431 to 432, 43N use a process handle to select a processing element. In one embodiment, the processing elements are stored in the system memory 411 and can be addressed using the effective address to real address translation techniques described herein. The process handle can be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 431 to 432, 43N (i.e., calling the system software to add a processing element to the processing element link table). The lower 16 bits of the process handle can be the offset of the processing element within the processing element link table.

[0110] Figure 4D An exemplary accelerator integrated slice 490 is illustrated. As used herein, a "slice" includes a specified portion of the processing resources of the accelerator integrated circuit 436. The application effective address space 482 within the system memory 411 stores the processing element 483. In one embodiment, the processing element 483 is stored in response to a GPU call 481 from an application 480 executed on the processor 407. The processing element 483 contains the processing state of the corresponding application 480. The work descriptor (WD) 484 contained in the processing element 483 can be a single job requested by the application, or it can contain a pointer to a job queue. In the latter case, the WD 484 is a pointer to the job request queue in the application address space 482.

[0111] Graphics acceleration module 446 and / or individual graphics processing engines 431-432, 43N may be shared by all processes or a subset of processes in the system. Embodiments of the present invention include an infrastructure for establishing a processing state and sending a WD 484 to the graphics acceleration module 446 to start a job in a virtualized environment.

[0112] In one implementation, the dedicated process programming model is implementation specific. In this model, a single process owns the graphics acceleration module 446 or a separate graphics processing engine 431. Since the graphics acceleration module 446 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 436 to obtain the belonging partition, and the operating system initializes the accelerator integrated circuit 436 to obtain the belonging process when the graphics acceleration module 446 is assigned.

[0113] In operation, the WD acquisition unit 491 in the accelerator integrated slice 490 acquires the next WD 484, which includes an indication of the work to be performed by one of the graphics processing engines of the graphics acceleration module 446. As shown, the data from the WD484 can be stored in the register 445 and used by the MMU 439, the interrupt management circuit 447 and / or the context management circuit 446. For example, one embodiment of the MMU 439 includes a segment / page walk circuit for accessing the segment / page table 486 within the OS virtual address space 485. The interrupt management circuit 447 can process the interrupt event 492 received from the graphics acceleration module 446. When performing graphics operations, the effective address 493 generated by the graphics processing engines 431 to 432, 43N is converted into an actual address by the MMU 439.

[0114] In one embodiment, the same set of registers 445 is replicated for each graphics processing engine 431 to 432, 43N and / or graphics acceleration module 446, and this set of registers can be initialized by a hypervisor or an operating system. Each of these replicated registers can be included in an accelerator integrated slice 490. Table 1 shows exemplary registers that can be initialized by a hypervisor.

[0115] Table 1 - Hypervisor Initialization Registers

[0116] 1 Slice Control Register 2 Real Address (RA) Dispatch Process Area Pointer 3 Authorization Mask Override Register 4 Interrupt vector table entry offset 5 Interrupt vector table entry limit 6 Status Register 7 Logical Partition ID 8 Real Address (RA) Manager Accelerator Utilizes Record Pointers 9 Storage Description Register

[0117] Example registers that may be initialized by the operating system are shown in Table 2.

[0118] Table 2 - Operating System Initialization Registers

[0119] 1 Process and thread identities 2 Effective Address (EA) context save / restore pointer 3 Virtual Address (VA) Accelerator Utilizes Record Pointers 4 Virtual Address (VA) Segment Table Pointer 5 Authorization Mask 6 Job Descriptor

[0120] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engine 431 to 432, 43N. The WD contains all the information needed by the graphics processing engine 431 to 432, 43N to complete its work, or the WD can be a pointer to a memory location where the application has established a command queue for work to be completed.

[0121] Figure 4E Additional details of one embodiment of a sharing model are illustrated. The embodiment includes a hypervisor real address space 498 in which a processing element list 499 is stored. The hypervisor real address space 498 is accessible via a hypervisor 496 that virtualizes a graphics acceleration module engine of an operating system 495.

[0122] The shared programming model allows all processes or a subset of processes from all partitions or a subset of partitions in the system to use the graphics acceleration module 446. There are two programming models where the graphics acceleration module 446 is shared by multiple processes and partitions: time-sliced ​​sharing and graphics direct sharing.

[0123] In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. In order for the graphics acceleration module 446 to support virtualization of the hypervisor 496, the graphics acceleration module 446 may comply with the following requirements: 1) Application job requests must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) The graphics acceleration module 446 guarantees that application job requests are completed within a specified amount of time, including any conversion errors, or the graphics acceleration module 446 provides the ability to preempt job processing. 3) When operating in a direct sharing programming model, fairness between processes must be guaranteed for the graphics acceleration module 446.

[0124] In one embodiment, for the shared model, the application 480 is required to make an operating system 495 system call using a graphics acceleration module 446 type, a work descriptor (WD), an authorization mask register (AMR) value, and a context save / restore region pointer (CSRP). The graphics acceleration module 446 type describes the target acceleration function of the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446 and can be in the following form: a graphics acceleration module 446 command; an effective address pointer to a user-defined structure; an effective address pointer to a command queue; or any other data structure used to describe the work to be performed by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state for the current process. The value passed to the operating system is similar to the application that sets the AMR. If the implementation of the accelerator integrated circuit 436 and the graphics acceleration module 446 does not support the user authorization mask override register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. The hypervisor 496 may optionally apply the current authorization mask override register (AMOR) value before placing the AMR on the processing element 483. In one embodiment, the CSRP is one of the registers 445 that contains the effective address of an area in the application address space 482 for the graphics acceleration module 446 to save and restore context state. This pointer is optional if state is not required to be saved between jobs or when a job is preempted. The context save / restore area may be a plugged in system memory.

[0125] Upon receiving the system call, the operating system 495 can verify that the application 480 is registered and authorized to use the graphics acceleration module 446. The operating system 495 then calls the hypervisor 496 with the information shown in Table 3.

[0126] Table 3 - Parameters of the operating system's call to the hypervisor

[0127] 1 Job Descriptor (WD) 2 Authorization Mask Register (AMR) value (may be masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0128] Upon receiving the hypervisor call, hypervisor 496 verifies that operating system 495 has registered and is authorized to use graphics acceleration module 446. Hypervisor 496 then places processing element 483 into a processing element link table for the corresponding graphics acceleration module 446 type. A processing element may include the information shown in Table 4.

[0129] Table 4 - Processing Component Information

[0130] 1 Job Descriptor (WD) 2 Authorization Mask Register (AMR) value (may be masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt vector table, derived from the hypervisor call parameters 9 Status Register (SR) Value 10 Logical Partition ID (LPID) 11 Real Address (RA) Manager Accelerator Utilizes Record Pointers 12 Storage Descriptor Register (SDR)

[0131] In one embodiment, the hypervisor initializes the plurality of accelerator integrated slices 490 of registers 445 .

[0132] like Figure 4F As shown, one embodiment of the present invention employs a unified memory addressable via a common virtual memory address space for accessing physical processor memories 401 to 402 and GPU memories 420 to 423. In this implementation, operations executed on GPUs 410 to 413 utilize the same virtual / effective memory address space to access processor memories 401 to 402, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion is allocated to second processor memory 402, a third portion is allocated to GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 401 to 402 and GPU memories 420 to 423, thereby allowing any processor or GPU to access any physical memory having a virtual address mapped to that memory.

[0133] In one embodiment, bias / coherency management circuits 494A-494E within one or more of MMUs 439A-439E ensure cache coherency between caches of a host processor (e.g., 405) and GPUs 410-413 and implement biasing techniques that indicate physical memory where certain types of data should be stored. Figure 4F 4. Multiple instances of bias / consistency management circuits 494A to 494E are illustrated in FIG. 4, but bias / consistency circuits may also be implemented within an MMU of one or more host processors 405 and / or within an accelerator integrated circuit 436.

[0134] One embodiment allows the GPU-attached memory 420 to 423 to be mapped as part of the system memory and accessed using shared virtual memory (SVM) technology, but without suffering from the typical performance drawbacks associated with full system cache coherence. The ability to access the GPU-attached memory 420 to 423 as system memory does not incur heavy cache coherence overhead, which provides a favorable operating environment for GPU offloading. This arrangement allows the host processor 405 software to set operands and access calculation results without the overhead of traditional I / O direct memory access (DMA) data copy. These traditional copies involve driver calls, interrupts, and memory mapped I / O (MMIO) accesses, which are inefficient relative to simple memory accesses. At the same time, the ability to access the GPU-attached memory 420 to 423 without cache coherence overhead may be critical to the execution time of the offloaded calculation. For example, in the case of a large number of streaming write memory services, the cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPU 410 to 413. The efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation all play an important role in determining the effectiveness of GPU offloading.

[0135] In one implementation, the selection between GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table may be used, which may be a page granular structure including 1 or 2 bits per GPU attached memory page (i.e., controlled at the granularity of a memory page). The bias table may be implemented in the stolen memory range of one or more GPU attached memories 420 to 423, with or without a bias cache in GPUs 410 to 413 (e.g., to cache frequently / recently used bias table entries). Alternatively, the entire bias table may be maintained within the GPU.

[0136] In one implementation, the bias table entry associated with each access to the GPU attached memory 420 to 423 is accessed before actually accessing the GPU memory, resulting in the following operations. First, local requests from GPUs 410 to 413 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 420 to 423. Local requests from the GPU whose pages are found in the host bias are forwarded to the processor 405 (e.g., over a high-speed link as discussed above). In one embodiment, the request from the processor 405 to find the requested page in the host processor bias completes the request like a normal memory read. Alternatively, the request for the GPU bias page can be forwarded to the GPU 410 to 413. Then, if the GPU is not currently using the page, the GPU can transfer the page to the host processor bias.

[0137] The bias state of a page can be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, a hardware-only based mechanism.

[0138] One mechanism for changing the bias state employs an API call (e.g., OpenCL) which in turn calls a GPU device driver which in turn sends a message (or queues a command descriptor) to the GPU, thereby directing the GPU to change the bias state and, for certain transitions, perform a cache flush operation in the host. The cache flush operation is required for a transition from host processor 405 bias to GPU bias, but not for the reverse transition.

[0139] In one embodiment, cache coherency is maintained by temporarily rendering GPU bias pages uncacheable to host processor 405. To access these pages, processor 405 may request access from GPU 410, which may or may not grant access immediately, depending on the implementation. Therefore, to reduce communication between processor 405 and GPU 410, it is advantageous to ensure that GPU bias pages are pages that are needed by the GPU but not by the host processor 405, and vice versa.

[0140] Graphics processing pipeline

[0141] Figure 5 2. A graphics processing pipeline 500 is illustrated in accordance with an embodiment. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included in a parallel processing subsystem as described herein, such as the parallel processing subsystem 200 of FIG. 2. In one embodiment, the parallel processing subsystem 200 is Figure 12 . As described herein, various parallel processing systems may implement the graphics processing pipeline 500 via one or more instances of a parallel processing unit (e.g., parallel processing unit 202 of FIG. 2 ). For example, a shader unit (e.g., graphics multiprocessor 234 of FIG. 3 ) may be configured to perform the functions of one or more of a vertex processing unit 504, a tessellation control processing unit 508, a tessellation evaluation processing unit 512, a geometry processing unit 516, and a fragment / pixel processing unit 524. The functions of the data assembler 502, the primitive assemblers 506, 514, 518, the tessellation unit 510, the rasterizer 522, and the raster operation unit 526 may also be performed by other processing engines within a processing cluster (e.g., processing cluster 214 of FIG. 3 ) and corresponding partition units (e.g., partition units 220A to 220N of FIG. 2 ). The graphics processing pipeline 500 may also be implemented using one or more dedicated processing units for the functions. In one embodiment, one or more portions of the graphics processing pipeline 500 may be executed by parallel processing logic within a general purpose processor (e.g., a CPU). In one embodiment, one or more portions of the graphics processing pipeline 500 may access on-chip memory (e.g., parallel processor memory 222 as shown in FIG. 2 ) via a memory interface 528, which may be an example of the memory interface 218 of FIG. 2 .

[0142] In one embodiment, data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. Data assembler 502 then outputs vertex data including vertex attributes to vertex processing unit 504. Vertex processing unit 504 is a programmable execution unit that executes vertex shader programs to illuminate and transform vertex data as specified by the vertex shader programs. Vertex processing unit 504 reads data stored in cache, local or system memory for processing vertex data, and can be programmed to transform vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0143] A first instance of primitive assembler 506 receives vertex attributes from vertex processing unit 50. Primitive assembler 506 reads the stored vertex attributes as needed and constructs graphics primitives for processing by tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc. as supported by various graphics processing application programming interfaces (APIs).

[0144] The tessellation control processing unit 508 treats the input vertices as control points of a geometric patch. These control points are transformed from an input representation from the patch (e.g., a basis for the patch) to a representation suitable for surface evaluation by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 may also calculate tessellation factors for the edges of the geometric patch. The tessellation factors apply to individual edges and quantify the viewpoint-dependent level of detail associated with the edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and tessellate the patch into a plurality of geometric primitives, such as lines, triangles, or quadrilateral primitives, which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the tessellated patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitive.

[0145] A second instance of primitive assembler 514 receives vertex attributes from tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphics primitives for processing by geometry processing unit 516. Geometry processing unit 516 is a programmable execution unit that executes geometry shader programs to transform graphics primitives received from primitive assembler 514 as specified by the geometry shader programs. In one embodiment, geometry processing unit 516 is programmed to tessellate the graphics primitives into one or more new graphics primitives and to compute parameters for rasterizing the new graphics primitives.

[0146] In some embodiments, the geometry processing unit 516 can add or delete elements in the geometry stream. The geometry processing unit 516 outputs parameters and vertices specifying new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphics primitives for processing by the viewport scaling, culling, and clipping unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or the system memory for processing geometry data. The viewport scaling, culling, and clipping unit 520 performs clipping, culling, and viewport scaling, and outputs the processed graphics primitives to the rasterizer 522.

[0147] The rasterizer 522 can perform depth culling and other depth-based optimizations. The rasterizer 522 also performs scan conversion on new graphics primitives to generate fragments and outputs these fragments and associated coverage data to the fragment / pixel processing unit 524. The fragment / pixel processing unit 524 is a programmable execution unit configured to execute a fragment shader program or a pixel shader program. The fragment / pixel processing unit 524 transforms the fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 524 can be programmed to perform operations including but not limited to texture mapping, shading, blending, texture correction, and perspective correction to generate shaded fragments or pixels output to the raster operation unit 526. The fragment / pixel processing unit 524 can read data stored in a parallel processor memory or system memory to use when processing fragment data. The fragment or pixel shader program can be configured to color with samples, pixels, tiles, or other granularity according to the sampling rate configured for the processing unit.

[0148] The raster operation unit 526 is a processing unit that performs raster operations including but not limited to stencil printing, z-testing, blending, etc., and outputs pixel data as processed graphics data for storage in graphics memory (e.g., parallel processor memory 222 in FIG. 2 and / or as Figure 1 The raster operation unit 526 may be configured to compress the z or color data written to the memory and decompress the z or color data read from the memory.

[0149] Machine Learning Overview

[0150] A machine learning algorithm is an algorithm that can learn based on a set of data. Embodiments of machine learning algorithms can be designed to model high-level abstractions within a data set. For example, an image recognition algorithm can be used to determine which of several categories a given input belongs to; a regression algorithm can output a numerical value given an input; and a pattern recognition algorithm can be used to generate translated text or perform text-to-speech and / or speech recognition.

[0151] One exemplary type of machine learning algorithm is a neural network. There are many types of neural networks; a simple type of neural network is a feedforward network. A feedforward network can be implemented as an acyclic graph in which nodes are arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer separated by at least one hidden layer. The hidden layer transforms the input received by the input layer into a representation useful for generating output in the output layer. The network nodes are fully connected to the nodes in the adjacent layers via edges, but there are no edges between the nodes within each layer. Data received at the nodes of the input layer of the feedforward network is propagated (i.e., "fed forward") to the nodes of the output layer via an activation function, which calculates the state of the nodes of each successive layer in the network based on coefficients ("weights"), which are respectively associated with each of the edges connecting these layers. Depending on the specific model represented by the algorithm being executed, the output from the neural network algorithm can take a variety of forms.

[0152] Before a machine learning algorithm can be used to model a specific problem, the algorithm is trained using a training data set. Training a neural network involves: selecting a network topology; using a set of training data representing the problem being modeled by the network; and adjusting weights until the network model behaves with minimal error for all instances of the training data set. For example, during a supervised learning training process for a neural network, the output generated by the network in response to an input representing an instance in the training data set is compared to the "correct" labeled output for the instance; an error signal representing the difference between the output and the labeled output is calculated; and when the error signal is propagated back through the layers of the network, the weights associated with the connections are adjusted to minimize the error. The network is considered "trained" when the error for each output generated from an instance of the training data set is minimized.

[0153] The accuracy of a machine learning algorithm can be greatly affected by the quality of the data set used to train the algorithm. The training process can be computationally intensive and can take a significant amount of time on a conventional general purpose processor. Therefore, many types of machine learning algorithms are trained using parallel processing hardware. This is particularly useful for optimizing the training of neural networks, as the calculations performed when adjusting the coefficients in a neural network are naturally suited to parallel implementations. In particular, many machine learning algorithms and software applications have been adapted to use parallel processing hardware within general purpose graphics processing devices.

[0154] Figure 6is a generalized diagram of a machine learning software stack 600. Machine learning applications 602 may be configured to train a neural network using a training data set or to implement machine intelligence using a trained deep neural network. Machine learning applications 602 may include training and inference capabilities for a neural network and / or specialized software that may be used to train a neural network prior to deployment. Machine learning applications 602 may implement any type of machine intelligence, including but not limited to: image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

[0155] Hardware acceleration for machine learning applications 602 can be implemented via a machine learning framework 604. The machine learning framework 604 can provide a library of machine learning primitives. Machine learning primitives are basic operations that machine learning algorithms typically perform. Without the machine learning framework 604, developers of machine learning algorithms would be required to create and optimize the main computational logic associated with the machine learning algorithm, and then re-optimize the computational logic when a new parallel processor is developed. Instead, machine learning applications can be configured to use primitives provided by the machine learning framework 604 to perform necessary calculations. Exemplary primitives include tensor convolutions, activation functions, and pooling, which are computational operations performed when training a convolutional neural network (CNN). The machine learning framework 604 can also provide primitives for implementing basic linear algebra subroutines, such as matrix and vector operations, performed by many machine learning algorithms.

[0156] The machine learning framework 604 can process input data received from the machine learning application 602 and generate appropriate inputs to the computation framework 606. The computation framework 606 can abstract the underlying instructions provided to the GPGPU driver 608 so that the machine learning framework 604 can take advantage of hardware acceleration via the GPGPU hardware 610 without requiring the machine learning framework 604 to be intimately familiar with the architecture of the GPGPU hardware 610. In addition, the computation framework 606 can implement hardware acceleration for the machine learning framework 604 across multiple types and generations of GPGPU hardware 610.

[0157] GPGPU machine learning acceleration

[0158] Figure 7 A highly parallel general purpose graphics processing unit 700 is illustrated in accordance with an embodiment. In one embodiment, a general purpose processing unit (GPGPU) 700 may be configured to be particularly efficient in processing the type of computational workload associated with training deep neural networks. Additionally, a GPGPU 700 may be directly linked to other instances of a GPGPU for creating a multi-GPU cluster, thereby improving the speed of training particularly deep neural networks.

[0159] GPGPU 700 includes a host interface 702 for implementing a connection with a host processor. In one embodiment, host interface 702 is a PCI Express interface. However, the host interface may also be a supplier-specific communication interface or communication structure. GPGPU 700 receives commands from the host processor and uses a global scheduler 704 to distribute execution threads associated with those commands to a group of computing clusters 706A to 706H. Computing clusters 706A to 706H share a cache memory 708. Cache memory 708 may act as a higher-level cache in the cache memory within computing clusters 706A to 706H.

[0160] GPGPU 700 includes memory 714A-714B, which is coupled to computing clusters 706A-706H via a set of memory controllers 712A-712B. In various embodiments, memory 714A-714B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory (such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory). In one embodiment, memory units 224A-224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM).

[0161] In one embodiment, each computing cluster 706A-706H includes a set of graphics multiprocessors, such as Figure 4A The graphics multiprocessor 400 of the computing cluster includes multiple types of integer and floating point logic units that can perform computational operations at a range of precisions, including precisions suitable for machine learning computations. For example and in one embodiment, at least a subset of the floating point units in each of the computing clusters 706A to H can be configured to perform 16-bit or 32-bit floating point operations, while a different subset of the floating point units can be configured to perform 64-bit floating point operations.

[0162] Multiple instances of GPGPU 700 can be configured to operate as a computing cluster. The communication mechanism used by the computing cluster for synchronization and data exchange varies across embodiments. In one embodiment, multiple instances of GPGPU 700 communicate through a host interface 702. In one embodiment, GPGPU 700 includes an I / O hub 708 that couples GPGPU 700 with a GPU link 710, which implements direct connection to other instances of GPGPU. In one embodiment, GPU link 710 is coupled to a dedicated GPU-GPU bridge, which implements communication and synchronization between multiple instances of GPGPU 700. In one embodiment, GPU link 710 is coupled to a high-speed interconnect for transmitting and receiving data to other GPGPUs or parallel processors. In one embodiment, multiple instances of GPGPU 700 are located in a separate data processing system and communicate via a network device, which can be accessed via a host interface 702. In one embodiment, in addition to or as an alternative to the host interface 702, GPU link 710 can be configured to enable connection to a host processor.

[0163] Although the illustrated configuration of GPGPU 700 can be configured to train a neural network, one embodiment provides an alternative configuration of GPGPU 700 that can be configured for deployment in a high-performance or low-power inference platform. In the inference configuration, GPGPU 700 includes fewer computing clusters 706A to H relative to the training configuration. In addition, the memory technology associated with memory 714A to 714B can be different between the inference and training configurations. In one embodiment, the inference configuration of GPGPU 700 can support inference-specific instructions. For example, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which are typically used during inference operations for deployed neural networks.

[0164] Figure 8 A multi-GPU computing system 800 is illustrated in accordance with an embodiment. The multi-GPU computing system 800 may include a processor 802 coupled to a plurality of GPGPUs 806A to D via a host interface switch 804. In one embodiment, the host interface switch 804 is a PCI Express switch device that couples the processor 802 to a PCI Express bus, through which the processor 802 may communicate with the set of GPGPUs 806A to D. Each of the plurality of GPGPUs 806A to 806D may be Figure 7GPGPU 700 of the embodiment of the present invention. GPGPU 806A to D can be interconnected via a set of high-speed point-to-point GPU-GPU links 816. The high-speed GPU-GPU links can be connected via dedicated GPU links (such as Figure 7 806A to 806D. The P2P GPU link 816 enables each of the GPGPUs 806A to 806D to communicate directly with each other without having to communicate through a host interface bus (to which the processor 802 is connected). In the case where GPU-GPU traffic is directed to the P2P GPU link, the host interface bus can still be used for system memory access or communication with other instances of the multi-GPU computing system 800 (e.g., via one or more network devices). Although in the illustrated embodiment, the GPGPUs 806A to D are connected to the processor 802 via the host interface switch 804, in one embodiment, the processor 802 includes direct support for the P2P GPU link 816 and can be directly connected to the GPGPUs 806A to 806D.

[0165] Machine Learning Neural Network Implementation

[0166] The computing architecture provided by the embodiments described herein can be configured to perform these types of parallel processing that are particularly suitable for training and deploying neural networks for machine learning. A neural network can be generalized as a network of functions with a graph relationship. As is well known in the art, there are many types of neural network implementations used in machine learning. One exemplary type of neural network is a feedforward network as previously described.

[0167] The second exemplary type of neural network is a convolutional neural network (CNN). CNN is a specialized feedforward neural network for processing data (such as image data) with a known, grid-like topology. Therefore, CNNs are commonly used for computational vision and image recognition applications, but they can also be used for other types of pattern recognition, such as speech and language processing. The nodes in the input layer of a CNN are organized as a set of "filters" (feature detectors inspired by the receptive fields found in the retina), and the output of each set of filters is propagated to the nodes in the successive layers of the network. The calculations for a CNN include applying a convolution mathematical operation to each filter to produce the output of the filter. Convolution is a specialized mathematical operation performed by two functions to produce a third function, which is a modified version of one of the two original functions. In convolutional network terminology, the first function about the convolution can be called the input, and the second function can be called the convolution kernel. The output can be called a feature map. For example, the input to the convolution layer can be a multidimensional data array that defines the various color components of the input image. The convolution kernel can be a multidimensional parameter array, where the parameters are adapted by a training process for the neural network.

[0168] A recurrent neural network (RNN) is a class of feedforward neural networks that include feedback connections between layers. RNNs enable modeling of sequence data by sharing parameter data across different parts of the neural network. The architecture of an RNN includes loops. These loops represent the effect of the current value of a variable on its own value at future times, as at least a portion of the output data from the RNN is used as feedback for processing subsequent inputs in the sequence. This feature makes RNNs particularly useful for language processing due to the mutable nature of the language data that can be composed.

[0169] The figures described below present exemplary feedforward, CNN, and RNN networks, and describe the general process for training and deploying each of those types of networks, respectively. It will be understood that these descriptions are exemplary and non-limiting with respect to any specific embodiment described herein, and that the illustrated concepts can generally be applied to deep neural networks and machine learning techniques in general.

[0170] The exemplary neural network described above can be used to perform deep learning. Deep learning is machine learning performed using deep neural networks. In contrast to shallow neural networks that include only a single hidden layer, the deep neural networks used in deep learning are artificial neural networks composed of multiple hidden layers. Deeper neural networks are generally more computationally intensive to train. However, the additional hidden layers of the network enable multi-step pattern recognition, which results in reduced output errors relative to shallow machine learning techniques.

[0171] The deep neural networks used in deep learning typically include a front-end network for performing feature recognition coupled to a back-end network representing a mathematical model that can perform operations (e.g., object classification, speech recognition, etc.) based on the feature representations provided to the model. Deep learning enables machine learning to be performed without having to perform manual feature engineering for the model. Instead, deep neural networks can learn features based on statistical structures or correlations within the input data. The learned features can be provided to a mathematical model that can map the detected features to an output. The mathematical model used by the network is typically dedicated to the specific task to be performed, and different models will be used to perform different tasks.

[0172] Once a neural network is structured, a learning model can be applied to the network to train the network to perform a specific task. The learning model describes how to adjust the weights within the model to reduce the output error of the network. Backpropagation of errors is a common method for training neural networks. An input vector is presented to the network for processing. The output of the network is compared to the desired output using a loss function, and an error value is calculated for each neuron in the output layer. These error values ​​are then propagated backward until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then learn from those errors using an algorithm (such as a stochastic gradient descent algorithm) to update the weights of the neural network.

[0173] Fig. 9A 4 to B illustrate an exemplary convolutional neural network. Fig. 9A The diagram shows the various layers within a CNN. Fig. 9A As shown in , an exemplary CNN for modeling image processing can receive an input 902 that describes the red, green, and blue (RGB) components of an input image. The input 902 can be processed by multiple convolutional layers (e.g., convolutional layer 904, convolutional layer 906). Optionally, the outputs from the multiple convolutional layers can be processed by a set of fully connected layers 908. The neurons in the fully connected layer have full connections to all activations in the previous layer, as previously described for the feedforward network. The outputs from the fully connected layer 908 can be used to generate output results from the network. Matrix multiplication can be used instead of convolution to calculate the activations within the fully connected layer 908. Not all CNN implementations use the fully connected layer 908. For example, in some implementations, the convolutional layer 906 can generate the output of the CNN.

[0174] The convolutional layers are sparsely connected, which is different from the traditional neural network configuration found in the fully connected layer 908. Traditional neural network layers are fully connected so that each output unit interacts with each input unit. However, the convolutional layers are sparsely connected because the output of the convolution of the receptive field (rather than the corresponding state value of each node in the receptive field) is input to the nodes of the subsequent layer, as shown. The kernel associated with the convolutional layer performs a convolution operation, the output of which is sent to the next layer. The dimensionality reduction performed within the convolutional layer is one aspect that enables CNNs to scale to process large images.

[0175] Fig. 9B Illustrated are exemplary computational stages within a convolutional layer of a CNN. An input 912 to a convolutional layer of a CNN may be processed in three stages of a convolutional layer 914. The three stages may include a convolution stage 916, a detector stage 918, and a pooling stage 920. The convolutional layer 914 may then output data to a successive convolutional layer. The last convolutional layer of the network may generate output feature map data or provide input to a fully connected layer, for example to generate a classification value for input to the CNN.

[0176] Several convolutions are performed in parallel in the convolution stage 916 to produce a set of linear activations. The convolution stage 916 may include an affine transformation, which is any transformation that can be specified as a linear transformation plus a translation. Affine transformations include rotations, translations, scaling, and combinations of these transformations. The convolution stage calculates the output of a function (e.g., a neuron) connected to a specific region in the input, which can be determined as a local region associated with the neuron. The neuron calculates the dot product between the weight of the neuron and the region in the local input (the neuron is connected to the local input). The output from the convolution stage 916 defines a set of linear activations processed by successive stages of the convolution layer 914.

[0177] The linear activations may be processed by the detector stage 918. In the detector stage 918, each linear activation is processed by a non-linear activation function. The non-linear activation function increases the non-linear nature of the overall network without affecting the receptive field of the convolutional layer. Several types of non-linear activation functions may be used. One specific type is the rectified linear unit (ReLU), which uses an activation function defined as f(x)=max(0,x) so that the activation is thresholded at zero.

[0178] The pooling stage 920 uses a pooling function that replaces the output of the convolutional layer 906 with a summary statistic of nearby outputs. The pooling function can be used to introduce translation invariance into the neural network so that a slight translation to the input does not change the pooled output. The invariance of local translation can be useful in scenarios where the presence of features in the input data is more important than the precise location of the features. Various types of pooling functions can be used during the pooling stage 920, including maximum pooling, average pooling, and L2 norm pooling. In addition, some CNN implementations do not include a pooling stage. Instead, such an implementation substitutes an additional convolution stage, which has an increased stride relative to the previous convolution stage.

[0179] The output from the convolutional layer 914 may then be processed by the next layer 922. The next layer 922 may be an additional convolutional layer or one of the fully connected layers 908. For example, Fig. 9A The first convolution layer 904 can output to the second convolution layer 906, and the second convolution layer can output to the first layer in the fully connected layer 908.

[0180] Fig.10 An exemplary recurrent neural network 1000 is illustrated. In a recurrent neural network (RNN), the previous state of the network affects the output of the current state of the network. RNNs can be constructed in a variety of ways using a variety of functions. The use of RNNs generally revolves around the use of mathematical models to predict the future based on previous input sequences. For example, RNNs can be used to perform statistical language modeling to predict upcoming words given a previous word sequence. The illustrated RNN 1000 can be described as having the following: an input layer 1002, which receives an input vector; a hidden layer 1004, which is used to implement a recursive function; a feedback mechanism 1005, which is used to implement a 'memory' of previous states; and an output layer 1006, which is used to output a result. The RNN 1000 operates based on time steps. The state of the RNN at a given time step is affected based on the previous time step via the feedback mechanism 1005. For a given time step, the state of the hidden layer 1004 is defined by the previous state and the input at the current time step. At the initial input (x 1 ) can be processed by the hidden layer 1004. The second input (x 2 ) can be used by the hidden layer 1004 to process the initial input (x 1 ) is processed by the state information determined during the period. The given state can be calculated as s t =f(Ux t + Ws t-1), where U and W are parameter matrices. Function f is typically nonlinear, such as a variant of the hyperbolic tangent function (Tanh) or a modified function f(x)=max(0,x). However, the specific mathematical function used in hidden layer 1004 may vary depending on the specific implementation details of RNN 1000.

[0181] In addition to the basic CNN and RNN networks described, variations of those networks can also be implemented. An example RNN variant is the Long Short Term Memory (LSTM) RNN. LSTM RNNs are able to learn long-term dependencies that may be necessary for processing longer language sequences. A variant of CNN is a convolutional deep belief network, which has a structure similar to a CNN and is trained in a manner similar to a deep belief network. A deep belief network (DBN) is a generative neural network consisting of multiple layers of stochastic (random) variables. A DBN can be trained layer by layer using greedy unsupervised learning. The learned weights of the DBN can then be used to provide a pre-trained neural network by determining a set of optimal initial weights for the neural network.

[0182] Fig.11 The training and deployment of a deep neural network is illustrated. Once a given network has been structured for a task, the neural network is trained using a training data set 1102. Various training frameworks 1104 have been developed to enable hardware acceleration of the training process. For example, Figure 6 The machine learning framework 604 can be configured as a training framework 604. The training framework 604 can be hooked up to the untrained neural network 1106 and enable the untrained neural network to be trained to generate a trained neural network 1108 using the parallel processing resources described herein.

[0183] To start the training process, initial weights can be chosen randomly or by pre-training with a deep belief network. The training cycle can then be performed in a supervised or unsupervised manner.

[0184] Supervised learning is a learning method in which training is performed as an arbitration operation, such as when the training data set 1102 includes inputs (which are paired with the expected outputs of the inputs), or when the training data set includes inputs with known outputs and the outputs of the neural network are manually graded. The network processes the inputs and compares the resulting outputs with a set of expected or desired outputs. Then, the error is back-propagated through the system. The training framework 1104 can be adjusted to adjust the weights of the untrained neural network 1106. The training framework 1104 can provide tools for monitoring the extent to which the untrained neural network 1106 converges to a model suitable for generating the correct answer based on the known input data. The training process occurs repeatedly when the weights of the network are adjusted to improve the output generated by the neural network. The training process can continue until the neural network reaches a statistically expected accuracy associated with the trained neural network 1108. Then, the trained neural network 1108 can be deployed to implement any number of machine learning operations.

[0185] Unsupervised learning is a learning method in which a network attempts to train itself using unlabeled data. Thus, for unsupervised learning, the training data set 1102 will include input data without any associated output data. The untrained neural network 1106 can learn groupings within the unlabeled inputs and can determine how individual inputs relate to the overall data set. Unsupervised training can be used to generate a self-organizing map, which is a type of trained neural network 1107 that can perform operations useful in data dimensionality reduction. Unsupervised training can also be used to perform anomaly detection, which allows identification of data points in the input data set that deviate from the normal pattern of the data.

[0186] Variations of supervised and unsupervised training may also be employed. Semi-supervised learning is a technique in which the training data set 1102 includes a mixture of labeled and unlabeled data of the same distribution. Incremental learning is a variation of supervised learning in which input data is continually used for further training the model. Incremental learning enables a trained neural network 1108 to adapt to new data 1112 without forgetting the knowledge embedded within the network during initial training.

[0187] Whether supervised or unsupervised, the training process for particularly deep neural networks may be too computationally intensive for a single computing node. The training process can be accelerated using a distributed network of computing nodes rather than a single computing node.

[0188] Fig.12is a block diagram illustrating distributed learning. Distributed learning is a training model that uses multiple distributed computing nodes to perform supervised or unsupervised training of a neural network. The distributed computing nodes may each include one or more host processors and one or more general processing nodes, such as Figure 7 A highly parallel general purpose graphics processing unit 700 in FIG. As illustrated, distributed learning can perform model parallelism 1202 , data parallelism 1204 , or a combination of model and data parallelism 1204 .

[0189] In model parallelization 1202, different computing nodes in a distributed system can perform training calculations for different parts of a single network. For example, each layer of a neural network can be trained by different processing nodes of the distributed system. The benefits of model parallelism include the ability to scale to particularly large models. Splitting the calculations associated with different layers of a neural network enables training of very large neural networks, where the weights of all layers will not fit into the memory of a single computing node. In some instances, model parallelism can be particularly useful in performing unsupervised training of large neural networks.

[0190] In data parallelization 1204, different nodes of the distributed network have complete instances of the model, and each node receives a different portion of the data. Then, the results from different nodes are combined. Although different methods for data parallelization are possible, data parallel training methods all require a technique for combining results and synchronizing model parameters between each node. Exemplary methods for combining data include parameter averaging and update-based data parallelization. Parameter averaging trains each node on a subset of the training data and sets global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server that maintains parameter data. Update-based data parallelism is similar to parameter averaging, except that updates to the model are passed instead of passing parameters from the node to the parameter server. In addition, update-based data parallelism can be performed in a decentralized manner, where updates are compressed and passed between nodes.

[0191] For example, the combined model and data parallelism 1206 can be implemented in a distributed system where each computing node includes multiple GPUs. Each node can have a complete instance of the model, with separate GPUs within each node used to train different parts of the model.

[0192] Distributed training has increased overhead relative to training on a single machine. However, the parallel processors and GPGPUs described herein can each implement various techniques for reducing the overhead of distributed training, including techniques for implementing high-bandwidth GPU-GPU data transfer and accelerated remote data synchronization.

[0193] Example Machine Learning Applications

[0194] Machine learning can be applied to solve a variety of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. Applications of computer vision range from reproducing human visual capabilities (such as recognizing faces) to creating new categories of visual capabilities. For example, a computer vision application can be configured to recognize sound waves from vibrations induced in objects visible in a video. Parallel processor-accelerated machine learning enables the use of significantly larger training data sets than previously feasible training data sets to train computer vision applications, and enables the use of low-power parallel processors to deploy inference systems.

[0195] Parallel processor-accelerated machine learning has autonomous driving applications, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on data sets that define appropriate responses to specific training inputs. The parallel processors described herein can enable rapid training of increasingly complex neural networks for autonomous driving solutions and enable the deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0196] Deep neural networks accelerated by parallel processors have enabled machine learning methods for automatic speech recognition (ASR). ASR involves creating a function that computes the most likely speech sequence given a sequence of input sounds. Accelerated machine learning using deep neural networks has been implemented to replace the hidden Markov models (HMMs) and Gaussian mixture models (GMMs) previously used for ASR.

[0197] Parallel processor accelerated machine learning can also be used to accelerate natural language processing. Automatic learning programs can use statistical inference algorithms to produce models that are robust to erroneous or unfamiliar inputs. Exemplary natural language processor applications include automatic machine translation between human languages.

[0198] Parallel processing platforms for machine learning can be divided into training platforms and deployment platforms. Training platforms are typically highly parallel and include optimizations for accelerating multi-GPU single-node training and multi-node multi-GPU training. Exemplary parallel processors suitable for training include Figure 7The highly parallel general purpose graphics processing unit 700 and Figure 8 800. In contrast, deployed machine learning platforms typically include lower-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0199] Fig.13 An exemplary inference system-on-chip (SOC) 1300 suitable for performing inference using a training model is illustrated. The SOC 1300 may integrate processing components, including a media processor 1302, a vision processor 1304, a GPGPU 1306, and a multi-core processor 1308. The SOC 1300 may additionally include an on-chip memory 1305, which may implement a shared on-chip data pool accessible by each of the processing components. The processing components may be optimized for low-power operation to enable deployment to a variety of machine learning platforms, including autonomous vehicles and autonomous robots. For example, an implementation of the SOC 1300 may be used as part of a master control system for an autonomous vehicle. In the case where the SOC 1300 is configured for use in an autonomous vehicle, the SOC is designed and configured to comply with relevant functional safety standards of the deployment jurisdiction.

[0200] During operation, the media processor 1302 and the visual processor 1304 can work in concert to accelerate computer vision operations. The media processor 1302 can enable low latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in the on-chip memory 1305. The visual processor 1304 can then parse the decoded video and perform preliminary processing operations on the frames of the decoded video in preparation for processing the frames using a trained image recognition model. For example, the visual processor 1304 can accelerate convolution operations for CNNs (for performing image recognition on high-resolution video data), while the back-end model calculations are performed by the GPGPU 1306.

[0201] The multi-core processor 1308 may include control logic for facilitating the sequencing and synchronization of data transfers and shared memory operations performed by the media processor 1302 and the vision processor 1304. The multi-core processor 1308 may also act as an application processor for executing software applications that may use the inference computing capabilities of the GPGPU 1306. For example, at least a portion of the navigation and driving logic may be implemented in software executed on the multi-core processor 1308. Such software may directly issue computational workloads to the GPGPU 1306, or may issue computational workloads to the multi-core processor 1308, which may offload at least a portion of those operations to the GPGPU 1306.

[0202] GPGPU 1306 may include a computing cluster, such as a low-power configuration of computing clusters 706A to 706H within a highly parallel general-purpose graphics processing unit 700. The computing cluster within GPGPU 1306 may support instructions that are specifically optimized for performing inference calculations on trained neural networks. For example, GPGPU 1706 may support instructions for performing low-precision calculations (such as 8-bit and 4-bit integer vector operations).

[0203] Specialized hardware for efficient machine learning operations

[0204] The embodiments described herein provide high-level machine learning computation primitives that can be used to abstract many of the underlying computational details of performing machine learning computations. The high-level primitives described herein enable software logic to request high-level machine learning operations while abstracting the underlying implementation details of those operations. For example and in one embodiment, software logic can request a convolution operation using a given set of filters for an image. A single high-level instruction can be executed, which has operands to define input and output buffer addresses and addresses for buffer storage filters and / or kernel data. The GPGPU can then divide the high-level convolution instruction into multiple sub-operations, which are executed by the underlying computational units of the GPGPU. In one embodiment, direct hardware support for one or more subroutines of the basic linear arithmetic subroutines (BLAS) is provided, although embodiments can provide hardware support for other libraries of subroutines. The compiler logic and associated runtime library can compile source code that utilizes supported high-level computational subroutines and output compiled source code that calls the machine learning macroinstruction unit.

[0205] Machine learning acceleration logic with custom coarse-grained pipelining

[0206] Fig.1414 is a block diagram of a data processing system 1400 according to an embodiment. The data processing system 1400 is a heterogeneous processing system having a processor 1402, a unified memory 1410, and a GPGPU 1420 including machine learning acceleration logic. The processor 1402 and the GPGPU 1420 may be any of the processors and GPGPU / parallel processors described herein. The processor 1402 may execute instructions for a compiler 1415 stored in a system memory 1412. The compiler 1415 is executed on the processor 1402 to compile a source code 1414A into a compiled code 1414B. The compiled code 1414B may include code that may be executed by the processor 1402 and / or code that may be executed by the GPGPU 1420. During compilation, the compiler 1415 may perform operations to insert metadata, including hints about the level of data parallelism present in the compiled code 1414B and / or hints about data locality associated with threads that will be dispatched based on the compiled code 1414B. Compiler 1415 may include the necessary information to perform such operations, or may perform these operations with the aid of runtime library 1416. Runtime library 1416 may also facilitate compiler 1415 in the compilation of source code 1414A, and may also include instructions that are linked with compiled code 1414B at runtime to facilitate execution of the compiled instructions on GPGPU 1420.

[0207] Unified memory 1410 represents a unified address space that can be accessed by processor 1402 and GPGPU 1420. Unified memory includes system memory 1412 and GPGPU memory 1418. GPGPU memory 1418 includes GPGPU local memory 1434A-1434B within GPGPU 1420, and may also include some or all of system memory 1412. For example, compiled code 1414B stored in system memory 1412 may also be mapped into GPGPU memory 1418 for access by GPGPU 1420.

[0208] GPGPU 1420 includes a plurality of computing blocks 1424A-1424N, which may be Figure 2A1424N。GPGPU 1420 also includes a set of registers 1425, cache memory 1427 and power and performance module 1426, which can be used as a shared resource for computing blocks 1424A-1424N. In one embodiment, registers 1425 include directly and indirectly accessible registers, wherein the indirectly accessible registers are optimized for use in sparse matrix computing operations. Power and performance module 1426 can be configured to adjust the power delivery and clock frequency for computing blocks 1424A-1424N, thereby power-gating idle components within computing blocks 1424A-1424N under heavy workloads. GPGPU 1420 includes GPGPU local memory 1434A-1434B, which is a physical memory module that shares a graphics card or multi-chip module with GPGPU 1420.

[0209] In one embodiment, the GPGPU local memory 1434A-1434B resides in the hybrid memory module 1430. The hybrid memory module 1430 includes a set of compute and memory controller units 1432A-1432B that provide both memory controller and compute functionality. The compute and memory controller units 1432A-1432B include logic modules that can perform near-data compute operations on data directly within the GPGPU local memory 1434A-1434B. The compute and memory controller units 1432A-1432B can receive direct scheduling of memory-bound operations from the machine learning scheduler controller 1422 or can receive offloads of these operations from the sparse compute accelerator unit 1423 or the compute blocks 1424A-1424B. In one embodiment, the compute and memory controllers 1432A-1432B include compute logic that is capable of performing a subset of the compute operations that can be performed by the compute blocks 1424A-1424N. For example and in one embodiment, the compute and memory controller units 1432A-1432B, in addition to performing operations required for memory controller operations, may also be configured to perform a subset of compute operations that are particularly useful for significantly memory bound operations, or operations where memory bandwidth is more deterministic for performance than compute throughput. In one embodiment, the compute logic of the compute and memory controller units 1432A-1432B may be a processor having a different instruction set relative to the instruction set supported by the compute blocks 1424A-1424N. In one embodiment, the hybrid memory module 1430 is implemented via 3D stacking technology so that the GPGPU local memory 1434A-1434B can be vertically stacked on top of the compute / memory controller units 1432A-1432B, which are coupled via high bandwidth through-silicon interconnects. The high bandwidth connection between the compute and memory controller units 1432A-1432B and the GPGPU local memory 1434A-1434B can enable memory binding operations to be efficiently performed within the hybrid memory module 1430 using lower power compute units, as opposed to cycling large amounts of data into and out of the cache 1427 from the GPGPU local memory 1434A-1434B for processing via the compute blocks 1424A-1424N.

[0210] In one embodiment, support for near data compute offloading is implemented via extensions to the ISA supported by compute blocks 1424A-1424N. In one embodiment, support for near data compute offloading is firmware implemented logic executed by machine learning scheduler controller 1422. Prior to performing near data compute operations, for example, via a near data compute kernel, a set of virtual addresses to be accessed by a near data compute kernel may be translated into physical addresses recognizable by compute and memory controller units 1432A-1432B. Address translation may be performed for a kernel before it is dispatched or offloaded to a compute memory controller unit 1432A-1432B.

[0211] In one embodiment, GPGPU 1420 includes machine learning acceleration logic, which includes a machine learning instruction acquisition and decoding unit 1421, a machine learning scheduler controller 1422, and a sparse computing accelerator unit 1423. The machine learning instruction acquisition and decoding unit 1421 is an acquisition and decoding unit that includes logic for acquiring and decoding machine learning instructions that define complex, customizable behaviors. The instructions can be sequenced and / or serialized via the machine learning scheduler controller 1422 to be executed via one or more of the computing blocks 1424A-1424N. In one embodiment, the machine learning scheduler controller 1422 is an ASIC that can be configured to perform advanced scheduling operations. In one embodiment, the machine learning scheduler controller 1422 is a microcontroller or a low-energy per-instruction processing core capable of executing instructions loaded from a firmware module.

[0212] In one embodiment, some functions to be performed by computational blocks 1424A-1424N may be directly scheduled or offloaded to a sparse computational accelerator unit 1423. The sparse computational accelerator unit 1423 includes processing element logic configured to efficiently perform computational operations on sparse matrices. In one embodiment, the sparse computational accelerator unit 1423 is configured to perform matrix multiplication for a neural network having sparse weight values. In one embodiment, the sparse computational accelerator unit 1423 is an application specific integrated circuit that is explicitly configured to perform parallel matrix multiplication operations where one or more operands are sparse or very sparse matrices. In one embodiment, the sparse computational accelerator unit 1423 is a field programmable gate array (FPGA) that provides fixed function logic that can be updated between workloads.

[0213] Fig.15ADetails of the machine learning instruction and acquisition unit 1421 according to an embodiment are illustrated. In one embodiment, the machine learning instruction acquisition & decoding unit 1421 includes a cache memory 1502, a machine learning instruction acquisition unit 1504, and a machine learning instruction decoding unit 1506. The machine learning instruction acquisition unit 1504 can acquire one or more machine learning macroinstructions and store the macroinstructions in the cache memory 1502. The machine learning instruction decoding unit 1506 can decode the machine learning macroinstructions and determine a set of operations to be performed in response. In one embodiment, the machine learning instruction acquisition and decoding unit 1421 includes a microcontroller 1510 to implement complex operations, such as selecting one of multiple techniques to perform a specific machine learning operation, such as a convolution operation. The microcontroller 1510 can also determine whether to perform operations for the macroinstructions via programmable logic within the GPGPU or via dedicated machine learning logic within the GPGPU.

[0214] In one embodiment, the microcontroller 1510 can load firmware logic from the machine learning firmware module 1508 to define the operations to be performed in response to the machine learning macroinstructions. In one embodiment, the machine learning firmware module 1508 can be updated via the driver logic of the GPGPU to expand the set of operations supported via the machine learning macroinstructions and / or expand the capabilities of the supported macroinstructions. In one embodiment, the microcontroller 1510 implements explicit support for convolution operations or other matrix or neural network related operations via the machine learning acceleration logic 1516.

[0215] The calculations for a CNN include applying a convolution mathematical operation to each filter to produce the output of that filter. Each filter is a kernel with trainable weights that is convolved across the width and height of the input volume to compute the dot product between the filter's entry and the input at any location. When the filter is convolved on the input volume, a two-dimensional activation map is generated to indicate the filter response at each spatial location. An activation map is generated for each filter applied to the input volume. The filter size used within a CNN can vary based on the implementation details of the neural network.

[0216] In one embodiment, parameter analysis logic 1512 may analyze the parameters of a requested convolution operation. A convolution operation has two inputs, input data and a convolution filter. The input data includes a set of H x WThe convolution filter has R rows and S columns. In one embodiment, the parameter analysis logic 1512 determines whether to perform at least a portion of the convolution via dedicated convolution logic based on the size of the convolution filter R x S, for example, if the size of the convolution filter indicates that the convolution will be performed less efficiently via the GPGPU programmable logic. In one embodiment, based on the convolution parameters including the size of the convolution filter, the input image or feature map dimensions, and the current operating metrics of the GPGPU, the machine learning acceleration logic 1516 can select an algorithm to use to perform the requested convolution operation.

[0217] For example, the machine learning acceleration logic 1516 can be configured to select one of several possible algorithms to implement convolution. In one embodiment, convolution is performed via convolution based on fast Fourier transform (FFT). FFT convolution uses the following principle, that is, multiplication in the frequency domain corresponds to convolution in the time domain. Thus, the Fourier transform of the convolution of two functions is the product of the Fourier transforms of those functions. The input data can be transformed into the frequency domain by using a discrete Fourier transform (DFT), multiplied by the frequency response of the filter, and then transformed back into the time domain by using an inverse DFT. For example and in one embodiment, for convolution using a small filter size (e.g., 1x1, 3x3), Winograd's minimum filtering algorithm can be used to perform convolution. Larger filter sizes (e.g., 4x4) can be performed via other FFT algorithms. Convolution for even larger filter sizes (5x5, 7x7) can be performed via specialized fixed-function convolution hardware. Alternatively, direct convolution may be performed in the original domain of the data by using batched matrix operations via hardware acceleration of the general matrix-to-matrix multiplication (GEMM) subroutine.

[0218] Fig. 15BDetails of a machine learning scheduler controller according to an embodiment are illustrated. In one embodiment, the machine learning scheduler controller 1422 includes a microcontroller 1520, which is configured to execute instructions or commands to implement machine learning scheduling and task management logic 1526. The machine learning scheduling and task management logic 1526 can facilitate the scheduling and preemption of various pipeline commands and instructions that implement the complex machine learning acceleration operations described herein. The machine learning scheduling and task management logic 1526 can be implemented via instructions stored in the machine learning scheduler firmware module 1518. The instructions stored in the machine learning scheduler firmware module 1518 can be updated in the field to achieve the enhancement and expansion of the capabilities of the machine learning scheduler controller 1422. The machine learning scheduler controller 1422 may additionally include an interrupt controller 1519 to enable the machine learning scheduler controller 1422 to receive and process interrupts from computing elements within a general-purpose graphics processor. Although the machine learning scheduler controller 1422 is illustrated as including a microcontroller 1520, in one embodiment, the machine learning scheduling controller is implemented via an FPGA module embedded in a GPGPU.

[0219] Fig.16 An exemplary convolution operation according to an embodiment is illustrated. An input volume buffer 1604 represents a 2D channel of input data. Although a 2D convolution is illustrated, convolution can also be performed on a three-dimensional input volume by using a three-dimensional filter. A receptive field map tile 1602 highlights a portion of the input volume. A dot product is performed between the data within the receptive field map tile 1602 and the convolution filter to generate data points within the output buffer 1606. The combination of data points within the output buffer 1606 represents an activation map generated by the convolution. Each point within the activation map is generated by sliding the receptive field map tile across the input volume buffer 1604. The activation map data can be input to an activation function to determine an output activation value.

[0220] In one embodiment, convolution of the input volume buffer 1604 is performed via a set of high-level matrix operations 1605. The high-level matrix operations may be performed via primitive operations, such as BLAS operations, which are accelerated via macro instructions, which may be decoded via the machine learning instruction fetch and decode unit 1421. The machine learning instruction fetch and decode unit 1421 may dispatch operations to the machine learning scheduler controller 1422 for scheduling. The operations may then be dispatched to one or more compute blocks 1424A-1424N. The compute blocks 1424A-1424N may communicate with the hybrid memory module 1430 to store data in local graphics memory. The compute blocks 1424A-1424N may also offload memory intensive operations to near data compute processors within the hybrid memory module 1430. In one embodiment, the machine learning scheduler controller 1422 may dispatch compute operations directly to the hybrid memory module 1430.

[0221] Fig.17 1700 is a flow chart of logic 1700 for performing coarse-grained scheduling of machine learning operations for a computational pipeline according to an embodiment. Figure 14-Figure 1 5 and the hardware within the machine learning instruction acquisition and decoding unit 1421 and the machine learning scheduler controller 1422 implement logic 1700. Logic 1700 can acquire machine learning computation instructions and decode them for execution within the GPGPU, as shown at box 1702. The machine learning instructions are instructions that specify a set of multiple operations to be performed by the computational pipeline within the graphics processor described herein. The machine learning instructions are decoded into decoded machine learning instructions associated with a set of machine learning related operations. The decoded machine learning instructions enable the GPGPU to perform complex machine learning operations via the computational units and processing elements of the general purpose graphics processor.

[0222] The logic 1700 may determine a set of pipeline commands to be executed to execute the decoded machine learning instruction, as shown at block 1704. For example, the parameter analysis logic 1512 of FIG. 15 may determine the type or subtype of machine learning operation to be performed for the instruction, while the machine learning acceleration logic 1516 may determine the exact set of operations to be performed to execute the decoded machine learning instruction. For example and in one embodiment, the logic 1700 may determine that the machine learning instruction is a convolution instruction for processing a CNN. The machine learning acceleration logic 1516 may then determine the required operations to be performed to implement a specific convolution implementation, as well as a specific set of pipeline commands that may be used to implement such operations. For example, the set of operations may be a batch of matrix multiplication primitive operations that will be performed to perform convolution operations across a set of matrices.

[0223] Based on the pipeline command set determined at block 1704, the logic 1700 may schedule the pipeline command set to the computation pipeline of the general processing unit across a set of computation blocks, thereby enabling execution of the decoded machine learning instructions, as shown at block 1706. The logic 1700 may schedule the pipeline command set to the computation pipeline of the general processing unit across a set of computation blocks, as shown at block 1706. Fig.14 The machine learning scheduler controller 1422 of FIG. 15 can be used to schedule pipeline command sets. Scheduling can include scheduling various commands or associated instructions to various computing elements within the computing pipeline. The command can be implemented as a computational block (e.g., Fig.14 The instructions may also be executed as instructions executed by computing elements within computing blocks 1424A-1424N. Fig.14 Alternatively, the command or instruction executed via the computational block may trigger offloading of secondary instructions or commands to one or more of the sparse computational accelerator unit 1423 and the hybrid memory module 1430 based on the type of operation to be performed. As shown at block 1708, the logic 1700 may then retire the decoded machine learning instructions in response to completion of the pipeline command set scheduled at block 1706.

[0224] Machine Learning Acceleration Using Near Data Computing

[0225] Near data computing is a computing paradigm that can be implemented on a processing system in which a subset of processing elements within the system are configured to have significantly higher memory bandwidth relative to other computing systems within the system. The performance of memory-bound operations can be significantly improved by performing such operations on computing elements that are "close" to the data in memory, even though the near data computing elements are less complex than other computing elements. In some embodiments, near data computing is achieved by enhancing the memory controller logic with the ability to perform at least a subset of the computing operations supported by the main computing elements within the system. In one embodiment, near data computing is achieved by augmenting the memory controller with an efficient, low-power processor core that provides a near data computing ISA. The low-power processor core can receive instructions from a scheduler unit and / or receive instructions from other computing elements within a general-purpose graphics processor unit. In one embodiment, the near data computing paradigm can be particularly useful for executing or accelerating sparse matrix operations with low arithmetic intensity.

[0226] Fig.18 1 is a block diagram illustrating a hybrid memory computing system 1800 according to an embodiment. In one embodiment, the hybrid memory computing system 1800 illustrates Fig.141430, which includes computing and memory controller units 1432A-1432B and GPGPU local memory 1432A-1432B. In the illustrated hybrid memory computing system 1800, the hybrid memory module 1430 additionally includes a control processor 1802 and a main memory controller 1805. The control processor 1802 and the main memory controller 1805 can work in conjunction with the DMA controller 1803 to implement DMA memory transfers of data to, from, and between modules of the GPGPU local memory 1434A-1434B.

[0227] In one embodiment, the control processor 1802 receives a request for an incoming compute operation 1801 to be satisfied by compute logic within one or more of the compute and memory controller units 1432A-1432B. The control processor 1802 can then dispatch the compute operation to the appropriate compute and memory controller unit 1432A-1432B based on the address set to be accessed by the compute operation. The compute operation can be received in the form of a near data compute kernel. In one embodiment, the memory address accessed by the near data compute kernel to be executed on the compute and memory controller unit 1432A-1432B is converted from a virtual address to a physical address before the kernel is received at the hybrid memory module 1430, because the compute and memory controller units 1432A-1432B are partitioned based on physical addresses, with different units associated with different address ranges. In one embodiment, in situations where compute operations are to be performed on a set of physical addresses handled by multiple memory controllers, the DMA controller 1803 may be used to transfer data associated with an address range from different modules of GPGPU local memory 1434A-1434B to a single module, where at least a portion of the data is stored in one or more cache memories 1806A-1806B within the main memory controller 1805. The compute and memory controller units 1432A-1432B may then perform the desired arithmetic operations on the data stored in the cache memories 1806A-1806B, which may then be ejected back to the GPGPU local memory 1434A-1434B.

[0228] For memory access operations, the main memory controller 1805 can receive incoming memory operations 1807, routing the memory operations to the appropriate compute and memory controller units 1432A-1432B based on the physical address to be accessed. When a request is received for an address range that crosses the physical address boundary that divides multiple compute and memory controller units 1432A-1432B, multiple memory requests can be dispatched and serviced in parallel. The compute and memory controller units 1432A-1432B can exchange data between associated modules of the GPGPU local memory 1434A-1434B and a set of buffers managed by the DMA controller 1803. For example and in one embodiment, for read and write operations, DMA operations can be configured by the DMA controller 1803 to transfer data from the GPGPU local memory 1434A-1434B via the I / O buffers 1804.

[0229] Although separate interfaces are illustrated for incoming compute operations 1801 and incoming memory operations 1807, in one embodiment a unified memory and compute interface is provided in which memory access commands are a subset of compute operations. For example, a load or store operation may be received by the control processor 1802. The load or store command may then be executed by the main memory controller. In such an embodiment, complex memory accesses, such as scatter / gather operations, may be performed directly via the hybrid memory computing system 1800.

[0230] In one embodiment, hybrid memory module 1430 is implemented as a hybrid memory cube where GPGPU local memories 1434A-1434B are stacked on top of a logical layer that includes compute and memory controller units 1432A-1432B, control processor 1802, and main memory controller 1805. However, embodiments are not limited to a hybrid memory cube implementation as hybrid memory module 1430 may be implemented via any memory system having one or more memory controllers capable of performing arithmetic operations.

[0231] The computational and processing elements of the general purpose graphics processing unit described herein may include various types of arithmetic logic units, including floating point and integer logic units. Large arrays of such processing units may be included in a graphics processing unit such as Fig.14 In the computational blocks 1424A-1424N of the GPGPU 1420 in FIG. A smaller array of such processing units may be included in, for example, Fig.14 and Fig.18 The computation and memory controller units 1432A-1432B shown in .

[0232] The memory bandwidth between the memory and the compute elements remains nearly constant regardless of the memory capacity due to the pin count limit per chip. Such bandwidth limitations may introduce scalability issues for memory intensive workloads such as neural network training. Scaling issues may become particularly exacerbated when training sparse neural networks. Training sparse neural networks is not arithmetic intensive, but may be severely limited by memory bandwidth in the absence of specialized hardware tailored for operations on sparse neural networks. The general purpose graphics processing unit provided by the embodiments described herein includes a sparse computational accelerator unit, such as a Fig.14 The sparse computing accelerator unit 1432 is configured as follows: Figure 21-22 The training of sparse neural networks can also be efficiently performed by using the near-data computing resources provided by the hybrid memory module 1430.

[0233] An example of sparse conjugate gradient pseudocode is shown in Table 5.

[0234] Table 5 - Sparse conjugate gradient pseudocode

[0235] 0 for(....){ 1 for(cow = 0; cow < 8; cow++ ){ 2 for(kcol = 0; kcol < 8; kcol++ ){ 3 a[node[krow] + node[kcol]*n] += coeff * em[krow+kcol*8]; 4 } 5 } 6 }

[0236] The pseudo code execution illustrated in Table 5 is applicable to the sparse conjugate gradient of sparse matrix system. The trip count for the two innermost loops (iteration by "know" and "kcol") is usually small. Therefore, any parallelization or vectorization that can be performed will be more effective when applied to the outermost loop. The operation performed in row 3 causes indirect load / store (such as gathering / scattering in vector code) and has very few calculations present in the innermost loop, and it can be more efficient to unload the calculations performed in the two innermost loops to the near data calculation processor in the memory controller. The unloading of near data calculation operations can be performed in a similar manner to unloading calculation operations from a general-purpose processor (such as a CPU) to a GPU. However, instead of unloading calculation operations across devices, near data calculation unloading will unload calculation operations to the computing resources in the memory controller, because the computing resources in the memory controller will have a significantly higher communication bandwidth to the memory.

[0237] Table 6 below illustrates the checker and executor kernels that can be used to implement near-data computation offloading.

[0238] Table 6 - Verifier and Executor Kernels

[0239] 0 for(....){ 1 / / Checker pins physical memory page, encapsulates physical address 2 inspector_kernel(...); / / Execute data copy from host to device 3 / / Execute by the memory controller(s) to the executor - note that the data may already be 4 / / Partitioned across multiple memory controllers by the checker core 5 <<<executor_kernel(...)> >> / / Kernel call 6 }

[0240] As shown in Table 6, the checker pins the physical memory page and packs the physical memory address. Then the executor kernel is called on the device. The operation performed by the checker is similar to the data copy from the host to the device in the CUDA high-level parallel programming language. The executor kernel call can be analogized to the CUDA kernel call.

[0241] Table 7 illustrates an exemplary checker kernel.

[0242] Table 7 - Verifier Kernel

[0243] 0 my_inspector_kernel(addr_a, addr_em,...){ 1 for(cow = 0; cow < 8; cow++ ){ 2 for(kcol = 0; kcol < 8; kcol++ ){ 3 / / Download the page and calculate / pack the physical address 4 get_pa(&a[node[krow]+node[kcol]*n], pa_addr_a, mem_ctrl_id_a); 5 addr_a[mem_ctrl_id].append(pa_addr_a); 6 get_pa(&em[krow+kcol*8], pa_addr_em, mem_ctrl_id_em); 7 / / If the physical address is handled by a different memory controller 8 / / DMA and bring all data to main memory controller 9 if(mem_ctrl_id_a == mem_ctrl_id_em){ 10 / / Here because mem_ctrl_a handles, stores and loads 11 / / The rest of the loaded data is passed to its memory area 12 pa_addr_em = dma_pa(buff[mem_ctrl_id_a], pa_addr_em); 13 } 14 addr_em[mem_ctrl_id].append(pa_addr_em); 15 } 16 } 17 }

[0244] The checker core determines the relevant physical memory addresses that will be accessed by the calculations shown in Table 5. Those addresses are then pinned and packaged into data structures. If the physical addresses are handled by different memory controllers, DMA can be performed to move the data to the main memory controller, which is the memory controller that will perform the calculations.

[0245] Table 8 illustrates an exemplary executor kernel.

[0246] Table 8 - Example Executor Kernels

[0247] 0 my_executor_kernel(my_addr_a, my_addr_em, coeff){ 1 / / Each memory controller handles addresses near it 2 / / my_addr_a is addr_a[mem_ctrl_id] etc. 3 for(i=0; i<len(my_addr_a);i++){ 4 *(my_addr_a) += coeff * *(my_addr_em); 5 } 6 }

[0248] As shown in Table 8, the executor function accepts two types of variables: 1) those variables calculated / prepared by the checker kernel / function (e.g., addresses) and 2) variables passed from the original kernel and used by the checker (e.g., coefficients). Variables passed from the original kernel are called live-in values. The executor receives a series of variables going to the near memory calculation function, including live-in values ​​(e.g., coefficients) and addresses (my_addr_a, my_addr_em). The embodiments described herein provide support for heterogeneous processing ISAs that implement offloading between processors. The executor kernel can be encapsulated within a function to implement kernel offloading. The offload calls provided by the heterogeneous processing ISA can be used to offload calculations from general-purpose computing elements within a GPGPU to near memory computing elements.

[0249] 19A-19B are flow charts illustrating logic for performing near data computing operations via embodiments described herein. Fig.19A Logic 1900 is illustrated for marking workloads that may be optimally executed via near-data compute logic. Fig.19B Logic 1910 for dispatching near data computing workloads to a memory controller having computing logic is illustrated. In various embodiments, the illustrated logic 1900, 1910 may be provided by software or hardware units within a data processing system as described herein, such as, but not limited to, Fig.14 The data processing system 1400 in FIG.

[0250] like Fig.19A As shown in FIG. 1 , one embodiment provides logic 1900 implemented via a data processing system that includes compilation logic to compile a GPGPU workload for execution, as shown at block 1902. The compilation logic may be provided by a compiler and one or more compile time and / or runtime libraries, such as Fig.14 1415 and runtime library 1416 in. During or after compilation performed at block 1902, logic 1900 may profile the workload to determine the computational and memory complexity of the workload, as shown at block 1904. The workloads most suitable for near data computation are those with high memory access complexity and low arithmetic or computational complexity. For example, the sparse conjugate gradient workload shown in Table 5 performs a limited number of mathematical operations (e.g., multiplication, addition), and the memory access pattern is complex. For workloads with low computational complexity and high memory access complexity, as determined at block 1905, logic 1900 may mark those workloads for near data computation, as shown at block 1908. For data with high computational complexity and / or low memory access complexity, logic 1900 may mark the workload for execution on the primary computational resources of the GPGPU.

[0251] In one embodiment, marking a workload may be performed by a marking hint or metadata information associated with the workload. For example and in one embodiment, the compiled data for the compute kernel within the workload may have a processor hint or metadata that identifies the compute kernel as a near data compute kernel. In one embodiment, the near data compute kernel may be directly scheduled to the compute logic within the compute and memory controller units 1432A-1432B described herein. In one embodiment, the workload is scheduled to the compute blocks 1424A-1424N described herein and may be offloaded to the near data compute resources at runtime.

[0252] like Fig.19BAs shown in , one embodiment provides logic 1910 implemented via a data processing system, the data processing system including workload execution logic to load near data computing workloads for execution on a GPGPU, as shown at block 1912. In one embodiment, the workload is a parallel computing kernel (e.g., an executor kernel as in Table 8), for which multiple instances are executed via parallel processing logic. At block 1914, logic 1910 may check a set of memory addresses to be accessed by the workload. In the case where the GPGPU hardware and programming model implementation uses virtual memory addresses, as determined at block 1915, logic 1910 may convert the virtual address into a physical address, as shown at block 1916. In one embodiment, for example, in the case where the data to be accessed is sparse, the set of physical addresses to be accessed may be encapsulated into a data structure. Logic 1910 may also determine one or more memory controllers associated with the physical address. The memory to be accessed may span multiple memory areas controlled by multiple memory controllers. If the accessed memory is controlled by multiple memory controllers, as determined at block 1919 , the logic 1910 may configure the DMA operation to transfer data to a memory region controlled by a single memory controller, as shown at block 1920 .

[0253] In various embodiments, different approaches to memory merging may be implemented to minimize the amount of data transfers or to minimize latency associated with any data transfers that will be performed prior to near memory computations. For example and in one embodiment, data is transferred to a memory region associated with a primary set of loads and stores to be performed by the workload, as shown in Table 7. When the data set is properly located, logic 1900 may dispatch the workload to a memory controller. Logical operations and memory accesses for the workload may then be performed within the memory controller. In one embodiment, instead of performing a Fig.19B As shown in the pseudo code listed above to merge data within a single memory region, in some instances, the logical operations can be divided among the memory controllers. For example, certain perfectly parallel workloads can be partitioned and executed simultaneously on multiple memory controllers.

[0254] The computational logic implemented within the compute and memory controller units 1432A-1432B described herein may vary across embodiments. In one embodiment, an architecturally simple and low-power compute unit may be incorporated into each memory controller, and the ISA of the GPGPU is extended to enable a specific subset of operations to be scheduled or offloaded to the memory controller for near data computation. In one embodiment, the memory controller logic may include ALU and / or FPU logic 2000 configured to perform parallel fused multiply-add operations, such as Fig. 20 as shown in .

[0255] Fig. 20 The exemplary multiply-add logic 2001 is generally described with respect to floating point operations. However, the logic 2001 is configured to selectively perform integer and fixed point operations. The multiply-add operation can be performed on multiple data elements in the same number of clock cycles as a single multiplication on unpacked data. The multiply-add logic accepts multiple inputs, including source 1 [63:0] 2031, source 2 [63:0] 2033, and enable 2080. Operation control 2002 processes input control signals for the multiply-add logic 2001 and provides an enable 2080 input to activate the multiply-add logic 2011. The multiply-add logic 2001 includes four 16×16 multiplier circuits (e.g., 16×16 multiplier A 2010A, 16×16 multiplier B 2010B, 16×16 multiplier C 2010C, 16×16 multiplier D 2010D). The 32-bit intermediate results generated by the 16×16 multiplier A 2010A and the 16×16 multiplier B 2010B are received by the adder 2020A, while the 32-bit intermediate results generated by the 16×16 multiplier C 2010C and the 16×16 multiplier D 2010D are received by the adder 2020B. The output of the adder 2020B (i.e., bits 31 to 0 of the result) and the output of the adder 2020A (i.e., bits 63 to 32 of the result) are combined into a 64-bit result and transmitted to the result register 2030. In one embodiment, each of the adder 2020A and the adder 2020B consists of four 8-bit adders with appropriate propagation delays. However, alternative embodiments may implement the adders 2020A-2020B in any number of ways (e.g., two 32-bit adders and / or redundant arithmetic compression circuits).

[0256] Idle computing acceleration

[0257] Sparse matrix operations are commonly found in many application areas, including machine learning. Therefore, optimizations to hardware to achieve more efficient processing of sparse matrix operations can be of particular use in GPGPU hardware optimized for machine learning operations. Sparse matrix data sets can have a skewed distribution of non-zeros, where a portion of the matrix is ​​sparse, with a reasonable number of non-zeros per column or row, and the rest of the matrix is ​​very sparse, with only a few non-zeros per column or row, or super-sparse, with the entire row or column being empty. In super-sparse matrices, the number of non-zeros can be less than the number of rows and columns in the matrix. The skewed distribution can arise from natural graphs that follow a power law distribution, with a few popular nodes with many edges to other nodes and many other nodes with only a few edges. In machine learning data sets, matrix columns and rows represent features and samples, respectively, some of which appear more frequently than other features, resulting in skewed non-zeros across columns.

[0258] Embodiments described herein provide a hardware accelerator architecture that can improve the processing efficiency of GPGPU hardware when processing skewed sparse matrix data. Fig.14 The hardware accelerator architecture is implemented in the sparse computing accelerator unit 1423 of FIG. Figure 21-22 The elements of the sparse computing hardware accelerator architecture are shown in FIG.

[0259] Fig.21 The sparse computing accelerator architecture 2100 according to one embodiment is illustrated. In one embodiment, the sparse computing accelerator architecture 2100 is configured to operate on an arbitrarily large set of input data (e.g., matrices, vectors) that resides in an external (e.g., off-chip) memory, such as Fig.14 In one embodiment, the sparse computing accelerator architecture 2100 can also operate directly on data stored in high-bandwidth non-volatile memory, such as 3D XPoint or Nano-RAM. The sparse computing accelerator architecture 2100 can independently communicate with the memory to read input data and write back the calculation results without using the main computing resources within the host GPGPU.

[0260] In one embodiment, the sparse computing accelerator architecture 2100 includes a sparse computing accelerator unit 1423 and Fig.14 The machine learning scheduler controller 1422 may include a sparse prefetch unit 2130 configured to prefetch addresses containing non-zero values ​​of a sparse matrix. Prefetching a limited number of non-zero values ​​of the sparse matrix and storing them in the prefetch buffer and cache memory of the sparse computing accelerator architecture 2100 may trigger page faults for any virtual memory addresses that do not reside in physical memory. Pre-triggering page faults will reduce access latency for the prefetched addresses, even if the data associated with those addresses is not stored in the cache memory within the sparse computing accelerator architecture 2100 when the memory addresses are accessed by the computing kernels executing on the architecture.

[0261] In one embodiment, the sparse prefetch unit 2130 is coupled to the data management unit 2120 within the machine learning scheduler controller 1422. In one embodiment, the data management unit 2120 includes a read unit and a write unit, wherein the read unit includes a processing element (PE) scheduler 2121, an NxN comparator 2122, and a read buffer 2123. In one embodiment, the write unit includes a write buffer 2124, although the write unit may include other components in various embodiments depending on the target use case of the sparse computing accelerator architecture 2100. In addition, although the data management unit 2120 is illustrated as a component of the machine learning scheduler controller 1422, not all embodiments are limited to such a configuration, as the data management unit 2120 may be a module separate from the machine learning scheduler 1422 and / or may be integrated into the hardware logic of the sparse computing accelerator unit 1423.

[0262] In one embodiment, the sparse computing accelerator unit 1423 includes a plurality of processing elements (eg, PEs 2110A-2110N). In one embodiment, the processing elements 2110A-2110N may each include Fig. 20 The ALU and / or FPU logic 2000 of the processor may be similar to the logic of the processor 2100, and may be configured to process vector operands of SIMD operations. In one embodiment, processing element 2110A-2110N includes input buffer and unpacking unit 2111A-2111N, random access memory 2112A-2112N and output buffer 2113A-2113N. The buffer in processing element 2110A-2110N may be a static random access memory buffer, and RAM 2112A-2112N may be any random access memory described herein, including static or dynamic RAM. Input buffer and unpacking unit 2111A-2111N support dense matrix format, compressed sparse matrix format and other sparse matrix format optimization, such as unique value compression. The processing elements 2110A-2110N may include multiply-add logic including multipliers and adders as described herein, wherein the multiply and add logic may be configured to perform fused or combined multiply-add operations. The multiply and add logic may be configured to accept inputs from RAM 2112A-2112N or from external memory via input buffers and unpacking units 2111A-2111N. The output may be written to a sum register or RAM 2112A-2112N. The data stored in RAM 2112A-2112N or output buffers 2113A-2113N may be output to a write buffer 2124 within the data management unit 2120.

[0263] Although there are hardware architecture solutions for accelerating matrix and vector operations, such architecture solutions do not support matrix and vector operations for machine learning algorithms operating on sparse data sets (e.g., text), such as multiplication of sparse vectors, support for both row-oriented and column-oriented matrix data formats, and scaling & update operations. The sparse computing accelerator architecture 2100 described herein supports both row-oriented and column-oriented matrix data formats, as well as other commonly used matrix and vector operations supported by existing accelerators. For example, one embodiment provides a sparse computing accelerator architecture 2100, which is configured to efficiently perform operations, including multiplication (matrix, vector) operations in both row-oriented and column-oriented formats for any combination of sparse or dense matrices and sparse or dense vectors (e.g., sparse matrices, sparse vectors; sparse matrices, dense vectors; dense matrices, sparse vectors; dense matrices, dense vectors). The sparse computing accelerator architecture 2100 may additionally support vector dot product operations (e.g., vector, vector), including sparse vector, sparse vector; sparse vector, dense vector; and dense vector, dense vector operations. The sparse computing accelerator architecture 2100 may additionally support scaling and updating (ScaleAndUpdate) operations with sparse matrix, dense vector operands. The sparse computing accelerator architecture 2100 is generally intended to operate on large matrix data, where performance is typically limited by the memory bandwidth available to access such data. Therefore, the accelerator architecture has been designed to scale and fully utilize all available memory bandwidth. In one embodiment, the available memory bandwidth is increased by implementing the sparse computing accelerator architecture 2100 as a near data computing architecture, such as in Fig.18 The hybrid memory computing system 1800 is maximized as described above.

[0264] The key challenge presented to the development of sparse matrix vector accelerator is the development of logic for reducing the waiting time associated with random and / or irregular access to dense vectors.When dense vectors are in memory, random and / or irregular access may cause performance problems.For example, access may require the execution of gathering or scattering operations to write or read irregular patterned data to and from memory.In order to solve such problems, accelerator as described herein is configured to be blocked so that the dense vector corresponding to each matrix block is suitable for operation on the matrix data in PE RAM.During operation, sparse computing accelerator unit 1423 can send non-zero matrix data stream to processing element for processing against the vector data stored in the internal RAM 2112A-2112N of each processing element 2110A-2110N.Random access to stored vector data is performed on the local RAM 2112A-2112N inside the processing element 2110A-2110N, thereby avoiding irregular access to memory during the execution of computing workload.

[0265] Fig. 22 An additional sparse computing architecture 2200 for sparse matrix operations according to an embodiment is illustrated. One embodiment provides a heterogeneous architecture that implements efficient processing of skew matrices containing sparse matrix blocks and very sparse and / or super sparse matrix blocks. Input matrix data 2202 stored in a memory is read by a matrix partitioning module 2210, which outputs a set of sparse blocks 2220 and, if present, a set of very sparse or super sparse blocks 2222. Sparse blocks 2220 are stored in a memory 2230 optimized for raw bandwidth, while very sparse or super sparse blocks 2222 are stored in a memory 2232 optimized to achieve low latency for short bursts of parallel access. Various types of memory 2230, 2232 are coupled to the computing resources of the sparse computing architecture 2200 via interconnect 2233.

[0266] In some embodiments, the computing resources of the sparse computing architecture 2200 include sparse computing tiles 2234 and very / super sparse computing tiles 2236. A set of schedulers 2235 is configured to schedule tasks for execution on the sparse computing tiles 2234 and very or super sparse computing tiles 2236. The sparse computing tiles 2234 may include Fig.14 and Fig.21The elements illustrated in the sparse computing accelerator unit 1423 of the present invention are shown in Figure 1424, except that in one embodiment the data management unit (DMU) is integrated into the sparse computing tile 2234 instead of the machine learning scheduler controller 1422. The non-zero data in the sparse block 2220 stored in the memory 2230 can be streamed to the on-chip RAM of the sparse computing tile 2234. The technology that enables the sparse computing tile 2234 to efficiently process sparse data is less effective on very sparse and ultra-sparse matrices. Very / ultra-sparse matrices have very few non-zeros. Therefore, processing such matrices incurs relatively high blocking overhead (e.g., row or column pointers). The higher blocking overhead means that the processing bookkeeping data consumes more computing time and memory bandwidth relative to the processing of the actual non-zero matrix elements. In addition, very / ultra-sparse matrices have very few non-zeros per column or row and accessing columns and rows involves fewer and shorter memory accesses. In addition, a smaller amount of accessed data is reused during processing. The very / ultra sparse compute tile 2236 overcomes these inefficiencies by adjusting the architecture of the sparse compute tile 2234.

[0267] In order to increase the efficiency of the very / super sparse computation tile 2236, the matrix partitioning module 2210 generates a sparse matrix of larger blocks. Larger blocks result in reduced blocking overhead relative to the non-zero data to be processed. Larger matrix blocks have larger associated vector subsets that will be processed against the very / super sparse block 2222. Instead of storing the vector subsets in on-chip RAM, as in the sparse computation tile 2234, the vector subsets are stored in a parallel optimized memory 2232. The very / super sparse computation tile 2236 uses a data management unit optimized for gather / scatter operations (e.g., G / S DMU 2237). In one embodiment, the G / S DMU 2237 includes a cache 2238 to capture moderate data reuse that can be used for vector subset data. In some embodiments, the very / super sparse computation tile 2236 may also include fewer processing elements relative to the sparse computation tile 2234. In some embodiments, either or both of the sparse compute tile 2234 and / or the very / ultra sparse compute tile 2236 may be integrated into the compute or memory controller units 1432A-1432B of the hybrid memory module 1430 described herein to optimize the sparse computing capabilities of the near data compute module.

[0268] In one embodiment, the matrix partition module 2210 includes a matrix property analysis unit 2211, a block partition determination unit 2212, and a matrix optimization unit 2213. The matrix property analysis unit 2211 is configured to analyze various properties of the matrix, such as the number of non-zeros of each column or row. The metric determined by the matrix property analysis unit 2211 is provided to the block partition determination unit, which determines the appropriate technology used to partition the matrix into blocks. The block partition determination unit then determines the matrix block boundaries so that parts of matrices with similar properties are placed in the same block. The matrix optimization unit 2213 then applies various optimizations to improve the processing efficiency of the computing unit when processing blocks. For example and in one embodiment, the matrix optimization unit 2213 can optimize the matrix format for each block so that super sparse blocks use a dual compression format, and thin and tall matrix blocks use a row-oriented format to avoid memory dispersion. The matrix optimization unit 2213 can also optimize the scheduling of blocks for processing by the scheduler 2235 by generating scheduling hints for use when scheduling workloads to processing elements.

[0269] Figures 23A-23B 2300, 2310 is a flow chart illustrating logic 2300, 2310 for performing sparse computing operations within a GPGPU provided by embodiments described herein. Fig.14 and Fig.21 The sparse computing accelerator unit 1423 in the embodiment implements the logic 2300. In one embodiment, the sparse computing accelerator unit 1423 includes Fig. 22 Various aspects of the sparse computing architecture 2200 can be implemented as follows: Figure 14-Figure 1 5 and the hardware within the machine learning instruction fetch and decode unit 1421 and the machine learning scheduler controller 1422 to implement logic 2310. In one embodiment, at least a portion of logic 2310 can be implemented in a hybrid memory module, such as Fig.14 and / or Fig.18 Within the computing element of the hybrid memory module 1430.

[0270] like Fig.23A As shown in , logic 2300 causes the hardware within the GPGPU to read the input matrix into the sparse computing architecture, as shown at block 2302. Logic 2300 can then process the matrix via a partition module, as shown at block 2304. The partition module can be Fig. 222300 and can perform operations including matrix analysis, partition determination, and matrix optimization. Processing the matrix at block 2304 provides information to the logic 2300 to determine at block 2305 whether the matrix is ​​a very sparse or ultra sparse matrix, where a very sparse matrix has very few non-zero data values ​​per column or row and an ultra sparse matrix has zero data values ​​for an entire row or column. As shown at block 2306, in the case where the input matrix is ​​only sparse and not very or ultra sparse, the logic 2300 can output a set of sparse matrix blocks to a bandwidth optimized memory, such as Fig. 22 2230 of the memory. As described at block 2308, the logic 2300 may then compute the tiles, such as Fig. 22 234 to process sparse matrix blocks. As shown at block 2307, in the case where the input matrix is ​​very sparse or super sparse, the logic 2300 can output a set of very sparse or super sparse matrix blocks to a latency optimized memory, such as Fig. 22 2232 of the memory. As shown at block 2309, the logic 2300 may then compute the tiles, such as Fig. 22 The very / ultra sparse computation block 2236 is used to process very sparse or ultra sparse matrix blocks.

[0271] like Fig. 23B As shown in FIG. 23, logic 2310 enables the sparse computing architecture described herein to be integrated into a machine learning optimized microarchitecture within a GPGPU. Logic 2310 may determine a set of pipeline commands to execute in response to a decoded machine learning instruction on the GPGPU, as shown at block 2312. The decoded machine learning instruction may be Fig.17 1702 in the decoded machine learning instructions. As shown at block 2314, in one embodiment, the logic 2310 may process the set of pipeline commands via programmable logic within a hardware-based scheduler, such as the machine learning scheduler controller 1422 described herein. The logic 2310 may then determine at block 2315 whether the pipeline command specifies any sparse matrix operations. If sparse matrix operations are to be performed, the logic 2310 may schedule the sparse matrix operations to a sparse matrix accelerator within the GPGPU, such as a sparse matrix accelerator, as shown at block 2317. Fig.14 and Fig.21 Sparse computing accelerator unit 1423 or Fig. 222234 and / or very / ultra sparse compute tile 2236. If no sparse operation is specified, logic 2310 may dispatch the command operation to a general purpose compute block within the GPGPU, as shown at block 2316. In some embodiments, a subset of sparse matrix and general purpose operations may also be performed via near data compute elements, where the compute operations are memory bandwidth sensitive.

[0272] Additional Exemplary Graphics Processing Systems

[0273] Details of the embodiments described above may be incorporated into the graphics processing systems and devices described below. Figures 24 to 37 The graphics processing systems and devices of illustrative embodiments illustrate alternative systems and graphics processing hardware that may implement any and all of the techniques described above.

[0274] Additional Exemplary Graphics Processing System Overview

[0275] Fig.24 2400 is a block diagram of a processing system 2400 according to an embodiment. In various embodiments, the system 2400 includes one or more processors 2402 and one or more graphics processors 2408, and may be a single processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 2402 or processor cores 2407. In one embodiment, the system 2400 is a processing platform incorporated into a system-on-chip (SoC) integrated circuit for use in a mobile device, handheld device, or embedded device.

[0276] Embodiments of system 2400 may include or be incorporated into the following: a server-based gaming platform; a gaming console, including a gaming and media console, a mobile gaming console, a handheld gaming console, or an online gaming console. In some embodiments, system 2400 is a mobile phone, a smart phone, a tablet computing device, or a mobile Internet device. Data processing system 2400 may also include a wearable device (such as a smart watch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device), coupled to the wearable device, or integrated into the wearable device. In some embodiments, data processing system 2400 is a television or set-top box device having one or more processors 2402 and a graphical interface generated by one or more graphics processors 2408.

[0277] In some embodiments, one or more processors 2402 each include one or more processor cores 2407 for processing instructions, which perform the operation of the system and user software when executed. In some embodiments, each processor core in the one or more processor cores 2407 is configured to process a specific instruction set 2409. In some embodiments, the instruction set 2409 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). Multiple processor cores 2407 can each process different instruction sets 2409, and the instruction set may include instructions for facilitating emulation of other instruction sets. The processor core 2407 may also include other processing devices, such as a digital signal processor (DSP).

[0278] In some embodiments, the processor 2402 includes a cache memory 2404. Depending on the architecture, the processor 2402 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of the processor 2402. In some embodiments, the processor 2402 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which may be shared among the processor cores 2407 using known cache coherence techniques. In addition, a register file 2406 is included in the processor 2402, which may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of the processor 2402.

[0279] In some embodiments, the processor 2402 is coupled to a processor bus 2410, which is used to transmit communication signals, such as address, data, or control signals, between the processor 2402 and other components in the system 2400. In one embodiment, the system 2400 uses an exemplary 'hub' system architecture, including a memory controller hub 2416 and an input-output (I / O) controller hub 2430. The memory controller hub 2416 facilitates communication between memory devices and other components of the system 2400, while the I / O controller hub (ICH) 2430 provides connections to I / O devices via a local I / O bus. In one embodiment, the logic of the memory controller hub 2416 is integrated within the processor.

[0280] The memory device 2420 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device having suitable performance to act as processing memory. In one embodiment, the memory device 2420 may operate as system memory of the system 2400 to store data 2422 and instructions 2421 for use when one or more processors 2402 execute applications or processes. The memory controller hub 2416 is also coupled to an optional external graphics processor 2412, which may communicate with one or more graphics processors 2408 in the processor 2402 to perform graphics and media operations.

[0281] In some embodiments, the ICH 2430 enables peripherals to be connected to the memory device 2420 and the processor 2402 via a high-speed I / O bus. The I / O peripherals include, but are not limited to, an audio controller 2446, a firmware interface 2428, a wireless transceiver 2426 (e.g., Wi-Fi, Bluetooth), a data storage device 2424 (e.g., a hard drive, flash memory, etc.), and a traditional I / O controller 2440 for coupling traditional (e.g., Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 2442 connect input devices, such as a keyboard and mouse 2444 combination. A network controller 2434 may also be coupled to the ICH 2430. In some embodiments, a high-performance network controller (not shown) is coupled to the processor bus 2410. It should be understood that the system 2400 shown is exemplary and not limiting, as other types of data processing systems configured in different ways may also be used. For example, I / O controller hub 2430 may be integrated within one or more processors 2402 , or memory controller hub 2416 and I / O controller hub 2430 may be integrated into a discrete external graphics processor, such as external graphics processor 2412 .

[0282] Fig.25 is a block diagram of an embodiment of a processor 2500 having one or more processor cores 2502A- 2502N, an integrated memory controller 2514, and an integrated graphics processor 2508. Fig.25Those elements having the same reference numerals (or names) as elements of any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. Processor 2500 may include additional cores up to and including additional core 2502N represented by a dashed box. Each of processor cores 2502A to 2502N includes one or more internal cache units 2504A to 2504N. In some embodiments, each processor core may also access one or more shared cache units 2506.

[0283] Internal cache units 2504A to 2504N and shared cache unit 2506 represent a cache memory hierarchy within processor 2500. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache before external memory is classified as LLC. In some embodiments, cache coherence logic maintains coherence between the various cache units 2506 and 2504A to 2504N.

[0284] In some embodiments, the processor 2500 may also include a set of one or more bus controller units 2516 and a system agent core 2510. The one or more bus controller units 2516 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express). The system agent core 2510 provides management functions for various processor components. In some embodiments, the system agent core 2510 includes one or more integrated memory controllers 2514 to manage access to various external memory devices (not shown).

[0285] In some embodiments, one or more of the processor cores 2502A to 2502N include support for simultaneous multithreading. In such embodiments, the system agent core 2510 includes components for coordinating and operating the cores 2502A to 2502N during multithreaded processing. In addition, the system agent core 2510 may also include a power control unit (PCU) that includes logic and components for regulating the power state of the processor cores 2502A to 2502N and the graphics processor 2508.

[0286] In some embodiments, in addition, the processor 2500 also includes a graphics processor 2508 for performing graphics processing operations. In some embodiments, the graphics processor 2508 is coupled to a set of shared cache units 2506 and a system agent core 2510, which includes one or more integrated memory controllers 2514. In some embodiments, a display controller 2511 is coupled to the graphics processor 2508 to drive the graphics processor output to one or more coupled displays. In some embodiments, the display controller 2511 can be a separate module coupled to the graphics processor via at least one interconnect, or can be integrated within the graphics processor 2508 or the system agent core 2510.

[0287] In some embodiments, a ring-based interconnect unit 2512 is used to couple the internal components of the processor 2500. However, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies, including those well known in the art. In some embodiments, the graphics processor 2508 is coupled to the ring interconnect 2512 via an I / O link 2513.

[0288] Exemplary I / O links 2513 represent at least one of a plurality of varieties of I / O interconnects, including package I / O interconnects that facilitate communication between various processor components and high-performance embedded memory modules 2518, such as eDRAM modules. In some embodiments, each of processor cores 2502A to 2502N and graphics processor 2508 use embedded memory modules 2518 as a shared last-level cache.

[0289] In some embodiments, the processor cores 2502A to 2502N are homogeneous cores that execute the same instruction set architecture. In another embodiment, the processor cores 2502A to 2502N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of the processor cores 2502A to 2502N execute a first instruction set, and at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, the processor cores 2502A to 2502N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In addition, the processor 2500 may be implemented on one or more chips or as a SoC integrated circuit having the illustrated components in addition to other components.

[0290] Fig.2626 is a block diagram of a graphics processor 2600, which may be a discrete graphics processing unit or may be a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates via a memory mapped I / O interface to registers on the graphics processor and using commands placed in the processor memory. In some embodiments, the graphics processor 2600 includes a memory interface 2614 for accessing memory. The memory interface 2614 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0291] In some embodiments, the graphics processor 2600 also includes a display controller 2602 for driving display output data to a display device 2620. The display controller 2602 includes hardware for one or more overlapping planes of the display and a composition of multiple layers of video or user interface elements. In some embodiments, the graphics processor 2600 includes a video codec engine 2606 for encoding media to one or more media encoding formats, decoding media from one or more media encoding formats, or transcoding media between one or more media encoding formats, including but not limited to: Moving Picture Experts Group (MPEG) formats (such as MPEG-2), Advanced Video Coding (AVC) formats (such as H.264 / MPEG-4 AVC), and Society of Motion Picture and Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) formats (such as JPEG), and Motion JPEG (MJPEG) formats.

[0292] In some embodiments, graphics processor 2600 includes a block image transfer (BLIT) engine 2604 for performing two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 2610. In some embodiments, GPE 2610 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0293] In some embodiments, GPE 2610 includes a 3D pipeline 2612 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 2612 includes programmable and fixed functional elements that perform various tasks within the elements and / or generate execution threads to 3D / media subsystem 2615. Although 3D pipeline 2612 can be used to perform media operations, embodiments of GPE 2610 also include a media pipeline 2616 that is specifically used to perform media operations, such as video post-processing and image enhancement.

[0294] In some embodiments, the media pipeline 2616 includes fixed-function or programmable logic units to perform one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, instead of or on behalf of the video codec engine 2606. In some embodiments, in addition, the media pipeline 2616 also includes a thread generation unit to generate threads for execution on the 3D / media subsystem 2615. The generated threads perform calculations for media operations on one or more graphics execution units included in the 3D / media subsystem 2615.

[0295] In some embodiments, the 3D / media subsystem 2615 includes logic for executing threads generated by the 3D pipeline 2612 and the media pipeline 2616. In one embodiment, the pipeline sends a thread execution request to the 3D / media subsystem 2615, which includes thread dispatch logic for arbitrating various requests and dispatching various requests to available thread execution resources. The execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, the 3D / media subsystem 2615 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) to share data between threads and store output data.

[0296] Additional Exemplary Graphics Processing Engines

[0297] Fig. 27 is a block diagram of a graphics processing engine 2710 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 2710 is Fig.26 The version of the GPE 2610 shown in . Fig. 27 Elements having the same reference numeral (or name) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to these. Fig.262610. The 3D pipeline 2612 and the media pipeline 2616 of the GPE 2710. The media pipeline 2616 is optional in some embodiments of the GPE 2710 and may not be explicitly included in the GPE 2710. For example and in at least one embodiment, separate media and / or image processors are coupled to the GPE 2710.

[0298] In some embodiments, the GPE 2710 is coupled to or includes a command streamer 2703 that provides a command stream to the 3D pipeline 2612 and / or the media pipeline 2616. In some embodiments, the command streamer 2703 is coupled to a memory, which may be a system memory, or one or more cache memories of an internal cache memory and a shared cache memory. In some embodiments, the command streamer 2703 receives commands from the memory and sends the commands to the 3D pipeline 2612 and / or the media pipeline 2616. The commands are instructions obtained from a ring buffer storing commands for the 3D pipeline 2612 and the media pipeline 2616. In one embodiment, in addition, the ring buffer may also include a batch command buffer storing multiple batches of multiple commands. Commands for 3D pipeline 2612 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for 3D pipeline 2612 and / or image data and memory objects for media pipeline 2616. 3D pipeline 2612 and media pipeline 2616 process commands and data by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to graphics core array 2714.

[0299] In various embodiments, the 3D pipeline 2612 can execute one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 2714. The graphics core array 2714 provides a unified execution resource block. The multi-purpose execution logic (e.g., execution unit) within the graphics core array 2714 includes support for various 3D API shader languages ​​and can execute multiple simultaneous execution threads associated with multiple shaders.

[0300] In some embodiments, graphics core array 2714 also includes execution logic for performing media functions such as video and / or image processing. In one embodiment, the execution unit also includes general logic that can be programmed to perform parallel general computing operations in addition to graphics processing operations. The general logic can be connected to Fig.24 (multiple) processor cores 2407 or Fig.25 The general logic within cores 2502A to 2502N performs processing operations in parallel or in combination.

[0301] Output data generated by threads executing on the graphics core array 2714 can output data to memory in a unified return buffer (URB) 2718. URB 2718 can store data for multiple threads. In some embodiments, URB 2718 can be used to send data between different threads executing on the graphics core array 2714. In some embodiments, URB 2718 can also be used for synchronization between threads on the graphics core array and fixed function logic within shared function logic 2720.

[0302] In some embodiments, graphics core array 2714 is scalable such that the array includes a variable number of graphics cores each having a variable number of execution units based on the target power and performance level of GPE 2710. In one embodiment, execution resources are dynamically scalable such that execution resources can be enabled or disabled as needed.

[0303] The graphics core array 2714 is coupled to a shared function logic 2720, which includes a plurality of resources shared between the graphics cores in the graphics core array. The shared functions within the shared function logic 2720 are hardware logic units that provide dedicated supplementary functions to the graphics core array 2714. In various embodiments, the shared function logic 2720 includes, but is not limited to, a sampler 2721, a math 2722, and an inter-thread communication (ITC) 2723 logic. In addition, some embodiments implement one or more caches 2725 within the shared function logic 2720. The shared functions are implemented in the case where the demand for a given dedicated function is insufficient to be included within the graphics core array 2714. Instead, a single instantiation of the dedicated function is implemented as an independent entity in the shared function logic 2720 and shared between execution resources within the graphics core array 2714. The exact set of functions shared between the graphics core array 2714 and included within the graphics core array 2714 varies between embodiments.

[0304] Fig.28 is a block diagram of another embodiment of a graphics processor 2800 . Fig.28 Elements having the same reference number (or name) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to these.

[0305] In some embodiments, graphics processor 2800 includes ring interconnect 2802, pipeline front end 2804, media engine 2837, and graphics cores 2880A to 2880N. In some embodiments, ring interconnect 2802 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of many processors integrated into a multi-core processing system.

[0306] In some embodiments, the graphics processor 2800 receives batches of commands via a ring interconnect 2802. Incoming commands are interpreted by a command streamer 2803 in a pipeline front end 2804. In some embodiments, the graphics processor 2800 includes scalable execution logic for performing 3D geometry processing and media processing via (multiple) graphics cores 2880A to 2880N. For 3D geometry processing commands, the command streamer 2803 supplies the commands to a geometry pipeline 2836. For at least some media processing commands, the command streamer 2803 supplies the commands to a video front end 2834, which is coupled to a media engine 2837. In some embodiments, the media engine 2837 includes a video quality engine (VQE) 2830 for video and image post-processing and a multi-format encoding / decoding (MFX) 2833 engine for providing hardware accelerated media data encoding and decoding. In some embodiments, the geometry pipeline 2836 and the media engine 2837 each generate an execution thread, which is used for thread execution resources provided by at least one graphics core 2880A.

[0307] In some embodiments, the graphics processor 2800 includes scalable thread execution resource characterization modular cores 2880A to 2880N (sometimes referred to as core slices), each of which has multiple sub-cores 2850A to 2850N, 2860A to 2860N (sometimes referred to as core sub-slices). In some embodiments, the graphics processor 2800 can have any number of graphics cores 2880A to 2880N. In some embodiments, the graphics processor 2800 includes a graphics core 2880A, which has at least a first sub-core 2850A and a second sub-core 2860A. In other embodiments, the graphics processor is a low-power processor with a single sub-core (e.g., 2850A). In some embodiments, the graphics processor 2800 includes multiple graphics cores 2880A to 2880N, each of which includes a group of first sub-cores 2850A to 2850N and a group of second sub-cores 2860A to 2860N. Each of the group of first sub-cores 2850A to 2850N includes at least a first group of execution units 2852A to 2852N and media / texture samplers 2854A to 2854N. Each of the group of second sub-cores 2860A to 2860N includes at least a second group of execution units 2862A to 2862N and samplers 2864A to 2864N. In some embodiments, each sub-core 2850A to 2850N, 2860A to 2860N shares a group of shared resources 2870A to 2870N. In some embodiments, the shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0308] Additional Exemplary Execution Units

[0309] Fig.29 Illustrated is thread execution logic 2900 comprising an array of processing elements employed in some embodiments of a GPE. Fig.29 Elements having the same reference number (or name) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to these.

[0310] In some embodiments, the thread execution logic 2900 includes a shader processor 2902, a thread dispatcher 2904, an instruction cache 2906, a scalable execution unit array including a plurality of execution units 2908A to 2908N, a sampler 2910, a data cache 2912, and a data port 2914. In one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., any one of execution units 2908A, 2908B, 2908C, 2908D up to 2908N-1 and 2908N) based on the computational requirements of the workload. In one embodiment, the included components are interconnected via an interconnect structure that links to each of the components. In some embodiments, the thread execution logic 2900 includes one or more connections to a memory (such as a system memory or a cache memory) through the instruction cache 2906, the data port 2914, the sampler 2910, and one or more of the execution units 2908A to 2908N. In some embodiments, each execution unit (e.g., 2908A) is an independently programmable general-purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, execution unit arrays 2908A to 2908N are scalable to include any number of individual execution units.

[0311] In some embodiments, execution units 2908A to 2908N are primarily used to execute shader programs. Shader processor 2902 can process various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 2904. In one embodiment, thread dispatcher includes logic to arbitrate thread initiation requests from graphics and media pipelines and instantiate the requested threads on one or more of execution units 2908A to 2908N. For example, the geometry pipeline (e.g., Fig.28 2836) can dispatch vertex, tessellation or geometry shaders to thread execution logic 2900 ( Fig.29 ) for processing. In some embodiments, thread dispatcher 2904 can also process runtime thread generation requests from executing shader programs.

[0312] In some embodiments, execution units 2908A to 2908N support instruction sets (including native support for many standard 3D graphics shader instructions) so that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with minimal conversion. These execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., compute and media shaders). Each of execution units 2908A to 2908N is capable of multi-issue single instruction multiple data (SIMD) execution, and multi-threaded operations implement an efficient execution environment in the face of high latency memory access. Each hardware thread within each execution unit has a dedicated high-bandwidth register stack and an associated independent thread state. For pipelines capable of integer, single-precision and double-precision floating-point operations, SIMD branching capabilities, logical operations, transcendental operations, and other miscellaneous operations, execution is multi-issued per clock. While waiting for data from memory or one of the shared functions, dependency logic within execution units 2908A to 2908N causes the waiting thread to sleep until the requested data has been returned. While the waiting thread is sleeping, hardware resources can be dedicated to processing other threads. For example, during a delay associated with a vertex shader operation, an execution unit can perform operations for a pixel shader, a fragment shader, or another type of shader program including a different vertex shader.

[0313] Each of the execution units 2908A to 2908N operates on an array of data elements. The number of data elements is the "execution size," or number of lanes of an instruction. An execution lane is a logical unit for the execution of data element access, masking, and flow control within an instruction. The number of lanes may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) for a particular graphics processor. In some embodiments, the execution units 2908A to 2908N support integer and floating point data types.

[0314] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as compressed data types, and the execution unit will process various elements based on the data size of the element. For example, when operating on a 256-bit wide vector, 256 bits of the vector are stored in registers, and the execution unit operates on the vector as four separated 64-bit compressed data elements (quadruple word (QW) size data elements), eight separated 32-bit compressed data elements (double word (DW) size data elements), sixteen separated 16-bit compressed data elements (word (W) size data elements) or thirty-two separated 8-bit data elements (byte (B) size data elements). However, different vector widths and register sizes are possible.

[0315] One or more internal instruction caches (e.g., 2906) are included in the thread execution logic 2900 to cache thread instructions for the execution unit. In some embodiments, one or more data caches (e.g., 2912) are included to cache thread data during thread execution. In some embodiments, a sampler 2910 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 2910 includes a specialized texture or media sampling function to process texture or media data during the sampling process before providing the sampled data to the execution unit.

[0316] During execution, the graphics and media pipeline sends a thread initiation request to the thread execution logic 2900 via the thread generation and dispatch logic. Once a set of geometric objects has been processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 2902 is called to further calculate output information and cause the result to be written to the output surface (e.g., color buffer, depth buffer, stencil printing buffer, etc.). In some embodiments, the pixel shader or fragment shader calculates the value of various vertex attributes that are to be interpolated across rasterized objects. In some embodiments, the pixel processor logic within the shader processor 2902 then executes the pixel or fragment shader program supplied by the application programming interface (API). In order to execute the shader program, the shader processor 2902 dispatches the thread to the execution unit (e.g., 2908A) via the thread dispatcher 2904. In some embodiments, the pixel shader 2902 uses the texture sampling logic in the sampler 2910 to access the texture data in the texture map stored in the memory. Arithmetic operations on texture data and input geometry data compute pixel color data for each geometry fragment, or discard one or more pixels without further processing.

[0317] In some embodiments, data port 2914 provides a memory access mechanism for thread execution logic 2900 to output processed data to memory for processing on the graphics processor output pipeline. In some embodiments, data port 2914 includes or is coupled to one or more cache memories (e.g., data cache 2912) to cache data via the data port for memory access.

[0318] Fig.303000 is a block diagram illustrating a graphics processor instruction format 3000 according to some embodiments. In one or more embodiments, a graphics processor execution unit supports an instruction set having instructions in a variety of formats. Solid line boxes illustrate components that are typically included in execution unit instructions, while dashed lines include optional components or components that are only included in a subset of instructions. In some embodiments, the instruction format 3000 described and illustrated are macroinstructions because they are instructions supplied to the execution unit, in contrast to micro-operations that are generated by instruction decoding once the instruction is processed.

[0319] In some embodiments, the graphics processor execution unit natively supports instructions in 128-bit instruction format 3010. 64-bit compressed instruction format 3030 can be used for some instructions based on the selected instruction, instruction options and number of operands. The native 128-bit instruction format 3010 provides access to all instruction options, while some options and operations are restricted to 64-bit format 3030. The native instructions available in 64-bit format 3030 vary according to the embodiment. In some embodiments, instructions are compressed in part using a set of index values ​​in index field 3013. The execution unit hardware references a set of compression tables based on the index values ​​and uses the compression table output to reconstruct the native instructions in 128-bit instruction format 3010.

[0320] For each format, the instruction opcode 3012 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous add operation across each color channel, the color channel representing a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, the instruction control field 3014 enables control of certain execution options such as channel selection (e.g., prediction) and data channel order (e.g., swizzling). For instructions in the 128-bit instruction format 3010, the execution size field 3016 limits the number of data channels that will be executed in parallel. In some embodiments, the execution size field 3016 is not available for use in the 64-bit compressed instruction format 3030.

[0321] Some execution unit instructions have up to three operands, including two source operands (src0 3020, src1 3022) and a destination 3018. In some embodiments, the execution unit supports dual destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 3024), where the instruction opcode 3012 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value passed with the instruction.

[0322] In some embodiments, the 128-bit instruction format 3010 includes an access / addressing mode field 3026, which specifies, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is provided directly by bits in the instruction.

[0323] In some embodiments, the 128-bit instruction format 3010 includes an access / addressing mode field 3026, which specifies an addressing mode and / or access mode for the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes, including 16-byte aligned access modes and 1-byte aligned access modes, wherein the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, the instruction can use byte aligned addressing for source operands and destination operands, and when in a second mode, the instruction can use 16-byte aligned addressing for all source operands and destination operands.

[0324] In one embodiment, the addressing mode portion of the access / addressing mode field 3026 determines whether the instruction is to use direct addressing or indirect addressing. When using direct register addressing mode, the bits in the instruction directly provide the register address of one or more operands. When using indirect register addressing mode, the register address of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0325] In some embodiments, instructions are grouped based on the opcode 3012 bit field to simplify opcode decoding 3040. For 8-bit opcodes, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is only an example. In some embodiments, the move and logic opcode group 3042 includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 3042 shares five most significant bits (MSBs), where the move (mov) instruction takes the form of 0000xxxxb, and the logic instruction takes the form of 0001xxxxb. The flow control instruction group 3044 (e.g., call (call), jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 3046 includes a mixture of instructions, including synchronization instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). The parallel math instruction group 3048 includes component-wise arithmetic instructions (e.g., add, multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel math group 3048 performs arithmetic operations in parallel across data lanes. The vector math group 3050 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic calculations on vector operands, such as dot product calculations.

[0326] Additional Example Graphics Pipeline

[0327] Fig.31 is a block diagram of another embodiment of a graphics processor 3100 . Fig.31 Elements having the same reference number (or name) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to these.

[0328] In some embodiments, the graphics processor 3100 includes a graphics pipeline 3120, a media pipeline 3130, a display engine 3140, a thread execution logic 3150, and a rendering output pipeline 3170. In some embodiments, the graphics processor 3100 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or by commands issued to the graphics processor 3100 through the ring interconnect 3102. In some embodiments, the ring interconnect 3102 couples the graphics processor 3100 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 3102 are interpreted by a command streamer 3103, which supplies instructions to separate components of the graphics pipeline 3120 or the media pipeline 3130.

[0329] In some embodiments, the command streamer 3103 directs the operation of the vertex fetcher 3105, which reads vertex data from memory and executes vertex processing commands provided by the command streamer 3103. In some embodiments, the vertex fetcher 3105 provides vertex data to the vertex shader 3107, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, the vertex fetcher 3105 and the vertex shader 3107 execute vertex processing instructions by dispatching execution threads to execution units 3152A to 3152B via the thread dispatcher 3131.

[0330] In some embodiments, execution units 3152A-3152B are vector processor arrays with instruction sets for performing graphics and media operations. In some embodiments, execution units 3152A-3152B have an attached L1 cache 3151 that is dedicated to each array or shared between arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0331] In some embodiments, the graphics pipeline 3120 includes a tessellation component for performing hardware accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 3111 configures the tessellation operation. A programmable domain shader 3117 provides back-end evaluation of the tessellation output. The tessellator 3113 operates at the direction of the hull shader 3111 and contains dedicated logic for generating a set of detailed geometric objects based on a coarse geometric model that is provided as input to the graphics pipeline 3120. In some embodiments, if tessellation is not used, the tessellation components (e.g., the hull shader 3111, the tessellator 3113, and the domain shader 3117) can be bypassed.

[0332] In some embodiments, the complete geometric object may be processed by the geometry shader 3119 via one or more threads dispatched to the execution units 3152A-3152B, or may proceed directly to the clipper 3129. In some embodiments, the geometry shader operates on the entire geometric object (rather than vertices or vertex patches as in previous stages of the graphics pipeline). If tessellation is disabled, the geometry shader 3119 receives input from the vertex shader 3107. In some embodiments, the geometry shader 3119 may be programmed by a geometry shader program to perform geometry tessellation when the tessellation unit is disabled.

[0333] Before rasterization, the clipper 3129 processes the vertex data. The clipper 3129 can be a fixed function clipper or a programmable clipper with clipping and geometry shader functions. In some embodiments, the rasterizer and depth test component 3173 in the rendering output pipeline 3170 dispatches a pixel shader to convert the geometric object into its per-pixel representation. In some embodiments, the pixel shader logic is included in the thread execution logic 3150. In some embodiments, the application can bypass the rasterizer and depth test component 3173 and access the unrasterized vertex data via the outflow unit 3123.

[0334] The graphics processor 3100 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be passed between the main components of the processor. In some embodiments, execution units 3152A to 3152B and associated caches 3151, texture and media samplers 3154, and texture / sampler caches 3158 are interconnected via data ports 3156 to perform memory accesses and communicate with the rendering output pipeline components of the processor. In some embodiments, samplers 3154, caches 3151, 3158, and execution units 3152A to 3152B each have a separate memory access path.

[0335] In some embodiments, the rendering output pipeline 3170 includes a rasterizer and a depth test component 3173, which converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a window device / masker unit for performing fixed-function triangle and line rasterization. Associated rendering caches 3178 and depth caches 3179 are also available in some embodiments. Pixel operation components 3177 perform pixel-based operations on data, but in some instances, pixel operations associated with 2D operations (e.g., using mixed bit block image transfer) are performed by 2D engines 3141, or replaced by overlapping display planes at display time by display controller 3143. In some embodiments, a shared L3 cache 3175 can be used for all graphics components, thereby allowing data to be shared without using main system memory.

[0336] In some embodiments, the graphics processor media pipeline 3130 includes a media engine 3137 and a video front end 3134. In some embodiments, the video front end 3134 receives pipeline commands from the command streamer 3103. In some embodiments, the media pipeline 3130 includes a separate command streamer. In some embodiments, the video front end 3134 processes media commands before sending the commands to the media engine 3137. In some embodiments, the media engine 3137 includes a thread generation function for generating threads for dispatching to the thread execution logic 3150 via the thread dispatcher 3131.

[0337] In some embodiments, the graphics processor 3100 includes a display engine 3140. In some embodiments, the display engine 3140 is external to the processor 3100 and is coupled to the graphics processor via a ring interconnect 3102, or some other interconnect bus or structure. In some embodiments, the display engine 3140 includes a 2D engine 3141 and a display controller 3143. In some embodiments, the display engine 3140 includes dedicated logic that can operate independently of the 3D pipeline. In some embodiments, the display controller 3143 is coupled to a display device (not shown), which can be a system integrated display device (such as in a laptop computer), or an external display device attached via a display device connector.

[0338] In some embodiments, the graphics pipeline 3120 and the media pipeline 3130 can be configured to perform operations based on multiple graphics and media programming interfaces and are not dedicated to any one application programming interface (API). In some embodiments, the driver software of the graphics processor converts API calls dedicated to specific graphics or media libraries into commands that can be processed by the graphics processor. In some embodiments, support is provided for all open graphics libraries (OpenGL), open computing languages ​​(OpenCL) and / or Vulkan graphics and computing APIs from the Khronos Group. In some embodiments, support can also be provided for the Direct3D library from Microsoft. In some embodiments, a combination of these libraries can be supported. Support can also be provided for the open source computer vision library (OpenCV). If a mapping can be made from the pipeline of a future API to the pipeline of a graphics processor, future APIs with compatible 3D pipelines will also be supported.

[0339] Graphics Pipeline Programming

[0340] Fig.32A is a block diagram illustrating a graphics processor command format 3200 according to some embodiments. Fig.32B is a block diagram illustrating a graphics processor command sequence 3210 according to an embodiment. Fig.32ASolid line boxes in illustrate components that are typically included in a graphics command, while dashed lines include components that are optional or included only in a subset of the graphics commands. Fig.32A The exemplary graphics processor command format 3200 includes a data field for identifying the target client 3202 of the command, a command operation code (opcode) 3204, and associated data 3206 for the command. Some commands also include a sub-opcode 3205 and a command size 3208.

[0341] In some embodiments, client 3202 specifies the client unit of the graphics device that processes the command data. In some embodiments, the graphics processor command parser checks the client field of each command to adjust the further processing of the command and routes the command data to the appropriate client unit. In some embodiments, the graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing the command. Once the command is received by the client unit, the client unit reads the opcode 3204 and the sub-opcode 3205 (if present) to determine the operation to be performed. The client unit uses the information in the data field 3206 to execute the command. For some commands, an explicit command size 3208 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands in the command based on the command opcode. In some embodiments, the commands are aligned via multiples of double words.

[0342] Fig.32B An exemplary graphics processor command sequence 3210 is shown in the flowchart in FIG. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses a version of the command sequence shown to set up, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for exemplary purposes only, as the embodiments are not limited to these particular commands or to the command sequence. Moreover, the commands may be issued as a batch of commands in a command sequence so that the graphics processor will process the command sequence in an at least partially simultaneous manner.

[0343] In some embodiments, the graphics processor command sequence 3210 may begin with a pipeline dump clear command 3212 to cause any active graphics pipeline to complete currently pending commands for the pipeline. In some embodiments, the 3D pipeline 3222 and the media pipeline 3224 are not operating at the same time. The pipeline dump clear is performed to cause the active graphics pipeline to complete any pending commands. In response to the pipeline dump clear, the command parser for the graphics processor will suspend command processing until the active drawing engine completes pending operations and invalidates the associated read cache. Optionally, any data marked as 'dirty' in the rendering cache can be dumped to memory. In some embodiments, the pipeline dump clear command 3212 can be used for pipeline synchronization or before placing the graphics processor in a low power state.

[0344] In some embodiments, pipeline select command 3213 is used when a command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, pipeline select command 3213 is required only once within an execution context before issuing pipeline commands unless the context is to issue commands for both pipelines. In some embodiments, pipeline flush command 3212 is required immediately prior to a pipeline switch via pipeline select command 3213.

[0345] In some embodiments, pipeline control commands 3214 configure the graphics pipeline for operation and are used to program 3D pipeline 3222 and media pipeline 3224. In some embodiments, pipeline control commands 3214 configure the pipeline state of the active pipeline. In one embodiment, pipeline control commands 3214 are used for pipeline synchronization and for clearing data from one or more cache memories within the active pipeline before processing a batch of commands.

[0346] In some embodiments, the return buffer state command 3216 is used to configure a set of return buffers for the corresponding pipeline to write data. Some pipeline operations require the allocation, selection or configuration of one or more return buffers into which the operation writes intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, the return buffer state 3216 includes selecting the size and number of return buffers to use for the set of pipeline operations.

[0347] The remaining commands in the command sequence differ based on the active pipeline for operation. Based on pipeline determination 3220 , the command sequence is tailored to either the 3D pipeline 3222 starting at 3D pipeline state 3230 or the media pipeline 3224 starting at media pipeline state 3240 .

[0348] The commands for configuring the 3D pipeline state 3230 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables to be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API in use. In some embodiments, the 3D pipeline state 3230 commands can also selectively disable or bypass specific pipeline elements (if those elements will not be used).

[0349] In some embodiments, 3D primitive 3232 commands are used to submit 3D primitives to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive 3232 commands are forwarded to the vertex acquisition function in the graphics pipeline. The vertex acquisition function uses the 3D primitive 3232 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, 3D primitive 3232 commands are used to perform vertex operations on 3D primitives via vertex shaders. In order to process vertex shaders, the 3D pipeline 3222 dispatches the shader execution thread to the graphics processor execution unit.

[0350] In some embodiments, the 3D pipeline 3222 is triggered via an execution 3234 command or event. In some embodiments, a register write triggers the command execution. In some embodiments, the execution is triggered via a 'go' or 'kick' command in a command sequence. In one embodiment, a pipeline synchronization command is used to trigger the command execution to dump and clear the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing on the 3D primitives. Once the operation is completed, the generated geometric objects are rasterized and the pixel engine shades the generated pixels. For those operations, additional commands for controlling pixel shading and pixel backend operations may also be included.

[0351] In some embodiments, when performing media operations, the graphics processor command sequence 3210 follows the media pipeline 3224 path. Generally, the specific purpose and manner of programming the media pipeline 3224 depends on the media or computing operation to be performed. During media decoding, specific media decoding operations can be offloaded to the media pipeline. In some embodiments, the media pipeline can also be bypassed, and media decoding can be performed in whole or in part using resources provided by one or more general processing cores. In one embodiment, the media pipeline also includes elements for general purpose graphics processor unit (GPGPU) operations, wherein the graphics processor is used to perform SIMD vector operations using compute shader programs that are not explicitly related to rendering graphics primitives.

[0352] In some embodiments, the media pipeline 3224 is configured in a similar manner to the 3D pipeline 3222. A set of commands 3240 for configuring the media pipeline state is dispatched or placed in the command queue before the media object commands 3242. In some embodiments, the media pipeline state commands 3240 include data for configuring the media pipeline elements that will be used to process the media objects. This includes data for configuring the video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some embodiments, the media pipeline state commands 3240 also support the use of one or more pointers to "indirect" state elements that contain a batch of state settings.

[0353] In some embodiments, media object commands 3242 supply pointers to media objects for media pipeline processing. The media object includes a memory buffer that contains video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object commands 3242. Once the pipeline states are configured and media object commands 3242 are queued, media pipeline 3224 is triggered via an execute command 3244 or an equivalent execute event (e.g., a register write). The output from media pipeline 3224 can then be post-processed by operations provided by 3D pipeline 3222 or media pipeline 3224. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0354] Graphics software architecture

[0355] Fig.33 An exemplary graphics software architecture of a data processing system 3300 according to some embodiments is illustrated. In some embodiments, the software architecture includes a 3D graphics application 3310, an operating system 3320, and at least one processor 3330. In some embodiments, processor 3330 includes a graphics processor 3332 and one or more general purpose processor cores 3334. Graphics application 3310 and operating system 3320 are each executed in a system memory 3350 of the data processing system.

[0356] In some embodiments, the 3D graphics application 3310 includes one or more shader programs, which include shader instructions 3312. The shader language instructions can be in a high-level shader language, such as a high-level shader language (HLSL) or an OpenGL shader language (GLSL). The application also includes executable instructions 3314, which are in a machine language suitable for execution by a general-purpose processor core 3334. The application also includes graphics objects 3316 defined by vertex data.

[0357] In some embodiments, the operating system 3320 is a Microsoft® Windows® operating system from Microsoft Corporation, a proprietary UNIX-style operating system, or an open source UNIX-style operating system using a Linux kernel variant. The operating system 3320 can support a graphics API 3322, such as a Direct3D API, an OpenGL API, or a Vulkan API. When the Direct3D API is in use, the operating system 3320 uses a front-end shader compiler 3324 to compile any shader instructions 3312 using HLSL into a lower-level shader language. The compilation can be a just-in-time (JIT) compilation, or the application can perform shader precompilation. In some embodiments, during the compilation of the 3D graphics application 3310, a high-level shader is compiled into a low-level shader. In some embodiments, the shader instruction 3312 is provided in an intermediate form (such as a version of the standard portable intermediate representation (SPIR) used by the Vulkan API).

[0358] In some embodiments, the user mode graphics driver 3326 includes a backend shader compiler 3327 that converts shader instructions 3312 into hardware-specific representations. When the OpenGL API is in use, shader instructions 3312 in the GLSL high-level language are passed to the user mode graphics driver 3326 for compilation. In some embodiments, the user mode graphics driver 3326 uses operating system kernel mode functions 3328 to communicate with the kernel mode graphics driver 3329. In some embodiments, the kernel mode graphics driver 3329 communicates with the graphics processor 3332 to dispatch commands and instructions.

[0359] IP Core Implementation

[0360] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit such as a processor. For example, a machine-readable medium may include instructions representing various logic within a processor. When read by a machine, the instructions may cause the machine to manufacture logic for performing the techniques described herein. This representation (referred to as an "IP core") is a reusable unit of logic for an integrated circuit that may be stored on a tangible machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be supplied to various customers or manufacturing facilities that load the hardware model on a manufacturing machine that manufactures the integrated circuit. The integrated circuit may be manufactured so that the circuit performs the operations described in association with any of the embodiments described herein.

[0361] Fig.34 34 is a block diagram illustrating an IP core development system 3400 that can be used to manufacture an integrated circuit for performing operations according to an embodiment. The IP core development system 3400 can be used to generate modular, reusable designs that can be incorporated into a larger design or used to construct an entire integrated circuit (e.g., a SOC integrated circuit). The design facility 3430 can generate a software simulation 3410 for the IP core design in a high-level programming language (e.g., C / C++). The software simulation 3410 can be used to design, test, and verify the behavior of the IP core using a simulation model 3412. The simulation model 3412 can include functional, behavioral, and / or timing simulations. A register transfer level (RTL) design 3415 can then be created or synthesized based on the simulation model 3412. The RTL design 3415 is an abstraction of the behavior of an integrated circuit (including associated logic executed using the modeled digital signals) that models the flow of digital signals between hardware registers. In addition to the RTL design 3415, a lower-level design at the logic level or transistor level can also be created, designed, or synthesized. Therefore, the specific details of the initial design and simulation can vary.

[0362] The RTL design 3415 or equivalent may be further synthesized by the design facility into a hardware model 3420, which may be in a hardware description language (HDL) or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design may be stored using a non-volatile memory 3440 (e.g., a hard disk, flash memory, or any non-volatile storage medium) for delivery to a third-party manufacturing facility 3465. Alternatively, the IP core design may be transmitted (e.g., via the Internet) via a wired connection 3450 or a wireless connection 3460. The manufacturing facility 3465 may then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit may be configured to perform operations according to at least one embodiment described herein.

[0363] Exemplary System-on-Chip Integrated Circuit

[0364] Figure 35 to Figure 37 An exemplary integrated circuit and associated graphics processor that can be manufactured using one or more IP cores according to various embodiments described herein are illustrated. In addition to what is illustrated, other logic and circuits may also be included, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores.

[0365] Fig.3535 is a block diagram illustrating an exemplary system-on-chip integrated circuit 3500 that can be manufactured using one or more IP cores according to an embodiment. The exemplary integrated circuit 3500 includes one or more application processors 3505 (e.g., CPUs), at least one graphics processor 3510, and may additionally include an image processor 3515 and / or a video processor 3520, any of which may be modular IP cores from the same or multiple different design facilities. The integrated circuit 3500 includes peripheral or bus logic, including a USB controller 3525, a UART controller 3530, an SPI / SDIO controller 3535, and an I 2 S / I 2 The integrated circuit may also include a display device 3545 coupled to one or more of a high-definition multimedia interface (HDMI) controller 3550 and a mobile industry processor interface (MIPI) display interface 3555. Storage may be provided by a flash memory subsystem 3560 (including flash memory and a flash memory controller). A memory interface may be provided via a memory controller 3565 to access SDRAM or SRAM memory devices. In addition, some integrated circuits also include an embedded security engine 3570.

[0366] Fig.36 is a block diagram illustrating an exemplary graphics processor 3610 of a system-on-chip integrated circuit that may be manufactured using one or more IP cores according to an embodiment. The graphics processor 3610 may be Fig.35 A variation of the graphics processor 3510 of FIG. The graphics processor 3610 includes a vertex processor 3605 and one or more fragment processors 3615A to 3615N (e.g., 3615A, 3615B, 3615C, 3615D, all the way to 3615N-1 and 3615N). The graphics processor 3610 can execute different shader programs via separate logic, so that the vertex processor 3605 is optimized to perform operations of the vertex shader program, while one or more fragment processors 3615A to 3615N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. The vertex processor 3605 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. (Multiple) fragment processors 3615A to 3615N use the primitives and vertex data generated by the vertex processor 3605 to generate a frame buffer displayed on a display device. In one embodiment, the fragment processor(s) 3615A-3615N are optimized to execute fragment shader programs provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0367] In addition, graphics processor 3610 also includes one or more memory management units (MMUs) 3620A-3620B, cache(s) 3625A-3625B, and circuit interconnect(s) 3630A-3630B. One or more MMUs 3620A-3620B provide virtual to physical address mappings for integrated circuit 3610, including for vertex processor 3605 and / or fragment processor(s) 3615A-3615N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 3625A-3625B. In one embodiment, one or more MMUs 3620A-3620B may communicate with other MMUs within the system, including with Fig.35 The graphics processor 3610 may be synchronized with one or more MMUs associated with one or more application processors 3505, image processor 3515, and / or video processor 3520 so that each processor 3505 to 3520 may participate in a shared or unified virtual memory system. According to an embodiment, one or more circuit interconnects 3630A to 3630B may enable the graphics processor 3610 to interact with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0368] Fig.37 is a block diagram illustrating an additional exemplary graphics processor 3710 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores in accordance with an embodiment. The graphics processor 3710 may be Fig.35 A variation of the graphics processor 3510. The graphics processor 3710 includes Fig.35 One or more MMUs 3520A-3520B, caches 3525A-3525B, and circuit interconnects 3530A-3530B of the integrated circuit 3500.

[0369] The graphics processor 3710 includes one or more shader cores 3715A to 3715N (e.g., 3715A, 3715B, 3715C, 3715D, 3715E, 3715F, all the way to 3715N-1 and 3715N), wherein the one or more shader cores provide a unified shader core architecture, wherein a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders and / or compute shaders. The exact number of shader cores present may vary between embodiments and implementations. In addition, the graphics processor 3710 also includes an inter-core task manager 3705, which acts as a thread dispatcher for dispatching execution threads to one or more shader cores 3715A to 3715N and a tiling unit 3718 for accelerating tiling operations for tile-based rendering, wherein rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize the use of internal caches.

[0370] The following clauses and / or examples refer to specific embodiments or examples thereof. Details in the examples may be used anywhere in one or more embodiments. Various features of different embodiments or examples may be combined in various ways with some features included and other features excluded to suit a variety of different applications. Examples may include subject matter such as methods, components for performing actions of the methods, at least one machine-readable medium including instructions that, when executed by a machine, cause the machine to perform the actions of the methods, or devices or systems according to the embodiments and examples described herein. Various components may be components for performing the operations or functions described.

[0371] Example 1 is directed to a computing device that performs machine learning operations, the computing device comprising: a decoding unit, which is used to decode a single instruction into a decoded instruction, wherein the decoded instruction enables the computing device to perform a complex machine learning computing operation.

[0372] Example 2 may include the subject matter of Example 1, and further include a fetch unit to fetch a single instruction.

[0373] Example three may include the subject matter of Example two, and further include parameter analysis logic to determine the type of machine learning operation to be performed for the single instruction.

[0374] Example 4 may include the subject matter of Example 3, and further includes machine learning acceleration logic that is used to determine a set of operations to be performed in order to execute the decoded instruction.

[0375] Example five may include the subject matter of Example four, further comprising a microcontroller executing firmware instructions, wherein the firmware instructions are used to implement the parameter analysis logic and the machine learning acceleration logic.

[0376] Example six may include the subject matter of Example one, wherein the complex machine learning computational operation is to perform a convolution for a convolutional neural network.

[0377] Example seven may include the subject matter of Example six, wherein the convolution comprises a plurality of matrix operations.

[0378] Example eight may include the subject matter of Example seven, further comprising a scheduler controller to schedule the plurality of matrix operations to one or more of a plurality of types of computing units.

[0379] Example nine may include the subject matter of Example eight, wherein the multiple types of computing units include general purpose graphics computing units and sparse computing units.

[0380] Example ten may include the subject matter of Example eight, wherein the plurality of types of computing units include general purpose graphics computing units and near data computing units.

[0381] Example 11 is directed to a method for performing machine learning operations, the method comprising: obtaining a single instruction and decoding the single instruction into a decoded instruction, wherein the decoded instruction is associated with a set of multiple machine learning operations to be executed via a computing pipeline of a general-purpose graphics processing unit; determining a set of pipeline commands for executing the set of multiple machine learning operations; and scheduling the set of pipeline commands to the computing pipeline of the general-purpose graphics processing unit.

[0382] Example twelve may include the subject matter of Example eleven, wherein determining a set of pipeline commands for performing the set of multiple machine learning operations comprises analyzing parameters associated with the decoded instructions.

[0383] Example thirteen may include the subject matter of Example eleven, further comprising retiring the decoded instructions in response to completion of the set of pipeline commands.

[0384] Example fourteen may include the subject matter of Example eleven, wherein the single instruction is to cause the general purpose graphics processing unit to perform a convolution for a layer of a convolutional neural network.

[0385] Example fifteen may include the subject matter of Example eleven, wherein scheduling the group of pipeline commands to the computing pipeline of the general graphics processing unit includes scheduling the group of pipeline commands to multiple computing pipelines, the multiple computing pipelines including a general computing pipeline and at least one computing pipeline selected from a sparse computing pipeline or a near data computing pipeline.

[0386] Example 16 is directed to a data processing system, comprising: a non-temporary machine-readable medium for storing instructions for execution by one or more processors of the data processing system; and a general-purpose graphics processing unit, comprising a fetch unit for fetching a single instruction and a decode unit for decoding the single instruction into a decoded instruction, wherein the decoded instruction causes the data processing system to execute multiple pipeline commands to perform complex machine learning computing operations.

[0387] Example seventeen may include the subject matter of Example sixteen, wherein the general purpose graphics processing unit includes parameter analysis logic and machine learning acceleration logic, wherein the parameter analysis logic is used to determine the type of machine learning operation to be performed for the single instruction, and the machine learning acceleration logic is used to determine multiple pipeline commands to be executed in order to perform the complex machine learning computing operation.

[0388] Example eighteen may include the subject matter of Example seventeen, wherein the general purpose graphics processing unit includes a microcontroller that executes firmware instructions, wherein the firmware instructions are used to implement the parameter analysis logic and the machine learning acceleration logic.

[0389] Example nineteen may include the subject matter of Example sixteen, further comprising a scheduler controller to schedule the plurality of matrix operations to one or more of the plurality of types of computational units.

[0390] Example 20 may include the subject matter of Example 19, wherein the plurality of types of compute units include a general purpose graphics compute unit, and one of a sparse compute unit or a near data compute unit.

[0391] The embodiments described herein refer to hardware configured to perform certain operations or have predetermined functionality, such as a specific configuration of an application-specific integrated circuit (ASIC). Such an electronic device typically includes a set of one or more processors coupled to one or more other components, such as one or more storage devices (non-temporary machine-readable storage media), user input / output devices (e.g., keyboards, touch screens, and / or displays), and network connections. The coupling of the processor set and other components is typically through one or more buses and bridges (also referred to as bus controllers). The storage devices and signals that carry network traffic represent one or more machine-readable storage media and machine-readable communication media, respectively. Thus, the storage device of a given electronic device typically stores code and / or data for execution on a set of one or more processors of the electronic device.

[0392] Of course, one or more parts of the embodiment can be implemented by using different combinations of software, firmware and / or hardware. Throughout this detailed description, for the purpose of explanation, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that embodiments can be put into practice without some of these specific details. In some instances, well-known structures and functions are not described in detail to avoid obscuring the inventive subject matter of the embodiment. Therefore, the spirit and scope of the present invention should be determined with respect to the appended claims.

Claims

1. A computing device for performing a machine learning operation, the computing device comprising: a decoding unit to decode a single instruction into a decoded instruction, the decoded instruction causing the computing device to perform a complex machine learning computing operation, wherein the decoded instruction is associated with a set of multiple machine learning operations to be executed via a computing pipeline of a general purpose graphics processing unit; as well as a memory controller including a near data computation unit; The operations include profiling computing operations to determine computational and memory complexities of the computing operations, and offloading computing operations with low computational complexity and high memory access complexity to a near data computing unit in a memory controller.

2. A computing device as described in claim 1, further comprising a fetch unit for fetching the single instruction.

3. A computing device as described in claim 2, further comprising parameter analysis logic that is used to determine the type of machine learning operation to be performed for the single instruction.

4. A computing device as described in claim 3, further comprising machine learning acceleration logic that is used to determine a set of operations to be performed in order to execute the decoded instruction.

5. The computing device of claim 4, further comprising a microcontroller that executes firmware instructions for implementing the parameter analysis logic and the machine learning acceleration logic.

6. A computing device as described in claim 1, wherein the complex machine learning computing operation is to perform convolution for a convolutional neural network.

7. A computing device as described in claim 6, wherein the convolution includes multiple matrix operations.

8. The computing device as described in claim 7 further comprises a scheduler controller, which is used to schedule the plurality of matrix operations to one or more of a plurality of types of computing units.

9. A computing device as described in claim 8, wherein the multiple types of computing units include general-purpose graphics computing units and sparse computing units.

10. The computing device of claim 8, wherein the plurality of types of computing units include general purpose graphics computing units and near data computing units.

11. A method of performing a machine learning operation, the method comprising: fetching a single instruction and decoding the single instruction into decoded instructions, the decoded instructions being associated with a set of multiple machine learning operations to be executed via a computation pipeline of a general purpose graphics processing unit; determining a set of pipeline commands for performing the set of the plurality of machine learning operations, wherein the operations include profiling the computational operations to determine computational and memory complexities of the computational operations, and offloading computational operations having low computational complexity and high memory access complexity to a near data computation unit in a memory controller; Dispatching the set of pipeline commands to a computation pipeline of the general purpose graphics processing unit; and The decoded instructions are retired in response to completion of the set of pipeline commands.

12. The method of claim 11, wherein determining a set of pipeline commands for performing the set of multiple machine learning operations comprises analyzing parameters associated with the decoded instructions.

13. The method of claim 11, wherein the single instruction is to cause the general purpose graphics processing unit to perform a convolution for a layer of a convolutional neural network.

14. The method of claim 11, wherein scheduling the set of pipeline commands to the computing pipeline of the general-purpose graphics processing unit includes scheduling the set of pipeline commands to multiple computing pipelines, the multiple computing pipelines including a general-purpose computing pipeline and at least one computing pipeline selected from a sparse computing pipeline or a near data computing pipeline.

15. A general purpose graphics processing device comprising means for executing the method as claimed in any one of claims 11 to 14.

16. A data processing system comprising: a non-transitory machine-readable medium for storing instructions for execution by one or more processors of the data processing system; as well as A general purpose graphics processing unit comprising a fetch unit for fetching a single instruction and a decode unit for decoding the single instruction into a decoded instruction, wherein the decoded instruction causes the data processing system to execute a plurality of pipeline commands to perform complex machine learning computational operations, wherein the operations include profiling the computational operations to determine computational and memory complexities of the computational operations, and offloading computational operations having low computational complexity and high memory access complexity to a near data computational unit in a memory controller.

17. The data processing system of claim 16, the general purpose graphics processing unit comprising parameter analysis logic to determine a type of machine learning operation to be performed for the single instruction.

18. The data processing system of claim 17, wherein the general purpose graphics processing unit comprises machine learning acceleration logic for determining a plurality of pipeline commands to be executed in order to perform the complex machine learning computational operation.

19. The data processing system of claim 18, wherein the general purpose graphics processing unit comprises a microcontroller that executes firmware instructions to implement the parameter analysis logic and the machine learning acceleration logic.

20. The data processing system of claim 19, wherein the complex machine learning computational operation is to perform a convolution for a convolutional neural network.

21. A data processing system as described in claim 20, wherein the convolution includes multiple matrix operations.

22. The data processing system of claim 21, further comprising a scheduler controller to schedule the plurality of matrix operations to one or more of a plurality of types of computing units.

23. The data processing system of claim 22, wherein the plurality of types of computing units include general purpose graphics computing units and sparse computing units.

24. The data processing system of claim 22, wherein the plurality of types of computing units include general purpose graphics computing units and near data computing units.

25. The data processing system of claim 22, wherein the plurality of types of computing units include general purpose graphics computing units, sparse computing units, and near data computing units.

26. A computer readable medium having stored thereon instructions which, when executed, cause a computing device to perform the method of any one of claims 11-14.

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