Variable Epoch Spike Train Filtering

Abstract

Variable epoch spike train filtering. Systems and techniques for variable epoch spike train filtering are described herein. A spike trace storage device can be initiated for an epoch. Here, the spike trace storage device is included in a neuron of neuromorphic hardware. Multiple spikes can be received at the neuron during the epoch. The spike trace storage device can be incremented for each of the multiple spikes to produce a count of the received spikes. An epoch learning event can be obtained, and a spike trace can be produced using the count of the received spikes in the spike trace storage device in response to the epoch learning event. The network parameters of the neuron can be modified using the spike trace.

Description

Technical Field

[0001] The present disclosure generally relates to digital signal processing, and more particularly to spike train filtering in spiking neural networks, where spike train filtering is tolerant to a wide range of learning epoch durations. Some examples are applicable to neuromorphic computing using digital neuromorphic cores. Background Art

[0002] A neuromorphic processor is a processor configured to mimic certain aspects of the brain and its underlying architecture, particularly its neurons and the interconnections between neurons, although such a processor may deviate from its biological counterpart. A neuromorphic processor may consist of many neuromorphic (neural network) cores interconnected via a network architecture such as a bus or routing device, which may direct communication between the cores. The network of cores may communicate via short packetized spike messages sent from core to core. Each core may implement a certain number of primitive non-linear time computational units (e.g., neurons). When the activation of a neuron exceeds a certain threshold level, it may generate a spike message, which is propagated to a set of fan-out neurons contained in the destination core. The network may then distribute the spike message to the destination neurons, and those neurons in turn update their activation in an instantaneous, time-dependent manner.

[0003] One or more state variables representing the activation level of a neuron may be maintained for each neuron. In typical operation, in response to the occurrence of a spike at an input or output, the state variable undergoes a step change, which decays exponentially as a function of time. Historically, analog architectures have been used to model neurons, which is well-suited for modeling exponentially decaying state variables. In digital neuromorphic architectures, modeling the exponential decay function presents multiple computational challenges. Brief Description of the Drawings

[0004] In the drawings, which are not necessarily to scale, the same reference numerals may describe similar components in different views. The same reference numerals with different letter suffixes may represent different instances of similar components. The drawings generally illustrate, by way of example and not by way of limitation, the various embodiments discussed in this document.

[0005] Figure 1 is a high-level diagram of a model neuromorphic core structure according to an embodiment.

[0006] Figure 2A is a diagrammatic illustration of the configuration and dendritic accumulation process of a multi-compartment neuron according to an embodiment.

[0007] Figure 2BIt is a diagrammatic view showing the state structure of multiple chambers according to an embodiment.

[0008] Figure 3A It is a block diagram illustrating the state dynamics of a dendritic chamber according to a simple neuron model according to an embodiment.

[0009] Figure 3B It is a block diagram illustrating the state dynamics of a dendritic chamber and the dendritic accumulation process according to a multi-chamber neuron model according to an embodiment.

[0010] Figure 4 It is a simplified timing diagram illustrating trace variables as a function of time according to an example use case according to an embodiment.

[0011] Figure 5 It is a block diagram illustrating component interactions for variable epoch spike train filtering according to an embodiment.

[0012] Figure 6 It illustrates a flowchart of an example of a method for variable epoch spike train filtering according to an embodiment.

[0013] Figure 7 It is a block diagram illustrating an example of a machine on which one or more embodiments can be implemented.

[0014] Figure 8 It is a block diagram of a register architecture according to an embodiment of the present invention.

[0015] Figure 9 It is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue / execution pipeline according to an embodiment of the present invention.

[0016] Figure 10 It is a block diagram illustrating both an exemplary embodiment of an in-order architecture core to be included in a processor and an exemplary register renaming, out-of-order issue / execution architecture core according to an embodiment of the present invention. <S

[0017] Figure 11A -B It illustrates a block diagram of a more specific exemplary in-order core architecture, where the core will be one of several logic blocks in a chip (including other cores of the same type and / or different types).

[0018] Figure 12 It is a block diagram of a processor according to an embodiment of the present invention, the processor may have more than one core, may have an integrated memory controller, and may have integrated graphics.

[0019] Figures 13 - 16 It is a block diagram of an exemplary computer architecture.

[0020] Figure 17A block diagram contrasting the use of a software instruction converter for converting binary instructions in a source instruction set into binary instructions in a target instruction set, according to an embodiment of the present invention. Detailed Description

[0021] Many biologically inspired neural network learning algorithms utilize filtered spike trains or "spike traces" as dynamic variables in equations that describe changes in network parameters over time. These trace variables typically span a range of filter time constants. Traces with small time constants measure the exact time offsets between neighboring spike events, while traces with large time constants measure the long-term average spike activity rate. Typically, spike traces have been handled via the application of an exponential decay between spike events. For example, when a first spike is received, the time offset from the last spike or other time reference is recorded in a temporary storage device. When a subsequent spike is received, the offset is used to decay the first spike to produce a trace. The spike trace is then used as a baseline to which the decay of the second spike is added. To limit the provision of the temporary storage device, a certain maximum offset time is typically supported, and this defines the learning epoch. The trace value will be updated at each learning epoch event based at least on the spike arrival time offset, and the learning rule of the network will be evaluated at each learning epoch. In this way, short or long learning epoch durations can be supported. However, for low-bit precision traces, due to rounding errors when combining several spike events, this technique only supports traces with small time constants with acceptable power or performance efficiency and accuracy.

[0022] To address this problem, a purely spike-based learning architecture can be extended by adjusting the values between spikes and modifying the exponential decay function to differently address single-spike events and multi-spike events. For example, in a multi-spike scenario, a temporary spike storage device can record the count of spikes rather than the time offset since the event. When performing a single exponential decay operation across these several spikes, this count can be used to reconstruct or model spike arrivals. In doing so, errors such as rounding errors are reduced and less computation is performed, resulting in higher accuracy and efficiency. However, for a single spike during a relevant epoch, storing the timing offset and using this timing offset for exponential decay provides high accuracy without additional computation. Thus, these enhancements greatly improve the efficiency and accuracy of large time constant traces (also referred to as rate-based traces) at a marginal additional implementation cost compared to baseline implementations.

[0023] Figures 1 - 4 Illustrated is an example of neuromorphic hardware, such as a neural core, and its operation - for example, in a baseline mode where each spike is exponentially decayed to update the spike trace. Figure 5 and 6Illustrated are modifications to these baseline examples, whereby spike counts are made and then that count is used in an exponential decay operation to update a spike trace.

[0024] Figure 1 is a high-level diagram of a model neural core architecture according to an embodiment. The neural core 145 can be on a die with several other neural cores to form a neural chip 150. A number of neural chips can also be packaged and networked together to form a neuromorphic hardware 155, which can be included in any number of devices such as servers, mobile devices, sensors, actuators, etc. The illustrated neural core architecture functionally models the behavior of biological neurons. At the input to synapses (modeled, for example, by the synaptic variable memory 105), signals (such as incoming spikes) are provided, and the synapses can include a fan-out within the core to other dendritic structures with appropriate weights and delay offsets. The signals can be modified by the synaptic variable memory 105 (e.g., synaptic weights can be applied to address spikes corresponding to the respective synapses), and can be made available to the neuron model 110. The neuron model 110 can include multiple components for modeling dendritic activity and soma activity. In an example, the architecture can include a dendritic accumulator and a soma state store. The neuron model 110 is configured to generate output spikes (e.g., outgoing spikes via an axon to one or several destination cores) based on the weighted spike state.

[0025] In an example, a neuromorphic computing system can employ spike-timing-dependent plasticity (STDP) learning. Here, a network of neural network cores communicates via short packetized spike messages sent from core to core. Each core implements a certain number of neurons that operate as primitive non-linear time computing units. When the activation of a neuron exceeds a certain threshold level, it generates a spike message that is propagated to a set of fan-out neurons included in a destination core. In managing its activation level, a neuron can maintain a trace variable (e.g., as an impulse response) that increments in response to spikes. Operations on the trace variable can model multiple time-related features. For example, following a spike, the trace variable can decay exponentially. This exponential decay, modeled as an exponential function, can continue for multiple time steps during which additional spikes may or may not arrive. Other example uses of the trace variable are discussed below (e.g., spike trace storage devices).

[0026] To facilitate spike trace management, storage device 115 can record temporary incoming spike information, and storage device 120 records temporary outgoing spike information. Additionally, persistent trace variable storage device 140 maintains trace information over time. Storage devices 115, 120, and 140 are used by trace computation circuitry 130 and 135 (such as a trace decay modeler) to provide updated incoming and outgoing traces for use by learning engine 125. At a learning epoch event (such as the end of an epoch), learning engine 140 uses incoming trace X, outgoing trace Y, and current synaptic weight W(old) to produce a new set of synaptic weights W(new). The new synaptic weights are then installed in synaptic variable memory 105 to modify (e.g., weight) future incoming spikes, thus modifying the likelihood of particular combinations of incoming spikes resulting in outgoing spikes. Thus, the architectural role of trace computation circuitry 130 and 135 is to maintain trace variable states X and Y, respectively, in response to spike events (incoming spikes) received as input to the core or spike events (outgoing spikes) generated by neuron units 110 within the core. Each spike event can generate a temporary state of trace computation that accumulates over the duration of an interval defined as Learning epoch a periodic time. At the end of each learning epoch, the learning engine modifies the synaptic variable state (W) as a function, in part, of the computed X and Y trace values.

[0027] The network distributes spike messages to destination neurons, and in response to receiving a spike message, those neurons update their activation in an instantaneous, time-dependent manner, which is similar to the operation of biological neurons.

[0028] A basic implementation of some applicable learning algorithms can be provided by spike-timing-dependent plasticity, which adjusts the strength of connections (such as synapses) between neurons in a neural network based on the timing correlation between input (e.g., incoming) spikes and output (e.g., outgoing) spikes. Input spikes that occur immediately following an output spike are considered causally related to the output and their weights are strengthened, while the weights of other input spikes are weakened. These techniques use spike times or model spike times to allow modification of the operation of a modeled neural network according to multiple machine learning paradigms (such as in an unsupervised learning paradigm or in a reinforcement learning paradigm).

[0029] The core can also support backpropagation processing. In biology, when the soma forms a spike (e.g., an outgoing spike), in addition to the spike propagating downstream to other neurons, the spike also propagates backward through the dendritic tree, which is beneficial for learning. Synaptic plasticity at the synapse is a function of when the postsynaptic neuron fires and when the presynaptic neuron is firing - the synapse knows when the neuron is fired. In a multi-compartment architecture, once the soma fires, there are other units that know the neuron has fired to support learning, e.g., so that all the input fan-in synapses can see the neuron firing. The learning engine 125 can implement spike-timing-dependent plasticity (STDP) and receive this backpropagating action potential (bAP) notification (e.g., via the trace calculation circuitry 135), and thus communicate with the synapse 105.

[0030] Figure 2A FIG. is a diagrammatic illustration of the configuration of a multi-compartment neuron and the dendritic integration process according to an embodiment. Figure 2A The figure of illustrates the dendritic (e.g., postsynaptic within a modeled neuron) integration process for disposing and scheduling incoming spikes into the future within a neural core. Synaptic inputs 210 are provided to the dendritic accumulator structure 220, which can be configured as a dedicated data store or a data structure allocated in a general-purpose data store to maintain a synaptic stimulus counter for the weight values for a particular compartment 230. In this context, the compartment 230 is an abstract neural unit that contains state and configuration variables 240 representing the dynamic state of the neuron. The compartment 230 is a component of the dendritic tree that can be processed sequentially with associated compartments. When a compartment is processed, some state information is retained for the compartment and passing this state information provides a wide class of information processing that can occur within the core.

[0031] The dendritic accumulator structure 220 can maintain a synaptic stimulus counter for the weight values for a particular compartment 230, where the compartment is a decomposition of the neural tree structure or simply an abstract neural unit. Each compartment 230 can have state variables (u, v) representing the dynamic state of the neuron.

[0032] The sequential process with the update logic 250 can traverse all these compartments 230, receive the accumulated synaptic stimuli and state variables 245 from each compartment in the compartment 230, and provide a spike output 255. Since this is a sequential process, the update logic 250 can retain the instantaneous state information associated with each compartment by utilizing a temporary register storage device in the logic. By propagating this information according to the data flow of the tree, the process can simulate the information processing of a biological dendritic tree.

[0033] Figure 2B FIG. is a diagrammatic illustration of the state structure of multiple compartments according to an embodiment. Figure 2BIllustrated is how the sequential iteration through chamber index 230 generally resembles a tree. Each in row 230 of this state structure, which can be a memory address in the core SRAM, represents a chamber 230 that receives synaptic input 210 via synaptic connection 260. The core walks through these, where numbers and state variables 245 are propagated from each of the chambers 230 until a final routing chamber 230A, which would be the soma (in biological nomenclature), provides spike output 255. Figure 2B All the other chambers 230 in Figure 2B operate in a similar manner and thereby transform and propagate the transient dendritic state. Any dendritic index can be configured as a chamber in a dendritic tree or a soma. Each chamber in the tree structure can transform and propagate (u,v) state variables according to a real-valued signal processing model as described below.

[0034] Figure 3A is a block diagram illustrating the state dynamics of a dendritic chamber according to a simple neuron model according to an embodiment. According to the dynamics of a dendritic chamber 300A according to a simple neuron model (the following use of the term "dendrite" is to be interpreted as synonymous with the phrase "dendritic chamber" and as an abbreviation of the phrase "dendritic chamber"), the dendritic chamber 300A is essentially a discrete-time filtering circuit. First state variable operations 310 based on a stored first state variable (in this example, current U) and the received spike input 210 can be performed. Then second state variable operations 320 based on a stored second state variable (in this example, voltage V) and the output of the first variable operations 310 can be subsequently performed. A threshold function 345 can be utilized to determine whether the dendritic chamber 300A should form a spike or at least indicate a spike value even if it does not actually form a spike.

[0035] Figure 3B is a block diagram illustrating the state dynamics of a dendritic chamber and the dendritic integration process according to a multi-chamber neuron model according to an embodiment. The dendritic chambers 300B, 300A can be, for example, the dendritic chambers 230 described above. Figure 3B The figure of Figure 3B is similar to Figure 3A the figure in Figure 3A , and the description of similar units will not be repeated. However, in the design shown in Figure 3B two points J U 330, J V 332 have been added in the logic to enhance the design for multi-chamber processing, where information from earlier chambers A, B340 in the sequential process can be concatenated.

[0036] As an example, a neuron can be stimulated with excitatory and inhibitory inputs, each with its own exponential filtering time constant. This spiking neuron model and networks of such neurons can implement powerful neural information processing algorithms (such as E / I networks).

[0037] For the multi-compartment support described herein, an E / I neuron can be constructed from two basic units, one integrating the "E" input with a τ E time constant and the other integrating the "I" input with a τ I time constant. In another example, a more complex single neuron model can include the complexity implemented by an E / I neuron. Since many neuromorphic algorithms may not require this complexity, the currently described architecture provides a flexible and efficient neuromorphic processing solution. The architecture can be generalized to an extremely flexible neuromorphic neuron processor that can be programmed to implement conventional neuron models (some potentially valuable for machine learning applications).

[0038] The structures described above provide a way to connect earlier inputs A, B 340 as in a tree structure, at the leaves of the dendritic tree. In each of these connection operations J U 330, J V 332, there are two state variables u (current) and v (voltage) of the interlink, and the state variables u (current) and v (voltage) are two dynamic variables. In this example, since there are two such variables, there are two different connection possibilities (junction points in the signal flow) 330, 332.

[0039] Current from the earlier input 340 can be provided at the first junction point 330, and voltage from the earlier input 340 can be provided at the second junction point 332. The spike function 322 can determine whether the spike threshold has been reached to determine whether to send a spike S 255 (or a value representing a spike), and in addition determine the value Y 350 of other information in the form of continuous data related to the current state of the dendritic compartment 300B (i.e., one or more numbers representing the state variables of the dendritic compartment 300B).

[0040] In biology, efficiency can be achieved by transmitting the number 350 (i.e., continuous data) instead of just transmitting the binary spike 255. The generation of neural networks focused on spike-based signaling is mainly driven by efficiency, which comes from using only the absolute minimum of information for long-distance parallel communication for energy and performance efficiency. Although it is possible to handle a large space of algorithmic problems with spike-based signaling methodology, this method can only go so far. There is still value in transmitting the number 350 instead of just transmitting the binary spike event 255 with a time code, especially when transmitted locally enough. For this purpose, biological neurons use their dendritic trees. The dendritic tree can be regarded as a spatially local region of the neuron, on which it is efficient to send continuous current or voltage values across the membrane of the neuron.

[0041] A series of connection operations similar to the instruction set of the core support can be provided. For example, one can add the u variable together with the input from another chamber. Or, instead of the addition operation, the multiplication operation can be used as a connection operation. For example, it can also include the AND of spike conditions such as whether the input chamber has exceeded its threshold and then whether the v of that chamber has exceeded its threshold - one can take the AND condition of the two, or the OR condition of the two. There are multiple different operations that can be defined (see Table 1 below).

[0042] Compared with the conventional feedforward artificial neural network model or a purely spike-based network, the structure including information from other chambers endows the dendritic tree structure with a great deal of computational power. This creates a very flexible interconnected dynamic system of these differential equation state variables. The design is characterized by a backward, event-driven sequential traversal of sequential units to propagate spike information back to the synapses for synaptic plasticity (e.g., the update of weights according to the STDP rule). The forward iteration on the interrupt unit is at the cost of performance and energy, and thus is only done sparingly, i.e., whenever the unit forms a spike. Usually, this occurs when a spike is formed at the root of the tree corresponding to the soma chamber of the neuron.

[0043] In biology, when the soma forms a spike, the spike propagates backward down through the dendritic tree - this is beneficial for learning. Generally speaking, synaptic plasticity at the synapse is a function of when the postsynaptic neuron fires and when the presynaptic neuron is firing, so the synapse needs to be notified when the neuron fires. Once the soma chamber fires, the multi-chamber architecture may pose a problem for learning because there are other input chambers that need to be notified of the neuron firing in order to support learning, so that all its input fan-in synapses can see the event. This can be part of the spike-timing-dependent plasticity (STDP) model, which can implement Hebbian learning, anti-Hebbian learning, and other models.

[0044] Backpropagation can be implemented to allow the core to send spikes backward in the absence of other configurations of the core. However, for efficiency reasons, it may not be desirable for backpropagation to be continuously active. Since a time-multiplexed pipelined implementation (for efficient hardware implementation) is used, there are multiple forward processing steps that are all in execution when the system is traversing all the chambers. Backward spike propagation can be considered analogous to exceptions in normal processor technology. The pipeline can be flushed, and the processing can return to a known point. Here, when traversing each chamber, the processing will identify the spike chamber - at this moment the processor may need to flush the active chambers and then perform a backward traversal / propagation. In the example, the spike events thus backpropagated are then stored in the postsynaptic trace state storage device 120.

[0045] Figure 4 FIG. is a simplified timing diagram of a trace variable 402 as a function of time according to an example use case according to an embodiment. According to an embodiment, the trace variable 402 can be maintained at a neuron as a function of time t. For simplicity and ease of illustration, the trace variable 402 is depicted as a continuous function over time periods T1 - T9, although in an actual embodiment, each time period T1 - T9 may contain 50 - 100 actual discrete time increments, and the value of the trace variable 402 will remain constant for the duration of each individual time step.

[0046] Input stimuli 404A, 404B, and 404C (collectively input events 404) are depicted as pulses, which can be spikes at the input or output of a neuron. In some implementations, the input events 404 can vary in their weighting aspects. Each input stimulus 404A - 404C causes a response in the neuron that affects the trace variable 402. In the depicted example, each input stimulus causes a step change in the positive direction indicated at 406A, 406B, and 406C, followed by an exponential decay as indicated at 408A, 408B, and 408C. The exponential decay 408 follows an exponential curve that can be defined by a time constant τ. The neuron can be configured with an activation threshold 410, and when the trace variable exceeds the activation threshold 410 (as depicted at 412 and 414), it may cause a corresponding activation response, such as an output spike or a change in the input weights or threshold of the neuron (not depicted). The resulting trace is a filtered time spike train trace.

[0047] At n each exponential decay function's basic calculation over a time increment can be expressed as , where x 0 represents the initial value, and αis the decay factor corresponding to the time constant τ of the exponential function. As a basic method, n multiplication operations will be calculated. However, according to some embodiments, n The N-bit expression of can be represented in binary as n i representing the binary value of each bit position i Advantageously, the calculation technique reduces the x n calculation to at most [log2 n multiplication operations.

[0048] In related embodiments, to improve computational efficiency, the number N constant of is pre-calculated and stored in a data store to be looked up instead of calculated.

[0049] In related embodiments, a neuron performs a delay calculation of an exponential decay function at a time when the delay value of the exponential decay function is to be used for processing or making a decision (such as in response to an input stimulus). Thus, during the time increment when there is no input stimulus, the neuron engine does not need to calculate the exponential decay of the trace variable. This saves the system from having to expend energy and computational resources, especially when the delay calculation of the delayed result can be performed with fewer operations, as illustrated above. When performing the delayed exponential decay calculation, consider the time increment during which the function undergoes decay.

[0050] Figure 4 The exponential decay illustrated in

[0051] To address these issues, the spike time offset (e.g., SpikeTime) state associated with each trace variable within each learning epoch can be re - utilized. Instead of maintaining the spike offset time (e.g., SpikeTime), when so configured, this state is used to count the number of spike events (e.g., SpikeCount) received during the learning epoch, and a downstream exponential decay machinery then provides a superset of what is arithmetically required for calculating long - time scale (rate averaging) trace values with high accuracy. Under the assumption that SpikeCount spikes occur evenly spaced in time, compared to the above - mentioned baseline solution, with negligible additional configuration parameters and logic, the trace function can support precise spike train filtering.

[0052] Referring back to Figure 1 , the trace calculation unit is used to perform SpikeCount - based decay of spikes to produce spike traces. Thus, in response to spike events received as input to the core (incoming spikes) or spike events generated by neuron units within the core (outgoing spikes), the trace calculation maintains trace variable states X and Y respectively. Each spike event generates a temporary state for trace calculation that accumulates over the duration of an interval defined as the periodic time of a learning epoch. At the end of each learning epoch, the learning engine modifies the synaptic variable state (W) as a function of the calculated X and Y trace values. In the example, Figure 1 the hardware architecture shown in

[0053] In the baseline trace calculation described above, the above - indicated temporary (e.g., per - epoch) trace state is the spike time offset within the epoch in which the spike occurs. For each spike event, the old trace variable (e.g., X(old)) is exponentially decayed to the time of the spike, where the spike count is then added and again decayed to the end of the epoch (e.g., decayed to the current time). The updated trace values X and Y (e.g., X(new) and Y(new)) are then presented to the learning engine.

[0054] For learning rules that expect high temporal precision, such exact decay calculations may be useful in order to distinguish spike time differences at the granularity of a single time step. However, when the learning rule expects trace values that have been averaged over a large number of spike events (e.g., filtered with a large time constant), the trace values become insensitive to specific time offsets within an epoch. In this case, temporally exact decay calculations may be unnecessarily expensive (e.g., in terms of processing time, storage usage, etc.). Additionally, considering the very low bit precision of typical neuromorphic implementations, rounding errors may be relatively large (e.g., even for stochastic rounding) and apply to each individual decay calculation. For rate traces, rounding errors thus accumulate and may significantly reduce the final accuracy of the trace results as presented to the learning engine.

[0055] Figure 5 is a block diagram illustrating component interactions for variable epoch spike train filtering according to an embodiment. These interactions illustrate enhancements to the Figure 4 baseline decay operation to address the issues pointed out above. For example, instead of storing individual spike arrival time values within an epoch (e.g., in a "temporary trace state storage device" memory), a cumulative spike count 510 is maintained for incoming spikes 505. The count 510 is reset to zero at the start of each epoch and then incremented on each spike event during the epoch. In the example, the count 510 has a maximum supported value, after which additional spikes will not be counted. Spike counting is the only per-spike processing performed.

[0056] To simulate the arrival time of the counted spikes, the count 510 can be scaled 515 by an ISI parameter. In the example, a single ISI parameter corresponds to the minimum inter-spike interval (e.g., spike spacing), which is used to scale the total spike count 515 within an epoch to a pulse value that is optimal for the dynamic range of the trace variable:

[0057] (1)Impulse = (SpikeCount * (ISI+1)) * 2 SHIFT+1

[0058] where 'SHIFT' is a constant that depends on the bit width of the trace variable (e.g., SHIFT = width of the trace state variable minus the width of the maximum SpikeCount*(ISI+1) product). Given the Impulse value from equation (1), the trace calculation can apply a single exponential decay calculation 520 for each epoch to the trace value X[i-1] of the previous epoch to obtain the end-of-epoch trace value X[i] 525:

[0059] (2)X[i] = expDecay(Tau, Tepoch, X[i-1] – Impulse) + Impulse

[0060] where expDecay() exponentially decays the "X[i-1]-Impulse" trace input value over Tepoch time steps (e.g., the number of time steps in an epoch period) with a certain time constant Tau. For example, this function can be implemented in the manner described above with respect to Figure 4 the description. According to this implementation, as long as Tepoch is a power of two (e.g., 2, 4, 8, 16, 32, etc.), only a single multiplication and stochastic rounding are used, which is the minimum possible.

[0061] Mathematically, calculating Impulse and X[i] in the manner described in equations (1) and (2) corresponds to the ideal case where SpikeCount spike events occur evenly spaced over an epoch at intervals of Tepoch / SpikeCount, with the first event delayed by Tepoch / (SpikeCount*2). This is the optimal spike pattern for minimizing numerical jitter in the trace values 525 calculated from epoch to epoch.

[0062] The advantage of using SpikeCount decay over baseline SpikeTime decay is the reduction in rounding error over larger epoch time frames and increased computational efficiency. In a fully spike-based baseline solution (e.g., where each SpikeTime is tracked and decayed), there is no "spike counter" accumulation stage, which is used here to aggregate multiple spikes into a single event for each epoch disposal. A fully spike-based solution typically activates the exponential decay circuitry twice for each spike: once for the decay trace value obtained at the spike time before adding a new spike pulse, and a second time to obtain the end-of-epoch trace value. Depending on the implementation of the expDecay() function (e.g., in hardware), each exponential decay can further perform more than one multiplication operation for each decay iteration. Thus, while a fully spike-based implementation is more faithful to the underlying biological model, it is both less accurate due to numerical rounding effects and less computationally efficient than a SpikeCount-based solution. The following table illustrates some of the differences between the SpikeTime baseline and the SpikeCount architecture:

[0063]

[0064] SpikeCount can be minimally modified to account for the accuracy of the SpikeTime regime for sparse spikes in an epoch. That is, the spike-time based trace decay (e.g., SpikeTime regime) and spike-count based rate decay (e.g., SpikeCount regime) patterns need not be mutually exclusive for a particular trace variable. In an example, an additional bit in a temporary SpikeTime / SpikeCount trace status value can be used to distinguish values between a "one spike with SpikeTime" and "more than one spike with SpikeCount" situation. In the former case, the trace variable can be updated in a time-precise manner based on the spike-time offset (e.g., SpikeTime). In this case, baseline decay is applied to the SpikeTime value. In the latter case, an optimized rate-based approximation can be applied as a function of the SpikeCount value. Such an implementation optimally unifies trace calculations across spike-based and rate-based regimes.

[0065] Figure 6 FIG. illustrates an example flow diagram of a method 600 for variable epoch spike train filtering according to an embodiment. The operations of method 600 are performed by computer hardware such as the computer hardware described above (e.g., neuromorphic hardware) or the computer hardware described below (e.g., processing circuitry).

[0066] At operation 605, a spike trace storage device (e.g., a temporary trace variable storage device or the like) is initiated (e.g., set to a default value, reset, etc.) for an epoch. In an example, the spike trace storage device is included in a neuron of neuromorphic hardware. In an example, the spike trace storage device is a register of a neuron. An epoch is a time period during which a neuron is modified. That is, the behavior of the neuron with respect to how it generates outgoing spikes based on incoming spikes changing is constant for an epoch. The time period can be defined by a time step of the neuromorphic hardware such that the time step is incremented based on some signaling activity (or opportunity) within the neuromorphic hardware rather than an external record of elapsed time (such as elapsed seconds, minutes, etc.).

[0067] At operation 610, a plurality of spikes can be received at a neuron during an epoch.

[0068] At operation 615, the spike trace storage device is incremented for each of the plurality of spikes to produce a count of the received spikes. As noted above, the spike trace storage device is keeping track of how many spikes arrive rather than the time offset at which the spikes arrive.

[0069] At operation 620, an epoch learning event is obtained. In an example, the epoch learning event is the end of an epoch. The epoch learning event can be signaled (e.g., received by) a neuron, or the neuron can sense (e.g., retrieve) the epoch event from an external source (e.g., a metadata register of neuromorphic hardware). The epoch learning event signals the activity in the neural core for learning (e.g., updating) purposes at the start of each epoch rather than for each spike.

[0070] At operation 625, a spike trace is generated in response to the epoch learning event using a count of received spikes in a spike trace storage device. In an example, generating the spike trace using the count of received spikes includes scaling the count of received spikes by a constant. In an example, the constant is the minimum inter-spike interval. In an example, generating the spike trace using the count of received spikes includes multiplying the scaled count of received spikes by two to the power of SHIFT + 1. Here, SHIFT is a constant. It is a constant defined by the width of the spike trace storage device minus the width of the maximum scaled count of received spikes. In an example, SHIFT is defined by the width of the spike trace storage device (e.g., in bits) minus the width of the maximum scaled count of received spikes. These operations allow for spike reconstruction based on spike counts. Although individual spikes may have arrived at different offsets, the model assumes uniform arrival times of spikes. A decay model can be applied to these reconstructed spikes.

[0071] In an example, generating the spike trace using the count of received spikes includes applying a single exponential decay to a previous epoch trace value to obtain the spike trace. This illustrates applying the decay once per epoch rather than once per spike as in the baseline architecture described above. In an example, the single exponential decay is calculated by the following equation:

[0072] X[i] = expDecay (Tau, Tepoch, X[i-1] – Impulse) + Impulse

[0073] where X[i] is the spike trace, X[i-1] is the previous epoch trace, Impulse is the scaled count of received spikes, Tepoch is the number of time steps in an epoch, and Tau is a constant. In an example, Tepoch is a power of two.

[0074] At operation 630, the spike trace (e.g., X[i]) can be used to modify the neural connections of a neuron. In an example, modifying the neural connections of a neuron using the spike trace includes modifying the synaptic variable state as a function of the spike trace. Thus, learning is based on, for example, Figure 1The interaction of incoming and outgoing spikes modeled by the trace calculation circuitry and the programmable learning engine adjusts the synaptic weights as it occurs.

[0075] The examples described above specifically relate to the use of spike counters rather than spike time offsets. However, the operations of method 600 can be extended to include a hybrid model, whereby individual spikes during an epoch can be processed (e.g., decayed) according to a baseline architecture, and multiple spikes can be processed as described above. For example, method 600 can include initiating a spike trace storage device for a second epoch, receiving an individual spike during the second epoch, and storing the spike arrival (e.g., spike time offset) since the epoch in the spike trace storage device. Here, if no other spikes are received during the epoch, then upon obtaining a second epoch learning event for the second epoch, method 600 can generate a second spike trace using the spike arrival since the epoch in the spike trace storage device in response to the second epoch learning event. In an example, generating the second spike trace using the spike arrival since the epoch in response to the second epoch learning event includes applying exponential decay based on the spike arrival since the epoch. Thus, the second spike trace can use SpikeTime exponential decay rather than the SpikeCount decay described above with respect to operation 625. In an example, the spike trace storage device includes a bit indicating whether an individual spike or multiple spikes arrived during a given epoch, and wherein the exponential decay of the spike trace storage device, either as a count of received spikes or the spike arrival since the epoch, is controlled by the bit. Method 600 can then use the second spike trace to modify the neural connection of the neuron.

[0076] Figure 7The block diagram of an example machine 700 is illustrated on which any one or more of the techniques (e.g., methods) discussed herein can be performed. Examples as described herein can include logic or multiple components or mechanisms in machine 700 or can be operated by logic or multiple components or mechanisms in machine 700. A circuit system (e.g., a processing circuit system) is a collection of circuits implemented in a tangible entity of machine 700 that includes hardware (e.g., simple circuits, gates, logic, etc.). The members of the circuit system can be flexible over time. The circuit system includes members that can perform specified operations individually or in combination when operating. In an example, the hardware of the circuit system can be immutably designed to perform specific operations (e.g., hardwired). In an example, the hardware of the circuit system can include physically components that are variably connected (e.g., execution units, transistors, simple circuits, etc.), including machine-readable media that are physically modified (e.g., magnetically, electrically, movable placement of immovable mass particles, etc.) to encode instructions for specific operations. When connecting physical components, the underlying electrical properties of the hardware components are changed, for example, from insulators to conductors or vice versa. Instruction-enabled embedded hardware (e.g., execution units or loading mechanisms) create members of the circuit system via variable connections to the hardware to perform portions of specific operations when in operation. Thus, in an example, the machine-readable media unit is part of the circuit system or is communicatively coupled to other components of the circuit system when the device is operating. In an example, any physical component in the physical components can be used in more than one member of more than one circuit system. For example, in operation, an execution unit can be used in a first circuit of a first circuit system at one point in time and reused by a second circuit in the first circuit system or by a third circuit in a second circuit system at different times. Following are additional examples of these components of machine 700.

[0077] In alternative embodiments, machine 700 can operate as a stand-alone device or can be connected (e.g., networked) to other machines. In a networked deployment, machine 700 can operate in the capacity of a server machine, a client machine, or both in a server-client network environment. In an example, machine 700 can act as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. Machine 700 can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, web device, network router, switch or bridge, or any machine capable of executing instructions (sequential or otherwise) specifying actions to be taken by that machine. Further, while only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods discussed herein, such as cloud computing, software as a service (SaaS), other computer cluster configurations.

[0078] Machine (e.g., computer system) 700 can include a hardware processor 702 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), a main memory 704, a static memory (e.g., a memory or storage device for firmware, microcode, basic input / output (BIOS), unified extensible firmware interface (UEFI), etc.) 706, and a mass storage device 708 (e.g., a hard disk drive, a tape drive, a flash storage device, or other block device), some or all of which may communicate with each other via a link (e.g., a bus) 730. Machine 700 can further include a display unit 710, an alphanumeric input device 712 (e.g., a keyboard), and a user interface (UI) navigation device 714 (e.g., a mouse). In an example, the display unit 710, the input device 712, and the UI navigation device 714 can be a touch screen display. Machine 700 can additionally include a storage device (e.g., a drive unit) 708, a signal generation device 718 (e.g., a speaker), a network interface device 720, and one or more sensors 716, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensors. Machine 700 can include an output controller 728, such as a serial (e.g., universal serial bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection for communicating or controlling one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0079] The registers of the processor 702, main memory 704, static memory 706, or mass storage device 708 can be or include a machine-readable medium 722 that stores one or more sets of data structures or instructions 724 (e.g., software) that implement any one or more of the techniques or functions described herein or that are utilized by any one or more of the techniques or functions described herein. During execution by the machine 700, the instructions 724 can also reside entirely or at least partially within any one of the registers of the processor 702, main memory 704, static memory 706, or mass storage device 708. In an example, one or any combination of the hardware processor 702, main memory 704, static memory 706, or mass storage device 708 can constitute the machine-readable medium 722. Although the machine-readable medium 722 is illustrated as a single medium, the term "machine-readable medium" can include a single medium or multiple media (e.g., a centralized or distributed database or associated caches and servers) configured to store one or more instructions 724.

[0080] The term "machine-readable medium" can include any medium that is capable of storing, encoding, or carrying instructions for execution by the machine 700 and that causes the machine 700 to perform any one or more of the techniques of this disclosure, or any medium that is capable of storing, encoding, or carrying a data structure used by or associated with such instructions. Non-limiting examples of machine-readable media can include solid-state memory, optical media, magnetic media, and signals (e.g., radio frequency signals, other photon-based signals, sound signals, etc.). In an example, a non-transitory machine-readable medium includes a machine-readable medium having a plurality of particles that have invariant (e.g., rest) mass and are thus constituents of matter. Thus, a non-transitory machine-readable medium is a machine-readable medium that does not include transitory propagated signals. Specific examples of non-transitory machine-readable media can include: non-volatile memory such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)), and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0081] Instructions 724 can further be transmitted or received via a communication network 726 using a transmission medium via a network interface device 720 using any one of a plurality of transmission protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.). Among other things, example communication networks can include local area networks (LANs), wide area networks (WANs), packet data networks (e.g., the Internet), mobile telephone networks (e.g., cellular networks), plain old telephone (POTS) networks, and wireless data networks (e.g., Institute of Electrical and Electronics Engineers (IEEE) 802.11 series standards known as Wi-Fi®, IEEE 802.16 series standards known as WiMax®, IEEE 802.15.4 series standards, peer-to-peer (P2P) networks). In an example, network interface device 720 can include one or more physical jacks (e.g., Ethernet, coaxial, or phone jacks) or one or more antennas to connect to communication network 726. In an example, network interface device 720 can include multiple antennas to communicate wirelessly using at least one of single input multiple output (SIMO), multiple input multiple output (MIMO), or multiple input single output (MISO) techniques. The term "transmission medium" shall be understood to include any tangible medium that can store, encode, or carry instructions for execution by machine 700, and includes digital or analog communication signals or other intangible media that facilitate the communication of such software. The transmission medium is a machine-readable medium.

[0082] Figures 8 to 17 Illustrated are several additional examples of hardware structures or implementations that can be used to implement computer hardware.

[0083] Figure 8 is a block diagram of a register architecture 800 according to one embodiment of the present invention. In the illustrated embodiment, there are 32 vector registers 810 that are 512 bits wide; these registers are referred to as zmm0 through zmm31. The lower 256 bits of the lower 16 zmm registers are overlaid on registers ymm0-16. The lower 128 bits of the lower 16 zmm registers (the lower 128 bits of the ymm registers) are overlaid on registers xmm0-15.

[0084] Write mask registers 815 - In the illustrated embodiment, there are 8 write mask registers (k0 through k7), each 64 bits in size. In an alternative embodiment, write mask registers 815 are 16 bits in size. As previously described, in one embodiment of the present invention, vector mask register k0 cannot be used as a write mask; when the encoding that would normally indicate k0 is used for a write mask, it selects a hard-wired write mask of 0xFFFF, effectively disabling write masking for that instruction.

[0085] General-purpose registers 825 - In the illustrated embodiment, there are sixteen 64-bit general-purpose registers, which are used together with existing x86 addressing modes to address memory operands. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0086] Scalar floating-point stack register file (x87 stack) 845 on which the MMX packed integer plane register file 850 is aliased - In the illustrated embodiment, the x87 stack is an eight-element stack used to perform scalar floating-point operations on 32 / 64 / 80-bit floating-point data using the x87 instruction set extension, while the MMX registers are used to perform operations on 64-bit packed integer data and to hold operands for certain operations performed between the MMX and XMM registers.

[0087] Alternative embodiments of the present invention may use wider or narrower registers. Additionally, alternative embodiments of the present invention may use more, fewer, or different register files and registers.

[0088] The processor core can be implemented in different ways, for different purposes, and in different processors. For example, the implementation of such a core can include: 1) a general-purpose in-order core intended for general computing; 2) a high-performance general-purpose out-of-order core intended for general computing; 3) a specialized core mainly intended for graphics and / or scientific (throughput) computing. The implementation of different processors can include: 1) a CPU including one or more general-purpose in-order cores intended for general computing and / or one or more general-purpose out-of-order cores intended for general computing; and 2) a coprocessor including one or more specialized cores mainly intended for graphics and / or scientific (throughput). Such different processors result in different computer system architectures, which can include: 1) a coprocessor on a chip separate from the CPU; 2) a coprocessor on a separate die in the same package as the CPU; 3) a coprocessor on the same die as the CPU (in which case such a coprocessor is sometimes referred to as specialized logic, such as integrated graphics and / or scientific (throughput) logic, or as a specialized core); and 4) a system-on-a-chip that can include the described CPU (sometimes referred to as (one or more) application cores or (one or more) application processors), the coprocessor described above, and additional functionality on the same die. An exemplary core architecture is described next, followed by a description of exemplary processor and computer architectures.

[0089] Figure 9is a block diagram schematically showing both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue / execution pipeline in accordance with an embodiment of the present invention. Figure 10 is a block diagram schematically showing both an exemplary embodiment of an in-order architecture core to be included in a processor and an exemplary register renaming, out-of-order issue / execution architecture core in accordance with an embodiment of the present invention. Figure 9 The solid boxes in FIGS. -B schematically show the in-order pipeline and in-order core, while the optional addition of the dashed boxes schematically shows the register renaming, out-of-order issue / execution pipeline and core. Since the in-order aspects are a subset of the out-of-order aspects, the out-of-order aspects will be described.

[0090] In Figure 9 a processor pipeline 900 includes a fetch stage 902, a length decoding stage 904, a decode stage 906, an allocation stage 908, a rename stage 910, a schedule (also known as dispatch or issue) stage 912, a register read / memory read stage 914, an execution stage 916, a write-back / memory write stage 918, an exception handling stage 922, and a commit stage 924.

[0091] Figure 10 shows a processor core 990 including a front-end unit 930 coupled to an execution engine unit 950, and both the front-end unit 930 of the execution engine unit 950 are coupled to a memory unit 970. The core 990 may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As another option, the core 990 may be a specialized core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general purpose computing graphics processing unit (GPGPU) core, a graphics core, or the like.

[0092] The front-end unit 930 includes a branch prediction unit 932 coupled to an instruction cache unit 934, the instruction cache unit 934 being coupled to an instruction translation lookaside buffer (TLB) 936, the instruction translation lookaside buffer (TLB) 936 being coupled to an instruction fetch unit 938, and the instruction fetch unit 938 being coupled to a decode unit 940. The decode unit 940 (or decoder) may decode the instructions and generate, as output, one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals decoded from the original instructions or otherwise reflecting or derived from the original instructions. Various different mechanisms may be used to implement the decode unit 940. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memories (ROMs), etc. In one embodiment, the core 990 includes a microcode ROM or other medium (e.g., in the decode unit 940 or otherwise within the front-end unit 930) storing microcode for certain microinstructions. The decode unit 940 is coupled to a rename / allocator unit 952 in an execution engine unit 950.

[0093] The execution engine unit 950 includes a rename / allocator unit 952 coupled to a retirement unit 954 and a set of one or more scheduler units 956. The one or more scheduler units 956 represent any number of different schedulers, including reservation stations, a central instruction window, etc. The one or more scheduler units 956 are coupled to the one or more physical register file units 958. Each of the one or more physical register file units 958 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integers, scalar floating points, packed integers, packed floating points, vector integers, vector floating points, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the one or more physical register file units 958 include a vector register unit, a write mask register unit, and a scalar register unit. These register units may provide architectural vector registers, vector mask registers, and general-purpose registers. The one or more physical register file units 958 are overlapped by the retirement unit 954 to illustrate the various ways in which register renaming and out-of-order execution may be implemented (e.g., using one or more reorder buffers and one or more retirement register files; using one or more future heaps, one or more history buffers, and one or more retirement register files; using register maps and pools of registers; etc.). The retirement unit 954 and the one or more physical register file units 958 are coupled to the one or more execution clusters 960. The one or more execution clusters 960 include a set of one or more execution units 962 and a set of one or more memory access units 964. The execution units 962 may perform various operations (e.g., shift, add, subtract, multiply) and perform various operations on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include multiple execution units dedicated to a specific function or set of functions, other embodiments may include only one execution unit or multiple execution units that perform all functions. The one or more scheduler units 956, the one or more physical register file units 958, and the one or more execution clusters 960 are shown as potentially plural because certain embodiments create separate pipelines for certain types of data / operations (e.g., scalar integer pipelines, scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipelines, and / or memory access pipelines each having their own scheduler unit, one or more physical register file units, and / or execution cluster - and in the case of separate memory access pipelines, certain embodiments are executed, in which only the execution cluster of that pipeline has the one or more memory access units 964).It should also be understood that in the case of using separate pipelines, one or more of these pipelines can be out-of-order issue / execution and the rest are in-order.

[0094] A set of memory access units 964 is coupled to a memory unit 970, which includes a data TLB unit 972 coupled to a data cache unit 974, and the data cache unit 974 is coupled to a level 2 (L2) cache unit 976. In one exemplary embodiment, the memory access units 964 can include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 972 in the memory unit 970. An instruction cache unit 934 is further coupled to the level 2 (L2) cache unit 976 in the memory unit 970. The L2 cache unit 976 is coupled to one or more other levels of cache and ultimately to the main memory.

[0095] As an example, an exemplary register renaming, out-of-order issue / execution core architecture can implement pipeline 900 as follows: 1) Instruction fetch 938 performs the fetch and length decoding stages 902 and 904; 2) The decode unit 940 performs the decode stage 906; 3) The rename / allocator unit 952 performs the allocation stage 908 and the rename stage 910; 4) The (one or more) scheduler units 956 perform the schedule stage 912; 5) The (one or more) physical register file units 958 and the memory unit 970 perform the register read / memory read stage 914; The execution cluster 960 performs the execution stage 916; 6) The memory unit 970 and the (one or more) physical register file units 958 perform the write-back / memory write stage 918; 7) Various units may be involved in the exception handling stage 922; and 8) The retirement unit 954 and the (one or more) physical register file units 958 perform the commit stage 924.

[0096] The core 990 can support one or more instruction sets (e.g., the x86 instruction set (with some extensions that have been added to more recent versions); the MIPS instruction set of MIPS Technologies, Sunnyvale, CA; the ARM instruction set of ARM Holdings, Sunnyvale, CA (with optional additional extensions such as NEON)), including the (one or more) instructions described herein. In one embodiment, the core 990 includes logic for supporting packed data instruction set extensions (e.g., AVX1, AVX2), thereby allowing operations used by many multimedia applications to be performed using packed data.

[0097] It should be understood that the core can support multi-threading (two or more parallel sets of executing operations or threads), and can do so in a variety of ways, including time-sliced multi-threading, simultaneous multi-threading (where a single physical core provides a logical core for each of the threads of simultaneous multi-threading of the physical core), or a combination thereof (e.g., time-sliced fetching and decoding and subsequent simultaneous multi-threading such as in Intel® Hyper-Threading Technology).

[0098] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming can be used in an in-order architecture. Although the illustrated embodiments of the processor also include separate instruction and data cache units 934 / 974 and a shared L2 cache unit 976, alternative embodiments can have a single internal cache for both instructions and data, such as for example a level 1 (L1) internal cache or a multi-level internal cache. In some embodiments, the system can include a combination of an internal cache and an external cache, the external cache being external to the core and / or the processor. Alternatively, all caches can be external to the core and / or the processor.

[0099] Figure 11A -FIG. -B illustrates a block diagram of a more specific exemplary in-order core architecture, where the core would be one of several logical blocks in a chip (including other cores of the same type and / or different types). Depending on the application, the logical blocks communicate with certain fixed function logic, memory I / O interfaces, and other necessary I / O logic via a high-bandwidth interconnect network (e.g., a ring network).

[0100] Figure 11A is a block diagram of a single processor core according to an embodiment of the present invention, along with its connections to the on-die interconnect network 1102 and a local subset of its level 2 (L2) cache 1104. In one embodiment, the instruction decoder 1100 supports the x86 instruction set with packed data instruction set extensions. The L1 cache 1106 allows low-latency access to cache memory into the scalar and vector units. Although in one embodiment (for simplicity of design), the scalar unit 1108 and the vector unit 1110 use separate register sets (scalar registers 1112 and vector registers 1114 respectively), and the data passed between them is written to memory and then read back from the level 1 (L1) cache 1106, alternative embodiments of the present invention can use different methods (e.g., using a single register set or including a communication path that allows data to be passed between two register files without being written and read back).

[0101] The local subset of the L2 cache 1104 is a portion of the global L2 cache that is partitioned into separate local subsets, one for each processor core. Each processor core has a direct access path to its own local subset of the L2 cache 1104. Data read by a processor core is stored in its L2 cache subset 1104 and can be quickly accessed in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 1104 and flushed from other subsets if necessary. The ring network ensures consistency for shared data. The ring network is bidirectional to allow agents such as processor cores, L2 caches, and other logic blocks to communicate with each other within the chip. Each ring data path is 1012 bits wide in each direction.

[0102] Figure 11B is an expanded view of a portion of a processor core in accordance with an embodiment of the present invention. Figure 11A Figure 11B Includes a portion of the L1 data cache 1106A that includes the L1 cache 1104, and more details regarding the vector unit 1110 and the vector registers 1114. Specifically, the vector unit 1110 is a 16-width vector processing unit (VPU) (see the 16-width ALU 1128) that executes one or more of integer, single-precision floating-point, and double-precision floating-point instructions. The VPU supports dispatching register inputs with a swizzle unit 1120, performing numerical conversions with numerical conversion units 1122A-B, and replicating memory inputs with a replication unit 1124. A write mask register 1126 allows for speculative vector writes.

[0103] Figure 12 is a block diagram of a processor 1200 in accordance with an embodiment of the present invention, the processor 1200 may have more than one core, may have an integrated memory controller, and may have an integrated graphics device. Figure 12 The solid box in illustrates a processor 1200 having a single core 1202A, a system agent 1210, and a collection of one or more bus controller units 1216, while the optional addition of the dashed box illustrates an alternative processor 1200 having a collection of multiple cores 1202A-N, one or more integrated memory controller units 1214 within the system agent unit 1210, and dedicated logic 1208.

[0104] Accordingly, different implementations of the processor 1200 can include: 1) a CPU having dedicated logic 1208 (which can include one or more cores) that is an integrated graphics device and / or scientific (throughput) logic and cores 1202A-N that are one or more general-purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, a combination of both); 2) a coprocessor having cores 1202A-N that are a large number of dedicated cores primarily intended for graphics and / or scientific (throughput); and 3) a coprocessor having cores 1202A-N that are a large number of general-purpose in-order cores. Accordingly, the processor 1200 can be a general-purpose processor, a coprocessor, or a special-purpose processor, such as, for example, a network or communication processor, a compression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including 30 or more cores), an embedded processor, or the like. The processor can be implemented on one or more chips. The processor 1200 can be part of one or more substrates using any of a plurality of processing technologies (such as, for example, BiCMOS, CMOS, or NMOS) and / or can be implemented on one or more substrates using any of a plurality of processing technologies (such as, for example, BiCMOS, CMOS, or NMOS).

[0105] The memory hierarchy includes one or more levels of cache, sets within the cores, or one or more shared cache units 1206 and external memory (not shown) coupled to the set of integrated memory controller units 1214. The set of shared cache units 1206 can include one or more mid-level caches, such as a level 2 (L2), level 3 (L3), level 4 (L4), or other level of cache, a last-level cache (LLC), and / or a combination thereof. While in one embodiment a ring-based interconnect unit 1212 interconnects the integrated graphics logic 1208, the set of shared cache units 1206, and the system agent unit 1210 / (one or more) integrated memory controller units 1214, alternative embodiments can use any number of well-known techniques for interconnecting such units. In one embodiment, coherence is maintained between one or more cache units 1206 and cores 1202-A-N.

[0106] In some embodiments, one or more of the cores 1202A-N have multithreading capabilities. The system agent 1210 includes those components that coordinate and operate the cores 1202A-N. The system agent unit 1210 can include, for example, a power control unit (PCU) and a display unit. The PCU can be or include the logic and components required to regulate the power states of the cores 1202A-N and the integrated graphics logic 1208. The display unit is used to drive one or more externally connected displays.

[0107] Core 1202A-N may be homogeneous or heterogeneous in terms of the architectural instruction set; i.e., two or more of cores 1202A-N may be capable of executing the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set.

[0108] Figures 13 - 16 is a block diagram of an exemplary computer architecture. Other system designs and configurations known in the fields of laptop computers, desktop computers, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular telephones, portable media players, handheld devices, and various other electronic devices are suitable. In general, a wide variety of systems or electronic devices that can incorporate the processors and / or other execution logics disclosed herein are generally suitable.

[0109] Now referring to Figure 13 , a block diagram of a system 1300 in accordance with one embodiment of the present invention is shown. System 1300 may include one or more processors 1310, 1315 coupled to a controller hub 1320. In one embodiment, controller hub 1320 includes a Graphics Memory Controller Hub (GMCH) 1390 and an Input / Output Hub (IOH) 1350 (which may be on separate chips); GMCH 1390 includes a memory 1340 and a graphics controller to which a coprocessor 1345 is coupled; IOH 1350 couples input / output (I / O) devices 1360 to GMCH 1390. Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), memory 1340 and coprocessor 1345 are directly coupled to processor 1310, and controller hub 1320 is in a single chip with IOH 1350.

[0110] In Figure 13 the optional nature of additional processor 1315 is indicated by dashed lines. Each processor 1310, 1315 may include one or more of the processing cores described herein and may be a certain version of processor 1200.

[0111] Memory 1340 may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of both. For at least one embodiment, controller hub 1320 communicates with (one or more) processors 1310, 1315 via a multi-drop bus such as a Front Side Bus (FSB), a point-to-point interface such as QuickPath Interconnect (QPI), or a similar connection 1395.

[0112] In one embodiment, the coprocessor 1345 is a specialized processor such as, for example, a high throughput MIC processor, a network or communications processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, or the like. In one embodiment, the controller hub 1320 may include an integrated graphics accelerator.

[0113] There may be many differences between the physical resources 1310, 1315 in terms of a spectrum of metrics of merit including architecture, microarchitecture, thermal, power consumption characteristics, and the like.

[0114] In one embodiment, the processor 1310 executes instructions that control general types of data processing operations. Coprocessor instructions may be embedded within the instructions. The processor 1310 identifies these coprocessor instructions as being of a type that should be executed by an attached coprocessor 1345. Accordingly, the processor 1310 issues these coprocessor instructions (or control signals representing coprocessor instructions) to the coprocessor 1345 over a coprocessor bus or other interconnect. The (one or more) coprocessor 1345 accepts and executes the received coprocessor instructions.

[0115] Now referring Figure 14 , a block diagram of a first more specific exemplary system 1400 in accordance with an embodiment of the present invention is shown. As shown in Figure 14 , the multiprocessor system 1400 is a point-to-point interconnect system and includes a first processor 1470 and a second processor 1480 coupled via a point-to-point interconnect 1450. Each of the processors 1470 and 1480 may be some version of the processor 1200. In one embodiment of the present invention, the processors 1470 and 1480 are the processors 1310 and 1315, respectively, while the coprocessor 1438 is the coprocessor 1345. In another embodiment, the processors 1470 and 1480 are the processor 1310 and the coprocessor 1345, respectively.

[0116] The processors 1470 and 1480 are shown including integrated memory controller (IMC) units 1472 and 1482, respectively. The processor 1470 also includes point-to-point (P-P) interfaces 1476 and 1478 as part of its bus controller unit; similarly, the second processor 1480 includes P-P interfaces 1486 and 1488. The processors 1470, 1480 may exchange information via the point-to-point (P-P) interface 1450 using P-P interface circuits 1478, 1488. As in Figure 14As shown, IMCs 1472 and 1482 couple the processors to corresponding memories, namely memory 1432 and memory 1434, which may be portions of main memories that are locally attached to the corresponding processors.

[0117] Each of processors 1470, 1480 may exchange information with chipset 1490 via separate P-P interfaces 1452, 1454 using point-to-point interface circuits 1476, 1494, 1486, 1498. Chipset 1490 may optionally exchange information with coprocessor 1438 via high performance interface 1439. In one embodiment, coprocessor 1438 is a special-purpose processor such as, for example, a high throughput MIC processor, a network or communications processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, or the like.

[0118] A shared cache (not shown) may be included in either processor or external to both processors, but is connected to the processors via a P-P interconnect such that if a processor is placed in a low power mode, local cache information of either processor or both processors may be stored in the shared cache.

[0119] Chipset 1490 may be coupled to first bus 1416 via interface 1496. In one embodiment, first bus 1416 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I / O interconnect bus, but the scope of the present invention is not limited thereto.

[0120] As shown in Figure 14 Various I / O devices 1414 may be coupled to first bus 1416 along with bus bridge 1418 that couples first bus 1416 to second bus 1420. In one embodiment, one or more additional processors 1415 are coupled to first bus 1416, the one or more additional processors 1415 such as coprocessors, high throughput MIC processors, GPGPUs, accelerators (such as, for example, a graphics accelerator or a Digital Signal Processing (DSP) unit), field programmable gate arrays, or any other processor. In one embodiment, second bus 1420 may be a Low Pin Count (LPC) bus. In one embodiment, various devices may be coupled to second bus 1420, the various devices including, for example, keyboard and / or mouse 1422, communication device 1427, and storage unit 1428, the storage unit 1428 such as a disk drive or other mass storage device that may include instructions / code and data 1430. Additionally, audio I / O 1424 may be coupled to second bus 1420. Note that other architectures are possible. For example, instead of Figure 14For a point-to-point architecture, the system can implement a multi-drop bus or other such architectures.

[0121] Now referring to Figure 15 , a block diagram of a second more specific exemplary system 1500 in accordance with an embodiment of the present invention is illustrated. Figure 14 and 15 The same units in Figure 15 are omitted Figure 14 from certain aspects of Figure 15 to avoid obscuring other aspects of

[0122] Figure 15 It is illustrated that processors 1470, 1480 may respectively include integrated memory and I / O control logic ("CL") 1472 and 1482. Thus, CL 1472, 1482 includes an integrated memory controller unit and includes I / O control logic. Figure 15 It is illustrated that not only memories 1432, 1434 are coupled to CL 1472, 1482, but also I / O devices 1514 are coupled to control logic 1472, 1482. Conventional I / O devices 1515 are coupled to chipset 1490.

[0123] Now referring to Figure 16 , a block diagram of an SoC 1600 in accordance with an embodiment of the present invention is shown. Figure 12 Similar units in Figure 16 have the same reference numerals. Additionally, the dashed boxes are optional features on a more advanced SoC.In

[0124] Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation methods. Embodiments of the present invention may be implemented as a computer program or program code executed on a programmable system that includes at least one processor, a storage system (including volatile and non-volatile memory and / or storage units), at least one input device, and at least one output device.

[0125] Program code such as code 1430 illustrated in Figure 14 may be applied to input instructions to perform the functions described herein and generate output information. The output information may be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor, such as, for example; a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0126] The program code may be implemented in a high-level procedural or object-oriented programming language to communicate with the processing system. If desired, the program code may also be implemented in assembly or machine language. In fact, the mechanisms described herein are not limited in scope to any particular programming language. In various cases, the language may be a compiled or interpreted language.

[0127] One or more aspects of at least one embodiment may be implemented by instructions represented in a machine-readable medium that represent various logic within a processor, which when read by the machine cause the machine to fabricate logic to perform the techniques described herein. Such representations, referred to as “IP cores,” may be stored on a tangible machine-readable medium and provided to various customers or manufacturing facilities to be loaded into the manufacturing machines of actual fabrication logic or processors.

[0128] Such machine-readable storage media may include, but are not limited to, non-transitory tangible arrangements of articles manufactured or formed by a machine or device, including storage media such as hard disks, and any other type of disk, including floppy disks, optical disks, compact disk read-only memory (CD-ROM), rewritable compact disks (CD-RW), and magneto-optical disks, semiconductor devices such as read-only memory (ROM), random access memory (RAM) (such as dynamic random access memory (DRAM), static random access memory (SRAM)), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase change memory (PCM), magnetic cards or optical cards; or any other type of medium suitable for storing electronic instructions.

[0129] Accordingly, embodiments of the present invention also include non-transitory tangible machine-readable media that contain instructions or contain design data, such as a hardware description language (HDL) that defines the structural, circuit, device, processor, and / or system features described herein. Such embodiments may also be referred to as program products.

[0130] In some cases, an instruction converter may be used to convert instructions from a source instruction set to a target instruction set. For example, the instruction converter may translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), transform, emulate, or otherwise convert the instructions into one or more other instructions to be processed by the core. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on the processor, outside the processor, or partly on the processor and partly outside the processor.

[0131] Figure 17 is a block diagram contrasting the use of a software instruction converter according to an embodiment of the present invention, the software instruction converter being used to convert binary instructions in a source instruction set to binary instructions in a target instruction set. In the illustrated embodiment, the instruction converter is a software instruction converter, but the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. Figure 17 illustrates that a program in a high-level language 1702 can be compiled using an x86 compiler 1704 to generate x86 binary code 1706 that can be natively executed by a processor 1716 having at least one x86 instruction set core. The processor 1716 having at least one x86 instruction set core represents any processor that can implement substantially the same functions as an Intel processor having at least one x86 instruction set core, either by compatibly executing or otherwise processing (1) a substantial portion of the instruction set of the Intel x86 instruction set core or (2) the object code version of an application or other software targeted to run on an Intel processor having at least one x86 instruction set core, so as to obtain substantially the same results as an Intel processor having at least one x86 instruction set core. The x86 compiler 1704 represents a compiler adapted to generate x86 binary code 1706 (e.g., object code) that can be executed, with or without additional linking processing, on a processor 1716 having at least one x86 instruction set core. Similarly, Figure 17Illustrated is that a program in a high-level language 1702 can be compiled using an alternative instruction set compiler 1708 to generate alternative instruction set binary code 1710 that can be natively executed by a processor 1714 that does not have at least one x86 instruction set core (e.g., a processor having a core that executes the MIPS instruction set of MIPS Technologies (Sunnyvale, CA) and / or executes the ARM instruction set of ARM Holdings (Sunnyvale, CA)). An instruction converter 1712 is used to convert the x86 binary code 1706 into code that can be natively executed by the processor 1714 that does not have an x86 instruction set core. The converted code is not likely to be the same as the alternative instruction set binary code 1710 because it is difficult to make an instruction converter that can do so; however, the converted code will implement general operations and is composed of instructions from an alternative instruction set. Thus, the instruction converter 1712 represents software, firmware, hardware, or a combination thereof, and allows a processor or other electronic device that does not have an x86 instruction set processor or core to execute the x86 binary code 1706 through emulation, simulation, or any other process.

[0132] Additional remarks and examples

[0133] Example 1 is a neural core for variable epoch spike train filtering, the neural core including: a spike trace storage device; a trace decay modeling circuit system for generating a spike trace in response to an epoch learning event using a count of received spikes in the spike trace storage device; and a processing circuit system for: receiving a plurality of spikes at the neural core during an epoch to which the epoch learning event corresponds; incrementing the spike trace storage device for each of the plurality of spikes to generate a count of received spikes; and modifying network parameters of the neural core using the spike trace in response to the occurrence of the epoch learning event.

[0134] In Example 2, the subject matter of Example 1 includes, wherein, to generate a spike trace using a count of received spikes, the trace decay modeling circuit system scales the count of received spikes by a constant.

[0135] In Example 3, the subject matter of Example 2 includes, wherein, the constant is the minimum inter-spike interval.

[0136] In Example 4, the subject matter of Examples 2-3 includes, wherein, to generate a spike trace using a count of received spikes, the trace decay modeling circuit system multiplies the scaled count of received spikes by two to the power of SHIFT plus one, where SHIFT is a constant defined by the width of the spike trace storage device minus the width of the maximum scaled count of received spikes.

[0137] In Example 5, the subject matter of Examples 2 - 4 includes, wherein, in order to generate a spike trace using the count of received spikes, the trace decay modeling circuitry applies a single exponential decay to a previous epoch trace value to obtain the spike trace.

[0138] In Example 6, the subject matter of Example 5 includes, wherein a single exponential decay is calculated as: X[i]=expDecay(Tau, Tepoch, X[i - 1]-Impulse)+Impulse, where X[i] is the spike trace, X[i - 1] is the previous epoch trace, Impulse is the count of scaled received spikes, Tepoch is the number of time steps in an epoch, and Tau is a constant.

[0139] In Example 7, the subject matter of Example 6 includes, wherein Tepoch is a power of two.

[0140] In Example 8, the subject matter of Examples 1 - 7 includes, wherein the processing circuitry is further used to: receive a single spike during a second epoch; store the spike arrivals since the epoch in a spike trace storage device; obtain a second epoch learning event for the second epoch; and modify the network parameters of a neural core using the second spike trace; and wherein the trace decay modeling circuitry is further used to generate a second spike trace using the spike arrivals since the epoch in the spike trace storage device in response to the second epoch learning event.

[0141] In Example 9, the subject matter of Example 8 includes, wherein, in order to generate a second spike trace using the spike arrivals since the epoch in response to the second epoch learning event, the trace decay modeling circuitry applies an exponential decay based on the spike arrivals since the epoch.

[0142] In Example 10, the subject matter of Example 9 includes, wherein the spike trace storage device includes a bit indicating whether a single spike or multiple spikes arrived during a given epoch, and wherein the exponential decay of the spike trace storage device, either as the count of received spikes or the spike arrivals since the epoch, is controlled by the bit.

[0143] In Example 11, the subject matter of Examples 1 - 10 includes, wherein the epoch learning event is the end of an epoch.

[0144] In Example 12, the subject matter of Examples 1 - 11 includes, wherein the spike trace storage device is a register of a neural core.

[0145] In Example 13, the subject matter of Examples 1 - 12 includes, wherein, in order to modify the network parameters of a neural core using the spike trace, the processing circuitry modifies the synaptic variable state as a function of the spike trace.

[0146] Example 14 is a system for variable epoch spike train filtering, the system including: a plurality of neural chips, each neural chip including a plurality of neural cores, the neural cores among the plurality of neural cores including: a spike trace storage device; a trace decay modeling circuit system for generating a spike trace in response to an epoch learning event using a count of received spikes in the spike trace storage device; and a processing circuit system for: receiving a plurality of spikes at the neural core during an epoch to which the epoch learning event corresponds; incrementing the spike trace storage device for each of the plurality of spikes to generate a count of received spikes; and modifying network parameters of the neural core using the spike trace in response to the occurrence of the epoch learning event; and an interconnect for providing communication from the neural chips to each other and from the neural chips to devices external to the system.

[0147] In Example 15, the subject matter of Example 14 includes, wherein, to generate a spike trace using a count of received spikes, the trace decay modeling circuit system scales the count of received spikes by a constant.

[0148] In Example 16, the subject matter of Example 15 includes, wherein, the constant is the minimum inter-spike interval.

[0149] In Example 17, the subject matter of Examples 15-16 includes, wherein, to generate a spike trace using a count of received spikes, the trace decay modeling circuit system multiplies the scaled count of received spikes by two to the power of SHIFT plus one, where SHIFT is a constant defined by the width of the spike trace storage device minus the width of the maximum scaled count of received spikes.

[0150] In Example 18, the subject matter of Examples 15-17 includes, wherein, to generate a spike trace using a count of received spikes, the trace decay modeling circuit system applies a single exponential decay to a previous epoch trace value to obtain the spike trace.

[0151] In Example 19, the subject matter of Example 18 includes, wherein, the single exponential decay is calculated by: X[i]=expDecay(Tau, Tepoch, X[i-14]-Impulse)+Impulse, where, X[i] is the spike trace, X[i-14] is the previous epoch trace, Impulse is the scaled count of received spikes, Tepoch is the number of time steps in the epoch, and Tau is a constant.

[0152] In Example 20, the subject matter of Example 19 includes, wherein, Tepoch is a power of two.

[0153] In Example 21, the subject matter of Examples 14-20 includes, wherein the processing circuitry is further used to: receive a single spike during a second epoch; store the spike arrivals since the epoch in a spike trace storage device; obtain a second epoch learning event for the second epoch; and modify the network parameters of the neural core using the second spike trace; and wherein the trace decay modeling circuitry is further used to generate a second spike trace in response to the second epoch learning event using the spike arrivals since the epoch in the spike trace storage device.

[0154] In Example 22, the subject matter of Example 21 includes, wherein, to generate a second spike trace using the spike arrivals since the epoch in response to the second epoch learning event, the trace decay modeling circuitry applies an exponential decay based on the spike arrivals since the epoch.

[0155] In Example 23, the subject matter of Example 22 includes, wherein the spike trace storage device includes a bit indicating whether a single spike or multiple spikes arrived during a given epoch, and wherein the exponential decay of the spike trace storage device, which is either a count of the received spikes or the spike arrivals since the epoch, is controlled by the bit.

[0156] In Example 24, the subject matter of Examples 14-23 includes, wherein the epoch learning event is the end of the epoch.

[0157] In Example 25, the subject matter of Examples 14-24 includes, wherein the spike trace storage device is a register of the neural core.

[0158] In Example 26, the subject matter of Examples 14-25 includes, wherein, to modify the network parameters of the neural core using the spike trace, the processing circuitry modifies the synaptic variable state as a function of the spike trace.

[0159] In Example 27, the subject matter of Examples 14-26 includes, wherein the system is included in a sensor device, and wherein an interconnect connects the neural chip to the sensor.

[0160] In Example 28, the subject matter of Example 27 includes, wherein the sensor is at least one of a camera, a thermometer, a barometer, a position sensor, a humidity sensor, or a microphone.

[0161] In Example 29, the subject matter of Examples 27-28 includes, wherein the interconnect provides classification data from the neural core to a consumer device.

[0162] In Example 30, the subject matter of Example 29 includes, wherein the consumer device is a network interface for communicating with a remote machine via a network.

[0163] Example 31 is a method for variable epoch spike train filtering, the method comprising: receiving a plurality of spikes at a neural core during an epoch; incrementing a value in a spike trace storage device for each of the plurality of spikes to produce a count of the received spikes, the spike trace storage device being included in the neural core of neuromorphic hardware; producing a spike trace using the count of the received spikes in the spike trace storage device in response to an epoch learning event; and modifying network parameters of the neural core using the spike trace.

[0164] In example 32, the subject matter of example 31 includes, wherein producing a spike trace using the count of the received spikes includes scaling the count of the received spikes by a constant.

[0165] In example 33, the subject matter of example 32 includes, wherein the constant is the minimum inter-spike interval.

[0166] In example 34, the subject matter of examples 32-33 includes, wherein producing a spike trace using the count of the received spikes includes multiplying the scaled count of the received spikes by two to the power of SHIFT + 1, where SHIFT is a constant defined by the width of the spike trace storage device minus the width of the maximum scaled count of the received spikes.

[0167] In example 35, the subject matter of examples 32-34 includes, wherein producing a spike trace using the count of the received spikes includes applying a single exponential decay to a previous epoch trace value to obtain the spike trace.

[0168] In example 36, the subject matter of example 35 includes, wherein the single exponential decay is calculated by: X[i]=expDecay(Tau, Tepoch, X[i - 31] - Impulse)+Impulse, where X[i] is the spike trace, X[i - 31] is the previous epoch trace, Impulse is the scaled count of the received spikes, Tepoch is the number of time steps in the epoch, and Tau is a constant.

[0169] In example 37, the subject matter of example 36 includes, wherein Tepoch is a power of two.

[0170] In example 38, the subject matter of examples 31-37 includes receiving a single spike during a second epoch; storing the spike arrivals since the epoch in the spike trace storage device; producing a second spike trace using the spike arrivals since the epoch in the spike trace storage device in response to a second epoch learning event; and modifying network parameters of the neural core using the second spike trace.

[0171] In Example 39, the subject matter of Example 38 includes, wherein generating a second spike trace in response to a second epoch learning event using spike arrivals since the epoch includes applying an exponential decay based on spike arrivals since the epoch.

[0172] In Example 40, the subject matter of Example 39 includes, wherein the spike trace storage device includes a bit indicating whether a single spike or multiple spikes arrived during a given epoch, and wherein the exponential decay of the spike trace storage device, which is either a count of received spikes or spike arrivals since the epoch, is controlled by the bit.

[0173] In Example 41, the subject matter of Examples 31 - 40 includes, wherein the epoch learning event is the end of the epoch.

[0174] In Example 42, the subject matter of Examples 31 - 41 includes, wherein the spike trace storage device is a register of a neural core.

[0175] In Example 43, the subject matter of Examples 31 - 42 includes, wherein modifying network parameters of a neural core using a spike trace includes modifying a synaptic variable state as a function of the spike trace.

[0176] Example 44 is at least one machine-readable medium including instructions that, when executed by a machine, cause the machine to perform any of the methods of Examples 31 - 43.

[0177] Example 45 is a system including an apparatus for performing any of the methods of Examples 31 - 43.

[0178] Example 46 is at least one machine-readable medium including instructions for variable epoch spike train filtering that, when executed by a processing circuitry, configure the processing circuitry to perform operations including: receiving a plurality of spikes at a neural core during an epoch; incrementing a value in a spike trace storage device for each of the plurality of spikes to produce a count of received spikes, the spike trace storage device being included in a neural core of neuromorphic hardware; generating a spike trace in response to an epoch learning event using the count of received spikes in the spike trace storage device; and modifying network parameters of the neural core using the spike trace.

[0179] In Example 47, the subject matter of Example 46 includes, wherein generating a spike trace using the count of received spikes includes scaling the count of received spikes by a constant.

[0180] In Example 48, the subject matter of Example 47 includes, wherein the constant is the minimum inter-spike interval.

[0181] In Example 49, the subject matter of Examples 47 - 48 includes, wherein generating a spike trace using a count of received spikes includes multiplying the count of scaled received spikes by two to the SHIFT plus one power, where SHIFT is a constant defined by the width of the spike trace storage device minus the width of the maximum scaled count of received spikes.

[0182] In Example 50, the subject matter of Examples 47 - 49 includes, wherein generating a spike trace using a count of received spikes includes applying a single exponential decay to a previous epoch trace value to obtain the spike trace.

[0183] In Example 51, the subject matter of Example 50 includes, wherein calculating the single exponential decay is by: X[i]=expDecay(Tau, Tepoch, X[i - 46]-Impulse)+Impulse, where X[i] is the spike trace, X[i - 46] is the previous epoch trace, Impulse is the count of scaled received spikes, Tepoch is the number of time steps in an epoch, and Tau is a constant.

[0184] In Example 52, the subject matter of Example 51 includes, wherein Tepoch is a power of two.

[0185] In Example 53, the subject matter of Examples 46 - 52 includes, wherein the operations include: receiving a single spike during a second epoch; storing the spike arrivals since the epoch in a spike trace storage device; generating a second spike trace using the spike arrivals since the epoch in the spike trace storage device in response to a second epoch learning event; and modifying network parameters of a neural core using the second spike trace.

[0186] In Example 54, the subject matter of Example 53 includes, wherein generating a second spike trace using the spike arrivals since the epoch in response to a second epoch learning event includes applying an exponential decay based on the spike arrivals since the epoch.

[0187] In Example 55, the subject matter of Example 54 includes, wherein the spike trace storage device includes a bit indicating whether a single spike or multiple spikes arrived during a given epoch, and wherein the exponential decay of the spike trace storage device, which is either the count of received spikes or the spike arrivals since the epoch, is controlled by the bit.

[0188] In Example 56, the subject matter of Examples 46 - 55 includes, wherein the epoch learning event is the end of an epoch.

[0189] In Example 57, the subject matter of Examples 46 - 56 includes, wherein the spike trace storage device is a register of a neural core.

[0190] In Example 58, the subject matter of Examples 46-57 includes, wherein modifying the network parameters of a neural core using a spike trace includes modifying the state of a synaptic variable as a function of the spike trace.

[0191] Example 59 is a system for variable epoch spike train filtering, the system including: means for receiving a plurality of spikes at a neural core during an epoch; means for incrementing a value in a spike trace storage device for each of the plurality of spikes to produce a count of the received spikes, the spike trace storage device being included in a neural core of neuromorphic hardware; means for producing a spike trace using the count of the received spikes in the spike trace storage device in response to an epoch learning event; and means for modifying network parameters of the neural core using the spike trace.

[0192] In Example 60, the subject matter of Example 59 includes, wherein the means for producing a spike trace using the count of the received spikes includes means for scaling the count of the received spikes by a constant.

[0193] In Example 61, the subject matter of Example 60 includes, wherein the constant is the minimum inter-spike interval.

[0194] In Example 62, the subject matter of Examples 60-61 includes, wherein the means for producing a spike trace using the count of the received spikes includes means for multiplying the scaled count of the received spikes by two to the SHIFT plus one power, where SHIFT is a constant defined by the width of the spike trace storage device minus the width of the maximum scaled count of the received spikes.

[0195] In Example 63, the subject matter of Examples 60-62 includes, wherein the means for producing a spike trace using the count of the received spikes includes means for applying a single exponential decay to a previous epoch trace value to obtain the spike trace.

[0196] In Example 64, the subject matter of Example 63 includes, wherein the single exponential decay is calculated by: X[i]=expDecay(Tau, Tepoch, X[i-59]-Impulse)+Impulse, where X[i] is the spike trace, X[i-59] is the previous epoch trace, Impulse is the scaled count of the received spikes, Tepoch is the number of time steps in the epoch, and Tau is a constant.

[0197] In Example 65, the subject matter of Example 64 includes, wherein Tepoch is a power of two.

[0198] In Example 66, the subject matter of Examples 59-65 includes components for receiving a single spike during a second epoch; components for storing spike arrivals since the epoch in a spike trace storage device; components for generating a second spike trace using the spike arrivals since the epoch in the spike trace storage device in response to a second epoch learning event; and components for modifying network parameters of a neural core using the second spike trace.

[0199] In Example 67, the subject matter of Example 66 includes where the components for generating a second spike trace using the spike arrivals since the epoch in response to a second epoch learning event include components for applying an exponential decay based on the spike arrivals since the epoch.

[0200] In Example 68, the subject matter of Example 67 includes where the spike trace storage device includes a bit indicating whether a single spike or multiple spikes arrived during a given epoch, and where the exponential decay of the spike trace storage device, which is either a count of received spikes or the spike arrivals since the epoch, is controlled by the bit.

[0201] In Example 69, the subject matter of Examples 59-68 includes where the epoch learning event is the end of the epoch.

[0202] In Example 70, the subject matter of Examples 59-69 includes where the spike trace storage device is a register of the neural core.

[0203] In Example 71, the subject matter of Examples 59-70 includes where the components for modifying network parameters of the neural core using the spike trace include components for modifying the synaptic variable state as a function of the spike trace.

[0204] Example 72 is at least one machine-readable medium including instructions that, when executed by a machine, cause the machine to perform any of the methods of Examples 31-43. The instructions, when executed by a processing circuit system, cause the processing circuit system to perform operations to implement any one of Examples 1-71.

[0205] Example 73 is a device that includes components for implementing any one of Examples 1-71.

[0206] Example 74 is a system for implementing any one of Examples 1-71.

[0207] Example 75 is a method for implementing any one of Examples 1-71.

[0208] The present application provides the following technical solutions:

[0209] 1. A system for variable epoch spike train filtering, the system comprising:

[0210] Multiple neural chips, each neural chip including a plurality of neural cores, the neural cores among the plurality of neural cores including:

[0211] A spike trace storage device;

[0212] A trace decay modeling circuit system for generating a spike trace using a count of received spikes in the spike trace storage device in response to an epoch learning event; and

[0213] A processing circuit system for:

[0214] Receiving a plurality of spikes at a neural core during an epoch to which the epoch learning event corresponds;

[0215] Incrementing the spike trace storage device for each of the plurality of spikes to generate a count of received spikes; and

[0216] Modifying network parameters of the neural core using the spike trace in response to the occurrence of an epoch learning event; and

[0217] An interconnect for providing communication from the neural chips to each other and from the neural chips to devices external to the system.

[0218] 2. The system according to claim 1, wherein, in order to generate a spike trace using a count of received spikes, the trace decay modeling circuit system scales the count of received spikes by a constant.

[0219] 3. The system according to claim 2, wherein, in order to generate a spike trace using a count of received spikes, the trace decay modeling circuit system applies a single exponential decay to a previous epoch trace value to obtain the spike trace.

[0220] 4. The system according to claim 3, wherein the single exponential decay is calculated by:

[0221] X[i]=expDecay(Tau, Tepoch, X[i-1]-Impulse)+Impulse, where X[i] is the spike trace, X[i-1] is the previous epoch trace, Impulse is the scaled count of received spikes, Tepoch is the number of time steps in the epoch, and Tau is a constant.

[0222] 5. The system according to claim 1, wherein, in order to modify network parameters of the neural core using the spike trace, the processing circuit system modifies a synaptic variable state as a function of the spike trace.

[0223] 6. The system as described in Technical Solution 1, wherein the system is included in a sensor device, and wherein the interconnection connects the neural chip to the sensor.

[0224] 7. The system as described in Technical Solution 6, wherein the sensor is at least one of a camera, a thermometer, a barometer, a position sensor, a humidity sensor, or a microphone.

[0225] 8. The method as described in Technical Solution 6, wherein the interconnection provides classified data from the neural core to a consumer device.

[0226] Wherein, the interconnection provides the classified data from the neural core to the consumer device.

[0227] 9. The method as described in Technical Solution 8, wherein the consumer device is a network interface for communicating with a remote machine via a network.

[0228] 10. A neural core for variable epoch spike train filtering, the neural core comprising:

[0229] A spike trace storage device;

[0230] A trace decay modeling circuit system for generating a spike trace in response to an epoch learning event using a count of received spikes in the spike trace storage device; and

[0231] A processing circuit system for:

[0232] Receiving a plurality of spikes at the neural core during an epoch to which the epoch learning event corresponds;

[0233] Incrementing the spike trace storage device for each of the plurality of spikes to generate a count of received spikes; and

[0234] Modifying network parameters of the neural core using the spike trace in response to the occurrence of an epoch learning event.

[0235] 11. The neural core as described in Technical Solution 10, wherein, in order to generate a spike trace using the count of received spikes, the trace decay modeling circuit system scales the count of received spikes by a constant.

[0236] 12. The neural core as described in Technical Solution 11, wherein, in order to generate a spike trace using the count of received spikes, the trace decay modeling circuit system multiplies the scaled count of received spikes by two to the power of SHIFT + 1, where SHIFT is a constant defined by the width of the spike trace storage device minus the width of the maximum scaled count of received spikes.

[0237] 13. The neural core as described in technical solution 11, wherein, in order to generate a spike trace using the count of received spikes, the trace decay modeler circuitry applies a single exponential decay to a previous epoch trace value to obtain a spike trace.

[0238] 14. The neural core as described in technical solution 13, wherein the single exponential decay is calculated by:

[0239] X[i]=expDecay(Tau, Tepoch, X[i - 10] - Impulse)+Impulse, where X[i] is the spike trace, X[i - 10] is the previous epoch trace, Impulse is the count of scaled received spikes, Tepoch is the number of time steps in an epoch, and Tau is a constant.

[0240] 15. The neural core as described in technical solution 10, wherein the processing circuitry is further configured to:

[0241] Receive a single spike during a second epoch;

[0242] Store the spike arrivals since the epoch in a spike trace storage device;

[0243] Obtain a second epoch learning event for the second epoch; and

[0244] Modify the network parameters of the neural core using the second spike trace; and

[0245] wherein the trace decay modeler circuitry is further configured to generate a second spike trace using the spike arrivals since the epoch in the spike trace storage device in response to the second epoch learning event.

[0246] 16. The neural core as described in technical solution 15, wherein, in order to generate a second spike trace using the spike arrivals since the epoch in response to the second epoch learning event, the trace decay modeler circuitry applies an exponential decay based on the spike arrivals since the epoch.

[0247] 17. The neural core as described in technical solution 10, wherein, in order to modify the network parameters of the neural core using the spike trace, the processing circuitry modifies the synaptic variable state as a function of the spike trace.

[0248] 18. At least one machine-readable medium including instructions for variable epoch spike train filtering, the instructions configuring the processing circuitry to perform operations including the following when executed by the processing circuitry:

[0249] Receive a plurality of spikes at a neural core during an epoch;

[0250] Increment a value in a spike trace storage device for each increasing spike among a plurality of spikes to produce a count of received spikes, the spike trace storage device being included in a neural core of neuromorphic hardware;

[0251] Produce a spike trace using the count of received spikes in the spike trace storage device in response to an epoch learning event; and

[0252] Modify network parameters of the neural core using the spike trace.

[0253] 19. The at least one machine-readable medium according to claim 18, wherein producing a spike trace using the count of received spikes includes scaling the count of received spikes by a constant.

[0254] 20. The at least one machine-readable medium according to claim 19, wherein producing a spike trace using the count of received spikes includes multiplying the scaled count of received spikes by two to the power of SHIFT + 1, where SHIFT is a constant defined by the width of the spike trace storage device minus the width of the maximum scaled count of received spikes.

[0255] 21. The at least one machine-readable medium according to claim 19, wherein producing a spike trace using the count of received spikes includes applying a single exponential decay to a previous epoch trace value to obtain the spike trace.

[0256] 22. The at least one machine-readable medium according to claim 21, wherein the single exponential decay is calculated by:

[0257] X[i]=expDecay(Tau, Tepoch, X[i - 18] - Impulse)+Impulse, where X[i] is the spike trace, X[i - 18] is the previous epoch trace, Impulse is the scaled count of received spikes, Tepoch is the number of time steps in the epoch, and Tau is a constant.

[0258] 23. The at least one machine-readable medium according to claim 18, wherein the operations include:

[0259] Receive a single spike during a second epoch;

[0260] Store the spike arrivals since the epoch in the spike trace storage device;

[0261] Produce a second spike trace using the spike arrivals since the epoch in the spike trace storage device in response to a second epoch learning event; and

[0262] Modify network parameters of the neural core using the second spike trace.

[0263] 24. The at least one machine-readable medium as described in embodiment 23, wherein generating a second spike trace using spike arrivals since an epoch in response to a second epoch learning event includes applying an exponential decay based on spike arrivals since the epoch.

[0264] 25. The at least one machine-readable medium as described in embodiment 18, wherein modifying network parameters of a neural core using a spike trace includes modifying a synaptic variable state as a function of the spike trace.

[0265] The above detailed description includes references to the accompanying drawings that form a part of the detailed description. The drawings illustrate specific embodiments that may be implemented. These embodiments are also referred to herein as "examples." Such examples may include elements in addition to those shown or described. However, the inventors also contemplate examples in which only those elements shown or described are provided. Additionally, the inventors also contemplate examples using any combination or arrangement of those elements shown or described with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0266] All publications, patents, and patent documents mentioned in this document are incorporated herein by reference in their entirety as if individually incorporated by reference. In cases of inconsistent usage between this document and those documents incorporated by reference in this way, the usage in the incorporated (one or more) reference documents should be regarded as supplementary to the usage in this document; for irreconcilable inconsistencies, the usage in this document shall prevail.

[0267] In this document, as is common in patent documents, the terms "a" or "an" are used to include one or more than one, independent of any other instances or uses of "at least one" or "one or more." Unless otherwise indicated, in this document, the term "or" is used to refer to a non-exclusive or, such that "A or B" includes "A but not B," "B but not A," and "A and B." In the appended claims, the terms "comprising" and "wherein" are used as the plain English equivalents of the respective terms "including" and "wherein." Additionally, in the following claims, the terms "comprising" and "comprise" are open-ended, i.e., a system, apparatus, article, or process that includes elements in addition to those listed after such terms in the claims is still considered to fall within the scope of the claim. Further, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

[0268] The foregoing description is intended to be illustrative and not restrictive. For example, the above-described examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments can be used, such as can be used by those of ordinary skill in the art upon review of the foregoing description. The abstract is used to allow the reader to quickly ascertain the nature of the technical disclosure and is submitted with the understanding that the abstract will not be used to interpret or limit the scope or meaning of the claims. Additionally, in the foregoing detailed description, various features may be grouped together to simplify the disclosure. This should not be construed as intending that features of the disclosure that are not claimed are essential to any claim. Rather, the subject matter of the invention may lie in less than all of the features of a particular disclosed embodiment. Accordingly, the following claims are hereby incorporated into the detailed description, where each claim stands on its own as a separate embodiment. The scope of the embodiments should be determined with reference to the appended claims along with the full scope of equivalents to which such claims are entitled.

Claims

1. A system for variable epoch spike train filtering, the system comprising: A plurality of neural chips, each neural chip including a plurality of neural cores, the neural cores among the plurality of neural cores including: A spike trace storage device; A trace decay modeling circuit system for generating a spike trace using a count of received spikes in the spike trace storage device in response to an epoch learning event; and A processing circuit system for: Receiving a plurality of spikes at the neural core during an epoch to which the epoch learning event corresponds; Incrementing the spike trace storage device for each of the plurality of spikes to generate a count of received spikes; and Modifying network parameters of the neural core using the spike trace in response to the occurrence of an epoch learning event; and An interconnect for providing communication from the neural chips to each other and from the neural chips to devices external to the system; Wherein, in order to modify network parameters of the neural core using the spike trace, the processing circuit system modifies the synaptic variable state according to the spike trace.

2. The system according to claim 1, wherein In order to generate a spike trace using a count of received spikes, the trace decay modeling circuit system scales the count of received spikes by a constant.

3. The system according to claim 2, wherein, The constant is the minimum inter-spike interval.

4. The system according to claim 2, wherein In order to generate a spike trace using a count of received spikes, the trace decay modeling circuit system multiplies the scaled count of received spikes by two to the power of SHIFT + 1, where SHIFT is a constant defined by the width of the spike trace storage device minus the width of the maximum scaled count of received spikes.

5. The system according to claim 2, wherein In order to generate a spike trace using a count of received spikes, the trace decay modeling circuit system applies a single exponential decay to a previous epoch trace value to obtain the spike trace.

6. The system according to claim 5, wherein The single exponential decay is calculated by: X[i]=expDecay(Tau,Tepoch,X[i - 1]-Impulse)+Impulse, where X[i] is the spike trace, X[i - 1] is the previous epoch trace, Impulse is the scaled count of received spikes, Tepoch is the number of time steps in the epoch, and Tau is a constant.

7. The system according to claim 6, wherein Tepoch is a power of two.

8. The system according to claim 1, wherein The processing circuit system is further for: Receiving a single spike during a second epoch; Storing the spike arrival since the epoch in the spike trace storage device; Obtaining a second epoch learning event for the second epoch; And Modifying network parameters of the neural core using the second spike trace; And Wherein, the trace decay modeling circuit system is further for generating a second spike trace using the spike arrival since the epoch in the spike trace storage device in response to the second epoch learning event.

9. The system according to claim 8, wherein, In order to generate a second spike trace using the spike arrival since the epoch in response to the second epoch learning event, the trace decay modeling circuit system applies an exponential decay based on the spike arrival since the epoch.

10. The system according to claim 9, wherein, The spike trace storage device includes a bit indicating whether a single spike or multiple spikes have arrived during a given epoch, and wherein the bit controls the exponential decay of the spike trace storage device as either a count of the received spikes or the spike arrivals since the epoch.

11. The system according to claim 1, wherein, An epoch learning event is the end of an epoch.

12. The system according to claim 1, wherein, The spike trace storage device is a register of the neural core.

13. The system according to claim 1, wherein, The system is included in a sensor device, and wherein the interconnection connects the neural chip to the sensor.

14. The system according to claim 13, wherein, The sensor is at least one of a camera, a thermometer, a barometer, a position sensor, a humidity sensor, or a microphone.

15. A neural core for variable epoch spike train filtering, the neural core comprising: A spike trace storage device; A trace decay modeling circuit system for generating a spike trace in response to an epoch learning event using a count of the received spikes in the spike trace storage device; And A processing circuit system for: Receiving a plurality of spikes at the neural core during an epoch to which the epoch learning event corresponds; Incrementing the spike trace storage device for each of the plurality of spikes to generate a count of the received spikes; And Modifying the network parameters of the neural core using the spike trace in response to the occurrence of the epoch learning event; Wherein, to modify the network parameters of the neural core using the spike trace, the processing circuit system modifies the synaptic variable state according to the spike trace.

16. The neural core as claimed in claim 15, wherein, To generate a spike trace using the count of the received spikes, the trace decay modeling circuit system scales the count of the received spikes by a constant.

17. The neural core according to claim 16, wherein The constant is the minimum inter-spike interval.

18. The neural core according to claim 16, wherein, To generate a spike trace using the count of the received spikes, the trace decay modeling circuit system multiplies the scaled count of the received spikes by two to the power of SHIFT plus one, where SHIFT is a constant defined by the width of the spike trace storage device minus the width of the maximum scaled count of the received spikes.

19. The neural core according to claim 16, wherein, To generate a spike trace using the count of the received spikes, the trace decay modeling circuit system applies a single exponential decay to the previous epoch trace value to obtain the spike trace.

20. The neural core according to claim 19, wherein, The single exponential decay is calculated by: X[i]=expDecay(Tau,Tepoch,X[i - 16]-Impulse)+Impulse, where X[i] is the spike trace, X[i - 16] is the previous epoch trace, Impulse is the scaled count of the received spikes, Tepoch is the number of time steps in the epoch, and Tau is a constant.

21. The neural core according to claim 15, wherein, The processing circuit system is further for: Receiving a single spike during a second epoch; Storing the spike arrivals since the epoch in the spike trace storage device; Obtaining a second epoch learning event for the second epoch; And Modifying the network parameters of the neural core using the second spike trace; And Wherein, the trace decay modeling circuit system is further for generating a second spike trace in response to the second epoch learning event using the spike arrivals since the epoch in the spike trace storage device.

22. The neural core according to claim 21, wherein, To generate a second spike trace using spike arrivals since an epoch in response to a second epoch learning event, the trace decay modeling circuitry applies exponential decay based on spike arrivals since the epoch.

23. The neural core according to claim 22, wherein, The spike trace storage device includes bits indicating whether a single spike or multiple spikes arrived during a given epoch, and wherein the exponential decay of the spike trace storage device, which is either a count of received spikes or spike arrivals since the epoch, is controlled by the bits.

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