Single-wafer cell protection circuit and charge-discharge circuit with improved ability to withstand spike voltage

Abstract

The present invention provides a single-wafer battery protection circuit and a charge and discharge circuit with enhanced spike voltage resistance. The battery protection circuit includes: a basic protection circuit, a clamping circuit, a gate-substrate control circuit, and a charge and discharge control MOS transistor; one end of the source or drain of the charge and discharge control MOS transistor is connected to the battery, and the other end is connected to a charger or a load, and the gate and the substrate are connected to the gate-substrate control circuit; the basic protection circuit detects the charge and discharge conditions of the battery and sends a control signal to the gate-substrate control circuit, enabling the gate-substrate control circuit to control the conduction of the charge and discharge control MOS transistor according to the control signal, thereby controlling the charge and discharge of the battery; the clamping circuit is used to clamp the supply voltage of the gate-substrate control circuit to prevent damage to the gate-substrate control circuit and the charge and discharge control MOS transistor. The present invention can protect the battery protection circuit from damage by spike voltages and DC high voltages, and extend the service life of the charge and discharge circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of battery charging and discharging, and particularly to a single-wafer battery protection circuit and a charging and discharging circuit with improved ability to resist spike voltages. Background Art

[0002] With the continuous increase in the functions of mobile terminals in recent years, the performance of mobile terminals has also been rapidly improved, which poses greater requirements for terminal batteries. Some application batteries need to be made very small, and some application batteries need to be made at low cost. However, traditional battery protection solutions usually occupy a large board area and are very costly, and are increasingly unable to meet the new market demands.

[0003] Traditional battery protection solutions are achieved by discrete devices. A control circuit chip and a chip containing two N-type power MOS transistors are required. The control circuit chip controls the charging and discharging of the battery by controlling the gate voltages of these two power MOS transistors. The control circuit chip is made using CMOS technology, while the power MOS transistor chip is usually made using a vertical structure DMOS or UMOS transistor. Since CMOS and DMOS / UMOS are two completely different technologies, the control circuit chip and the two power MOS transistor chips usually come from two different suppliers and are two independent chips. In addition, the charging and discharging peripheral circuit of this discrete device solution requires two resistors and a capacitor.

[0004] In order to reduce the area of the above discrete device battery protection solution and lower the solution cost, in Chinese Patent CN103474967A, our company proposed a single-wafer battery protection circuit and a charging and discharging circuit. This single-wafer battery protection circuit integrates the control circuit chip, the two power MOS transistor chips, and an external resistor of the traditional solution onto a semiconductor substrate. The external charging and discharging circuit only requires one resistor and one capacitor. The single-wafer battery protection solution proposed by our company not only integrates the control circuit chip and the two power MOS transistor chips onto a semiconductor substrate, but further, our company combines the two power MOS transistor structures of the traditional solution into one power MOS transistor to further reduce the solution area and lower the solution cost.

[0005] Currently, in order to minimize the circuit area and cost, 5V CMOS technology is usually selected for implementation. The breakdown voltage of MOS transistors in 5V CMOS technology is 8V - 12V. Since the battery protection circuit may generate spike voltages and DC high voltages up to 16V during charging and discharging and production testing, the single-wafer battery protection circuit made using 5V CMOS technology will be broken down by the spike voltage or DC high voltage, resulting in damage to the single-wafer battery protection circuit.

[0006] An intuitive solution is to select a semiconductor process with a higher breakdown voltage to increase the withstand voltage of the single-wafer battery protection circuit, enabling it to withstand a 16V spike voltage and a high DC voltage. However, this will increase the number of process layers and greatly increase the area occupied by semiconductor devices on the chip, significantly driving up the cost of the protection circuit.

[0007] In view of this, the present invention provides a single-wafer battery protection circuit and a charge-discharge circuit with improved spike voltage resistance to solve the problem of damage to the single-wafer battery protection circuit by high DC voltage and spike voltage. Summary of the Invention

[0008] The object of the present invention is to provide a single-wafer battery protection circuit and a charge-discharge circuit with improved spike voltage resistance, which can protect the single-wafer battery protection circuit from damage by high DC voltage and spike voltage during the battery production test process and charge-discharge use, and extend the service life of the charge-discharge circuit and the battery.

[0009] The technical solution provided by the present invention is as follows:

[0010] The present invention provides a single-wafer battery protection circuit with improved spike voltage resistance, including: a basic protection circuit, a clamping circuit, a gate-substrate control circuit, and a charge-discharge control MOS transistor;

[0011] One end of the source and drain of the charge-discharge control MOS transistor is connected to the negative terminal of the battery, and the other end of the source and drain of the charge-discharge control MOS transistor is connected to the negative pole of the charger or the load; the gate and substrate of the charge-discharge control MOS transistor are respectively connected to the gate-substrate control circuit.

[0012] The basic protection circuit detects the charge-discharge condition of the battery and sends a control signal to the gate-substrate control circuit, enabling the gate-substrate control circuit to control the conduction condition of the charge-discharge control MOS transistor according to the control signal, thereby controlling the charge-discharge of the battery;

[0013] The clamping circuit is used to clamp the supply voltage of the gate-substrate control circuit to prevent damage to the gate-substrate control circuit and the charge-discharge control MOS transistor.

[0014] The battery protection circuit in this solution involves a large number of semiconductor devices, which may be damaged by spike voltages or DC high voltages during the battery production test process and during charging and discharging. For example, the breakdown voltage of a MOS transistor in a 5V CMOS process is between 8V and 12V. If the spike voltage generated during the production test process and during charging and discharging exceeds this breakdown voltage, the MOS transistor will be damaged. Generally, an intuitive solution is to increase the breakdown voltage of the MOS transistor, which will increase the number of process layers and the area of the MOS transistor on the chip, increasing the cost of the chip. In order to protect the device from being damaged by spike voltages or DC high voltages while ensuring the cost and chip area, this solution adds a voltage clamping circuit to clamp the voltage within a certain range. Even if there are spike voltages or DC high voltages during the production test process and during charging and discharging, the voltage will be clamped within the safe voltage range by the voltage clamping circuit, ensuring that the protection circuit is not damaged.

[0015] During the production test process of the battery protection circuit, first, the battery protection chip and resistors and capacitors are made into a battery protection board, and then the battery protection board and the battery cell are connected together to form a battery with protection function. During the production test process of the battery, test equipment such as a protection board tester, an integrated tester, and a grading cabinet are often used. The protection board tester is used to detect whether the protection board is qualified, the integrated tester is used to detect whether the battery with protection function is qualified, and the grading cabinet is used to detect the capacity of the battery with protection function. These test equipment often generate spike voltages or DC high voltages up to 16V during the test process. Therefore, in the traditional battery protection solution, the breakdown voltages of the charging control MOS transistor Mc and the discharging control MOS transistor Md need to be made above 16V to prevent the battery with protection function from being broken down by the 16V spike voltage or DC high voltage during the production test process.

[0016] Theoretically, for a single-wafer battery protection circuit, the breakdown voltages of the source and drain of the charge and discharge control MOS transistors need to be made above 16V at the same time to ensure that the battery with protection function is not broken down by the spike voltage or DC high voltage up to 16V generated by the test equipment during the production test process. However, making the breakdown voltage of the charge and discharge control MOS transistor above 16V will result in a high cost.

[0017] By using the voltage clamping circuit of the present invention, the breakdown voltage of the charge and discharge control MOS transistor only needs to be 12V, which is the breakdown voltage of the traditional 5V CMOS process, to prevent the battery with protection function from being broken down by the spike voltage or DC high voltage up to 16V during the production test process and during charging and discharging.

[0018] Preferably, the gate-substrate control circuit includes a gate control part and a substrate control part; the gate control part is connected to the gate of the charge and discharge control MOS transistor, and the substrate control part is connected to the substrate of the charge and discharge control MOS transistor;

[0019] The gate control part outputs a gate control response signal according to the control signal to control the gate voltage of the charge and discharge control MOS transistor. The substrate control part outputs a substrate control response signal according to the control signal to control the substrate voltage of the charge and discharge control MOS transistor, thereby controlling the conduction state of the charge and discharge control MOS transistor.

[0020] Preferably, the clamping circuit includes a voltage dividing resistor R5 and a Zener diode; one end of the voltage dividing resistor R5 is connected to the supply voltage VDD, the other end of the voltage dividing resistor R5 is connected to the negative electrode of the Zener diode, and the positive electrode of the Zener diode is connected to the VSS terminal.

[0021] According to the voltage stabilizing principle of the Zener diode, this solution can well clamp the supply voltage of the gate substrate control circuit within a safe voltage range to protect the gate substrate control circuit and the charge and discharge control MOS transistor from being damaged.

[0022] Preferably, the clamping circuit includes a voltage dividing resistor R5 and N diodes connected in series in one direction, where N≥1;

[0023] One end of the voltage dividing resistor R5 is connected to the supply voltage VDD, the other end of the voltage dividing resistor R5 is connected to the positive end of the N diodes connected in series in one direction, and the negative end of the N diodes connected in series in one direction is connected to the VSS terminal.

[0024] Preferably, the clamping circuit includes a voltage dividing resistor R5 and N NMOS transistors connected in series, where N≥1;

[0025] One end of the voltage dividing resistor R5 is connected to the supply voltage VDD, and the other end of the voltage dividing resistor R5 is connected to the VSS terminal through the N NMOS transistors connected in series.

[0026] Preferably, the clamping circuit includes a voltage dividing resistor R5 and N PMOS transistors connected in series, where N≥1;

[0027] One end of the voltage dividing resistor R5 is connected to the supply voltage VDD, and the other end of the voltage dividing resistor R5 is connected to the VSS terminal through the N PMOS transistors connected in series.

[0028] Preferably, the clamping circuit includes a low dropout linear regulator.

[0029] Preferably, it further includes: an over-temperature protection circuit for detecting the temperature of the integrated chip of the battery protection circuit during charge and discharge, and jointly controlling the sending of the control signal with the basic protection circuit.

[0030] Preferably, the over-temperature protection circuit includes an over-temperature comparator and a logic control unit.

[0031] In this solution, the over-temperature protection circuit can detect the temperature of the chip where the battery protection circuit is located in real time. When the temperature is abnormal, the over-temperature protection circuit can send an over-temperature control signal to disconnect the charge and discharge circuit, playing a protective role for the battery protection circuit.

[0032] Preferably, the basic protection circuit specifically includes:

[0033] A reference circuit, a discharge over-current comparator, a discharge short-circuit comparator, a charge over-current comparator, an over-discharge voltage comparator, an over-charge voltage comparator, a delay circuit, and a charge and discharge detection circuit; the control signals include a first control signal VCHOC1, a second control signal VOC2, and a third control signal VOD2;

[0034] The reference circuit is used to generate the positive input signal VOC1 of the discharge over-current comparator; the positive input signal VSHORT of the discharge short-circuit comparator; the negative input signal VCHOC of the charge over-current comparator; the negative input signal VODV of the over-discharge voltage comparator; the positive input signal VOCV of the over-charge voltage comparator; and generate the positive input signal VPN and the negative input signal VOTP of the over-temperature comparator.

[0035] The discharge over-current comparator outputs a high level VDD or a low level VGND based on the comparison result of the positive input signal VOC1 and the negative input signal virtual ground voltage VM1;

[0036] The discharge short-circuit comparator outputs a high level VDD or a low level VGND based on the comparison result of the positive input signal VSHORT and the negative input signal virtual ground voltage VM1;

[0037] The charge over-current comparator outputs a high level VDD or a low level VGND based on the comparison result of the positive input signal virtual ground voltage VM1 and the negative input signal VCHOC; and outputs the first control signal VCHOC1 to the gate substrate control circuit;

[0038] The over-charge voltage comparator outputs a high level VDD or a low level VGND based on the comparison result of the positive input signal VOCV and the negative input signal VROCV after the VDD voltage is divided by a resistor;

[0039] The over-discharge voltage comparator outputs a high level VDD or a low level VGND based on the comparison result of the positive input signal VRODV after the VDD voltage is divided by a resistor and the negative input signal VODV;

[0040] The delay circuit performs respective delays based on the output results of the discharge overcurrent comparator, the discharge short - circuit comparator, the charge overcurrent comparator, the overcharge voltage comparator, and the overdischarge voltage comparator. The lengths of their respective delays may be different. Then, after logical processing, the second control signal VOC2 and the third control signal VOD2 are output.

[0041] Preferably, in the basic protection circuit, when both the second control signal VOC2 and the third control signal VOD2 output high levels, the gate - substrate control circuit outputs a high - level gate voltage VGATE as a gate control response signal according to the second control signal VOC2 and the third control signal VOD2;

[0042] When at least one of the second control signal VOC2 and the third control signal VOD2 outputs a low level VGND, the gate - substrate control circuit outputs a low - level gate voltage VGATE as a gate control response signal according to the second control signal VOC2 and the third control signal VOD2.

[0043] The present invention also provides a battery charging circuit, including the above - mentioned battery protection circuit, a charger, a battery, and an RC filtering circuit, where:

[0044] One end of the resistor R0 in the RC filtering circuit is connected to the supply voltage VDD terminal, and the other end of the resistor R0 is connected to the positive electrode of the battery;

[0045] One end of the capacitor C0 in the RC filtering circuit is connected to the supply voltage VDD terminal, and the other end of the capacitor C0 is connected to the negative electrode of the battery;

[0046] The positive electrode of the charger is connected to the positive electrode of the battery during charging to provide a charging voltage for the battery.

[0047] The present invention also provides a battery discharging circuit, including the above - mentioned battery protection circuit, an RC filtering circuit, a battery, and a load, where:

[0048] One end of the resistor R0 in the RC filtering circuit is connected to the supply voltage VDD terminal, and the other end of the resistor R0 is connected to the positive electrode of the battery;

[0049] One end of the capacitor C0 in the RC filtering circuit is connected to the supply voltage VDD terminal, and the other end of the capacitor C0 is connected to the negative electrode of the battery;

[0050] When the battery discharges, the positive electrode of the battery is connected to the positive electrode of the load to supply power to the load, and the negative electrode of the load is connected to the negative electrode of the battery through a charge and discharge control MOS transistor.

[0051] Through a single-wafer battery protection circuit and a charge and discharge circuit for improving the ability to resist spike voltage provided by the present invention, at least one of the following beneficial effects can be brought:

[0052] In the present invention, a clamping circuit is used to clamp the voltage between the power supply voltage GVDD of the gate substrate control circuit and the VSS terminal within a preset range, improving the withstand voltage of the battery protection circuit chip during production testing and during charge and discharge use, and preventing damage to the devices in the battery protection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The following will further illustrate the above characteristics, technical features, advantages and implementation manners of a single-wafer battery protection circuit and a charge and discharge circuit for improving the ability to resist spike voltage in a clear and understandable manner in combination with the drawings.

[0054] Figure 1 is the charging and discharging circuit structure diagram of a traditional discrete device battery protection circuit;

[0055] Figure 2 is the charging and discharging circuit structure diagram of an existing single-wafer battery protection circuit;

[0056] Figure 3 is a circuit schematic diagram of a gate substrate control circuit in an existing single-wafer battery protection solution technology;

[0057] Figure 4 is the structure diagram of a single-wafer battery protection circuit and a charge and discharge circuit for improving the ability to resist spike voltage according to the present invention;

[0058] Figure 5 is Figure 4 the structure diagram of the basic protection circuit in

[0059] Figure 6 is Figure 4 the circuit diagram of the overtemperature protection circuit in

[0060] Figure 7 is Figure 4 a circuit schematic diagram of a gate substrate control circuit in

[0061] Figure 8 is Figure 4 another circuit schematic diagram of a gate substrate control circuit in

[0062] Figure 9 is a circuit schematic diagram of a clamping circuit in an embodiment of the present invention;

[0063] Figure 10 It is another circuit schematic diagram of the clamping circuit in an embodiment of the present invention;

[0064] Figure 11 It is another circuit schematic diagram of the clamping circuit in an embodiment of the present invention;

[0065] Figure 12 It is another circuit schematic diagram of the clamping circuit in an embodiment of the present invention;

[0066] Figure 13 It is another circuit schematic diagram of the clamping circuit in an embodiment of the present invention. Detailed implementation manners

[0067] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will describe the specific implementation manners of the present invention with reference to the accompanying drawings. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings, and other implementation manners can be obtained.

[0068] To make the drawings concise, only the parts related to the present invention are schematically shown in each drawing, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, in some drawings, components with the same structure or function are only schematically shown as one of them, or only one of them is marked. In this article, "one" not only means "only this one", but also means "more than one" situation.

[0069] Figure 1

[0070] Figure 2 It is a charge and discharge circuit for a traditional discrete device battery protection solution. The control circuit A controls the charge and discharge of the battery by controlling the gate voltages of two power MOS transistors (Mc and Md). The control circuit A is made by CMOS process, while the power MOS transistors (Mc and Md) are usually made of a vertical structure DMOS or UMOS transistor. Since CMOS and DMOS / UMOS are two completely different processes, the control circuit A and the two power MOS transistors (Mc and Md) usually come from two different suppliers and are two independent chips. The peripheral circuit requires two resistors R0 and Rvm and a capacitor C0.It is the internal block diagram of the battery protection circuit and the charge and discharge circuit in the single-wafer battery protection solution technology. When the battery protection circuit enters overcharge voltage protection, overcharge current protection, or overcharge temperature protection, the charging path of the battery protection circuit is closed, and the voltage of the charger is completely provided by the external charging circuit. The basic protection circuit, over-temperature protection circuit, logic control unit I12, and logic control unit I13 inside the battery protection circuit are powered by the battery and have no high voltage, so the circuit will not be damaged by high voltage. However, the power supply voltage of the gate-substrate control circuit during charging protection is the charger voltage. During the production test process and the charger connection process, this voltage may reach a high voltage of 16V, which will damage the gate-substrate control circuit and may also damage the charge and discharge control MOS transistor M0. Figure 3 It is the circuit diagram of the gate-substrate control circuit in the existing single-wafer battery protection solution technology. Refer to Figure 3 As shown, it includes a gate control circuit that outputs VGATE and a substrate control circuit that outputs VSUB. Since the low-level VSS voltage and VGND voltage of the gate control circuit are not exactly the same potential, the low potential of the VOD voltage, VOC voltage, and VCHOC1 voltage input to the gate control circuit is the VGND voltage and needs to be converted to the VSS voltage. The VOD voltage, VOC voltage, and VCHOC1 voltage all require a level conversion circuit. Here, the level conversion circuit of the VOD voltage is taken as an example for illustration.

[0071] MOS transistors M7, M8, M9, M10, and logic control unit I6 complete the low-level conversion of the VOD voltage. When the VOD voltage is the high level VDD, transistor M7 is cut off and transistor M8 is turned on, and the VODP voltage is the high level VDD; when the VOD voltage is the low level VGND, transistor M7 is turned on and transistor M8 is cut off, and the VODP voltage is the low level VSS, completing the conversion from the VGND level to the VSS level. Similarly, the VOC voltage is converted to the VOCP voltage, the VCHOC1 voltage is converted to the VCHOC1P voltage, and the VCHOC1N voltage. When both the VODP voltage and the VOCP voltage are high levels, the VGATE terminal outputs a high level VDD. When either the VODP voltage or the VOCP voltage is the low level VSS, the VGATE terminal outputs a low level VSS. When the VOCP is at a high level, VGOC is at a low level, VGOCB is at a high level, the MOS transistor M1 is turned on, the MOS transistor M2 is cut off, and the output VSUB voltage is equal to the VGND voltage; when the VOCP is at a low level,

[0072] When VGOC is at a high level, VGOCB is at a low level, the MOS transistor M1 is turned off, the MOS transistor M2 is turned on, and the output VSUB voltage is equal to the VM voltage. When the VCHOC1 voltage is high, the VCHOC1P voltage is high and the VCHOC1N voltage is low. The MOS transistor M19 is turned on and the MOS transistor M20 is turned off, and the VSS voltage is equal to the VGND voltage. When the VCHOC1 voltage is low, the VCHOC1P voltage is low and the VCHOC1N voltage is high. The MOS transistor M19 is turned off and the MOS transistor M20 is turned on, and the VSS voltage is equal to the VM voltage.

[0073] In the above description, when the VCHOC1 voltage is at a low level, the VSS voltage is equal to the VM voltage. Then, the voltage difference between the VDD voltage and the VSS voltage is the voltage difference between the VDD voltage and the VM voltage. During the production test process and the charge and discharge use, a peak voltage or a DC voltage as high as 16V may be generated between the VDD voltage and the VM voltage. The breakdown voltage of the 5V CMOS process MOS transistor is between 8V and 12V, which is lower than the generated peak voltage or DC voltage. Then, the existing gate-substrate control circuit will be damaged or broken down.

[0074] Based on the above analysis conclusion, the present invention provides a new battery protection circuit. Figure 4 It is a structural diagram of a battery charge and discharge circuit in an embodiment of the present invention. Figure 5 is Figure 4 a structural diagram of the basic protection circuit in Figure 6 is Figure 4 a circuit diagram of the overtemperature protection circuit in Figure 7 、 Figure 8 is Figure 4 two circuit diagrams of the gate-substrate control circuit in Figure 7 、 Figure 8 As shown, the gate-substrate control circuit includes a gate control part and a substrate control part, and the gate control part and the substrate control part have a common circuit. Referring to Figures 4 to 7 shown, relative to Figure 2 the battery protection circuit in Figure 3 and the gate-substrate control circuit in ", Figure 4 In Figure 7As shown, the positive power supply terminal of the improved gate-substrate control circuit is the output voltage GVDD of the clamping circuit. When the battery protection circuit enters overcharge voltage protection, overcharge current protection, or overcharge temperature protection, the voltage of the negative power supply terminal VSS is VM. Otherwise, the voltage of the negative power supply terminal VSS is VGND. The supply voltage of the gate-substrate control circuit is GVDD~VM or GVDD~VGND, and this supply voltage is clamped to be lower than the breakdown voltage of all MOS transistors inside the gate-substrate control circuit, so the gate-substrate control circuit will not be damaged.

[0075] Referring to Figure 4 As shown, the battery protection circuit in an embodiment of the present invention includes: a basic protection circuit, an over-temperature protection circuit, a clamping circuit, a gate-substrate control circuit, a first logic control unit I12, a second logic control unit I13, and a charge and discharge control MOS transistor M0. One end of the source and drain of the charge and discharge control MOS transistor M0 is connected to the negative terminal of the battery, and the other end of the source and drain of the charge and discharge control MOS transistor M0 is connected to the negative pole of the charger or load; the gate and substrate of the charge and discharge control MOS transistor M0 are respectively connected to the gate-substrate control circuit; the basic protection circuit detects the charge and discharge conditions of the battery and sends a control signal to the gate-substrate control circuit, so that the gate-substrate control circuit controls the conduction condition of the charge and discharge control MOS transistor M0 according to the control signal, thereby controlling the charge and discharge of the battery.

[0076] Referring to Figure 5 As shown, Figure 4 The basic protection circuit in includes: a reference circuit, a discharge overcurrent comparator, a discharge short-circuit comparator, a charge overcurrent comparator, an over-discharge voltage comparator, an overcharge voltage comparator, a charge detection circuit, a delay circuit, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a logic control unit I0, a logic control unit I1, a logic control unit I2, a logic control unit I3, and a logic control unit I4.

[0077] Among them, the reference circuit is used to generate the positive input signal VOC1 of the discharge overcurrent comparator, the positive input signal VSHORT of the discharge short-circuit comparator, the negative input signal VCHOC of the charge overcurrent comparator, the reference output voltages VPN, VOTP, the positive input signal VOCV of the overcharge voltage comparator, and to generate the negative input signal VODV of the over-discharge voltage comparator.

[0078] Based on the comparison result of the positive input signal VOC1 and the negative input signal virtual ground voltage VM1, when VOC1 is greater than VM1, the discharge overcurrent comparator outputs a high level VDD, and when VOC1 is lower than VM1, it outputs a low level VGND.

[0079] The discharge short - circuit comparator is based on the comparison result of the magnitude between the positive input signal VSHORT and the negative input signal virtual ground voltage VM1. When VSHORT is greater than VM1, it outputs a high level VDD; when VSHORT is lower than VM1, it outputs a low level VGND.

[0080] The charge over - current comparator is based on the comparison result of the magnitude between the positive input signal virtual ground voltage VM1 and the negative input signal VCHOC. When VM1 is greater than VCHOC, it outputs a high level VDD; when VM1 is lower than VCHOC, it outputs a low level VGND.

[0081] The over - charge voltage comparator is based on the comparison result of the magnitude between the positive input signal VOCV and the negative input signal VROCV which is the voltage of VDD after resistor voltage division, and outputs a high level VDD or a low level VGND.

[0082] The over - discharge voltage comparator is based on the comparison result of the magnitude between the positive input signal VRODV which is the voltage of VDD after resistor voltage division and the negative input signal VODV, and outputs a high level VDD or a low level VGND.

[0083] The charge - discharge detection circuit is based on the comparison result of the magnitude between the positive input VGND and the negative input signal VM1, and outputs a high level VDD or a low level VGND. When VGND is greater than VM1, it outputs a high level VDD; when VGND is lower than VM1, it outputs a low level VGND.

[0084] The delay circuit is used to delay the output signals VOC1P of the discharge over - current comparator, VSHORTP of the discharge short - circuit comparator, VCHOC1 of the charge over - current comparator, VODVP of the over - discharge voltage comparator, and VOCVP of the over - charge voltage comparator, and the corresponding outputs after delay are VDOC1, VDSHORT, VDCHOC, VDODV, and VDOCV. VDOC1 is the signal of VOC1P after delay, VDSHORT is the signal of VSHORTP after delay, VDCHOC is the signal of VCHOC1 after delay, VDODV is the signal of VODVP after delay, and VDOCV is the signal of VOCVP after delay.

[0085] When VDOC1, VDSHORT, and VDODV are all high, the output of VOD3 is a high level VDD; when at least one of VDOC1, VDSHORT, and VDODV is low, the output of VOD3 is a low level VGND.

[0086] When VDCHOC and VDOCV are both high, the output of VOC3 is a high level VDD. When at least one of VDCHOC and VDOCV is low, the output of VOC3 is a low level VGND.

[0087] When at least one of VOD3 and VCHP is high, the output of VOD2 is the high level VDD. When both VOD3 and VCHP are low, the output of VOD2 is the low level VGND.

[0088] When at least one of VOC3 and VCHN is high, the output of VOC2 is the high level VDD. When both VOC3 and VCHN are low, the output of VOC2 is the low level VGND.

[0089] Figure 6 It is an over-temperature protection circuit, including an over-temperature comparator, a first logic control unit I14, a second logic control unit I15, and a third logic control unit I16.

[0090] Based on the comparison result of the positive input signal VPN and the negative input signal VOTP, the over-temperature comparator outputs a high level when VPN is greater than VOTP, and outputs a low level when VPN is less than VOTP.

[0091] When at least one of VOTPP and VCHN1 is high, the output of VCHOTP is the high level VDD. When both VOTPP and VCHN1 are low, the output of VCHOTP is low.

[0092] When at least one of VOTPP and VCHP is high, the output of VDISOTP is the high level VDD. When both VOTPP and VCHP are low, the output of VDISOTP is low.

[0093] Figure 7 It is a circuit schematic diagram of a gate-substrate control circuit. Resistors R11, R12, R13, R14, R15, R16 and MOS transistors M21, M22, M23, M24, M25, M26 are added to the original gate-substrate control circuit. The functions of the added resistors and MOS transistors are explained below with R11, R12, M21, and M22: Due to the addition of a clamping circuit, the positive power supply voltage of the gate-substrate control circuit is the output potential GVDD of the clamping circuit, and the input voltage VOD may be the high level VDD or the low level VGND. The voltages of GVDD~VDD and GVDD~VGND may exceed the gate breakdown voltage of MOS transistors M7 and M8, thus damaging MOS transistors M7 and M8. After adding R11, M21, R12, and M22, the maximum voltage from the GATE of M7 and M8 to GVDD is the parasitic diode voltage of M21 and M22, and this parasitic diode voltage will not damage the MOS transistors. Similarly, R13, R14, M23, and M24 protect M11 and M12 from damage; R15, R16, M25, and M26 protect M15 and M16 from damage.

[0094] Figure 8 It is to Figure 7M21, M22, M23, M24, M25, and M26 in it are replaced by diodes to achieve the same function as above.

[0095] Figure 9 It is a structural diagram of a clamping circuit in an embodiment of the present invention. It includes a series-connected voltage-dividing resistor R5 and a Zener diode Z0; the connection end of the voltage-dividing resistor R5 and the Zener diode Z0 is the output terminal GVDD, the other connection of the voltage-dividing resistor R5 is supplied with the power supply voltage VDD, and the other end of the Zener diode is connected to the VSS terminal.

[0096] The principle that the above circuit can clamp the voltage between GVDD and VSS within a preset range is as follows: the PN junction of the Zener diode has an extremely low resistance in the reverse breakdown state. Therefore, when the Zener diode is conducting, the voltage of GVDD~VSS is equal to the breakdown voltage of the Zener diode; when the Zener diode is not conducting, GVDD is almost equal to VDD.

[0097] When the voltage of VDD~VSS is lower than the conduction voltage of the Zener diode, GVDD is equal to VDD; when the voltage of VDD~VSS is higher than the conduction voltage of the Zener diode, the highest output voltage of GVDD~VSS is the Zener diode voltage. Generally, the conduction voltage of the Zener diode inside an integrated circuit is 5.5~6.5V. If the voltage of VDD~VSS continues to increase, the Zener diode voltage stabilizes at the conduction voltage of the Zener diode, and the remaining voltage drops on the resistor R5. There will be no problem even if the voltage drop on the resistor R5 is dozens of volts; therefore, the withstand voltage of VDD~VSS can be as high as dozens of volts without damaging the clamping circuit.

[0098] The power supply voltage of the gate substrate control circuit is the voltage of GVDD~VSS, and the maximum value is the conduction voltage of the Zener diode. It is lower than the breakdown voltage of the MOS transistor, which is 8V~12V. Therefore, the gate substrate control circuit will not be damaged.

[0099] Figure 10 It is a structural diagram of a clamping circuit in another embodiment of the present invention.

[0100] Refer to Figure 10 As shown, the clamping circuit includes a voltage-dividing resistor R5 and N serially connected one-way diodes, N≥1; one end of the voltage-dividing resistor R5 is connected to the power supply voltage VDD, the other end of the voltage-dividing resistor R5 is connected to the positive end of the N serially connected one-way diodes, and the negative end of the N serially connected one-way diodes is connected to the VSS terminal.

[0101] It can be seen that compared with Figure 9 the difference is that the Zener diode is replaced by N serially connected diodes that conduct unidirectionally from the GVDD terminal of the power supply voltage to the VSS terminal, where N≥1.

[0102] The principle that multiple diodes in series can clamp the voltage between GVDD and VSS within a preset range is as follows: By utilizing the slow-varying characteristic of the forward conduction voltage of the diode, when the diode conducts, the voltage of GVDD~VSS is equal to the sum of the conduction voltages of multiple diodes; when the diode does not conduct, GVDD is almost equal to VDD.

[0103] Figure 11 And Figure 12 is the structural diagram of the clamping circuit in another embodiment of the present invention.

[0104] Referring to Figure 11 、 12 As shown, the clamping circuit includes a voltage-dividing resistor R5 and N series-connected NMOS transistors, N≥1; one end of the voltage-dividing resistor R5 is connected to the supply voltage VDD, and the other end of the voltage-dividing resistor R5 is connected to the VSS terminal through the N series-connected NMOS transistors. Alternatively, the clamping circuit includes a voltage-dividing resistor R5 and N series-connected PMOS transistors, N≥1; one end of the voltage-dividing resistor R5 is connected to the supply voltage VDD, and the other end of the voltage-dividing resistor R5 is connected to the VSS terminal through the N series-connected PMOS transistors.

[0105] It can be seen that compared with Figure 9 , the difference is that the Zener diode is replaced by N series-connected NMOS transistors or N series-connected PMOS transistors, where N≥1.

[0106] The principle that multiple NMOS transistors in series can clamp the voltage between GVDD and VSS within a preset range is as follows: The drain and gate of the NMOS transistor are short-circuited together, and the NMOS transistor is equivalent to a diode, and the forward conduction voltage is the threshold voltage Vthn of the NMOS transistor. Therefore, when the NMOS transistor conducts, the GVDD voltage is equal to the sum of the threshold voltages of multiple NMOS transistors; when the NMOS transistor does not conduct, GVDD is almost equal to VDD.

[0107] The principle that multiple PMOS transistors in series can clamp the voltage between GVDD and VSS within a preset range is the same as the principle that multiple NMOS transistors in series clamp the voltage between GVDD and VSS within a preset range.

[0108] Figure 13 is the structural diagram of the clamping circuit in another embodiment of the present invention.

[0109] Referring to Figure 13 As shown, the clamping circuit includes a low-dropout linear regulator. It can be seen that compared with Figure 9 , the difference is that the clamping circuit is a low-dropout linear regulator.

[0110] The principle that the low dropout linear regulator (LDO) can clamp the voltage between GVDD and VSS within a preset range is as follows: When the voltage of VDD~VSS is low, the voltage of VDD~VSS is divided by resistors R6 and R7 to output a lower voltage VG3. VG3 is lower than the gate turn-on voltage of NMOS transistor M3, so NMOS transistor M3 is turned off, VD3 is high. After passing through the logic control unit I5, VEN0 is low, MOS transistor M6 is cut off, and MOS transistor M5 is turned on. The output GVDD voltage is equal to the VDD voltage. When the voltage of VDD~VSS is high, the voltage of VDD~VSS is divided by resistors R6 and R7 to output a higher voltage VG3. VG3 is higher than the gate turn-on voltage of NMOS transistor M3, so NMOS transistor M3 is turned on, VD3 is low. After passing through the logic control unit I5, VEN0 is high, MOS transistor M6 is turned on, and MOS transistor M5 is cut off. Since the positive input voltage reference voltage of the amplifier is equal to the negative input voltage VR10 of the amplifier, and at the same time the VR10 voltage is obtained by dividing the GVDD voltage by resistors R9 and R10, the output voltage: GVDD = reference voltage * (R9 + R10) / R10.

[0111] It should be noted that the above embodiments can be freely combined as needed. The above are only the preferred embodiments of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A single-wafer battery protection circuit for improving the ability to resist spike voltage, characterized by comprising: Basic protection circuit, clamping voltage circuit, gate-substrate control circuit, and charge-discharge control MOS transistor; One end of the source and drain of the charge-discharge control MOS transistor is connected to the negative terminal of the battery, and the other end of the source and drain of the charge-discharge control MOS transistor is connected to the negative terminal of the charger or the load; the gate and substrate of the charge-discharge control MOS transistor are respectively connected to the gate-substrate control circuit; The basic protection circuit detects the charge-discharge condition of the battery, sends a control signal to the gate-substrate control circuit, and enables the gate-substrate control circuit to control the conduction condition of the charge-discharge control MOS transistor according to the control signal, thereby controlling the charge-discharge of the battery; The clamping voltage circuit is used to clamp the supply voltage of the gate-substrate control circuit; The basic protection circuit specifically includes: A reference circuit, a discharge overcurrent comparator, a discharge short-circuit comparator, a charge overcurrent comparator, an over-discharge voltage comparator, an overcharge voltage comparator, a delay circuit, and a charge-discharge detection circuit; the control signals include a first control signal VCHOC1, a second control signal VOC2, and a third control signal VOD2; The reference circuit is used to generate the positive input signal VOC1 of the discharge overcurrent comparator; the positive input signal VSHORT of the discharge short-circuit comparator; the negative input signal VCHOC of the charge overcurrent comparator; the negative input signal VODV of the over-discharge voltage comparator; the positive input signal VOCV of the overcharge voltage comparator; and generate the input signals VPN and VOTP of the over-temperature protection circuit; The over-temperature protection circuit is used to detect the temperature of the integrated chip of the battery protection circuit during charge-discharge and jointly control the sending of the control signal with the basic protection circuit; The discharge overcurrent comparator outputs a high level VDD or a low level VGND based on the comparison result of the positive input signal VOC1 and the negative input signal virtual ground voltage VM1; The discharge short-circuit comparator outputs a high level VDD or a low level VGND based on the comparison result of the positive input signal VSHORT and the negative input signal virtual ground voltage VM1; The charge overcurrent comparator outputs a high level VDD or a low level VGND based on the comparison result of the positive input signal virtual ground voltage VM1 and the negative input signal VCHOC; and outputs the first control signal VCHOC1 to the gate-substrate control circuit; The overcharge voltage comparator outputs a high level VDD or a low level VGND based on the comparison result of the positive input signal VOCV and the negative input signal VROCV after the VDD voltage is divided by a resistor; The over-discharge voltage comparator outputs a high level VDD or a low level VGND based on the comparison result of the positive input signal VRODV after the VDD voltage is divided by a resistor and the negative input signal VODV; The delay circuit performs respective corresponding delays based on the output results of the discharge overcurrent comparator, the discharge short - circuit comparator, the charge overcurrent comparator, the overcharge voltage comparator, and the overdischarge voltage comparator, and then outputs the second control signal VOC2 and the third control signal VOD2 after logical processing.

2. The single-wafer battery protection circuit for improving the ability to resist peak voltage according to claim 1, wherein: The gate - substrate control circuit includes a gate control part and a substrate control part; the gate control part is connected to the gate of the charge - discharge control MOS transistor, and the substrate control part is connected to the substrate of the charge - discharge control MOS transistor; When the battery is charged and discharged, the gate control part outputs a gate control response signal according to the control signal to control the gate voltage of the charge - discharge control MOS transistor, and the substrate control part outputs a substrate control response signal according to the control signal to control the substrate voltage of the charge - discharge control MOS transistor, thereby controlling the conduction condition of the charge - discharge control MOS transistor.

3. The single-wafer battery protection circuit for improving the ability to resist peak voltage according to claim 1, wherein The clamping circuit includes a voltage - dividing resistor R5 and a Zener diode; one end of the voltage - dividing resistor R5 is connected to the supply voltage VDD, the other end of the voltage - dividing resistor R5 is connected to the negative electrode of the Zener diode, and the positive electrode of the Zener diode is connected to the VSS terminal.

4. A single-wafer battery protection circuit for improving the ability to resist spike voltage according to claim 1, characterized in that, The clamping circuit includes a voltage - dividing resistor R5 and N serially - connected single - way diodes, where N≥1; One end of the voltage - dividing resistor R5 is connected to the supply voltage VDD, the other end of the voltage - dividing resistor R5 is connected to the positive end of the N serially - connected single - way diodes, and the negative end of the N serially - connected single - way diodes is connected to the VSS terminal.

5. The single-wafer battery protection circuit for improving the ability to resist peak voltage according to claim 1, characterized in that, The clamping circuit includes a voltage - dividing resistor R5 and N serially - connected NMOS transistors, where N≥1; One end of the voltage - dividing resistor R5 is connected to the supply voltage VDD, and the other end of the voltage - dividing resistor R5 is connected to the VSS terminal through the N serially - connected NMOS transistors.

6. The single-wafer battery protection circuit for improving the ability to resist spike voltage according to claim 1, characterized in that, The clamping circuit includes a voltage - dividing resistor R5 and N serially - connected PMOS transistors, where N≥1; One end of the voltage - dividing resistor R5 is connected to the supply voltage VDD, and the other end of the voltage - dividing resistor R5 is connected to the VSS terminal through the N serially - connected PMOS transistors.

7. The single-wafer battery protection circuit for improving the ability to resist peak voltage according to claim 1, wherein The clamping circuit includes a low - dropout linear regulator.

8. The single-wafer battery protection circuit for improving the ability to resist spike voltage according to claim 1, wherein, In the basic protection circuit, when both the second control signal VOC2 and the third control signal VOD2 output high levels, the gate - substrate control circuit outputs a high - level gate voltage VGATE as the gate control response signal according to the second control signal VOC2 and the third control signal VOD2; When at least one of the second control signal VOC2 and the third control signal VOD2 outputs a low level, the gate - substrate control circuit outputs a low - level gate voltage VGATE as the gate control response signal according to the second control signal VOC2 and the third control signal VOD2.

9. A battery charging circuit, characterized in that it includes a single - wafer battery protection circuit for improving the anti - spike - voltage ability as described in any one of claims 1 to 8, as well as a charger, a battery, and an RC filter circuit, where: One end of the resistor R0 in the RC filter circuit is connected to the power supply voltage VDD terminal, and the other end of the resistor R0 is connected to the positive electrode of the battery; One end of the capacitor C0 in the RC filter circuit is connected to the power supply voltage VDD terminal, and the other end of the capacitor C0 is connected to the negative electrode of the battery. The positive electrode of the charger is connected to the positive electrode of the battery to provide a charging voltage for the battery, and the negative electrode of the charger is connected to the negative electrode of the battery through the charge and discharge control MOS transistor.

10. A battery discharge circuit, characterized by comprising a single-wafer battery protection circuit for improving the ability to resist spike voltages as described in any one of claims 1 to 8, as well as an RC filter circuit, a battery, and a load, wherein: One end of the resistor R0 in the RC filter circuit is connected to the power supply voltage VDD terminal, and the other end of the resistor R0 is connected to the positive electrode of the battery; One end of the capacitor C0 in the RC filter circuit is connected to the power supply voltage VDD terminal, and the other end of the capacitor C0 is connected to the negative electrode of the battery; The positive electrode of the battery is connected to the positive electrode of the load to provide power for the load, and the negative electrode of the load is connected to the negative electrode of the battery through the charge and discharge control MOS transistor.

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