Systems, methods, and apparatus for memory access and scheduling

Abstract

The present invention relates to systems, methods, and apparatus for memory access and scheduling. A memory controller method and apparatus includes modification of at least one of a first timing scheme or a second timing scheme based on information regarding one or more data requests to be included in at least one of a first queue scheduler or a second queue scheduler, the first timing scheme indicating when one or more requests in the first queue scheduler are to be issued to a first memory set via a first memory set interface and through a channel, the second timing scheme indicating when one or more requests in the second queue scheduler are to be issued to a second memory set via a second memory set interface and through the channel. Further, issuance of a request to at least one of the first memory set (in accordance with the modified first timing scheme) or the second memory set (in accordance with the modified second timing scheme) can be included.

Description

Technical Field

[0001] Various aspects described herein relate generally to systems, methods, and apparatus for optimizing management of memory resources, and more particularly to enhanced memory access, scheduling architectures, and methods associated therewith. Background Art

[0002] Advances in memory technology can be integrated into client and server platforms to achieve optimized performance. While the improved capabilities from such innovations may be apparent from experimental data, the methodology for implementing new technologies into manufactured products can present real-world challenges. In some implementations, new dedicated interfaces on the central processing unit (CPU) and / or dedicated sockets on the motherboard may be added to integrate these new technologies. Therefore, the benefits of providing the option to incorporate such advancements may be offset by the additional costs and usage associated with them. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] In the accompanying drawings, like reference characters generally refer to like parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the present disclosure. In the following description, various aspects of the present disclosure are described with reference to the following drawings, in which:

[0004] Figure 1 A first configuration of an exemplary computing system architecture is shown;

[0005] Figure 2 A second configuration of an exemplary computing system architecture is shown;

[0006] Figure 3 shows a logical representation of a first memory controller system having different multi-channel mode configurations;

[0007] Figure 4 shows a bar graph comparing read latency of a first queue scheduler in two exemplary dual channel mode configurations of a first memory controller system;

[0008] Figure 5 A logical representation of a first memory controller system having a dynamic multi-channel mode configuration is shown;

[0009] Figure 6 shows a logical representation of a second memory controller system having a dynamic multi-channel mode configuration;

[0010] Figure 7 A first exemplary method for performing data operations in accordance with some aspects is shown;

[0011] Figure 8A second exemplary method for performing data operations in accordance with some aspects is shown;

[0012] Figure 9 A third exemplary method for performing data operations in accordance with some aspects is shown; and

[0013] Figure 10 A fourth exemplary method for performing data operations in accordance with some aspects is shown. DETAILED DESCRIPTION

[0014] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and aspects in which the disclosure may be practiced.

[0015] Throughout the drawings, it should be noted that like reference numbers are used to depict the same or similar elements, features, and structures.

[0016] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over some aspects or designs.

[0017] The words "plurality" and "multiple" in the specification and claims explicitly refer to quantities greater than one. Therefore, any phrase that explicitly invokes the preceding words (e.g., "a number of [objects]," "a plurality of [objects]") referring to some number of objects explicitly refers to more than one of the objects. The terms "group," "set," "set," "series," "sequence," "grouping," and the like in the specification and claims, if any, refer to a quantity equal to or greater than one, i.e., one or more. The terms "proper subset," "reduced subset," and "smaller subset" refer to a subset of a set that is not equal to the set, i.e., a subset of the set that contains fewer elements than the set.

[0018] It should be understood that any vector and / or matrix notation utilized herein is in fact exemplary and is adopted only for the purpose of explanation. Therefore, it should be understood that the methods detailed in this disclosure are not limited to being implemented using only vectors and / or matrices, and that associated processes and calculations can be performed equivalently with respect to sets, sequences, groups, etc. of data, observations, information, signals, etc. In addition, it should be understood that references to "vectors" can refer to vectors of any size or orientation, including, for example, 1x1 vectors (e.g., scalars), 1xM vectors (e.g., row vectors), and Mx1 vectors (e.g., column vectors). Similarly, it should be understood that references to "matrices" can refer to matrices of any size or orientation, including, for example, 1x1 matrices (e.g., scalars), 1xM matrices (e.g., row vectors), and Mx1 matrices (e.g., column vectors).

[0019] As used herein, a "circuit" is understood to mean any type of logically implemented entity, which may include dedicated hardware or a processor executing software. Thus, a circuit may be an analog circuit, a digital circuit, a mixed-signal circuit, a logic circuit, a processor, a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a field-programmable gate array (FPGA), an integrated circuit, an application-specific integrated circuit (ASIC), or the like, or any combination thereof. Any other type of implementation of the corresponding functionality, which will be described in further detail below, may also be understood as a "circuit." It should be understood that any two (or more) of the circuits detailed herein may be implemented as a single circuit with equivalent functionality, etc., or conversely, any single circuit described herein may be implemented as two (or more) separate circuits with equivalent functionality, etc. Additionally, references to a "circuit" may refer to two or more circuits that together form a single circuit.

[0020] As used herein, "memory," "memory device," and the like may be understood as non-transitory computer-readable media in which data or information may be stored for retrieval. Thus, references to "memory" included herein may be understood to refer to volatile or non-volatile memory, including random access memory (RAM), read-only memory (ROM), flash memory, solid-state storage, magnetic tape, hard drives, optical drives, 3D XPoint TM etc., or any combination thereof. In addition, it will be appreciated that registers, shift registers, processor registers, data buffers, etc. are also encompassed by the term memory herein. It will be appreciated that a single component referred to as a "memory" or "a memory" may be comprised of more than one different type of memory, and thus may refer to a collective component comprising one or more types of memory. It will be readily understood that any single memory component may be divided into multiple, mutually equivalent memory components, and vice versa. In addition, while memory may be depicted as being separate from one or more other components (such as in the accompanying drawings), it will be appreciated that memory may be integrated within another component, such as on a common integrated chip.

[0021] Volatile memory can be a storage medium that requires power to maintain the state of the data stored by the medium. Non-limiting examples of volatile memory can include various types of RAM, such as dynamic random access memory (DRAM) or static random access memory (SRAM). One specific type of DRAM that can be used in a memory module is synchronous dynamic random access memory (SDRAM). In some aspects, the DRAM of the memory component can comply with standards promulgated by the Joint Electron Device Engineering Council (JEDEC), such as JESD79F for double data rate (DDR) SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for low power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such a standard (and similar standards) may be referred to as a DDR-based standard, and a communication interface of a storage device that implements such a standard may be referred to as a DDR-based interface.

[0022] Various aspects can be applied to any memory device including non-volatile memory. In one aspect, the memory device is a block-addressable memory device, such as those based on negative-AND (NAND) logic or negative-OR (NOR) logic technology. The memory can also include future generation non-volatile devices, such as 3D XPoint memory or other byte-addressable write-in-place non-volatile memory devices. 3D XPoint memory devices can include a transistor-free, stackable crosspoint architecture in which memory cells are located at the intersection of word lines and bit lines and can be individually addressed and in which bit storage is based on changes in bulk resistance.

[0023] In some aspects, the memory device may be or include a memory device using chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level phase change memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), antiferroelectric memory, magnetoresistive random access memory (MRAM) memory incorporating memristor technology, resistive memory including metal oxide substrate, oxygen vacancy substrate and conductive bridge random access memory (CB-RAM), or spin transfer torque (STT)-MRAM, a device based on spintronic magnetic junction memory, a device based on magnetic tunnel junction (MTJ), a device based on domain wall (DW) and spin-orbit transfer (SOT), a memory device based on semiconductor thyristors, or a combination of any of the above memory devices, or other memory. The term memory or memory device may refer to the die itself and / or to the packaged memory product.

[0024] Figure 1 A first configuration of the exemplary computing system 100 architecture is shown. Figure 1 As shown in , system 100 may include one or more processors 102-1 - 102-N, an interconnect 104, a memory controller 106, and / or a memory 108. Figure 1 One or more processors 102-1 - 102-N, an interconnect 104, a memory controller 106, and a memory 108 are illustrated within the computing system 100, although some aspects may employ additional and / or different processors, interconnects, memory controllers, memories, and / or other elements.

[0025] Continue to refer Figure 1 The one or more processors 102-1 - 102-N may be generally referred to herein as "processors 102," and more generally as "processor 102." Each of the one or more processors 102-1 - 102-N may include various components and / or aspects. While some of these components and / or aspects are described with reference to processor 102-1, each of the remaining processors 102-2 - 102-N may include the same or similar components and / or aspects discussed with reference to processor 102-1.

[0026] like Figure 1 As shown in , in some aspects, processor 102-1 may include one or more processor cores 110-1 - 110-M, a cache 112, a router 114, and / or an interconnect 116. Figure 1One or more processor cores 110-1 - 110-M, a cache 112, a router 114, and an interconnect 116 are illustrated within processor 102-1, though some aspects may employ additional and / or different processor cores, caches, routers, interconnects, and / or other elements.

[0027] In some aspects, the one or more processors 102-1 - 102-N can be configured to communicate via an interconnect 104 (e.g., a bus). According to at least one aspect, various components of the processor 102-1 can communicate with the cache 112 directly, through a bus (e.g., interconnect 116), and / or with a memory controller (e.g., memory controller 106).

[0028] Continue to refer Figure 1 The one or more processor cores 110-1-110-M may be generally referred to herein as "cores 110," and more generally as "cores 110." Each of the one or more processor cores 110-1-110-M may include various components and / or aspects. While some of these components and / or aspects are described with reference to processor core 110-1, each of the remaining processor cores 110-2-110-M may include the same or similar components and / or aspects discussed with reference to processor core 110-1.

[0029] Continue to refer Figure 1 In some aspects, cache 112 can be a shared cache or a private cache. According to at least one aspect, cache 112 can be configured to store data (e.g., including instructions) utilized by one or more components of processor 102-1 (such as core 110-1). In some aspects, cache 112 can be configured to locally cache data stored in memory 108 for faster access by one or more components of processors 102-1 – 102-N. In at least one aspect, cache 112 can have various levels. For example, cache 112 can include one or more level 1 (L1) caches 118-1 – 118-M, one or more mid-level caches, and / or one or more last-level caches (LLCs).

[0030] Continue to refer Figure 1 , router 114 can be used, for example, to facilitate communication between processor 102-1 and / or various components of system 100. In some aspects, processor 102-1 can include more than one router. According to at least one aspect, multiple routers 114 can thus communicate to enable data routing between various components within and / or external to processor 102-1.

[0031] In some aspects, cache 112 or any portion thereof may be included within one or more of the processing cores 110-1 - 110-M. In accordance with at least one aspect, processing core 110-1 may include cache 112-1. Figure 1 Cache 112 - 1 is illustrated within processing core 110 - 1 , although some aspects may employ additional and / or different caches, and / or other elements.

[0032] In some aspects, the one or more L1 caches 118-1 - 118-M may be generally referred to herein as "L1 cache 118." Each of the one or more L1 caches 118-1 - 118-M may include various components and / or aspects. While some of these components and / or aspects are described with reference to the L1 cache 118-1, each of the remaining L1 caches 118-2 - 118-M may include the same or similar components and / or aspects discussed with reference to the L1 cache 118-1.

[0033] In some aspects, core 110 can be implemented on a single integrated circuit (IC) chip. In accordance with at least one aspect, the IC chip can include one or more caches, one or more buses or interconnects, one or more memory controllers, and / or other components. In some aspects, the one or more caches can include shared and / or private caches (e.g., cache 112). In at least one aspect, the one or more buses or interconnects can include interconnect 116. In some aspects, the one or more memory controllers can include memory controllers related to Figure 1-10 Any memory controller described (eg, memory controller 106 ).

[0034] like Figure 1 , the memory controller 106 can be configured to implement logic 120, for example. In some aspects, the logic 120 can comprise a portion of a software stack of the computing system 100. According to at least one aspect, the logic 120 can be parsed into different subsets, such as 120-1 – 120-K. In some aspects, one or more of the subsets 120-1 – 120-K of the logic 120 can be stored in locations within the computing system 100, individually, collectively, and / or in some combination thereof. In at least one aspect, the logic 120 can be included in one or more processors 102-1 – 102-N, in a chipset, in memory controller 106, in stored code on a persistent storage device, and / or directly or via one or more interconnects or buses (such as reference 102). Figure 1-10 those described above) and are coupled to one or more processors 102-1 – 102-N. Although Figure 1 Logic 120 is illustrated within the memory controller 106 of FIG. 1 , though some aspects may employ additional and / or different logic and / or other elements.

[0035] Continue to refer Figure 1 , the logic 120 of the memory controller 106 may include a set of processor-executable instructions that, when executed by one or more processors 102-1 - 102-N, cause the one or more processors 102-1 - 102-N to perform one or more operations. In some aspects, the one or more operations may include issuing one or more read requests to the memory 108. In accordance with at least one aspect, the one or more operations may include issuing one or more write requests to the memory 108.

[0036] In some aspects, memory 108 may include a pool of memories of the same or different memory technologies. According to at least one aspect, memory 108 may be coupled to memory controller 106 via one or more interfaces. Figure 1 As shown in FIG, in some aspects, the memory 108 can be coupled to other components of the system 100 via a memory controller 106. In at least one aspect, the memory 108 can be coupled to the one or more processors 102-1 - 102-N via the interconnect 104. Although the memory controller 106 is shown as coupled between the interconnect 104 and the memory 108, the memory controller 106 can be located elsewhere in the system 100. For example, the memory controller 106 can be provided within one of the processors 102, such as within Figure 2 middle.

[0037] Figure 2 A second configuration of the exemplary computing system 200 architecture is shown. Figure 2 As shown in , system 200 may include a first processor 102-1, a second processor 102-N, a first memory interconnect 222-1, a second memory interconnect 222-2, a first memory 108-1, a second memory 108-2, a processor-processor interconnect 224, a first processor-hub interconnect 226-1, a second processor-hub interconnect 226-2, an input / output (I / O) hub 228, a graphics interconnect 230, a graphics adapter 232, a hub-hub interconnect 234, a bus bridge hub 236, a universal serial communication bus 238, an I / O device 240, a low bandwidth bus 242, a desktop I / O device 244, an NVM device 246, a storage protocol bus 248, a persistent storage device 250, a solid-state drive (SSD) 252, and / or a network interface controller (NIC) 254. Although in Figure 2The computing system 200 is illustrated as including a first processor 102-1, a second processor 102-N, a first memory interconnect 222-1, a second memory interconnect 222-2, a first memory 108-1, a second memory 108-2, a processor-processor interconnect 224, a first processor-hub interconnect 226-1, a second processor-hub interconnect 226-2, an I / O hub 228, a graphics interconnect 230, a graphics adapter 232, a hub-hub interconnect 234, a bus bridge hub 236, a universal serial communication bus 238, an I / O device 240, a low bandwidth bus 242, a desktop I / O device 244, an NVM device 246, a storage protocol bus 248, a persistent storage device 250, an SSD 252, and / or a NIC. 254, but some aspects may employ additional or fewer processors, memory interconnects, memories, processor-processor interconnects, processor-hub interconnects, I / O hubs, graphics interconnects, graphics adapters, hub-hub interconnects, bus bridge hubs, universal serial communications buses, I / O devices, low-bandwidth buses, desktop I / O devices, NVM devices, storage protocol buses, persistent storage devices, SSDs, NIC 130, and / or other elements.

[0038] Continue to refer Figure 2 , the first processor 102-1 and the second processor 102-2 may be generally referred to herein as "one or more processors 102-1 - 102-N," "processors 102," and more generally as "processors 102." Although Figure 2 Two processors 102 are shown in FIG, but this number is selected for illustrative purposes only. As previously indicated, additional or fewer processors may be implemented depending on system resources and requirements. Each of the one or more processors 102-1 – 102-N may include various components and / or aspects. While some of these components and / or aspects are described with reference to the first processor 102-1, each of the remaining processors 102-2 – 102-N may include the same or similar components and / or aspects discussed with reference to the first processor 102-1.

[0039] like Figure 2 As shown in , each processor 102 of the one or more processors 102-1 – 102-N includes a core region 256 and an integration region 258. For example, the core region 256 of the first processor 102-1 may include one or more processing cores 110-1 – 110-M, and the integration region 258 of the first processor 102-1 may include a first memory controller 206-1, a first processor-hub interface 260-1, a first processor-processor interface 262-1, and / or a first cache 112-1. Although in Figure 2The core region 256, the integrated region 258, the one or more processing cores 110-1– 110-M, the first memory controller 206-1, the first processor-hub interface 260-1, the first processor-processor interface 262-1, and the first cache 112-1 are illustrated within the first processor 102-1, although some aspects may employ additional or fewer regions, processing cores, memory controllers, processor-hub interfaces, processor-processor interfaces, caches, and / or other elements. For example, with respect to Figure 1 One or more components and / or aspects described for the one or more processors 102-1 - 102-N may be incorporated individually, collectively, or in any combination thereof into Figure 2 Each processor 102 of the one or more processors 102-1 – 102-N.

[0040] Continue to refer Figure 2 , the first cache 112-1 and the second cache 112-2 may be generally referred to herein as "one or more caches 112-1 - 112-N," "a plurality of caches 112," and more generally as "cache 112." Although Figure 2 Two caches 112 are shown in FIG, but this number is selected for illustrative purposes only. As previously indicated, additional or fewer caches may be implemented depending on system resources and requirements. Each of the one or more caches 112-1 – 112-N may include various components and / or aspects. While some of these components and / or aspects are described with reference to the first cache 112-1, each of the remaining caches 112-2 – 112-N may include the same or similar components and / or aspects discussed with reference to the first cache 112-1.

[0041] In some aspects, the one or more processing cores 110-1 - 110-M may each include hardware and firmware resources to support execution pipelines. Figure 1 One or more components (eg, L1 cache 118) and / or aspects described for the one or more processing cores 110-1 - 110-M may be incorporated individually, collectively, or in any combination thereof into Figure 2In each of the one or more processing cores 110-1-110-M, these resources may include at least a portion of a cache memory hierarchy and / or be able to access the cache memory hierarchy. For example, in some aspects, processing core 110-1 may include an L1 cache 118-1 and be able to access one or more caches 112-1-112-N. In at least one aspect, the cache memory hierarchy may be shared or private and may further include a dedicated level one (L1) instruction cache, a dedicated L1 data cache, a level two (L2) data / instruction cache, or a combination thereof. In some aspects, these resources may further include prefetch logic and buffers, branch prediction logic, decode logic, register files, various parallel execution resources including an arithmetic logic unit (ALU), a floating point unit (FPU), a load / store unit (L / SPU), an address generation unit (A / SPU), a data cache, I / O control logic, lookup tables and / or indexes, and the like. While specific implementations of one or more processing cores 110-1-110-M have been described, the present disclosure is not necessarily limited to these aspects.

[0042] Continue to refer Figure 2 , the first memory controller 206-1 and the second memory controller 206-2 may be generally referred to herein as "one or more memory controllers 206-1 - 206-N," "memory controllers 206," and more generally as "memory controllers 206." Although Figure 2 Two memory controllers 206 are shown, but this number is selected for illustrative purposes only. As previously indicated, additional or fewer memory controllers may be implemented depending on system resources and requirements. Each of the one or more memory controllers 206-1 - 206-N may include various components and / or aspects. While some of these components and / or aspects are described with reference to memory controller 206-1, each of the remaining memory controllers 206-2 - 206-N may include the same or similar components and / or aspects discussed with reference to the first memory controller 206-1.

[0043] In some aspects, each of the one or more memory controllers 206-1 - 206-N may be configured in some aspects to implement the logic 120. In the case described previously, the memory controller 206 from Figure 1 One or more of the aforementioned aspects of the logic 120 may be related to Figure 2 Individually, collectively, or in combination. Although the logic 120 is illustrated in the diagram Figure 2 206 , although some aspects may employ additional or fewer logic and / or other elements.

[0044] Continue to refer Figure 2 , the first memory interconnect 222-1 and the second memory interconnect 222-2 may be generally referred to herein as "one or more memory interconnects 222-1 - 222-N," "multiple memory interconnects 222," and more generally as "memory interconnects 222." Although Figure 2 Two memory interconnects 222 are shown, but this number is selected for illustrative purposes only. As previously indicated, additional or fewer memory interconnects may be implemented depending on system resources and requirements. Each of the one or more memory interconnects 222-1 – 222-N may include various components and / or aspects. While some of these components and / or aspects are described with reference to the first memory interconnect 222-1, each of the remaining memory interconnects 222-2 – 222-N may include the same or similar components and / or aspects discussed with reference to the first memory interconnect 222-1.

[0045] Continue to refer Figure 2 , the first memory 108-1 and the second memory 108-2 may be generally referred to herein as "one or more memories 108-1 - 108-N," "a plurality of memories 108," and more generally as "memories 108." Although Figure 2 Two memories 108 are shown in FIG, but this number is selected for illustrative purposes only. As previously indicated, additional or fewer memories may be implemented depending on system resources and requirements. Each memory 108 of the one or more memories 108-1 – 108-N may include various components and / or aspects. For example, each memory 108 of the one or more memories 108-1 – 108-N may include a group of memories. While some of these components and / or aspects are described with reference to the first memory 108-1, each of the remaining memories 108-2 – 108-N may include the same or similar components and / or aspects discussed with reference to the first memory 108-1.

[0046] In some aspects, each memory controller 206 of the one or more memory controllers 206-1 – 206-N can be configured to support bidirectional data transfer between one or more processors 102-1 – 102-N and the memory 108 via the memory interconnect 222. For example, the first memory controller 206-1 can be configured to support bidirectional data transfer between the one or more processors 102-1 – 102-N and the first memory 108-1 via the first memory interconnect 222-1. According to at least one aspect, each memory controller 206 of the one or more memory controllers 206-1 – 206-N can be configured to support bidirectional data transfer between the one or more processors 102-1 – 102-N and / or the one or more cache memories 112-1 – 112-N. As an example, in some aspects, each processor 102 of the one or more processors 102-1 – 102-N can be configured to control the first memory controller 206-1 to communicate with the memory 108-1 and / or the cache 112-1.

[0047] Continue to refer Figure 2 In some aspects, each of the one or more memory controllers 206-1 - 206-N can be configured to receive an I / O request to access a block of the memory 108 and / or cache 112. In accordance with at least one aspect, each of the one or more memory controllers 206-1 - 206-N can be configured to issue one or more requests (e.g., read requests, write requests) to the memory 108 and / or cache 112 based on the received I / O request. In at least one aspect, one or more of these processes can include collaboration with one or more components (e.g., drivers) identified in the received I / O request.

[0048] Continue to refer Figure 2 , memory 108-1 can be considered, for example, local to first processor 102-1 and representing a portion of memory 108 as a whole. In some aspects, cache 112-1 can be considered local to first processor 102-1 and representing a portion of cache 112 as a whole. In some aspects, system 200 can be a distributed memory multi-processor system in which each processor 102 of one or more processors 102-1 – 102-N can access every portion of memory 108 and / or cache 112, whether local or not. According to at least one aspect, access to non-local portions of memory 108 and / or cache 112 is permitted, although local access may have lower latency.

[0049] In some aspects, memory 108 can be DDR-type DRAM, and one or more memory interconnects 222-1-222-N and one or more memory controllers 206-1-206-N can comply with one or more DDR interface specifications. In at least one aspect, memory 108 can include two levels of memory (2LM), or 3D XPoint memory, or DRAM & 3D XPoint memory, etc. In some aspects, memory 108 can represent a bank of memory interfaces (or slots) that can be populated with corresponding memory circuits for DRAM capacity and / or 3D XPoint memory capacity. According to some aspects, the memory interface bank can comply with DDR interface specifications, such as DDR and / or DDR-Transactional (DDR-T).

[0050] Continue to refer Figure 2 , the first processor-hub interface 260-1 and the second processor-hub interface 260-2 may be generally referred to herein as "one or more processor-hub interfaces 260-1 - 260-N," "a plurality of processor-hub interfaces 260," and more generally as "processor-hub interfaces 260." Although in Figure 2 Two processor-hub interfaces 260 are shown, but this number is selected for illustrative purposes only. As previously indicated, additional or fewer processor-hub interfaces may be implemented depending on system resources and requirements. Each of the one or more processor-hub interfaces 260-1 – 260-N may include various components and / or aspects. Although some of these components and / or aspects are described with reference to the first processor-hub interface 260-1, each of the remaining processor-hub interfaces 260-2 – 260-N may include the same or similar components and / or aspects discussed with reference to the first processor-hub interface 260-1.

[0051] Continue to refer Figure 2 , the first processor-processor interface 262-1 and the second processor-processor interface 262-2 may be generally referred to herein as "one or more processor-processor interfaces 262-1 - 262-N," "multiple processor-processor interfaces 262," and more generally as "processor-processor interfaces 262." Although Figure 2Two processor-processor interfaces 262 are shown in FIG, but this number is selected for illustrative purposes only. As previously indicated, additional or fewer processor-processor interfaces may be implemented depending on system resources and requirements. Each of the one or more processor-processor interfaces 262-1 – 262-N may include various components and / or aspects. While some of these components and / or aspects are described with reference to the first processor-processor interface 262-1, each of the remaining processor-processor interfaces 262-2 – 262-N may include the same or similar components and / or aspects discussed with reference to the first processor-processor interface 262-1.

[0052] Continue to refer Figure 2 , the first processor-hub interconnect 226-1 and the second processor-hub interconnect 226-2 may be generally referred to herein as "one or more processor-hub interconnects 226-1 - 226-N," "a plurality of processor-hub interconnects 226," and more generally as "processor-hub interconnects 226." Although Figure 2 Two processor-hub interconnects 226 are shown, but this number is selected for illustrative purposes only. As previously indicated, additional or fewer processor-hub interconnects may be implemented depending on system resources and requirements. Each of the one or more processor-hub interconnects 226-1 – 226-N may include various components and / or aspects. Although some of these components and / or aspects are described with reference to the first processor-hub interconnect 226-1, each of the remaining processor-hub interconnects 226-2 – 226-N may include the same or similar components and / or aspects discussed with reference to the first processor-hub interconnect 226-1.

[0053] like Figure 2 As shown in , in some aspects, the I / O hub 228 may include a first hub-processor interface 264-1, a second hub-processor interface 264-2, a graphics interface 266, and / or a hub-hub interface 268. Figure 2 A first hub-processor interface 264-1, a second hub-processor interface 264-2, a graphics interface 266, and / or a hub-to-hub interface 268 are illustrated within the I / O hub 228, but some aspects may utilize additional or fewer hub-processor interfaces, graphics interfaces, hub-to-hub interfaces, and / or other components. For example, in some aspects, the I / O hub 228 may include a processor (e.g., a microprocessor) and one or more memories. For improved latency characteristics, the I / O hub 228 may be integrated into one or more processors 102-1 – 102-N in accordance with at least one alternative aspect.

[0054] Continue to refer Figure 2 , the first hub-processor interface 264-1 and the second hub-processor interface 264-2 may be generally referred to herein as "one or more hub-processor interfaces 264-1 - 264-N," "a plurality of hub-processor interfaces 264," and more generally as "hub-processor interfaces 264." Although Figure 2 Two hub-processor interfaces 264 are shown, but this number is selected for illustrative purposes only. As previously indicated, additional or fewer hub-processor interfaces may be implemented depending on system resources and requirements. Each of the one or more hub-processor interfaces 264-1 – 264-N may include various components and / or aspects. Although some of these components and / or aspects are described with reference to the first hub-processor interface 264-1, each of the remaining hub-processor interfaces 264-2 – 264-N may include the same or similar components and / or aspects discussed with reference to the first hub-processor interface 264-1.

[0055] like Figure 2 As shown in , each processor 102 of the one or more processors 102-1 – 102-N may include various interfaces. For example, in some aspects, the first processor 102-1 may include a first processor-processor interface 262-1 configured to support bidirectional data transfer with a processor-processor interface 262-2 of a second processor 102 via a processor-processor interconnect 224. As previously indicated, additional or fewer processor-processor interconnects 224 may be implemented depending on system resources and requirements. According to at least one aspect, the first processor 102-1 may include a first processor-hub interface 260-1 configured to support bidirectional data transfer with a first hub-processor interface 264-1 of an I / O hub 228 via a first processor-hub interconnect 226-1. In some aspects, the processor-processor interconnect 224 and the processor-hub interconnect 226 may be distinct instances of a common set of interconnects. In at least one aspect, the processor-processor interconnect 224 may be different from the processor-hub interconnect 226.

[0056] In some aspects, the I / O hub 228 can be configured to perform various communications. According to at least one aspect, the I / O hub 228 can be configured to communicate with the first processor-hub interface 260-1 via the first hub-processor interface 264-1. For example, the first hub-processor interface 264-1 can be configured to support the transmission of I / O request(s) for cache block(s) of the cache 112-1 to the first processor-hub interface 260-1. In some aspects, the I / O hub 228 can be configured to communicate with the graphics adapter 232 via the graphics interface 266 and the graphics interconnect 230. In at least one aspect, the graphics interconnect 230 can be implemented as a high-speed serial bus. For example, the graphics interconnect 230 can be implemented as a Peripheral Component Interconnect Express (PCIe) bus or another type of bus. According to some aspects, the I / O hub 228 can be configured to communicate with the bus bridge hub 236 via the hub-hub interface 268 and the hub-hub interconnect 234.

[0057] Continue to refer Figure 2 The bus bridge hub 236 can be configured to support a variety of bus protocols for different types of I / O devices or peripherals. In some aspects, the bus bridge hub 236 can be configured to communicate over a universal serial communication bus 238 to support various I / O devices 240. According to at least one aspect, the universal serial communication bus 238 can be implemented as a universal serial bus (USB), PCI, PCIe, NVM Express (NVMe), NVMe over fabric (NVMeoF), etc.

[0058] Continue to refer Figure 2 In some aspects, the bus bridge hub 236 can be configured to communicate over a low-bandwidth bus 242 to support legacy interfaces, referred to herein as desktop I / O devices 244. According to at least one aspect, the low-bandwidth bus can be implemented as a low pin count (LPC) bus, an inter-integrated circuit (I2C) bus, an industry standard architecture (ISA) bus, or the like. In some aspects, the desktop I / O devices 244 can include interfaces for a keyboard, a mouse, a serial port, a parallel port, and / or a removable media drive. In at least one aspect, the low-bandwidth bus 242 includes an interface for an NVM device 246 (e.g., a flash ROM).

[0059] Continue to refer Figure 2In some aspects, the bus bridge hub 236 can be configured to communicate via a storage protocol bus 248 to support a persistent storage device 250 and / or an SSD 252. According to at least one aspect, the storage protocol bus 248 can be implemented as a Serial AT Attachment (SATA) bus or a Small Computer System Interface (SCSI) bus, etc. In some aspects, the persistent storage device 250 can be implemented as a magnetic hard disk drive (HDD).

[0060] like Figure 2 As shown in , in some aspects, persistent storage 250 may include stored code 270. Although Figure 2 The stored code 270 is illustrated within the persistent storage device 250 of the processor, but some aspects may employ additional and / or different types of code, and / or other elements. According to at least one aspect, the stored code 270 may include data representing processor-executable instructions. In some aspects, the processor-executable instructions may include operating system instructions, application program instructions, etc., which, when executed by the processor, cause the processor to perform one or more of the operations described herein.

[0061] Continue to refer Figure 2 In some aspects, the bus bridge hub 236 can be configured to communicate with the NIC 254. According to at least one aspect, the NIC 254 can be configured to implement a packet-switched network communication protocol. In some aspects, the packet-switched network communication protocol can be a Gigabit Ethernet network communication protocol. In at least one aspect, the Gigabit Ethernet network communication protocol is defined by the IEEE 802.3-2008 standard.

[0062] Although particular examples of a communication bus and bus targets have been illustrated and described, some aspects may employ different communication buses and different target devices.

[0063] Figure 3 A first logical representation of a memory controller system 300 is shown with different multi-channel mode configurations. Figure 3 As shown in , system 300 may include a memory controller 306, a first memory aggregate interface 380, a second memory aggregate interface 382, ​​a first memory aggregate 384, and / or a second memory aggregate 386. Figure 3 300, a memory controller 306, a first memory aggregate interface 380, a second memory aggregate interface 382, ​​a first memory aggregate 384, and / or a second memory aggregate 386 are illustrated, but some aspects may employ additional or fewer memory controllers, memory interfaces, memory aggregates, and / or other elements. For example, with respect to Figure 3 One or more components and / or aspects of the system 300 described in connection with the present invention may be incorporated into Figure 1system 100 and / or Figure 2 In the system 200.

[0064] like Figure 3 As shown in , the memory controller 306 may include logic 120, a global scheduler 372, a latency register 374, a first queue scheduler 376, and / or a second queue scheduler 378. Figure 3 The memory controller 306 of FIGURE 1 illustrates logic 120, a global scheduler 372, latency registers 374, a first queue scheduler 376, a second queue scheduler 378, and logic 120, but some aspects may employ additional or fewer global schedulers, latency registers, queue schedulers, and logic and / or other elements. For example, regarding Figure 1 The memory controller 106 and / or Figure 2 One or more components and / or aspects described with respect to the one or more memory controllers 206 may be incorporated into the memory controller 306 , individually, collectively, or in any combination thereof.

[0065] Continue to refer Figure 3 , the logic 120 of the memory controller 306 may include a set of processor executable instructions that are executed by Figure 1 or 2 when one or more processors 102-1 – 102-N execute such that Figure 1 The one or more processors 102-1 - 102-N of the processor 102-1 or 102-2 implement a global scheduler 372, a first queue scheduler 376, and / or a second queue scheduler 378. In some aspects, the global scheduler 372 can be configured to read data from the latency register 374. According to at least one aspect, the global scheduler 372 can be configured to read data from the latency register 374 on a predetermined schedule. In some aspects, the predetermined schedule can be a predetermined time interval.

[0066] In some aspects, the latency register 374 can be configured to store data indicating an amount of time that the global scheduler 372 is configured to process requests from the first queue scheduler 376 targeting the first memory set 384 and / or requests from the second queue scheduler 378 targeting the second memory set 386. According to at least one aspect, the amount of time can be expressed as a number of clock cycles that the global scheduler 372 is configured to process requests from the first queue scheduler 376 targeting the first memory set 384 and / or requests from the second queue scheduler 378 targeting the second memory set 386. In some aspects, the number of clock cycles can be defined as a ratio of clock cycles that the global scheduler 372 is configured to process requests from the first queue scheduler 376 targeting the first memory set 384 before switching to processing requests from the second queue scheduler 378 targeting the second memory set 386.

[0067] In some aspects, the latency registers 374 can be loaded with default values ​​from the manufacturer. For example, the default value can be set to an equal amount of time (e.g., number of clock cycles) between requests in the first queue scheduler 376 targeting the first memory set 384 and / or requests in the second queue scheduler 378 targeting the second memory set 386. According to at least one aspect, in some aspects, the latency registers 374 can be set and / or updated using a basic input / output system (BIOS) platform configuration. In some aspects, updates to the latency registers can be used to reduce the latency of processing requests in the first queue scheduler 376 and increase the latency of processing requests in the second queue scheduler 378, or vice versa. In at least one aspect, this type of weighting can result in excessive bandwidth being allocated to either the first queue scheduler 376 or the second queue scheduler 378. Figure 1 While the general performance characteristics may generally be known, traffic targeting the first memory set 384 and the second memory set 386 may affect the effectiveness of such weighting.

[0068] Continue to refer Figure 3In some aspects, the global scheduler 372 can be configured to control the first queue scheduler 376 to issue one or more requests to the first memory set 384 according to the timing distribution indicated by the latency register 374. According to at least one aspect, the first queue scheduler 376 can be coupled to the first memory set interface 380 via a first memory interconnect (e.g., memory interconnect 222). In some aspects, the first memory interconnect can be included in a first memory bus that complies with a first interface specification (e.g., SDR, DDR, QDR). In at least one aspect, the one or more requests can be provided to the first memory set 384 via the first memory interconnect via a first channel (e.g., Channel A, Channel B, etc.). According to some aspects, the memory controller 306 can be configured to issue the requests via the second channel in single-channel mode or dual-channel mode. The first queue scheduler 376 can be a first rotating priority queue (RPQ) scheduler consistent with at least one aspect.

[0069] In some aspects, first memory cluster interface 380 can be implemented as a first dual in-line memory module (DIMM) socket. According to at least one aspect, the first DIMM socket can comply with a first interface specification. In some aspects, the first DIMM socket can include one or more first connections and / or posts configured to couple with a printed circuit board (PCB) (e.g., a motherboard). In at least one aspect, the first DIMM socket can include a slot configured to receive first memory cluster 384. According to some aspects, the first DIMM socket can be configured to mate with a first DIMM module including first memory cluster 384.

[0070] In some aspects, the first memory set 384 can be any type of memory described herein. According to at least one aspect, the first memory set 384 can include a group of volatile memories. In some aspects, the first memory set 384 can be included within a first DIMM module (e.g., a DDR DRAM) that complies with a first interface specification. In at least one aspect, the first DIMM module can include a plurality of pins configured to mate with a first DIMM socket. The first memory set 384 can be configured to return data to the memory controller 306 in response to receiving the one or more requests from the first queue scheduler 376.

[0071] Continue to refer Figure 3In some aspects, the global scheduler 372 can be configured to control the second queue scheduler 378 to issue one or more requests to the second memory set 386 according to the timing distribution indicated by the latency register 374. According to at least one aspect, the second queue scheduler 378 can be coupled to the second memory set interface 382 via a second memory interconnect (e.g., memory interconnect 222). In some aspects, the second memory interconnect can be included in a second memory bus that is the same as or different from the first memory bus. For example, the second memory bus can comply with a second interface specification (e.g., DDR-Transactions (DDR-T), NVM programming model, etc.) that is different from the first interface specification. In at least one aspect, the one or more requests can be provided to the second memory set 386 via the second memory interconnect via a second channel (e.g., Channel A, Channel B, etc.). According to some aspects, the memory controller 306 can be configured to issue the requests via the second channel in single-channel mode or dual-channel mode. The second queue scheduler 378 can be a second RPQ scheduler consistent with at least one aspect.

[0072] In some aspects, second memory cluster interface 382 can be implemented as a second DIMM socket. According to at least one aspect, the second DIMM socket can include one or more second connections and / or posts configured to couple to a PCB (e.g., a motherboard). In some aspects, the second DIMM socket can include a second slot configured to receive second memory cluster 386. In at least one aspect, the second DIMM socket can be configured to mate with a second DIMM module including second memory cluster 386. According to some aspects, the first DIMM socket and the second DIMM socket can be the same type of DIMM socket (e.g., DDR4).

[0073] In some aspects, the second memory set 386 can be any type of memory described herein. According to at least one aspect, the second memory set 386 can include a group of non-volatile memories. In some aspects, the second memory set 386 can be included in a second DIMM module (e.g., an NVDIMM module) that complies with a second interface specification (e.g., DDR-T, NVM programming model, etc.). In at least one aspect, the second DIMM module can include a plurality of pins configured to mate with a second DIMM socket. The second memory set 386 can be configured to return data to the memory controller 306 in response to receiving the one or more requests from the second queue scheduler 378.

[0074] In some aspects, the first and second channels can be a common channel (e.g., A). According to at least one aspect, the global scheduler 372 can be configured to control the first queue scheduler 376 to issue the one or more requests to the first memory set 384 (e.g., DDR DRAM) via the common channel in accordance with the timing allocation indicated by the latency register 374 and a first interface specification (e.g., DDR). In some aspects, the global scheduler 372 can be configured to control the second queue scheduler 378 to issue the one or more requests to the second memory set 386 (e.g., 3D XPoint memory) via the common channel in accordance with the timing allocation indicated by the latency register 374 and a second interface specification (e.g., DDR-T). The first memory set 384 can be configured to return data to the memory controller 306 in response to receiving the one or more requests from the first queue scheduler 376. The second memory set 386 can be configured to return data to the memory controller 306 in response to receiving the one or more requests from the second queue scheduler 378.

[0075] Figure 4 A bar graph 400 is shown comparing the read latency of the first queue scheduler 376 in two exemplary dual-channel mode configurations of the system 300. In the first dual-channel mode configuration, the first memory set 384 and the second memory set 386 each include DDR DRAM DIMM modules. In contrast, the first memory set 384 includes DDR DRAM DIMM modules, while the second memory set 386 includes DDR-T 3D XPoint NVM DIMM modules in the second dual-channel mode configuration. For both configurations, the latency registers are set to provide the global scheduler 372 with an equal amount of time to process requests in the first queue scheduler 376 and the second queue scheduler 378.

[0076] like Figure 4 As shown in FIG, in both configurations, read latency is recorded in nanoseconds (ns) for the first queue scheduler 376. Higher read latency is recorded in the first queue scheduler 376 for the second channel dual mode configuration than for the first dual channel mode configuration. It is believed that the presence of DDR-T traffic in the second queue scheduler 378 causes the increase in latency within the first queue scheduler 376 for the second dual channel mode configuration.

[0077] Given this information, in some aspects, dynamic switching techniques can be incorporated into Figure 5-10 The system 300 is described to provide a trade-off between latency and bandwidth. Figure 5-10The method described, the increased granularity in switching between services in the first queue scheduler 376 and the second queue scheduler 378 can provide improved resource utilization. Figure 5-10 The described services of the first queue scheduler 376 and the second queue scheduler 378 may provide information to the memory controller 306 to adjust its behavior for increased performance.

[0078] Figure 5 A first logical representation of a memory controller system 500 with a dynamic multi-channel mode configuration is shown. Figure 5 As shown in FIG, system 500 may include one or more processing cores 110-1 - 110-M, a memory controller 306, a first memory aggregate interface 380, a second memory aggregate interface 382, ​​a first memory aggregate 384, a second memory aggregate 386, and / or one or more processor interfaces 588. In the case previously described, one or more of the aforementioned aspects of such elements may be related to Figure 5 individually, jointly or in any combination thereof. Figure 5 The one or more processing cores 110-1 - 110-M, the memory controller 306, the first memory aggregate interface 380, the second memory aggregate interface 382, ​​the first memory aggregate 384, the second memory aggregate 386, and the one or more processor interfaces 588 are illustrated in the system 500, but some aspects may employ additional or fewer processing cores, memory controllers, memory interfaces, memory aggregates, and / or other elements. Figure 5 One or more components and / or aspects of the system 500 described in connection with the present invention may be incorporated into Figure 1 system 100 and / or Figure 2 In the system 200.

[0079] like Figure 5 As shown in FIG, the memory controller 306 may include logic 120, a global scheduler 372, a latency register 374, a first queue scheduler 376, and / or a second queue scheduler 378. In the case previously described, one or more of the aforementioned aspects of such elements may be described with respect to FIG. Figure 5 individually, jointly or in any combination thereof. Figure 5 Logic 120, a global scheduler 372, latency registers 374, a first queue scheduler 376, and a second queue scheduler 378 are illustrated in the memory controller 306, but some aspects may employ additional or fewer global schedulers, latency registers, queue schedulers and logic, and / or other elements.

[0080] As previously noted, the logic 120 of the memory controller 106 may include a set of processor-executable instructions that, when executed by one or more processors 102-1 - 102-N, cause the one or more processors 102-1 - 102-N to implement the global scheduler 372, the first queue scheduler 376, and / or the second queue scheduler 378.

[0081] In some aspects, the first queue scheduler 376 can be configured to issue one or more requests in the first queue scheduler 376 to the first memory set 384 via the first memory set interface 380 according to a first timing scheme. In accordance with at least one aspect, the one or more requests in the first queue scheduler 376 can include read requests targeting the first memory set 384 and / or write requests targeting the first memory set 384. In some aspects, the second queue scheduler 378 can be configured to issue one or more requests in the second queue scheduler 378 to the second memory set 384 via the second memory set interface 382 according to a second timing scheme. In at least one aspect, the one or more requests in the second queue scheduler 378 can include read requests targeting the second memory set 386 and / or write requests targeting the second memory set 386.

[0082] In some aspects, the global scheduler 372 can be configured to generate a first timing scheme. According to at least one aspect, the global scheduler 372 can be configured to generate the first timing scheme based on data read from the latency register 374, the one or more requests in the first queue scheduler 376, the one or more requests to be included in the first queue scheduler 376, the one or more requests in the second queue scheduler 378, and / or the one or more requests to be included in the second queue scheduler 378. In some aspects, the one or more requests to be included in the first queue scheduler 376 can include a read request targeting the first memory set 384 and / or a write request targeting the first memory set 384.

[0083] In some aspects, the global scheduler 372 can be configured to modify the first timing scheme based on the data read from the latency register 374, the one or more requests in the first queue scheduler 376, the one or more requests to be included in the first queue scheduler 376, the one or more requests in the second queue scheduler 378, and / or the one or more requests to be included in the second queue scheduler 378. According to at least one aspect, the global scheduler 372 can be configured to provide the first timing scheme to the first queue scheduler 376 and / or the second queue scheduler 378. In some aspects, the global scheduler 372 can be configured to provide the modified first timing scheme to the first queue scheduler 376 and / or the second queue scheduler 378.

[0084] In some aspects, the global scheduler 372 can be configured to generate a second timing scheme. According to at least one aspect, the global scheduler 372 can be configured to generate the second timing scheme based on the data read from the latency register 374, the one or more requests in the first queue scheduler 376, the one or more requests to be included in the first queue scheduler 376, the one or more requests in the second queue scheduler 378, and / or the one or more requests to be included in the second queue scheduler 378. In some aspects, the one or more requests to be included in the second queue scheduler 376 can include a read request targeting the second memory set 386 and / or a write request targeting the second memory set 386.

[0085] In some aspects, the global scheduler 372 can be configured to modify the second timing scheme based on the data read from the latency register 374, the one or more requests in the first queue scheduler 376, the one or more requests to be included in the first queue scheduler 376, the one or more requests in the second queue scheduler 378, and / or the one or more requests to be included in the second queue scheduler 378. According to at least one aspect, the global scheduler 372 can be configured to provide the second timing scheme to the first queue scheduler 376 and / or the second queue scheduler 378. In some aspects, the global scheduler 372 can be configured to provide the modified second timing scheme to the first queue scheduler 376 and / or the second queue scheduler 378.

[0086] In some aspects, the global scheduler 372 can be configured to generate a global timing scheme comprising a first timing scheme and a second timing scheme. According to at least one aspect, the global scheduler 372 can be configured to generate the global timing scheme based on data read from the latency register 374, the first timing scheme being based on the one or more requests in the first queue scheduler 376 and / or the one or more requests in the second queue scheduler 378. In some aspects, the global scheduler 372 can be configured to modify the global timing scheme based on the data read from the latency register 374, the first timing scheme being based on the one or more requests in the first queue scheduler 376 and / or the one or more requests in the second queue scheduler 378. In at least one aspect, the global scheduler 372 can be configured to provide the global timing scheme and / or the modified global timing scheme to the first queue scheduler 376 and / or the second queue scheduler 378.

[0087] In some aspects, the memory controller 306 can be configured to issue one or more requests in the first queue scheduler 376 to the first memory set 384 via the first memory set interface 380 in accordance with the modified first timing scheme. According to at least one aspect, the memory controller 306 can be configured to issue one or more requests in the second queue scheduler 378 to the second memory set 386 in accordance with the modified second timing scheme via the second memory set interface 382. In some aspects, the memory controller 306 can be configured to issue at least one of the one or more requests in the first queue scheduler 376 to the first memory set 384 via the first memory set interface 380 or the one or more requests in the second queue scheduler 378 to the second memory set 386 via the second memory set interface 382 in accordance with the modified global timing scheme.

[0088] Continue to refer Figure 5Components of any of systems 100, 200, 300, and / or 500 (e.g., memory controller 306) may, for example, include a clock. In some aspects, a first timing scheme may define a first number of clock cycles during which the one or more requests in first queue scheduler 376 are to be issued to first memory set 384 via first memory set interface 380 during a first duration. According to at least one aspect, a second timing scheme may define a second number of clock cycles during which the one or more requests in second queue scheduler 378 are to be issued to second memory set 386 via second memory set interface 382 during a second duration. The first timing scheme may further define a third number of clock cycles during which the one or more requests in first queue scheduler 376 are to be issued to first memory set 384 via first memory set interface 380 during a third duration. In at least one aspect, the second timing scheme may define a fourth number of clock cycles during which the one or more requests in second queue scheduler 378 are to be issued to second memory set 386 via second memory set interface 382 during a fourth duration.

[0089] In some aspects, the global scheduler 372 can be configured to modify the first timing scheme by adjusting a first number of clock cycles in which the one or more requests in the first queue scheduler 376 are to be issued to the first memory set 384 via the first memory set interface 380. According to at least one aspect, the global scheduler 372 can be configured to modify the second timing scheme by adjusting a second number of clock cycles in which the one or more requests in the second queue scheduler 378 are to be issued to the second memory set 386 via the second memory set interface 382. In some aspects, the global scheduler 372 can be configured to modify the global timing scheme by adjusting at least one of the first number of clock cycles in which the one or more requests in the first queue scheduler 376 are to be issued to the first memory set 384 via the first memory set interface 380 or the second number of clock cycles in which the one or more requests in the second queue scheduler 378 are to be issued to the second memory set 386 via the second memory set interface 382.

[0090] In some aspects, the number of periods defining the first through fourth durations, respectively, can be equal. According to at least one aspect, the number of periods defining the first through fourth durations, respectively, can be different. In some aspects, the number of periods defining the first through fourth durations, respectively, can be the same for one or more of the first through fourth durations and different for one or more of the first through fourth durations.

[0091] In some aspects, the first to fourth durations can be logically and / or temporally ordered. In some aspects, the first to fourth durations can be sequential in any order. For example, this can include a sequence of any order, including one or more of the first to fourth durations that repeat (e.g., periodically). According to at least one aspect, the first to fourth durations can be consecutive in any order. In some aspects, the first to fourth durations can be sequential, with guard intervals inserted between two or more of these durations. In at least one aspect, in some aspects, the first to fourth durations can be sequential, with overlap between two or more of these durations. Although specific implementations of the first to fourth durations have been described, the present disclosure is not necessarily limited to these aspects and can include more or fewer durations.

[0092] In some aspects, the first memory set 384 and the second memory set 386 can be configured to return data in response to one or more requests received therein. According to at least one aspect, in some aspects, the first memory set 384 can be configured to return data to the memory controller 306 in response to receiving the one or more requests from the first queue scheduler 376. In some aspects, the second memory set 386 can be configured to return data to the memory controller 306 in response to receiving the one or more requests from the first queue scheduler 376.

[0093] Continue to refer Figure 5 , the global scheduler 372 can, for example, be configured to determine whether one or more requests in the first queue scheduler 376 satisfy a capacity criterion for the first queue scheduler 376. In some aspects, the capacity criterion for the first queue scheduler 376 can be satisfied when a sum of the one or more requests in the first queue scheduler is greater than or equal to a capacity threshold for the first queue scheduler 376. According to at least one aspect, the capacity threshold for the first queue scheduler 376 can be a percentage of the total capacity of the first queue scheduler 376.

[0094] In some aspects, the global scheduler 372 can be configured to modify the first timing scheme based on capacity criteria being met for the first queue scheduler 376. According to at least one aspect, the global scheduler 372 can be configured to modify the first timing scheme based on capacity criteria being met for the first queue scheduler 376 by adjusting a number of clock cycles in which the one or more requests in the first queue scheduler 376 are to be issued to the first memory aggregate 384 via the first memory aggregate interface 380.

[0095] Continue to refer Figure 5, the global scheduler 372 can, for example, be configured to determine whether one or more requests in the second queue scheduler 378 satisfy a capacity criterion for the second queue scheduler 378. In some aspects, the capacity criterion for the second queue scheduler 378 can be satisfied when a sum of the one or more requests in the second queue scheduler is greater than or equal to a capacity threshold for the second queue scheduler 378. According to at least one aspect, the capacity threshold for the second queue scheduler 378 can be a percentage of the total capacity of the second queue scheduler 378.

[0096] In some aspects, the global scheduler 372 can be configured to modify the second timing scheme based on the capacity criteria being met for the second queue scheduler 378. According to at least one aspect, the global scheduler 372 can be configured to modify the second timing scheme based on the capacity criteria being met for the second queue scheduler 378 by adjusting a second number of clock cycles in which the one or more requests in the second queue scheduler 378 are to be issued to the second memory set 386 via the second memory set interface 382.

[0097] Continue to refer Figure 5 , each of the one or more processing cores 110-1 - 110-M may include a core interface 588. Although the core interface 588 may be included in Figure 5 In each of the one or more processing cores 110-1 - 110-M of the system 500, although some aspects may employ additional or fewer interfaces and / or other elements. As previously indicated, with respect to Figure 1 One or more components and / or aspects described for the one or more processing cores 110-1 - 110-M of and / or 2 may be incorporated individually, collectively, or in any combination thereof into Figure 5 of the one or more processing cores 110-1-110-M.

[0098] Continue to refer Figure 5 , the one or more core interfaces 588-1 – 588-M may be generally referred to herein as “core interfaces 588” and, more generally, as “core interfaces 588”. Each of the one or more core interfaces 588-1 – 588-M may include various components and / or aspects. While some of these components and / or aspects are described with reference to core interface 588-1, each of the remaining core interfaces 588-2 – 588-M may include the same or similar components and / or aspects discussed with reference to core interface 588-M.

[0099] In some aspects, each core interface 588 of the one or more core interfaces 588-1 - 588-M can be implemented in various ways. According to at least one aspect, each core interface 588 of the one or more core interfaces 588-1 - 588-M can be an interface to an Industry Standard Architecture (ISA) interconnect. In some aspects, each core interface 588 of the one or more core interfaces 588-1 - 588-M can be an interface to model-specific registers (MSRs). While specific implementations of the one or more core interfaces 588-1 - 588-M have been described, the present disclosure is not necessarily limited to these aspects.

[0100] In some aspects, each processor 110 of the one or more processing cores 110-1 - 110-M can be capable of providing information to the memory controller 306 via a core interface 588. According to at least one aspect, each core interface 588 of the one or more core interfaces 588-1 - 588-M can, for example, provide the information to a software stack of the system 500. As previously indicated, the software stack of the system 500 can include logic 120 implemented by the memory controller 306. In some aspects, the memory controller 306 can be exposed to the information provided by the one or more processing cores 110-1 - 110-M.

[0101] In some aspects, the information provided by the one or more processing cores 110-1 - 110-M via the one or more core interfaces 588-1 - 588-M may include various types of information. According to some aspects, the information provided by the one or more processing cores 110-1 - 110-M via the one or more core interfaces 588-1 - 588-M may relate to the one or more requests to be included in the first queue scheduler 376. The information provided by the one or more processing cores 110-1 - 110-M via the one or more core interfaces 588-1 - 588-M may relate to the one or more requests to be included in the second queue scheduler 378.

[0102] Continue to refer Figure 5 In some aspects, the logic 120, stored code 270, or another portion of the software stack of the system 500 may include a set of processor-executable instructions that, when executed by one or more processors 102-1 - 102-N, cause the one or more processors 102-1 - 102-N to perform one or more operations. According to at least one aspect, the one or more operations may be read hint operations. In some aspects, the one or more operations may include RPQ hint operations.

[0103] In some aspects, the read hint operation may include reading a hint associated with one or more requests (e.g., a read request or a write request) targeting at least one of the first memory set 384 or the second memory set 386. In accordance with at least one aspect, the read hint operation may expose information about the one or more requests to be included in at least one of the first queue scheduler 376 or the second queue scheduler 378 to the memory controller 306 via the one or more core interfaces 588-1 - 588-M. In some aspects, the exposed information may include capacity information and / or criticality information about the one or more requests to be included in at least one of the first queue scheduler 376 or the second queue scheduler 378.

[0104] In some aspects, the read hint operation can be logically implemented as Read(@X, NextReadHint). In at least one aspect, the read hint operation can expose information about one or more requests to be included in at least one of the first queue scheduler 376 or the second queue scheduler 378. According to at least one aspect, the exposed information can relate to the auxiliary capacity of at least one of the first queue scheduler 376 or the second queue scheduler 378. In some aspects, the exposed information can relate to the criticality of one or more requests within a particular stream of requests (e.g., read requests) to be included in at least one of the first queue scheduler 376 or the second queue scheduler 378. In at least one aspect, the exposed information can indicate the number of clock cycles that a particular position of the stream can tolerate based on the particular request of the stream with respect to where the next request of the stream belongs.

[0105] In some aspects, the global scheduler 372 can be configured to determine whether one or more requests to be included in the first queue scheduler 376 meet auxiliary capacity criteria for the first queue scheduler 376. According to at least one aspect, the auxiliary capacity criteria for the first queue scheduler 376 can be met when the sum of the one or more requests to be included in the first queue scheduler 376 is greater than or equal to an auxiliary capacity threshold for the first queue scheduler 376. In some aspects, the auxiliary capacity threshold for the first queue scheduler 376 can be equal to the capacity threshold for the first queue scheduler 376 minus the sum of the one or more requests to be included in the first queue scheduler 376. In at least one aspect, the auxiliary capacity threshold for the first queue scheduler 376 can be equal to the capacity threshold for the first queue scheduler 376 minus the sum of the one or more requests to be included in the first queue scheduler 376 plus the capacity threshold for the second queue scheduler 378 minus the sum of the one or more requests to be included in the second queue scheduler 378.

[0106] In some aspects, the global scheduler 372 can be configured to modify the first timing scheme based on the auxiliary capacity being met for the first queue scheduler 376. According to at least one aspect, the global scheduler 372 can be configured to modify the first timing scheme based on the auxiliary capacity criteria being met for the first queue scheduler 376 by adjusting a first number of clock cycles in which the one or more requests in the first queue scheduler 376 are to be issued to the first memory set 384 via the first memory set interface 380.

[0107] In some aspects, the global scheduler 372 can be configured to determine whether one or more requests to be included in the second queue scheduler 378 meet auxiliary capacity criteria for the second queue scheduler 378. According to at least one aspect, the auxiliary capacity criteria for the second queue scheduler 378 can be met when the sum of the one or more requests to be included in the second queue scheduler 378 is greater than or equal to an auxiliary capacity threshold for the second queue scheduler 378. In some aspects, the auxiliary capacity threshold for the second queue scheduler 378 can be equal to the capacity threshold for the second queue scheduler 378 minus the sum of the one or more requests to be included in the second queue scheduler 378. In at least one aspect, the auxiliary capacity threshold for the second queue scheduler 378 can be equal to the capacity threshold for the first queue scheduler 376 minus the sum of the one or more requests to be included in the first queue scheduler 376 plus the capacity threshold for the second queue scheduler 378 minus the sum of the one or more requests to be included in the second queue scheduler 378.

[0108] In some aspects, the global scheduler 372 can be configured to modify the second timing scheme based on the auxiliary capacity being met for the second queue scheduler 378. According to at least one aspect, the global scheduler 372 can be configured to modify the second timing scheme by adjusting a second number of clock cycles in which the one or more requests in the second queue scheduler 378 are to be issued to the first memory set 384 via the first memory set interface 380 based on the auxiliary capacity criteria being met for the second queue scheduler 378. In some aspects, the auxiliary capacity threshold for the first queue scheduler 376 can be less than or equal to the auxiliary capacity threshold for the second queue scheduler 378. In at least one aspect, the auxiliary capacity threshold for the first queue scheduler 376 can be greater than or equal to the auxiliary capacity threshold for the second queue scheduler 378 in some aspects.

[0109] In some aspects, the global scheduler 372 can be configured to determine whether a first request among the one or more requests to be included in the first queue scheduler 376 satisfies a first priority criterion. According to at least one aspect, the first priority criterion can be satisfied when the first request is to be processed by the memory controller 306 within a threshold number of instructions to be processed by the memory controller 306. In some aspects, the first priority criterion can be satisfied when the first request involves a target address to be accessed by the memory controller 306 within a threshold number of instructions to be processed by the memory controller 306. In at least one aspect, the first priority criterion can be satisfied when the first request involves a target address associated with a latency-sensitive application. According to some aspects, the first priority criterion can be satisfied when the first request involves a target address associated with a latency-resilient application.

[0110] In some aspects, the global scheduler 372 can be configured to modify at least one of the first or second timing schemes based on a first priority criterion being met. According to at least one aspect, the global scheduler 372 can be configured to modify the first timing scheme based on the first priority being met by adjusting a first number of clock cycles in which one or more requests in the first scheduler 376 are to be issued to the first memory aggregate 384 via the first memory aggregate interface 380. In some aspects, the global scheduler 372 can be configured to modify the second timing scheme based on the first priority being met by adjusting a second number of clock cycles in which the one or more requests in the second queue scheduler 378 are to be issued to the second memory aggregate 386 via the second memory aggregate interface 382.

[0111] In some aspects, the global scheduler 372 can be configured to determine whether a second request in the one or more requests to be included in the second queue scheduler 378 satisfies a second priority criterion. According to at least one aspect, the second priority criterion can be satisfied when the second request is to be processed by the memory controller 306 within a threshold number of instructions to be processed by the memory controller 306. In some aspects, the second priority criterion can be satisfied when the second request involves a target address to be accessed by the memory controller 306 within a threshold number of instructions to be processed by the memory controller 306. In at least one aspect, the second priority criterion can be satisfied when the second request involves a target address associated with a latency-sensitive application. According to some aspects, the second priority criterion can be satisfied when the second request involves a target address associated with a latency-resilient application.

[0112] In some aspects, the global scheduler 372 can be configured to modify at least one of the first timing scheme or the second timing scheme based on a second priority criterion being met. According to at least one aspect, the global scheduler 372 can be configured to modify the first timing scheme by adjusting a first number of clock cycles in which the one or more requests in the first queue scheduler 376 are to be issued to the first memory set 384 via the first memory set interface 380 based on the second priority criterion being met. In some aspects, the global scheduler 372 can be configured to modify the second timing scheme by adjusting a second number of clock cycles in which the one or more requests in the second queue scheduler 378 are to be issued to the second memory set 386 via the second memory set interface 382 based on the second priority criterion being met. In at least one aspect, the first priority criterion can be different from the second priority criterion. According to some aspects, the first priority criterion can be equal to the second priority criterion.

[0113] In some aspects, the RPQ hint operation can be logically implemented as RPQHints(TypeMask, LatencyMask). In at least one aspect, the read hint operation can expose information about at least one of the first queue scheduler 376 or the second queue scheduler 378. According to at least one aspect, the exposed information can allow the software stack to specify a global timing scheme. As previously indicated, the global timing scheme can define the order and duration of processing one or more requests from the first queue scheduler 376 and / or the second queue scheduler 378.

[0114] In some aspects, the exposed information may include an ordered list of requests for processing the one or more requests in the first queue scheduler 376 and / or the second queue scheduler 378. For example, the exposed ordered list may indicate the following order: (i) first queue scheduler 376; (ii) second queue scheduler 378; (iii) first queue scheduler 376; (iv) second queue scheduler 378. According to at least one aspect, the exposed information may include process duration information about the memory controller 306 indicating a length with which the memory controller 306 may process the one or more requests in the first queue scheduler 376 or the second queue scheduler 378. For example, the exposed process duration information may indicate the following durations: (i) 10 cycles; (ii) 40 cycles; (iii) 10 cycles; and (iv) 30 cycles.

[0115] In some aspects, the exposed information may include guard interval information indicating whether a guard interval is to be applied between two or more durations. For example, the exposed guard interval information may indicate: (i) guard; (ii) no guard; or (iii) guard. In at least one aspect, the exposed information may include information indicating whether overlap is permitted between two or more durations. For example, the exposed overlap information may indicate: (i) no overlap; (ii) overlap; or (iii) no overlap.

[0116] In some aspects, the global scheduler 372 can be configured to receive information from an interface to the processing core. According to at least one aspect, the global scheduler 372 can be configured to generate a global timing scheme based on the information received from the interface to the processing core. In some aspects, the interface to the processing core can be an interface to an Industry Standard Architecture (ISA) interconnect. In at least one aspect, the interface to the processing core can be an interface to model-specific registers (MSRs).

[0117] Figure 6 A second logical representation of a memory controller system 600 configured in a dynamic multi-channel mode is shown. Figure 6 As shown in FIG, system 600 may include one or more processing cores 110-1 - 110-M, a memory controller 306, a first memory aggregate interface 380, a second memory aggregate interface 382, ​​a first memory aggregate 384, a second memory aggregate 386, and / or one or more processor interfaces 588. In the case previously described, one or more of the aforementioned aspects of such elements may be related to Figure 6 individually, jointly or in any combination thereof. Figure 6 The one or more processing cores 110-1 - 110-M, the memory controller 306, the first memory aggregate interface 380, the second memory aggregate interface 382, ​​the first memory aggregate 384, the second memory aggregate 386, and the one or more processor interfaces 588 are illustrated in the system 600, but some aspects may employ additional or fewer processing cores, memory controllers, memory interfaces, memory aggregates, and / or other elements. Figure 6 One or more components and / or aspects of the system 600 described in connection with the present invention may be incorporated into Figure 1 system 100 and / or Figure 2 In the system 200.

[0118] like Figure 6As shown in FIG, the memory controller 306 may include logic 120, a global scheduler 372, a latency register 374, a first queue scheduler 376, a second queue scheduler 378, and / or a phase detector 690. In the case previously described, one or more of the aforementioned aspects of such elements may be described with respect to FIG. Figure 6 individually, jointly or in any combination thereof. Figure 6 Logic 120, a global scheduler 372, latency registers 374, a first queue scheduler 376, and a second queue scheduler 378 are illustrated in the memory controller 306 of , but some aspects may employ additional or fewer global schedulers, latency registers, queue schedulers and logic and / or other elements.

[0119] In some aspects, the logic 120 of the memory controller 106 may include a set of processor-executable instructions that, when executed by one or more processors 102-1 - 102-N, cause the one or more processors 102-1 - 102-N to implement the global scheduler 372, the first queue scheduler 376, the second queue scheduler 378, and the phase detector 690. According to at least one aspect, the phase detector 690 may be an ASIC. In some aspects, the phase detector 690 may be a programmable device, such as an FPGA. As previously noted, in some aspects, the memory controller 306 may be exposed to information provided by the one or more processing cores 110-1 - 110-M.

[0120] In some aspects, the phase detector 690 can be configured to analyze information exposed to the memory controller 306. According to at least one aspect, the phase detector 690 can be configured to receive information regarding one or more requests to be included in at least one of the first queue scheduler 376 or the second queue scheduler 378 during a predefined duration via the interface 588 to the processing core 110.

[0121] In some aspects, the phase detector 690 can be configured to determine whether the one or more requests to be included in the first queue scheduler 376 received within a predefined duration satisfy a phase detection criterion for the first queue scheduler 376. According to at least one aspect, the phase detection criterion for the first queue scheduler 376 can be satisfied when the sum of the one or more requests to be included in the first queue scheduler 376 received within the predefined duration is greater than or equal to a phase detection threshold for the first queue scheduler 376. In some aspects, the phase detector 690 can be configured to trigger the global scheduler 372 to modify at least one of the first timing scheme or the second timing scheme based on the phase detection criterion for the first queue scheduler 376 being satisfied. In at least one aspect, the phase detector 690 can be configured to modify at least one of the first timing scheme or the second timing scheme based on the phase detection criterion for the first queue scheduler 376 being satisfied.

[0122] In some aspects, the phase detector 690 can be configured to determine whether the one or more requests to be included in the second queue scheduler 378 received within a predefined duration satisfy a phase detection criterion for the second queue scheduler 378. According to at least one aspect, the phase detection criterion for the second queue scheduler 378 can be satisfied when the sum of the one or more requests to be included in the second queue scheduler 378 received within the predefined duration is greater than or equal to a phase detection threshold for the second queue scheduler 378. In some aspects, the phase detector 690 can be configured to trigger the global scheduler 372 to modify at least one of the first timing scheme or the second timing scheme based on the phase detection criterion for the second queue scheduler 378 being satisfied. In at least one aspect, the phase detector 690 can be configured to modify at least one of the first timing scheme or the second timing scheme based on the phase detection criterion for the second queue scheduler 378 being satisfied.

[0123] Figure 7A first exemplary method 700 for performing data operations of a memory controller according to some aspects is shown. In the method 700 for performing data operations of a memory controller, the method includes modifying at least one of a first timing scheme or a second timing scheme based on information about one or more data requests to be included in at least one of a first queue scheduler or a second queue scheduler, the first timing scheme indicating when to issue one or more requests in the first queue scheduler to the first memory set via a first memory set interface and over a common channel, the second timing scheme indicating when to issue one or more requests in the second queue scheduler to the second memory set via a second memory set interface and over the common channel 705, and issuing at least one of the requests to the first memory set according to the modified first timing scheme or the requests to the second memory set according to the modified second timing scheme 715.

[0124] Figure 8 A second exemplary method 800 for performing data operations according to some aspects is shown. In the method 800 for performing data operations of a memory controller, the method includes issuing one or more requests in a first queue scheduler to a first memory set via a first memory set interface and over a common channel according to a first timing scheme 805, issuing one or more requests in a second queue scheduler to a second memory set via a second memory set interface and over the common channel according to a second timing scheme 815, receiving information about one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler 825, and modifying at least one of the first or second timing schemes based on the information about the one or more requests to be included in at least one of the first or second queue schedulers 835.

[0125] Figure 9 A third exemplary method 900 for performing data operations according to some aspects is shown. In the method 900 for performing data operations of a memory controller, the method includes modifying at least one of a first timing scheme or a second timing scheme based on information about one or more data requests to be included in at least one of a first queue scheduler or a second queue scheduler, the first timing scheme indicating when to issue one or more requests in the first queue scheduler to the first memory set via a first memory set interface and over a common channel, the second timing scheme indicating when to issue one or more requests in the second queue scheduler to the second memory set via a second memory set interface and over the common channel 905, and issuing at least one of a request to the first memory set according to the modified first timing scheme or a request to the second memory set according to the modified second timing scheme 915.

[0126] Figure 10 A fourth exemplary method 1000 for performing data operations according to some aspects is shown. In the method 1000 for performing data operations of a memory controller, the method includes issuing one or more requests in a first queue scheduler to a first memory set via a first memory set interface and over a common channel according to a first timing scheme 1005, issuing one or more requests in a second queue scheduler to a second memory set via a second memory set interface and over the common channel according to a second timing scheme 1015, and modifying at least one of the first or second timing schemes based on at least one of the one or more requests in the first or second queue schedulers 1025.

[0127] Although it has been used Figure 1-10 The elements of the present disclosure describe specific implementations, but the present disclosure is not necessarily limited to these aspects. Additionally or alternatively, at least one or more circuits and / or processors described herein, including the one or more processors 102-1 - 102-N, memory controller 106, memory controller 206, memory controller 306, etc., may be implemented in any of the aforementioned aspects, implementations, and / or examples below.

[0128] The following examples relate to other aspects of the present disclosure:

[0129] Example 1 is a computing system, which may include: a memory controller, the memory controller including a first queue scheduler, the first queue scheduler being configured to issue one or more requests in the first queue scheduler to the first memory set in accordance with a first timing scheme, via a first memory set interface and through a common channel; a second queue scheduler, the second queue scheduler being configured to issue one or more requests in the second queue scheduler to the second memory set in accordance with a second timing scheme, via a second memory set interface and through the common channel; and a global scheduler, the global scheduler being configured to receive information about one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler; and modify at least one of the first timing scheme or the second timing scheme based on the information about the one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler.

[0130] Example 2 is a computing system, which may include: a first memory set; a second memory set; and a memory controller, wherein the memory controller is configured to modify at least one of a first timing scheme or a second timing scheme based on information about one or more data requests to be included in at least one of the first queue scheduler or the second queue scheduler through a global scheduler of the memory controller, the first timing scheme indicating when to issue one or more requests in the first queue scheduler to the first memory set via the first memory set interface and through a common channel, the second timing scheme indicating when to issue one or more requests in the second queue scheduler to the second memory set via the second memory set interface and through the common channel, and issuing at least one of a request to the first memory set in accordance with the modified first timing scheme or a request to the second memory set in accordance with the modified second timing scheme.

[0131] Example 3 is a computing system, which may include: a memory controller, the memory controller including a first queue scheduler, the first queue scheduler being configured to issue one or more requests in the first queue scheduler to the first memory set in accordance with a first timing scheme, via a first memory set interface and through a common channel; a second queue scheduler, the second queue scheduler being configured to issue one or more requests in the second queue scheduler to the second memory set in accordance with a second timing scheme, via a second memory set interface and through the common channel; and a global scheduler, the global scheduler being configured to modify at least one of the first timing scheme or the second timing scheme based on at least one of the one or more requests in the first queue scheduler or the one or more requests in the second queue scheduler.

[0132] Example 4 is a computing system, which may include: a first memory set; a second memory set; and a memory controller including a global scheduler, the global scheduler being configured to modify at least one of a first timing scheme or a second timing scheme based on information about one or more data requests included in at least one of the first queue scheduler or the second queue scheduler, the first timing scheme indicating when to issue one or more requests in the first queue scheduler to the first memory set via the first memory set interface and through a common channel, the second timing scheme indicating when to issue one or more requests in the second queue scheduler to the second memory set via the second memory set interface and through the common channel, and issuing at least one of a request to the first memory set in accordance with the modified first timing scheme or a request to the second memory set in accordance with the modified second timing scheme.

[0133] In Example 5, the subject matter of Example 1 or 2 may optionally include: the global scheduler is further configured to modify at least one of the first timing scheme or the second timing scheme based on at least one of the one or more requests in the first queue scheduler or the one or more requests in the second queue scheduler.

[0134] In Example 6, the subject matter of Example 3 or 4 can optionally include the global scheduler being further configured to receive information about one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler within a predefined time duration.

[0135] In Example 7, the subject matter of Example 6 may optionally include: the global scheduler is further configured to modify at least one of the first timing scheme or the second timing scheme further based on information about the one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler.

[0136] In Example 8, the subject matter of Examples 1, 3, 5, 6, or 7 may optionally include: the memory controller is configured to issue at least one of a request to the first memory set according to the modified first timing scheme or a request to the second memory set according to the modified second timing scheme.

[0137] In Example 9, the subject matter of Examples 1 to 8 can optionally include the first queue scheduler being implemented as a first Rotating Priority Queue (RPQ) scheduler.

[0138] In Example 10, the subject matter of Examples 1 to 9 can optionally include the global scheduler being further configured to provide the first timing scheme to the first queue scheduler.

[0139] In Example 11, the subject matter of Examples 1 to 10 may optionally include that the one or more requests in the first queue scheduler include at least one of a write request targeting the first memory set or a read request targeting the first memory set.

[0140] In Example 12, the subject matter of Examples 1 to 11 may optionally include: the one or more requests to be included in the first queue scheduler include at least one of a write request targeting the first memory set or a read request targeting the first memory set.

[0141] In Example 13, the subject matter of Examples 1 to 12 may optionally include: the memory controller includes a clock, and the first timing scheme defines a first number of clock cycles in which the one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface.

[0142] In Example 14, the subject matter of Example 13 can optionally include: the global scheduler is further configured to modify the first timing scheme by adjusting a first number of clock cycles in which the one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface.

[0143] In Example 15, the subject matter of Examples 1 to 14 can optionally include the first memory set comprising dynamic random access memory (DRAM), and the first memory set interface being implemented as a double data rate (DDR) interface.

[0144] In Example 16, the subject matter of Examples 1 to 15 can optionally include the second queue scheduler being implemented as a second Rotating Priority Queue (RPQ) scheduler.

[0145] In Example 17, the subject matter of Examples 1 to 16 can optionally include the global scheduler being further configured to provide the second timing scheme to the second queue scheduler.

[0146] In Example 18, the subject matter of Examples 1 to 17 may optionally include that the one or more requests in the second queue scheduler include at least one of a write request targeting the second memory set or a read request targeting the second memory set.

[0147] In Example 19, the subject matter of Examples 1 to 18 may optionally include: the one or more requests in the second queue scheduler to be included include at least one of a write request targeting the second memory set or a read request targeting the second memory set.

[0148] In Example 20, the subject matter of Examples 13 to 19 can optionally include the second timing scheme defining a second number of clock cycles in which the one or more requests in the second queue scheduler are to be issued to the second memory set via the second memory set interface.

[0149] In Example 21, the subject matter of Example 20 may optionally include: the global scheduler is further configured to modify the second timing scheme by adjusting a second number of clock cycles in which the one or more requests in the second queue scheduler are to be issued to the second memory set via the second memory set interface.

[0150] In Example 22, the subject matter of Example 20 or 21 can optionally include the first number of clock cycles being different from the second number of clock cycles.

[0151] In Example 23, the subject matter of Example 20 or 21 can optionally include the first number of clock cycles being equal to the second number of clock cycles.

[0152] In Example 24, the subject matter of Examples 1 to 23 can optionally include the second memory set comprising 3D XPoint memory, and the second memory set interface being implemented as a DDR-Transaction (DDR-T) interface.

[0153] In Example 25, the subject matter of Examples 1 to 24 can optionally include the global scheduler being further configured to receive a global timing scheme via an interface to the processing core, and the global timing scheme includes the first timing scheme and the second timing scheme.

[0154] In Example 26, the subject matter of Example 25 may optionally include: the first timing scheme includes a first number of clock cycles in which the one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface during a first duration, the second timing scheme includes a second number of clock cycles in which the one or more requests in the second queue scheduler are to be issued to the second memory set via the second memory set interface during a second duration, and the first duration and the second duration are sequential.

[0155] In Example 27, the subject matter of Example 25 or 26 may optionally include the global scheduler being further configured to receive, via an interface to the processing core, information about the one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler.

[0156] In Example 28, the subject matter of Examples 1 to 27 can optionally include the global scheduler being further configured to determine whether the one or more requests in the first queue scheduler meet capacity criteria for the first queue scheduler.

[0157] In Example 29, the subject matter of Example 28 can optionally include: when a sum of the one or more requests in the first queue scheduler is greater than or equal to a capacity threshold for the first queue scheduler, the capacity criterion for the first queue scheduler is met.

[0158] In Example 30, the subject matter of Example 29 can optionally include the capacity threshold for the first queue scheduler being a percentage of a total capacity of the first queue scheduler.

[0159] In Example 31, the subject matter of Examples 28 to 30 can optionally include the global scheduler being further configured to modify the first timing scheme based on a capacity criterion for the first queue scheduler being met.

[0160] In Example 32, the subject matter of Examples 28 to 31 may optionally include: the global scheduler is further configured to modify the first timing scheme by adjusting a first number of clock cycles in which the one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface based on capacity criteria for the first queue scheduler being met.

[0161] In Example 33, the subject matter of Examples 1 to 32 can optionally include the global scheduler being further configured to determine whether the one or more requests in the second queue scheduler meet capacity criteria for the second queue scheduler.

[0162] In Example 34, the subject matter of Example 33 can optionally include: when a sum of the one or more requests in the second queue scheduler is greater than or equal to a capacity threshold for the second queue scheduler, the capacity criterion for the second queue scheduler is met.

[0163] In Example 35, the subject matter of Example 34 can optionally include the capacity threshold for the second queue scheduler being a percentage of a total capacity of the second queue scheduler.

[0164] In Example 36, the subject matter of Examples 33 to 35 can optionally include the global scheduler being further configured to modify the second timing scheme based on a capacity criterion for the second queue scheduler being met.

[0165] In Example 37, the subject matter of Examples 33 to 36 may optionally include: the global scheduler is further configured to modify the second timing scheme by adjusting a second number of clock cycles in which the one or more requests in the second queue scheduler are to be issued to the second memory set via the second memory set interface based on capacity criteria for the second queue scheduler being met.

[0166] In Example 38, the subject matter of Examples 34 to 37 can optionally include: the capacity threshold for the first queue scheduler being less than or equal to the capacity threshold for the second queue scheduler.

[0167] In Example 39, the subject matter of Examples 34 to 37 can optionally include: the capacity threshold for the first queue scheduler being greater than or equal to the capacity threshold for the second queue scheduler.

[0168] In Example 40, the subject matter of Examples 1, 2, 5, or 6 to 39 may optionally include the global scheduler being further configured to determine whether the one or more requests to be included in the first queue scheduler meet auxiliary capacity criteria for the first queue scheduler.

[0169] In Example 41, the subject matter of Example 40 may optionally include: the auxiliary capacity criterion for the first queue scheduler is met when the sum of the one or more requests to be included in the first queue scheduler is greater than or equal to the auxiliary capacity threshold for the first queue scheduler.

[0170] In Example 42, the subject matter of Example 41 can optionally include the auxiliary capacity threshold for the first queue scheduler being equal to the capacity threshold for the first queue scheduler minus a sum of the one or more requests to be included in the first queue scheduler.

[0171] In Example 43, the subject matter of Examples 40 to 42 can optionally include the global scheduler being further configured to modify the first timing scheme based on an auxiliary capacity criterion for the first queue scheduler being satisfied.

[0172] In Example 44, the subject matter of Examples 40 to 43 may optionally include: the global scheduler is further configured to modify the first timing scheme by adjusting a first number of clock cycles in which the one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface based on an auxiliary capacity standard for the first queue scheduler being satisfied.

[0173] In Example 45, the subject matter of Examples 1, 2, 5, or 6 to 44 can optionally include the global scheduler being further configured to determine whether the one or more requests to be included in the second queue scheduler meet auxiliary capacity criteria for the second queue scheduler.

[0174] In Example 46, the subject matter of Example 45 can optionally include: the auxiliary capacity criterion for the second queue scheduler is met when the sum of the one or more requests to be included in the second queue scheduler is greater than or equal to the auxiliary capacity threshold for the second queue scheduler.

[0175] In Example 47, the subject matter of Example 46 can optionally include the auxiliary capacity threshold for the second queue scheduler being equal to the capacity threshold for the second queue scheduler minus a sum of the one or more requests to be included in the second queue scheduler.

[0176] In Example 48, the subject matter of Examples 45 to 47 can optionally include the global scheduler being further configured to modify the second timing scheme based on an auxiliary capacity criterion for the second queue scheduler being satisfied.

[0177] In Example 49, the subject matter of Examples 45 to 48 may optionally include: the global scheduler is further configured to modify the second timing scheme by adjusting a second number of clock cycles in which the one or more requests in the second queue scheduler are to be issued to the second memory set via the second memory set interface based on the auxiliary capacity criteria for the second queue scheduler being met.

[0178] In Example 50, the subject matter of Examples 46 to 49 can optionally include the auxiliary capacity threshold for the first queue scheduler being less than or equal to the auxiliary capacity threshold for the second queue scheduler.

[0179] In Example 51, the subject matter of Examples 46 to 50 can optionally include: the auxiliary capacity threshold for the first queue scheduler being greater than or equal to the auxiliary capacity threshold for the second queue scheduler.

[0180] In Example 52, the subject matter of Examples 1, 2, 5, or 6 to 51 may optionally include the global scheduler being further configured to determine whether a first request of the one or more requests to be included in the first queue scheduler satisfies a first priority criterion.

[0181] In Example 53, the subject matter of Example 52 can optionally include the first priority criterion being satisfied when the first request is to be processed by the memory controller within a threshold number of instructions to be processed by the memory controller.

[0182] In Example 54, the subject matter of Example 52 or 53 can optionally include the first priority criterion being satisfied when the target address related to the first request is to be accessed by the memory controller within a threshold number of instructions to be processed by the memory controller.

[0183] In Example 55, the subject matter of Examples 52 to 54 can optionally include the first priority criterion being satisfied when the target address related to the first request was previously accessed by the memory controller within a threshold number of instructions processed by the memory controller.

[0184] In Example 56, the subject matter of Examples 52 to 55 can optionally include the first priority criterion being satisfied when the target address related to the first request is associated with a latency-sensitive application.

[0185] In Example 57, the subject matter of Examples 52 to 56 can optionally include the first priority criterion being satisfied when the target address related to the first request is associated with a latency resilient application.

[0186] In Example 58, the subject matter of Examples 52 to 57 can optionally include the global scheduler being further configured to modify at least one of the first timing scheme or the second timing scheme based on the first priority criterion being satisfied.

[0187] In Example 59, the subject matter of Examples 52 to 58 may optionally include: the global scheduler is further configured to modify the first timing scheme by adjusting a first number of clock cycles in which the one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface based on the first priority criterion being satisfied.

[0188] In Example 60, the subject matter of Examples 52 to 59 may optionally include: the global scheduler is further configured to modify the second timing scheme by adjusting a second number of clock cycles in which the one or more requests in the second queue scheduler are to be issued to the second memory set via the second memory set interface based on the first priority criterion being satisfied.

[0189] In Example 61, the subject matter of Examples 1, 2, 5, or 6 to 60 may optionally include the global scheduler being further configured to determine whether a second request of the one or more requests to be included in the second queue scheduler satisfies a second priority criterion.

[0190] In Example 62, the subject matter of Example 61 can optionally include the second priority criterion being satisfied when the second request is to be processed by the memory controller within a threshold number of instructions to be processed by the memory controller.

[0191] In Example 63, the subject matter of Example 61 or 62 can optionally include the second priority criterion being satisfied when the target address related to the second request is to be accessed by the memory controller within a threshold number of instructions to be processed by the memory controller.

[0192] In Example 64, the subject matter of Examples 61 to 63 can optionally include the second priority criterion being satisfied when the target address related to the second request was previously accessed by the memory controller within a threshold number of instructions processed by the memory controller.

[0193] In Example 65, the subject matter of Examples 61 to 64 can optionally include the second priority criterion being satisfied when the target address related to the second request is associated with a latency-sensitive application.

[0194] In Example 66, the subject matter of Examples 61 to 65 can optionally include the second priority criterion being satisfied when the target address related to the second request is associated with a latency-resilient application.

[0195] In Example 67, the subject matter of Examples 61 to 66 can optionally include the global scheduler being further configured to modify at least one of the first timing scheme or the second timing scheme based on the second priority criterion being satisfied.

[0196] In Example 68, the subject matter of Examples 61 to 67 may optionally include: the global scheduler is further configured to modify the first timing scheme by adjusting a first number of clock cycles in which the one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface based on the second priority criterion being satisfied.

[0197] In Example 69, the subject matter of Examples 61 to 68 may optionally include: the global scheduler is further configured to modify the second timing scheme by adjusting a second number of clock cycles in which the one or more requests in the second queue scheduler are to be issued to the second memory set via the second memory set interface based on the second priority criteria being satisfied.

[0198] In Example 70, the subject matter of Examples 61 to 69 can optionally include the first priority criterion being different from the second priority criterion.

[0199] In Example 71, the subject matter of Examples 61 to 69 can optionally include the first priority criterion being equal to the second priority criterion.

[0200] In Example 72, the subject matter of Examples 1, 2, 5, or 6 to 71 may further include: a phase detector configured to receive information about the one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler during a predefined duration.

[0201] In Example 73, the subject matter of Example 72 can optionally include the phase detector being implemented as an application specific integrated circuit (ASIC).

[0202] In Example 74, the subject matter of Example 72 can optionally include the phase detector being implemented as a field programmable gate array (FPGA).

[0203] In Example 75, the subject matter of Examples 72 to 74 may optionally include: the phase detector is further configured to receive information about the one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler via an interface to the processing core during a predefined duration.

[0204] In Example 76, the subject matter of Examples 72 to 75 may optionally include: the phase detector is further configured to determine whether the one or more requests to be included in the first queue scheduler received within the predefined time duration meet the phase detection criteria for the first queue scheduler.

[0205] In Example 77, the subject matter of Example 76 may optionally include: the phase detection criterion for the first queue scheduler is satisfied when the sum of the one or more requests to be included in the first queue scheduler received within a predefined duration is greater than or equal to the phase detection threshold for the first queue scheduler.

[0206] In Example 78, the subject matter of Example 77 can optionally include the phase detector being further configured to trigger the global scheduler to modify at least one of the first timing scheme or the second timing scheme when a phase detection criterion for the first queue scheduler is satisfied.

[0207] In Example 79, the subject matter of Example 77 can optionally include the phase detector being further configured to modify at least one of the first timing scheme or the second timing scheme when a phase detection criterion for the first queue scheduler is satisfied.

[0208] In Example 80, the subject matter of Examples 72 to 79 may optionally include: the phase detector is further configured to determine whether the one or more requests to be included in the second queue scheduler received within the predefined time duration meet the phase detection criteria for the second queue scheduler.

[0209] In Example 81, the subject matter of Example 80 may optionally include: the phase detection criterion for the second queue scheduler is met when the sum of the one or more requests to be included in the second queue scheduler received within a predefined duration is greater than or equal to the phase detection threshold for the second queue scheduler.

[0210] In Example 82, the subject matter of Example 81 can optionally include the phase detector being further configured to trigger the global scheduler to modify at least one of the first timing scheme or the second timing scheme when a phase detection criterion for the second queue scheduler is satisfied.

[0211] In Example 83, the subject matter of Example 81 can optionally include the phase detector being further configured to modify at least one of the first timing scheme or the second timing scheme when a phase detection criterion for the second queue scheduler is satisfied.

[0212] Example 84 is a method for performing operations of a memory controller, wherein the method may include: issuing one or more requests in a first queue scheduler to a first memory set in accordance with a first timing scheme, via a first memory set interface and through a common channel; issuing one or more requests in a second queue scheduler to a second memory set in accordance with a second timing scheme, via a second memory set interface and through the common channel; receiving information about one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler; and modifying at least one of the first timing scheme or the second timing scheme based on the information about the one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler.

[0213] Example 85 is a method for performing operations of a memory controller, wherein the method may include: modifying at least one of a first timing scheme or a second timing scheme based on information about one or more data requests to be included in at least one of a first queue scheduler or a second queue scheduler, the first timing scheme indicating when one or more requests in the first queue scheduler are to be issued to the first memory set via a first memory set interface and through a common channel, and the second timing scheme indicating when one or more requests in the second queue scheduler are to be issued to the second memory set via a second memory set interface and through the common channel; and issuing at least one of a request to the first memory set in accordance with the modified first timing scheme or a request to the second memory set in accordance with the modified second timing scheme.

[0214] Example 86 is a method for performing operations of a memory controller, wherein the method may include: issuing one or more requests in a first queue scheduler to a first memory set in accordance with a first timing scheme, via a first memory set interface and through a common channel; issuing one or more requests in a second queue scheduler to a second memory set in accordance with a second timing scheme, via a second memory set interface and through the common channel; and modifying at least one of the first timing scheme or the second timing scheme based on at least one of the one or more requests in the first queue scheduler or the one or more requests in the second queue scheduler.

[0215] Example 87 is a method for performing operations of a memory controller, wherein the method may include: modifying at least one of a first timing scheme or a second timing scheme based on information about one or more data requests included in at least one of a first queue scheduler or a second queue scheduler, the first timing scheme indicating when to issue one or more requests in the first queue scheduler to the first memory set via a first memory set interface and through a common channel, and the second timing scheme indicating when to issue one or more requests in the second queue scheduler to the second memory set via a second memory set interface and through the common channel; and issuing at least one of a request to the first memory set in accordance with the modified first timing scheme or a request to the second memory set in accordance with the modified second timing scheme.

[0216] In Example 88, the subject matter of Example 84 or 85 may further include modifying at least one of the first timing scheme or the second timing scheme further based on at least one of the one or more requests in the first queue scheduler or the one or more requests in the second queue scheduler.

[0217] In Example 89, the subject matter of Example 86 or 87 may further include receiving information about one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler within a predefined time duration.

[0218] In Example 90, the subject matter of Example 89 may further include modifying at least one of the first timing scheme or the second timing scheme further based on information about the one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler.

[0219] In Example 91, the subject matter of Examples 84, 86, 88, 89, or 90 may further include issuing at least one of a request to the first set of memories in accordance with the modified first timing scheme or a request to the second set of memories in accordance with the modified second timing scheme.

[0220] In Example 92, the subject matter of Examples 84 to 91 can optionally include the first queue scheduler being implemented as a first rotating priority queue (RPQ) scheduler.

[0221] In Example 93, the subject matter of Examples 84 to 92 may further include providing the first timing scheme to the first queue scheduler.

[0222] In Example 94, the subject matter of Examples 84 to 93 may optionally include: the one or more requests in the first queue scheduler include at least one of a write request targeting the first memory set or a read request targeting the first memory set.

[0223] In Example 95, the subject matter of Examples 84 to 94 may optionally include: the one or more requests to be included in the first queue scheduler include at least one of a write request targeting the first memory set or a read request targeting the first memory set.

[0224] In Example 96, the subject matter of Examples 84 to 95 may optionally include the first timing scheme defining a first number of clock cycles in which the one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface.

[0225] In Example 97, the subject matter of Example 96 may optionally include: modifying at least one of the first timing scheme or the second timing scheme based on information about the one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler includes adjusting a first number of clock cycles in which the one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface.

[0226] In Example 98, the subject matter of Example 96 or 97 may optionally include: modifying at least one of the first timing scheme or the second timing scheme based on information about the one or more requests included in at least one of the first queue scheduler or the second queue scheduler includes adjusting a first number of clock cycles in which the one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface.

[0227] In Example 99, the subject matter of Examples 84 to 98 can optionally include the first memory set comprising dynamic random access memory (DRAM), and the first memory set interface being implemented as a DDR interface.

[0228] In Example 100, the subject matter of Examples 84 to 99 can optionally include the second queue scheduler being implemented as a second Rotating Priority Queue (RPQ) scheduler.

[0229] In Example 101, the subject matter of Examples 84 to 100 may further include providing the second timing scheme to the second queue scheduler.

[0230] In Example 102, the subject matter of Examples 84 to 101 may optionally include: the one or more requests in the second queue scheduler include at least one of a write request targeting the second memory set or a read request targeting the second memory set.

[0231] In Example 103, the subject matter of Examples 84 to 102 may optionally include: the one or more requests in the second queue scheduler to be included include at least one of a write request targeting the second memory set or a read request targeting the second memory set.

[0232] In Example 104, the subject matter of Examples 96 to 103 can optionally include the second timing scheme defining a second number of clock cycles in which the one or more requests in the second queue scheduler are to be issued to the second memory set via the second memory set interface.

[0233] In Example 105, the subject matter of Example 104 may optionally include: modifying at least one of the first timing scheme or the second timing scheme based on information about the one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler includes adjusting a first number of clock cycles in which the one or more requests in the second queue scheduler are to be issued to the second memory set via the second memory set interface.

[0234] In Example 106, the subject matter of Example 104 or 105 may optionally include: modifying at least one of the first timing scheme or the second timing scheme based on information about the one or more requests included in at least one of the first queue scheduler or the second queue scheduler includes adjusting a first number of clock cycles in which the one or more requests in the second queue scheduler are to be issued to the second memory set via the second memory set interface.

[0235] In Example 107, the subject matter of Examples 104 to 106 may optionally include the first number of clock cycles being different from the second number of clock cycles.

[0236] In Example 108, the subject matter of Examples 104 to 106 may optionally include the first number of clock cycles being equal to the second number of clock cycles.

[0237] In Example 109, the subject matter of Examples 84 to 108 may optionally include the second memory set comprising 3D XPoint memory, and the second memory set interface being implemented as a DDR-T interface.

[0238] In Example 110, the subject matter of Examples 84 to 109 may further include: receiving the global timing scheme via the interface to the processing core may optionally include the global timing scheme including the first timing scheme and the second timing scheme.

[0239] In Example 111, the subject matter of Example 110 may optionally include: the first timing scheme includes a first number of clock cycles in which the one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface during a first duration, the second timing scheme includes a second number of clock cycles in which the one or more requests in the second queue scheduler are to be issued to the second memory set via the second memory set interface during a second duration, and the first duration and the second duration are sequential.

[0240] In Example 112, the subject matter of Example 110 or 111 may optionally include receiving, via an interface to the processing core, information about the one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler.

[0241] In Example 113, the subject matter of Examples 84 to 112 may further include determining whether the one or more requests in the first queue scheduler meet capacity criteria for the first queue scheduler.

[0242] In Example 114, the subject matter of Example 113 can optionally include: when a sum of the one or more requests in the first queue scheduler is greater than or equal to a capacity threshold for the first queue scheduler, the capacity criterion for the first queue scheduler is met.

[0243] In Example 115, the subject matter of Example 114 can optionally include the capacity threshold for the first queue scheduler being a percentage of a total capacity of the first queue scheduler.

[0244] In Example 116, the subject matter of Examples 113 to 115 may further include: wherein modifying at least one of the first timing scheme or the second timing scheme based on at least one of the one or more requests in the first queue scheduler or the one or more requests in the second queue scheduler includes modifying the first timing scheme based on a capacity criterion for the first queue scheduler being satisfied.

[0245] In Example 117, the subject matter of Example 116 may optionally include: modifying the first timing scheme based on a capacity criterion for the first queue scheduler being satisfied includes adjusting a first number of clock cycles in which the one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface based on the capacity criterion for the first queue scheduler being satisfied.

[0246] In Example 118, the subject matter of Examples 84 to 117 may further include determining whether the one or more requests in the second queue scheduler meet capacity criteria for the second queue scheduler.

[0247] In Example 119, the subject matter of Example 118 can optionally include: when a sum of the one or more requests in the second queue scheduler is greater than or equal to a capacity threshold for the second queue scheduler, the capacity criterion for the second queue scheduler is met.

[0248] In Example 120, the subject matter of Example 119 can optionally include the capacity threshold for the second queue scheduler being a percentage of a total capacity of the second queue scheduler.

[0249] In Example 121, the subject matter of Examples 118 to 120 may optionally include modifying at least one of the first timing scheme or the second timing scheme based on at least one of the one or more requests in the first queue scheduler or the one or more requests in the second queue scheduler, including modifying the second timing scheme based on a capacity criterion for the second queue scheduler being satisfied.

[0250] In Example 122, the subject matter of Example 121 may optionally include: modifying the second timing scheme based on capacity criteria for the second queue scheduler being met includes adjusting a second number of clock cycles in which the one or more requests in the second queue scheduler are to be issued to the second memory set via the second memory set interface based on capacity criteria for the second queue scheduler being met.

[0251] In Example 123, the subject matter of Examples 119 to 122 can optionally include: the capacity threshold for the first queue scheduler being less than or equal to the capacity threshold for the second queue scheduler.

[0252] In Example 124, the subject matter of Examples 119 to 122 can optionally include: the capacity threshold for the first queue scheduler being greater than or equal to the capacity threshold for the second queue scheduler.

[0253] In Example 125, the subject matter of Examples 84, 85, 88, or 89 to 124 may further include determining whether the one or more requests to be included in the first queue scheduler meet auxiliary capacity criteria for the first queue scheduler.

[0254] In Example 126, the subject matter of Example 125 can optionally include: the auxiliary capacity criterion for the first queue scheduler is met when the sum of the one or more requests to be included in the first queue scheduler is greater than or equal to the auxiliary capacity threshold for the first queue scheduler.

[0255] In Example 127, the subject matter of Example 126 can optionally include the auxiliary capacity threshold for the first queue scheduler being equal to the capacity threshold for the first queue scheduler minus a sum of the one or more requests to be included in the first queue scheduler.

[0256] In Example 128, the subject matter of Examples 125 to 127 may optionally include: modifying at least one of the first timing scheme or the second timing scheme based on information about the one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler includes modifying the first timing scheme based on an auxiliary capacity standard for the first queue scheduler being satisfied.

[0257] In Example 129, the subject matter of Examples 125 to 128 may optionally include: modifying the first timing scheme based on an auxiliary capacity standard for the first queue scheduler being satisfied includes adjusting a first number of clock cycles in which the one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface based on the auxiliary capacity standard for the first queue scheduler being satisfied.

[0258] In Example 130, the subject matter of Examples 84, 85, 88, or 89 to 129 may further include determining whether the one or more requests to be included in the second queue scheduler meet auxiliary capacity criteria for the second queue scheduler.

[0259] In Example 131, the subject matter of Example 130 can optionally include: the auxiliary capacity criterion for the second queue scheduler is met when the sum of the one or more requests to be included in the second queue scheduler is greater than or equal to the auxiliary capacity threshold for the second queue scheduler.

[0260] In Example 132, the subject matter of Example 131 can optionally include: the auxiliary capacity threshold for the second queue scheduler being equal to the capacity threshold for the second queue scheduler minus a sum of the one or more requests to be included in the second queue scheduler.

[0261] In Example 133, the subject matter of Examples 130 to 132 may optionally include modifying at least one of the first timing scheme or the second timing scheme based on information about the one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler, including modifying the second timing scheme based on an auxiliary capacity criterion for the second queue scheduler being satisfied.

[0262] In Example 134, the subject matter of Example 133 may optionally include: modifying the second timing scheme based on the auxiliary capacity standard for the second queue scheduler being satisfied includes adjusting a second number of clock cycles in which the one or more requests in the second queue scheduler are to be issued to the second memory set via the second memory set interface based on the auxiliary capacity standard for the second queue scheduler being satisfied.

[0263] In Example 135, the subject matter of Examples 131 to 134 can optionally include: the auxiliary capacity threshold for the first queue scheduler being less than or equal to the auxiliary capacity threshold for the second queue scheduler.

[0264] In Example 136, the subject matter of Examples 131 to 134 can optionally include: the auxiliary capacity threshold for the first queue scheduler being greater than or equal to the auxiliary capacity threshold for the second queue scheduler.

[0265] In Example 137, the subject matter of Examples 84, 85, 88, or 89 to 136 may further include determining whether a first request of the one or more requests to be included in the first queue scheduler satisfies a first priority criterion.

[0266] In Example 138, the subject matter of Example 137 can optionally include the first priority criterion being satisfied when the first request is to be processed by the memory controller within a threshold number of instructions to be processed by the memory controller.

[0267] In Example 139, the subject matter of Example 137 or 138 may optionally include the first priority criterion being satisfied when the target address related to the first request is to be accessed by the memory controller within a threshold number of instructions to be processed by the memory controller.

[0268] In Example 140, the subject matter of Examples 137 to 139 may optionally include the first priority criterion being satisfied when the target address related to the first request was previously accessed by the memory controller within a threshold number of instructions processed by the memory controller.

[0269] In Example 141, the subject matter of Examples 137 to 140 can optionally include the first priority criterion being satisfied when the target address related to the first request is associated with a latency-sensitive application.

[0270] In Example 142, the subject matter of Examples 137 to 141 may optionally include: the first priority criterion is satisfied when a target address related to the request in the one or more requests to be included in the first queue scheduler is associated with a latency resilient application.

[0271] In Example 143, the subject matter of Examples 137 to 142 may optionally include: modifying at least one of the first timing scheme or the second timing scheme based on information about the one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler includes modifying at least one of the first timing scheme or the second timing scheme based on a first priority criterion being satisfied.

[0272] In Example 144, the subject matter of Example 143 may optionally include: modifying at least one of the first timing scheme or the second timing scheme based on the first priority criterion being satisfied includes modifying the first timing scheme based on the first priority criterion being satisfied by adjusting a first number of clock cycles in which the one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface.

[0273] In Example 145, the subject matter of Example 143 or 144 may optionally include: modifying at least one of the first timing scheme or the second timing scheme based on the first priority criterion being satisfied includes modifying the second timing scheme by adjusting a second number of clock cycles in which the one or more requests in the second queue scheduler are to be issued to the second memory set via the second memory set interface based on the first priority criterion being satisfied.

[0274] In Example 146, the subject matter of Examples 84, 85, 88, or 89 to 145 may further include determining whether a second request of the one or more requests to be included in the second queue scheduler satisfies a second priority criterion.

[0275] In Example 147, the subject matter of Example 146 can optionally include the second priority criterion being satisfied when the second request is to be processed by the memory controller within a threshold number of instructions to be processed by the memory controller.

[0276] In Example 148, the subject matter of Example 146 or 147 can optionally include the second priority criterion being satisfied when the target address related to the second request is to be accessed by the memory controller within a threshold number of instructions to be processed by the memory controller.

[0277] In Example 149, the subject matter of Examples 146 to 148 can optionally include the second priority criterion being satisfied when the target address related to the second request was previously accessed by the memory controller within a threshold number of instructions processed by the memory controller.

[0278] In Example 150, the subject matter of Examples 146 to 149 can optionally include the second priority criterion being satisfied when the target address related to the second request is associated with a latency-sensitive application.

[0279] In Example 151, the subject matter of Examples 146 to 150 can optionally include the second priority criterion being satisfied when the target address related to the second request is associated with a latency-resilient application.

[0280] In Example 152, the subject matter of Examples 146 to 151 may optionally include: modifying at least one of the first timing scheme or the second timing scheme based on information about the one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler includes modifying at least one of the first timing scheme or the second timing scheme based on a second priority criterion being satisfied.

[0281] In Example 153, the subject matter of Example 152 may optionally include: modifying at least one of the first timing scheme or the second timing scheme based on a second priority criterion being satisfied includes modifying the first timing scheme based on the second priority criterion being satisfied by adjusting a first number of clock cycles in which the one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface.

[0282] In Example 154, the subject matter of Example 152 or 153 may optionally include: modifying at least one of the first timing scheme or the second timing scheme based on a second priority criterion being satisfied includes modifying the second timing scheme by adjusting a second number of clock cycles in which the one or more requests in the second queue scheduler are to be issued to the second memory set via the second memory set interface based on the second priority criterion being satisfied.

[0283] In Example 155, the subject matter of Examples 146 to 154 can optionally include the first priority criterion being different than the second priority criterion.

[0284] In Example 156, the subject matter of Examples 146 to 154 can optionally include the first priority criterion being equal to the second priority criterion.

[0285] In Example 157, the subject matter of Examples 84, 85, 88, or 89 to 156 may optionally include receiving information about the one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler during a predefined duration.

[0286] In Example 158, the subject matter of Example 157 may optionally include receiving, via an interface to the processing core during a predefined time duration, information about the one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler.

[0287] In Example 159, the subject matter of Example 157 or 158 may further include determining whether the one or more requests received within a predefined time duration to be included in the first queue scheduler satisfy phase detection criteria for the first queue scheduler.

[0288] In Example 160, the subject matter of Example 159 may optionally include: the phase detection criterion for the first queue scheduler is satisfied when the sum of the one or more requests to be included in the first queue scheduler received within a predefined duration is greater than or equal to a phase detection threshold for the first queue scheduler.

[0289] In Example 161, the subject matter of Example 159 or 160 may optionally include: modifying at least one of the first timing scheme or the second timing scheme based on information about the one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler includes modifying at least one of the first timing scheme or the second timing scheme based on a phase detection criterion for the first queue scheduler being satisfied.

[0290] In Example 162, the subject matter of Example 161 may optionally include: modifying at least one of the first timing scheme or the second timing scheme based on a phase detection criterion for the first queue scheduler being satisfied includes modifying the first timing scheme by adjusting a first number of clock cycles in which the one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface based on the phase detection criterion for the first queue scheduler being satisfied.

[0291] In Example 163, the subject matter of Example 161 or 162 may optionally include: modifying at least one of the first timing scheme or the second timing scheme based on a phase detection criterion for the first queue scheduler being satisfied includes modifying the second timing scheme by adjusting a second number of clock cycles in which the one or more requests in the second queue scheduler are to be issued to the second memory set via the second memory set interface based on the phase detection criterion for the first queue scheduler being satisfied.

[0292] In Example 164, the subject matter of Examples 157 to 163 may further include determining whether the one or more requests received within a predefined time duration to be included in the second queue scheduler satisfy phase detection criteria for the second queue scheduler.

[0293] In Example 165, the subject matter of Example 164 may optionally include: the phase detection criterion for the second queue scheduler is satisfied when the sum of the one or more requests to be included in the second queue scheduler received within a predefined duration is greater than or equal to a phase detection threshold for the second queue scheduler.

[0294] In Example 166, the subject matter of Example 164 or 165 may further include: wherein modifying at least one of the first timing scheme or the second timing scheme based on information about the one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler includes modifying at least one of the first timing scheme or the second timing scheme based on a phase detection criterion for the second queue scheduler being satisfied.

[0295] In Example 167, the subject matter of Example 166 may optionally include: modifying at least one of the first timing scheme or the second timing scheme based on a phase detection criterion for the first queue scheduler being satisfied includes modifying the first timing scheme by adjusting a first number of clock cycles in which the one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface based on a phase detection criterion for the second queue scheduler being satisfied.

[0296] In Example 168, the subject matter of Example 166 or 167 may optionally include: modifying at least one of the first timing scheme or the second timing scheme based on a phase detection criterion for the first queue scheduler being satisfied includes modifying the second timing scheme based on a phase detection criterion for the second queue scheduler being satisfied by adjusting a second number of clock cycles in which the one or more requests in the second queue scheduler are to be issued to the second memory set via the second memory set interface.

[0297] Example 169 is a computing device comprising one or more processors configured to perform the method of any one of Examples 84 to 168.

[0298] Example 170 is a processing circuit configured to perform the method of any one of Examples 84 to 168.

[0299] Example 171 is a non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform the method of any one of Examples 84 to 168.

[0300] Example 172 is a non-transitory computer-readable medium storing instructions that, when executed by processing circuitry of a computing device, cause the computing device to perform the method of any one of Examples 84 to 168.

[0301] Although the above description and connection diagrams may depict electronic device components as separate elements, a skilled person will appreciate the various possibilities of combining or integrating discrete elements into a single element. This may include combining two or more circuits to form a single circuit, mounting two or more circuits onto a common chip or chassis to form an integrated element, executing discrete software components on a common processor core, etc. Conversely, a skilled person will recognize the possibility of dividing a single element into two or more discrete elements, such as dividing a single circuit into two or more separate circuits, dividing a chip or chassis into the discrete elements originally provided thereon, dividing a software component into two or more parts and executing each part on a separate processor core, etc.

[0302] It should be understood that the implementation of the methods detailed herein is illustrative in nature and is therefore understood to be capable of being implemented in corresponding devices. Similarly, it should be understood that the implementation of the devices detailed herein is understood to be capable of being implemented as corresponding methods. It should therefore be understood that the devices corresponding to the methods detailed herein may include one or more components configured to perform each aspect of the relevant methods.

[0303] All acronyms defined in the above description are further retained in all claims included herein.

[0304] The terms used herein are only used to describe the purpose of specific example aspects and are not intended to be restrictive. As used herein, the singular forms "one", "an" and "the" may also be intended to include plural forms unless the context clearly indicates otherwise. The term "and / or" includes any and all combinations of one or more of the associated listed items. The terms "comprise", "include", "contain" and "have" are inclusive and therefore specify the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or their groups. The method steps, processes and operations described herein will not be interpreted as necessarily requiring them to be performed in the particular order discussed or illustrated, unless specifically identified as the order of execution. It will also be understood that additional or alternative steps may be adopted.

[0305] Although can use term first, second, third etc. to describe various element, assembly, region, layer and / or part in this article, these element, assembly, region, layer and / or part should not be limited by these terms.These terms can only be used for an element, assembly, region, layer or part and another region, layer or part are distinguished.Terms such as " first ", " second " and other numerical terms do not imply sequence or order when used in this article, unless clearly indicated by context.Therefore, the first element, assembly, region, layer or part discussed below can be referred to as the second element, assembly, region, layer or part and do not depart from the teaching of example aspect.

[0306] Although the present disclosure has been particularly shown and described with reference to certain aspects, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims. The various aspects of the present disclosure are not necessarily mutually exclusive, as some aspects of the present disclosure may be combined with one or more aspects of the present disclosure to form new aspects. Therefore, the scope of the present disclosure is indicated by the appended claims, and it is therefore intended to include all changes within the meaning and scope of the equivalents of the claims.

Claims

1. A computing system comprising: A memory controller comprising a first queue scheduler configured to issue one or more requests in the first queue scheduler to the first memory set via the first memory set interface and over a common channel in accordance with a first timing scheme; a second queue scheduler configured to issue one or more requests in the second queue scheduler to the second memory set via the second memory set interface and over the common channel in accordance with a second timing scheme; as well as A global scheduler configured to receiving information regarding one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler; as well as modifying at least one of the first timing scheme or the second timing scheme based on information regarding the one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler; Wherein modifying at least one of the first timing scheme or the second timing scheme includes adjusting a number of clock cycles in which one or more requests in the corresponding queue scheduler are to be issued to the corresponding memory set via the corresponding memory set interface.

2. The computing system according to claim 1, Wherein the global scheduler is further configured to modify at least one of the first timing scheme or the second timing scheme further based on at least one of the one or more requests in the first queue scheduler or the one or more requests in the second queue scheduler.

3. The computing system according to claim 1 , The memory controller includes a clock, The first timing scheme defines a first number of clock cycles in which the one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface, and The second timing scheme defines a second number of clock cycles in which the one or more requests in the second queue scheduler are to be issued to the second memory set via the second memory set interface.

4. The computing system according to claim 1 , wherein the first memory set includes dynamic random access memory (DRAM), and The second set of memories includes three-dimensional (3D) XPoint memories.

5. The computing system according to any one of claims 1 or 2, wherein the first memory aggregate interface is a double data rate (DDR) interface, and The second memory aggregate interface is a DDR-Transaction (DDR-T) interface.

6. The computing system according to any one of claims 1 or 2, The global scheduler is further configured as determining whether the one or more requests in the first queue scheduler meet capacity criteria for the first queue scheduler, and The first timing scheme is modified based on capacity criteria for the first queue scheduler being met.

7. The computing system according to any one of claims 1 or 2, The global scheduler is further configured as determining whether one or more requests to be included in the second queue scheduler meet auxiliary capacity criteria for the second queue scheduler, and The second timing scheme is modified based on an auxiliary capacity criterion for the second queue scheduler being satisfied.

8. The computing system according to any one of claims 1 or 2, The global scheduler is further configured as determining whether a first request of the one or more requests to be included in the first queue scheduler satisfies a first priority criterion, and At least one of the first timing scheme or the second timing scheme is modified based on the first priority criterion being satisfied.

9. The computing system according to claim 8, Wherein the first priority criterion is satisfied when the first request is to be processed by the memory controller within a threshold number of instructions to be processed by the memory controller.

10. The computing system according to claim 8, Wherein the first priority criterion is satisfied when the first request relates to a target address to be accessed by the memory controller within a threshold number of instructions to be processed by the memory controller.

11. The computing system according to any one of claims 1 or 2, further comprising: A phase detector is configured to receive, via an interface to the processing core, information regarding one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler during a predefined time duration.

12. A method for performing operations of a memory controller, the method comprising: modifying at least one of a first timing scheme or a second timing scheme based on information regarding one or more data requests to be included in at least one of the first queue scheduler or the second queue scheduler, the first timing scheme indicating when one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface and over the common channel, and the second timing scheme indicating when one or more requests in the second queue scheduler are to be issued to the second memory set via the second memory set interface and over the common channel, and issuing at least one of a request to the first set of memories in accordance with the modified first timing scheme or a request to the second set of memories in accordance with the modified second timing scheme; Wherein modifying at least one of the first timing scheme or the second timing scheme includes adjusting a number of clock cycles in which one or more requests in the corresponding queue scheduler are to be issued to the corresponding memory set via the corresponding memory set interface.

13. The method according to claim 12, further comprising: At least one of the first timing scheme or the second timing scheme is modified further based on at least one of the one or more requests in the first queue scheduler or the one or more requests in the second queue scheduler.

14. The method according to any one of claims 12 or 13, wherein the first timing scheme defines a first number of clock cycles in which one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface, and Modifying at least one of the first timing scheme or the second timing scheme includes based on information about the one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler A first number of clock cycles in which the one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface is adjusted.

15. The method according to any one of claims 12 or 13, Wherein information regarding one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler is received during a predefined time duration via an interface to the processing core.

16. The method according to claim 15, further comprising: determining whether one or more requests received within a predefined time duration to be included in the first queue scheduler satisfy phase detection criteria for the first queue scheduler, and Wherein the phase detection criterion for the first queue scheduler is met when a sum of one or more requests to be included in the first queue scheduler received within a predefined time duration is greater than or equal to a phase detection threshold for the first queue scheduler.

17. A computing system comprising: A memory controller comprising a first queue scheduler configured to issue one or more requests in the first queue scheduler to the first memory set via the first memory set interface and over a common channel in accordance with a first timing scheme; a second queue scheduler configured to issue one or more requests in the second queue scheduler to the second memory set via the second memory set interface and over the common channel in accordance with a second timing scheme; as well as A global scheduler configured to modifying at least one of the first timing scheme or the second timing scheme based on at least one of the one or more requests in the first queue scheduler or the one or more requests in the second queue scheduler; Wherein modifying at least one of the first timing scheme or the second timing scheme includes adjusting a number of clock cycles in which one or more requests in the corresponding queue scheduler are to be issued to the corresponding memory set via the corresponding memory set interface.

18. The computing system according to claim 17, Wherein the global scheduler is further configured to receive information regarding one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler within a predefined time duration.

19. The computing system according to claim 18, Wherein the global scheduler is further configured to modify at least one of the first timing scheme or the second timing scheme further based on information regarding one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler.

20. The computing system according to any one of claims 17 or 18, Wherein the memory controller is configured to issue at least one of requests to the first set of memories in accordance with the modified first timing scheme or requests to the second set of memories in accordance with the modified second timing scheme.

21. A computing device comprising one or more processors configured to perform the method according to any one of claims 12 or 13.

22. A processing circuit configured to perform the method according to any one of claims 12 or 13.

23. A non-transitory computer-readable medium storing instructions that, when executed by a processing circuit of a computing device, cause the computing device to perform the method of any one of claims 12 to 16.

24. A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform the method according to any one of claims 12 to 16.

25. An apparatus for performing operations of a memory controller, the apparatus comprising: means for modifying at least one of a first timing scheme or a second timing scheme based on information regarding one or more data requests to be included in at least one of the first queue scheduler or the second queue scheduler, the first timing scheme indicating when one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface and over the common channel, the second timing scheme indicating when one or more requests in the second queue scheduler are to be issued to the second memory set via the second memory set interface and over the common channel, and means for issuing at least one of a request to the first set of memories in accordance with the modified first timing scheme or a request to the second set of memories in accordance with the modified second timing scheme; Wherein the means for modifying at least one of the first timing scheme or the second timing scheme comprises means for adjusting a number of clock cycles in which one or more requests in the respective queue scheduler are to be issued to the respective memory set via the respective memory set interface.

26. The apparatus of claim 25, further comprising: Means for modifying at least one of the first timing scheme or the second timing scheme further based on at least one of the one or more requests in the first queue scheduler or the one or more requests in the second queue scheduler.

27. The apparatus according to any one of claims 25 or 26, wherein the first timing scheme defines a first number of clock cycles in which one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface, and Means for modifying at least one of the first timing scheme or the second timing scheme based on information regarding one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler include Means for adjusting a first number of clock cycles in which one or more requests in a first queue scheduler are to be issued to a first memory aggregate via a first memory aggregate interface.

28. The apparatus according to any one of claims 25 or 26, Wherein information regarding one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler is received during a predefined time duration via an interface to the processing core.

29. The apparatus of claim 28, further comprising: means for determining whether one or more requests received within a predefined time duration to be included in the first queue scheduler satisfy phase detection criteria for the first queue scheduler, and Wherein the phase detection criterion for the first queue scheduler is met when a sum of one or more requests to be included in the first queue scheduler received within a predefined time duration is greater than or equal to a phase detection threshold for the first queue scheduler.

Images