Root Complex Integrated Endpoint Emulation for Compact PCIe Endpoints

Abstract

Aspects of the embodiments relate to systems and methods for emulating a PCIe root complex integrated endpoint. The systems and methods may include hardware logic implemented in a root complex system-on-chip and / or a connection device. The hardware may receive a request message to access one or more registers of a hardware device; determine that the request message includes a request to access one or more peripheral component interconnect express (PCIe) specific registers; and respond to the request message without providing information associated with the one or more PCIe specific registers.

Description

Background Art

[0001] The Peripheral Component Interconnect Express (PCIe) protocol defines an interconnect (or bus) hierarchy. Discreet devices can be connected to a root complex on a host device through the interconnect hierarchy. Some devices in a host device can be connected through the Bus 0 interconnect. Such devices can be considered root complex integrated endpoints (RCiEP). RCiEP can be integrated into a system on a chip (SOC) and have no PCIe link. However, despite the lack of a PCIe interface, these RCiEP devices can still be discovered as PCIe devices. Summary of the invention

[0002] According to one aspect of the present invention, there is provided an apparatus at least partially implemented in hardware, the apparatus comprising hardware logic for receiving a request message for accessing one or more registers of a hardware device; determining that the request message comprises a request for accessing one or more Peripheral Component Interconnect Express (PCIe) specific registers, the specific registers comprising at least one of the following: a PCIe capability register, a PCI Express extended capability register, a device / port type register, a link-related register, a link power management-related register, and a multi-function virtual channel capability register; and responding to the request message without providing information associated with the one or more PCIe specific registers.

[0003] According to another aspect of the present invention, a method performed by a simulated hardware element is provided, the method comprising: receiving a request message for accessing one or more registers of a hardware device; determining that the request message comprises a request for accessing one or more Peripheral Component Interconnect Express (PCIe) specific registers, the specific registers comprising at least one of the following: a PCIe capability register, a PCI Express extended capability register, a device / port type register, a link-related register, a link power management-related register, and a multi-function virtual channel capability register; and responding to the request message without providing information associated with the one or more PCIe specific registers.

[0004] According to another aspect of the present invention, a host system is provided, comprising: a processor running an operating system; a root complex compliant with Peripheral Component Interconnect Express (PCIe), the PCIe compliant root complex; and emulation hardware, comprising logic for: receiving a register access request message from the operating system; determining one or more PCIe specific registers in the request message, the specific registers comprising at least one of the following: a PCIe capability register, a PCI Express extended capability register, a device / port type register, a link-related register, a link power management-related register, and a multi-function virtual channel capability register; and hiding the PCIe specific registers from the operating system, comprising responding to the request message without providing information associated with the one or more PCIe specific registers. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 An embodiment of a block diagram of a computing system including a multi-core processor is shown.

[0006] Figure 2 is a schematic diagram of a system architecture 200 according to an embodiment of the present disclosure.

[0007] Figure 3 is a schematic diagram of a connection device emulating a root complex integrated endpoint according to an embodiment of the present disclosure.

[0008] Figure 4A is a process flow diagram of a root complex for supporting device emulation of a root complex integrated endpoint according to an embodiment of the present disclosure.

[0009] Figure 4B is a process flow chart of an endpoint device supporting device emulation of a root complex integrated endpoint according to an embodiment of the present disclosure.

[0010] Figure 5 is a process flow diagram of root complex hardware emulation logic for hiding PCIe specific messages from an operating system according to an embodiment of the present disclosure.

[0011] Figure 6 An embodiment of a computing system including an interconnect architecture is shown.

[0012] Figure 7 An embodiment of an interconnect architecture including a layered stack is shown.

[0013] Figure 8 Embodiments of requests or packets to be generated or received within an interconnect fabric are shown.

[0014] Fig. 9 An embodiment of a transmitter and receiver pair for an interconnect architecture is shown.

[0015] Fig.10 An embodiment of a multi-core processor is shown.

[0016] Fig.11 Another embodiment of a block diagram of a computing system is shown.

[0017] Fig.12 An embodiment of a block for a computing system including multiple processor sockets is shown.

[0018] The figures may not be drawn to scale. Like reference numerals in different figures denote similar elements. DETAILED DESCRIPTION

[0019] In the following description, many specific details are set forth, such as the following examples: specific types of processors and system configurations, specific hardware structures, specific architectural and microarchitectural details, specific register configurations, specific instruction types, specific system components, specific measurements / heights, specific processor pipeline stages and operations, etc., in order to provide a thorough understanding of the present invention. However, it is apparent to those skilled in the art that these specific details need not be employed to implement the present invention. In other instances, in order to avoid unnecessarily obscuring the present invention, well-known components or methods, such as specific and alternative processor architectures, specific logic circuits / codes for the described algorithms, specific firmware codes, specific interconnect operations, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, specific expressions of algorithms in code, specific power-off and gating techniques / logic, and other specific operational details of computer systems are not described in detail.

[0020] Although the following embodiments may be described with reference to energy conservation and energy efficiency in a particular integrated circuit, such as in a computing platform or microprocessor, other embodiments are also applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of the embodiments described herein can be applied to other types of circuits or semiconductor devices that can also benefit from better energy efficiency and energy conservation. For example, the disclosed embodiments are not limited to desktop computer systems or Ultrabooks. TM . And can also be used in other devices, such as handheld devices, tablet computers, other thin laptops, system-on-chip (SOC) devices, and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include microcontrollers, digital signal processors (DSPs), system-on-chips, network computers (NetPCs), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can perform the functions and operations taught below. In addition, the apparatus, methods, and systems described herein are not limited to physical computing devices, but can also involve software optimization for energy conservation and efficiency.

[0021] refer to Figure 1 , depicts an embodiment of a block diagram of a computing system including a multi-core processor. Processor 100 includes any processor or processing device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a coprocessor, a system on a chip (SOC), or other device that executes code. In one embodiment, processor 100 includes at least two cores, cores 101 and 102, which may include asymmetric cores or symmetric cores (embodiment shown). However, processor 100 may include any number of processing elements that may be symmetric or asymmetric.

[0022] In one embodiment, a processing element refers to hardware or logic that supports a software thread. Examples of hardware processing elements include: thread units, thread slots, threads, process units, contexts, context units, logical processors, hardware threads, cores, and / or any other element that can maintain the state of a processor (such as an execution state or an architecture state). In other words, in one embodiment, a processing element refers to any hardware that can be independently associated with a code (such as a software thread, an operating system, an application, or other code). A physical processor (or processor socket) generally refers to an integrated circuit, which may include any number of other processing elements such as a core or a hardware thread.

[0023] A core generally refers to logic located on an integrated circuit capable of maintaining an independent architectural state, where each independently maintained architectural state is associated with at least some dedicated execution resources. Unlike a core, a hardware thread generally refers to any logic located on an integrated circuit capable of maintaining an independent architectural state, where the independently maintained architectural states share access to execution resources. It can be seen that the line between the nomenclature of hardware threads and cores overlaps when certain resources are shared and other resources are dedicated to an architectural state. More generally, cores and hardware threads are viewed by an operating system as separate logical processors, where the operating system can schedule operations on each logical processor separately.

[0024] like Figure 1As shown, physical processor 100 includes two cores, cores 101 and 102. Here, cores 101 and 102 are considered to be symmetric cores, i.e., cores with the same configuration, functional units, and / or logic. In another embodiment, core 101 includes an out-of-order processor core, and core 102 includes an in-order processor core. However, cores 101 and 102 can be selected separately from any type of core, such as a native core, a software-managed core, a core suitable for executing a native instruction set architecture (ISA), a core suitable for executing a conversion instruction set architecture (ISA), a co-designed core, or other known cores. In a heterogeneous core environment (i.e., an asymmetric core), some form of translation (e.g., binary translation) can be utilized to schedule or execute code on one or both cores. However, for further discussion, the functional units shown in core 101 are described in further detail below, because the units in core 102 operate in a similar manner in the depicted embodiment.

[0025] As shown, core 101 includes two hardware threads 101a and 101b, which may also be referred to as hardware thread slots 101a and 101b. Therefore, in one embodiment, a software entity such as an operating system may view processor 100 as four separate processors, that is, four logical processors or processing elements capable of executing four software threads simultaneously. As described above, a first thread is associated with architecture state register 101a, a second thread is associated with architecture state register 101b, a third thread may be associated with architecture state register 102a, and a fourth thread may be associated with architecture state register 102b. Here, each architecture state register (101a, 101b, 102a, and 102b) may be referred to as a processing element, thread slot, or thread unit, as described above. As shown, architecture state register 101a is replicated in architecture state register 101b, so that each architecture state / context can be stored for logical processor 101a and logical processor 101b. In core 101, other smaller resources may also be replicated for threads 101a and 101b, such as instruction pointers and renaming logic in allocator and renamer block 130. Some resources may be shared through partitioning, such as reorder buffers, ILTB 120, load / store buffers, and queues in reorder / retirement unit 135. Other resources, such as general internal registers, page table base registers, low-level data cache and data-TLB 115, execution units 140, and portions of out-of-order unit 135 may be fully shared.

[0026] Processor 100 typically includes other resources, which may be fully shared, shared through partitioning, or dedicated to a processing element / pair of processing elements. Figure 1, an embodiment of a purely exemplary processor with illustrative logic units / resources of the processor is shown. Note that the processor may include or omit any of these functional units, as well as include any other known functional units, logic, or firmware not shown. As shown, core 101 includes a simplified, representative out-of-order (OOO) processor core. However, an in-order processor may be used in different embodiments. The OOO core includes a branch target buffer 120 for predicting branches to be executed / taken and an instruction translation buffer (I-TLB) 120 for storing address translation entries for instructions.

[0027] The core 101 also includes a decode module 125, which is coupled to the acquisition unit 120 to decode the acquired elements. In one embodiment, the acquisition logic includes individual sequencers associated with the thread slots 101a, 101b, respectively. Typically, the core 101 is associated with a first ISA, which defines / specifies instructions that can be executed on the processor 100. Machine code instructions that are typically part of the first ISA include a portion of the instruction (called an opcode) that references / specifies the instruction or operation to be performed. The decode logic 125 includes circuits that recognize these instructions from their opcodes and pass the decoded instructions in the pipeline for processing as defined by the first ISA. For example, as discussed in more detail below, in one embodiment, the decoder 125 includes logic designed or adapted to recognize specific instructions, such as transaction instructions. As a result of the decoder 125 recognition, the architecture or core 101 takes specific predefined actions to perform tasks associated with the appropriate instructions. It is important to note that any task, block, operation, and method described herein can be performed in response to a single or multiple instructions; some of which may be new or old instructions. Note that in one embodiment, decoders 126 recognize the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, decoders 126 recognize a second ISA (a subset of the first ISA or a different ISA).

[0028] In one example, the allocator and renamer block 130 includes an allocator for reserving resources, such as a register file for storing instruction processing results. However, threads 101a and 101b may be capable of out-of-order execution, where the allocator and renamer block 130 also reserves other resources, such as a reorder buffer that tracks instruction results. Unit 130 may also include a register renamer to rename program / instruction reference registers to other registers internal to processor 100. Reorder / retirement unit 135 includes components, such as the reorder buffers, load buffers, and store buffers mentioned above, to support out-of-order execution and later orderly retirement of instructions executed out-of-order.

[0029] In one embodiment, the scheduler and execution unit block 140 includes a scheduler unit for scheduling instructions / operations on the execution units. For example, floating point instructions are scheduled on the port of the execution unit with an available floating point execution unit. A register file associated with the execution unit is also included to store information instruction processing results. Exemplary execution units include floating point execution units, integer execution units, jump execution units, load execution units, store execution units, and other known execution units.

[0030] A lower level data cache and data translation buffer (D-TLB) 150 is coupled to the execution unit 140. The data cache is used to store recently used / operated elements, such as data operands, which may be saved in a memory consistency state. The D-TLB is used to store recent virtual / linear to physical address translations. As a specific example, the processor may include a page table structure to divide the physical memory into multiple virtual pages.

[0031] Here, cores 101 and 102 share access to a higher or more distant level cache, such as a second level cache associated with on-chip interface 110. Note that higher or more distant refers to cache levels increasing or further away from the execution units. In one embodiment, the higher level cache is a last level data cache - the last cache in the memory hierarchy on processor 100 - such as a second or third level data cache. However, the higher level cache is not limited to this, as it may be associated with or include an instruction cache. A trace cache - a type of instruction cache - may be coupled after decoder 125 to store recently decoded traces. Here, instructions may relate to macroinstructions (i.e., general instructions recognized by the decoders), which may be decoded into multiple microinstructions (micro-operations).

[0032] In the depicted configuration, the processor 100 also includes an on-chip interface module 110. Historically, a memory controller, described in more detail below, has been included in a computing system external to the processor 100. In such a scenario, the on-chip interface module 110 is used to communicate with devices external to the processor 100, such as system memory 175, a chipset (typically including a memory controller hub connected to the memory 175 and an I / O controller hub for connecting peripheral devices), a memory controller hub, a north bridge, or other integrated circuits. And in such a scenario, the bus 105 may include any known interconnect, such as a multi-drop bus, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g., cache coherent) bus, a layered protocol architecture, a differential bus, and a GTL bus.

[0033] Memory 175 may be dedicated to processor 100 or shared with other devices in the system. Common examples of memory 175 types include DRAM, SRAM, non-volatile memory (NV memory), and other known storage devices. Device 180 may include a graphics accelerator, a processor or card coupled to a memory controller hub, a data storage device coupled to an I / O controller hub, a wireless transceiver, a flash memory device, an audio controller, a network controller, or other known devices.

[0034] However, more recently, as more logic and devices are integrated on a single die such as a SOC, each of these devices may be incorporated on the processor 100. For example, in one embodiment, a memory controller hub is on the same package and / or die as the processor 100. Here, a portion of the core (the on-core portion) 101 includes one or more controllers for interfacing with other devices such as memory 175 or a graphics device 180. A configuration that includes an interconnect and controllers for interfacing with these devices is generally referred to as an on-core (or uncore configuration). As an example, an on-chip interface module 110 includes a ring interconnect for on-chip communication and a high-speed serial point-to-point link 105 for off-chip communication. However, in a SOC environment, even more devices, such as a network interface, a coprocessor, memory 175, a graphics processor 180, and any other known computer devices / interfaces may be integrated on a single die or integrated circuit to provide a small form factor with high functionality and low power consumption.

[0035] In one embodiment, processor 100 can execute compiler, optimization and / or converter code 177 to compile, convert and / or optimize application code 176 to support the apparatus and method described herein or engage with it. Compiler generally includes a program or assembly that converts source text / code into target text / code. Usually, using compiler to compile program / application code is to complete in multiple stages and multiple passes, to convert high-level programming language code into low-level machine or assembly language code. However, single-pass compiler can still be used for simple compilation. Compiler can utilize any known compilation technology and perform any known compiler operation, such as lexical analysis, preprocessing, parsing, semantic analysis, code generation, code conversion and code optimization.

[0036] Larger compilers typically include multiple phases, but most often these phases are included in two general phases: (1) the front end, where syntactic processing, semantic processing, and some transformations / optimizations may typically occur, and (2) the back end, where analysis, conversions, optimizations, and code generation may typically occur. Some compilers reference an intermediate section that illustrates the blurring depicted between the front end and back end of the compiler. As a result, references to the insertion, association, generation, or other operations of the compiler may occur in any of the above phases or passes, as well as any other known phase or pass of the compiler. As an illustrative example, a compiler may insert operations, calls, functions, and the like in one or more phases of compilation, such as inserting calls / operations in the front end phase of compilation and then transforming the calls / operations into lower level code in the transformation phase. Note that during dynamic compilation, compiler code or dynamically optimized code may insert such operations / calls, as well as optimize the code for execution at runtime. As a specific illustrative example, binary code (compiled code) may be dynamically optimized during runtime. Here, program code may include dynamically optimized code, binary code, or a combination thereof.

[0037] Similar to a compiler, a translator (e.g., a binary translator) statically or dynamically translates code to optimize and / or convert the code. Thus, references to the execution of code, application code, program code, or other software environment may refer to: (1) dynamically or statically executing a compiler program, code optimizer, or translator to compile program code, maintain software structure, perform other operations, optimize code, or convert code; (2) executing a main program code including operations / calls, such as optimized / compiled application code; (3) executing other program code associated with the main program code, such as a library, to maintain software structure, perform other software-related operations, or optimize code; or (4) a combination thereof.

[0038] Peripheral Component Interconnect Express (PCIe) endpoints may contain certain features that should not be exposed to the operating system or PCIe bus driver of the system on chip (SoC). To completely isolate the operation of the features from OS / driver influence, PCIExpress links and root ports can be hidden from OS / driver discovery and control, thereby emulating a root complex integrated endpoint (RCiEP) at the attached device.

[0039] The present disclosure describes systems and methods for facilitating a root complex and a small form factor PCIe endpoint (referred to herein as a device) to emulate a root complex integrated endpoint. The root complex integrated endpoint emulation can expose selected functions and features that are intended to be discoverable by the OS / driver, but does not expose the physical PCIe interface. The emulation allows the PCIe interface to be hidden from the OS / driver view in a manner that is fully compliant with the PCIe specification and readily available standard PCIe endpoint controller IP.

[0040] Figure 2 2 is a schematic diagram of a system architecture 200 according to an embodiment of the present disclosure. The system architecture 200 may include a system on a chip (SoC) 202 and a plurality of devices 220a-n connected to the SoC 202 via a PCIe-compliant switch bridge 230. The system architecture 200 may include one or more processors 210 coupled to a root complex 204 via a link such as a front-side bus. The processor 210 may include an operating system and a PCIe bus driver 212.

[0041] The host system 201 may also include a root complex 204. The root complex 204 may serve as a controller hub for PCIe-compliant systems and devices. The root complex 204 connects the processor 210 to one or more endpoint devices 220a-n across a PCIe-compliant switch bridge 230, which may include one or more switch devices for switching between connected devices. The SoC 202 may include one or more PCIe ports 218, which may serve as an interface with the PCIe-compliant switch bridge 230. Each device 220a-n may include a PCIe-compliant interface 222a-n, respectively, to communicate with the SoC 202 through the PCIe-compliant switch bridge 230. The switch bridge 230 may be coupled to the PCIe port 218 via a PCIe-compliant link 232. One or more devices 220a-220n may be coupled to the switch bridge via PCIe-compliant links 234a-n, respectively. In an embodiment, device 220m may be connected to port 218 across a point-to-point PCIe-compliant link 234m.

[0042] SoC 202 may include a plurality of root complex integrated endpoints (RCiEPs) 206a-n. RCiEPs 206a-n may be PCIe compliant endpoint devices that do not include a PCIe interface linked to root complex 204.

[0043] Endpoint device 220a may include emulation hardware 224 that allows endpoint device 220a to emulate an RCiEP device. Emulation hardware 224 includes logic to hide registers associated with PCIe functions from OS 212 when discovered by OS 212 of endpoint device 220a. Emulation hardware 224 may also hide messages associated with PCIe operations from OS 212.

[0044] For example, the emulation hardware 224 may detect register accesses by the OS to one or more registers associated with the PCIe functionality. The emulation hardware 224 may respond to the register accesses by sending a string of 0s for read operations, and may discard write operations to the registers. The emulation hardware 224 may allow register access requests that do not involve the PCIe functionality of the endpoint device 220, thereby allowing the endpoint device 220 to continue to operate within the SoC framework but without exposing the PCIe functionality.

[0045] SoC 202 may also include emulation hardware 214 for making endpoint device 220a appear to be an RCiEP device. When the emulation hardware receives a register access request to a PCIe specific register, the emulation hardware 214 may similarly hide (by redirecting access or manufacturing return data or manipulating return data) the PCIe specific register from OS 212. The emulation hardware 214 on SoC 202 may hide PCIe specific registers of endpoint device 220a and / or SoC PCIe port 208. In addition, the emulation hardware 214 in SoC 202 may also hide PCIe specific registers associated with root complex controller 216. For example, the emulation hardware 214 may make SoC PCIe port 208 transparent to OS 212.

[0046] The emulation of RCiEP in device 220a can be implemented on both or either SoC 202 and by device 220a (for example). The root complex 204, PCIe-compliant switch bridge 230, and all link-related control, power management, and capabilities are hidden from OS / driver 212 discovery. Instead, endpoint device 220a can be discovered using a Type 0 configuration cycle. Then, SoC 202 and device 220a can process standard messages defined in PCIe operations.

[0047] Figure 3 is a schematic diagram of a connection device emulating a root complex integrated endpoint according to an embodiment of the present disclosure. Figure 3 A logical diagram illustrating how emulation hardware may be implemented in SoC 302 (as SoC RCiEP emulation hardware (HW) 304 ) and / or in endpoint device 310 as device RCiEP HW 312 is provided.

[0048] During device discovery, the SoC 302 may hide its root complex register set from discovery by the OS / driver 308. The SoC 302 may generate a Type 0 configuration cycle to directly target the small form factor endpoint device 310. The SoC 302 may forward Type 0 configuration register accesses to the small form factor endpoint device 310. In some embodiments, the SoC 302 may receive Type 1 configuration register accesses. The SoC 302 may ignore or reconfigure Type 1 configuration register accesses. The SoC 302 may configure Type 0 for each small form factor endpoint device 310 and forward Type 0 configuration register accesses to each connected small form factor endpoint device 310. A number of PCIe defined standard configuration registers in the endpoint device 310 are hidden from the OS 308 via the SoC RCiEP emulation HW 304 or the device RCiEP HW 312. For example, the emulation hardware may provide read zeros and may discard write accesses. In some embodiments, the emulated hardware can change the read value during OS / driver discovery or programming (e.g., to an empty string or a string with all zeros, or to a string that does not conform to the PCIe protocol, or to a string that the OS cannot otherwise interpret). These operations effectively allow endpoint device 310, which is a compact PCIe endpoint, to be viewed by OS / driver 308 as a root complex integrated endpoint.

[0049] Registers to be hidden may include PCIe specific registers including: PCIe Capability register (offset 02h), Device / Port Type = '1001b' (RCiEP); link related registers within PCI Express Extended Capabilities; link power management related registers, and Multi-Function Virtual Channel Capability register.

[0050] Note, however, that these registers can still be physically implemented inside the endpoint device 310 so that the SoC 302 has a way for the firmware / BIOS to discover and configure the PCIe link 330 to make the endpoint device features operational. By maintaining the registers within the device as well as within the root complex, the emulated hardware allows the device to continue to conform to the PCIe endpoint controller IP architecture.

[0051] Figure 4A400 is a process flow chart of a root complex for supporting device emulation of a root complex integrated endpoint according to an embodiment of the present disclosure. System on chip (SoC) emulation hardware can receive a PCIe register access request (402) from the OS or a bus driver. The request can come as part of a device discovery process. The SoC emulation hardware can hide the PCIe registers from the OS (404). For example, for a read request, the SoC emulation hardware can return a bit string of all zeros. For a write access request, the SoC emulation hardware can discard the request. In some embodiments, the SoC emulation hardware can modify or abandon the transmission of any PCIe-related register information it receives from the endpoint device to further hide the PCIe registers. For example, the emulation hardware can modify the register information to information that does not represent the PCIe protocol, or in addition, information that the OS cannot interpret. The SoC emulation hardware can also hide all registers associated with the SoC PCIe port and / or the PCIe root complex.

[0052] The SoC emulation hardware may allow other register access requests that are not associated with PCIe to proceed to the endpoint device. The SoC may also send a Type 0 configuration cycle to the endpoint device to trigger register discovery of non-PCIe register information (406). The SoC may receive a response to the discovery request (408). The SoC emulation hardware may determine whether the response includes PCIe specific information (410). If the response does not include PCIe specific information, the SoC emulation hardware may send the response and accompanying information to the OS (414). If the response does include PCIe specific information, the SoC emulation hardware may modify or discard the PCIe specific information (412) before sending the response to the OS (414).

[0053] Figure 4B 450 is a process flow diagram of an endpoint device supporting device emulation of a root complex integrated endpoint according to an embodiment of the present disclosure. The PCIe endpoint device may receive a register access request message from the OS of a connected host system (452). Emulation hardware on the endpoint device may determine that the register access request includes a request for a PCIe specific register (454). The device emulation hardware may hide the PCIe specific registers from the OS in a manner similar to that described above.

[0054] Figure 5500 is a process flow diagram of root complex hardware emulation logic for hiding PCIe specific messages from an operating system according to an embodiment of the present disclosure. A PCIe endpoint device can send one or more PCIe specific messages to a SoC, some of which can be addressed to the OS. In addition to "hiding" registers, standard PCIe defined messages that devices typically send as part of normal operation or error reporting can also be hidden from the OS / driver. The SoC emulation hardware can receive one or more PCIe specific messages from a PCIe endpoint device across a PCIe-compliant link (502). The SoC emulation hardware can reroute the PCIe message away from the OS (504). The SoC can then process the message (506). For example, the SoC emulation hardware can redirect PCIe specific messages received from an endpoint device internally to a SoC error event collector or a proprietary central error reporting mechanism. If the emulation hardware is partially implemented on an endpoint device, the endpoint device can reroute the PCIe message to an intended SoC destination, such as an interrupt controller, a power management controller, or an error event handler.

[0055] One interconnect fabric architecture includes the Peripheral Component Interconnect (PCI) Express (PCIe) architecture. The primary goal of PCIe is to enable components and devices from different vendors to interoperate in an open architecture across multiple market segments; clients (desktop and mobile), servers (standard and enterprise), and embedded and communications devices. PCIe is a high-performance, general-purpose I / O interconnect protocol defined for a variety of future computing and communications platforms. Some PCI attributes, such as its usage model, load-store architecture, and software interface, have been maintained through its revisions, while the previous parallel bus implementation has been replaced by a highly scalable, fully serial interface. Recent versions of PCI Express take advantage of point-to-point interconnects, switch-based technology, and packet protocols to deliver new levels of performance and features. Power management, quality of service (QoS), hot-plug / hot-swap support, data integrity, and error handling are among some of the advanced features supported by PCI Express.

[0056] See also Figure 6 , shows an embodiment of a structure consisting of point-to-point links interconnecting a set of components. System 600 includes a processor 605 and a system memory 610 coupled to a controller hub 615. Processor 605 includes any processing element, such as a microprocessor, a main processor, an embedded processor, a coprocessor, or other processor. Processor 605 is coupled to controller hub 615 via a front side bus (FSB) 606. In one embodiment, FSB 606 is a serial point-to-point interconnect as described below. In another embodiment, link 606 includes a serial differential interconnect architecture that conforms to different interconnect standards.

[0057] System memory 610 includes any memory device, such as random access memory (RAM), non-volatile (NV) memory, or other memory accessible to devices in system 600. System memory 610 is coupled to controller hub 615 via memory interface 616. Examples of memory interfaces include double data rate (DDR) memory interfaces, dual channel DDR memory interfaces, and dynamic RAM (DRAM) memory interfaces.

[0058] In one embodiment, controller hub 615 is a root hub, root complex, or root controller in a Peripheral Component Interconnect Express (PCIe) interconnect hierarchy. Examples of controller hub 615 include a chipset, a memory controller hub (MCH), a north bridge, an interconnect controller hub (ICH), a south bridge, and a root controller / hub. Typically, the term chipset refers to two physically separate controller hubs, a memory controller hub (MCH) coupled to an interconnect controller hub (ICH). Note that current systems typically include an MCH integrated with processor 605, and controller 615 communicates with I / O devices in a similar manner to that described below. In some embodiments, peer-to-peer routing is optionally supported through root complex 615.

[0059] The root complex 615 may receive data packets from connected devices, such as I / O devices 625. The data packets may include a hint bit set that prompts the root complex to evaluate one or more reserved bits to determine if a hint bit is present in the data packet. The hint bits may provide the root complex with hints or high-level information about how the I / O device 625 tends to use an identified address range or page in memory. The root complex 615 may perform various optimizations on behalf of the processor core, as described above.

[0060] Here, controller hub 615 is coupled to switch / bridge 620 via serial link 619. Input / output modules 617 and 621 (also referred to as interfaces / ports 617 and 621) include / implement a layered protocol stack to provide communication between controller hub 615 and switch 620. In one embodiment, multiple devices can be coupled to switch 620.

[0061] The switch / bridge 620 routes packets / messages from the device 625 upstream (i.e., up the hierarchy toward the root complex (e.g., controller hub 615)) and downstream (i.e., down the hierarchy away from the root controller) from the processor 605 or the system memory 610 to the device 625. In one embodiment, the switch 620 is referred to as a logical assembly of multiple virtual PCI to PCI bridge devices. The device 625 includes any internal or external device or component to be coupled to the electronic system, such as an I / O device, a network interface controller (NIC), an add-in card, an audio processor, a network processor, a hard disk driver, a storage device, a CD / DVD ROM, a monitor, a printer, a mouse, a keyboard, a router, a portable storage device, a Firewire device, a Universal Serial Bus (USB) device, a scanner, and other input / output devices. Typically in PCIe terminology, a device, for example, is referred to as an endpoint. Although not specifically shown, the device 625 may include a PCIe to PCI / PCI-X bridge to support legacy or other versions of PCI devices. Endpoint devices in PCIe are generally classified as legacy, PCIe, or root complex integrated endpoints. Device 625 may be coupled to switch 620 via serial link 623 .

[0062] Graphics accelerator 630 is also coupled to controller hub 615 via serial link 632. In one embodiment, graphics accelerator 630 is coupled to MCH, which is coupled to ICH. Switch 620, and accordingly I / O device 625, is then coupled to ICH. I / O modules 631 and 618 are also used to implement a layered protocol stack to communicate between graphics accelerator 630 and controller hub 615. Similar to the MCH discussion above, the graphics controller or graphics accelerator 630 itself can be integrated into processor 605.

[0063] Go to Figure 7 , showing an embodiment of a layered protocol stack. The layered protocol stack 700 includes any form of layered communication stack, such as a Quick Path Interconnect (QPI) stack, a PCIe stack, a next generation high performance computing interconnect stack, or other layered stack. Although the following reference Figure 6-12 The discussion is related to the PCIe stack, but the same concepts can be applied to other interconnect stacks. In one embodiment, the protocol stack 700 is a PCIe protocol stack, including a transaction layer 705, a link layer 710, and a physical layer 720. Figure 6 The interfaces 617, 618, 621, 622, 626, and 631 in the embodiment may be represented as a communication protocol stack 700. The representation as a communication protocol stack may also be referred to as a module or interface that implements / includes the protocol stack.

[0064] PCI Express uses packets to transfer information between components. Packets are formed in the transaction layer 705 and the data link layer 710 to carry information from the sending component to the receiving component. As the transmitted packets flow through the other layers, they are extended with additional information necessary to process the packets at those layers. On the receiving side, the reverse process occurs, and the packet is transformed from its physical layer 720 representation to the data link layer 710 representation, and finally (for transaction layer packets) to a form that can be processed by the transaction layer 705 of the receiving device.

[0065] Transaction Layer

[0066] In one embodiment, the transaction layer 705 is used to provide an interface between the processing core of the device and the interconnect architecture (e.g., the data link layer 710 and the physical layer 720). In this regard, the primary responsibility of the transaction layer 705 is the assembly and disassembly of packets (i.e., transaction layer packets or TLPs). The translation layer 705 typically manages the credit-based flow control of the TLPs. PCIe implements split transactions, i.e., transactions with requests and responses separated by time, allowing the link to carry other traffic while the target device collects data for the response.

[0067] In addition, PCIe also utilizes credit-based flow control. In this scheme, the device advertises an initial amount of credit for each receive buffer in the transaction layer 705. The external device at the opposite end of the link, such as Figure 1 The controller hub 115 in the embodiment of the present invention calculates the number of credits consumed by each TLP. If the transaction does not exceed the credit limit, the transaction can be sent. After receiving the response, a certain number of credits are restored. An advantage of the credit scheme is that if the credit limit is not reached, the delay in the return of credits does not affect performance.

[0068] In one embodiment, the four transaction address spaces include a configuration address space, a memory address space, an input / output address space, and a message address space. A memory space transaction includes one or more read requests and write requests to transfer data to or from a memory mapped location. In one embodiment, a memory space transaction can use two different address formats, such as a short address format, such as a 32-bit address, or a long address format, such as a 64-bit address. Configuration space transactions are used to access the configuration space of a PCIe device. Transactions to the configuration space include read requests and write requests. Message space transactions (or simply messages) are defined to support in-band communication between PCIe agents.

[0069] Thus, in one embodiment, transaction layer 705 assembles packet header / payload 706. The current packet header / payload format can be found in the PCIe specification at the PCIe specification website.

[0070] Quick Reference Figure 8 , shows an embodiment of a PCIe transaction descriptor. In one embodiment, a transaction descriptor 800 is a mechanism for carrying transaction information. In this regard, the transaction descriptor 800 supports the identification of transactions in the system. Other potential uses include tracking modifications to default transaction ordering and association of transactions with channels.

[0071] Transaction descriptor 800 includes a global identifier field 802, an attribute field 1004, and a channel identifier field 806. In the illustrated example, global identifier field 802 is depicted as including a local transaction identifier field 808 and a source identifier field 810. In one embodiment, global transaction identifier 802 is unique for all outstanding requests.

[0072] According to one implementation, the local transaction identifier field 808 is a field generated by the requesting agent and is unique to all outstanding requests that need to be completed by the requesting agent. In addition, in this example, the source identifier 810 uniquely identifies the requester agent within the PCIe hierarchy. Therefore, together with the source ID 810, the local transaction identifier 808 field provides a global identification of a transaction within the hierarchy domain.

[0073] Attribute field 804 specifies the characteristics and relationships of the transaction. In this regard, attribute field 804 may be used to provide additional information that allows the default processing of the transaction to be modified. In one embodiment, attribute field 804 includes priority field 812, reserved field 814, sort field 816, and non-snooping field 818. Here, priority subfield 812 can be modified by the initiator to assign a priority to the transaction. Reserved attribute field 814 is reserved for future or vendor-defined use. Reserved attribute fields can be used to implement possible usage models that use priority or security attributes.

[0074] In this example, the sort attribute field 816 is used to provide optional information that conveys the type of sorting that can modify the default sorting rules. According to an example implementation, a sort attribute of "0" indicates that the default sorting rules are to be applied, wherein a sort attribute of "1" indicates that the sorting is relaxed, wherein writes can pass writes in the same direction, and read completions can pass writes in the same direction. The snoop attribute field 818 is used to determine whether the transaction is snooped. As shown, the channel ID field 806 identifies the channel associated with the transaction.

[0075] Link Layer

[0076] return Figure 7, the link layer 710 (also referred to as the data link layer 710) acts as an intermediate level between the transaction layer 705 and the physical layer 720. In one embodiment, the responsibility of the data link layer 710 is to provide a reliable mechanism for exchanging transaction layer packets (TLPs) between the two components of the link. One side of the data link layer 710 accepts the TLPs assembled by the transaction layer 705, applies a packet sequence identifier 710, i.e., an identification number or packet number, calculates and applies an error detection code, i.e., CRC 712, and submits the modified TLP to the physical layer 720 for transmission across the physical to an external device.

[0077] Physical Layer

[0078] In one embodiment, the physical layer 720 includes a logical sub-block 721 and an electronic block 722 to physically send packets to an external device. Here, the logical sub-block 721 is responsible for the "digital" functions of the physical layer 721. In this regard, the logical sub-block includes a transmit portion for preparing outgoing information for transmission by the physical sub-block 722, and a receiver portion for identifying and preparing received information before passing it to the link layer 1110.

[0079] Physical block 722 includes a transmitter and a receiver. The transmitter is provided with symbols by logic sub-block 721, and the transmitter serializes the symbols and sends them to an external device. The receiver is provided with serial symbols from an external device and converts the received signal into a bit stream. The bit stream is deserialized and provided to logic sub-block 721. In one embodiment, 8b / 10b transmission code is adopted, in which 10-bit symbols are sent / received. Here, special symbols are used to frame packets using frame 723. In addition, in one example, the receiver also provides a symbol clock recovered from the incoming serial stream.

[0080] As described above, although the transaction layer 705, link layer 710, and physical layer 1020 are discussed with reference to a specific embodiment of the PCIe protocol stack, the layered protocol stack is not limited thereto. In fact, any layered protocol may be included / implemented. As an example, a port / interface represented as a layered protocol includes: (1) a first layer for assembling packets, i.e., a transaction layer; a second layer for sequencing packets, i.e., a link layer; and a third layer for sending packets, i.e., a physical layer. As a specific example, a common standard interface (CSI) layered protocol is used.

[0081] Next reference Fig. 9, an embodiment of a PCIe serial point-to-point structure is shown. Although an embodiment of a PCIe serial point-to-point link is shown, the serial point-to-point link is not limited thereto because it includes any transmission path for sending serial data. In the illustrated embodiment, the basic PCIe link includes two low-voltage differential drive signal pairs: a transmit pair 906 / 911 and a receive pair 912 / 907. Therefore, device 905 includes a transmit logic 906 for sending data to device 910 and a receive logic 907 for receiving data from device 910. In other words, two transmission paths, namely paths 916 and 917, and two receive paths, namely paths 918 and 919, are included in the PCIe link.

[0082] A transmission path refers to any path for transmitting data, such as a transmission line, copper wire, optical fiber, a wireless communication channel, an infrared communication link, or other communication path. A connection between two devices (e.g., device 905 and device 910) is called a link, such as link 915. A link can support a channel - each channel represents a set of differential signal pairs (one pair for transmission and one pair for reception). To expand bandwidth, a link can aggregate multiple channels represented by xN, where N is any supported link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider.

[0083] A differential pair refers to two transmission paths, such as lines 916 and 917, to transmit differential signals. As an example, when line 916 switches from a low voltage level to a high voltage level, i.e., a rising edge, line 917 drives from a high logic level to a low logic level, i.e., a falling edge. Differential signals potentially exhibit better electrical characteristics, such as better signal integrity, i.e., cross-coupling, voltage overshoot / undershoot, oscillation, etc. This allows for better timing windows, which makes faster transmission frequencies possible.

[0084] Note that the above apparatus, methods, and systems can be implemented in any electronic device or system as described above. As a specific illustration, the following figure provides an exemplary system for utilizing the present invention as described herein. As the following system is described in more detail, many different interconnections are disclosed, described, and reviewed again from the above discussion. And it is apparent that the above advances can be applied to any of those interconnections, structures, or architectures.

[0085] Reference now Fig.10 , shows a block diagram of an embodiment of a multi-core processor. Fig.10 As shown in the embodiment of , the processor 1000 includes multiple domains. Specifically, the core domain 1030 includes multiple cores 1030A-1030N, the graphics domain 1060 includes one or more graphics engines with a media engine 1065, and the system agent domain 1010.

[0086] In various embodiments, system agent domain 1010 handles power control events and power management so that the various units (e.g., cores and / or graphics engines) of domains 1030 and 1060 can be independently controlled to dynamically operate in an appropriate power mode / level (e.g., active, turbo, sleep, hibernate, deep sleep or other advanced configuration power interface, such as state) based on the activity (or inactivity) occurring in a given unit. Each of domains 1030 and 1060 can operate at different voltages and / or powers, and further, the various units within a domain may each operate at independent frequencies and voltages. Note that while only three domains are shown, it should be understood that the scope of the present invention is not limited in this regard and that other domains may be present in other embodiments.

[0087] As shown, in addition to the various execution units and additional processing elements, each core 1030 also includes a low-level cache. Here, the various cores are coupled to each other and to a shared cache memory formed by multiple cells or slices of last level cache (LLC) 1040A-1040N; these LLCs typically include storage and cache controller functions and are shared between the cores and possibly between the graphics engines.

[0088] As shown, a ring interconnect 1050 couples the cores together and provides interconnection between the core domain 1030, the graphics domain 1060, and the system agent circuitry 1010 via a plurality of ring stops 1052A-1052N, each at a coupling between a core and an LLC slice. Fig.10 As shown, interconnect 1050 is used to carry various information, including address information, data information, confirmation information, and snoop / invalidation information. Although a ring interconnect is shown, any known on-die interconnect or structure can be used. As an illustrative example, some of the structures discussed above (e.g., another on-die interconnect, Intel on-chip system structure (IOSF), advanced microcontroller bus architecture (AMBA) interconnect, multi-dimensional mesh structure or other known interconnect architectures) can be utilized in a similar manner.

[0089] As further depicted, the system agent domain 1010 includes a display engine 1012 for providing control and interface to an associated display. The system agent domain 1010 may include other units, such as: an integrated memory controller 1020 that provides an interface to system memory (e.g., DRAM implemented with multiple DIMMs; consistency logic 1022 for performing memory consistency operations. There may be multiple interfaces to enable interconnection between the processor and other circuits. For example, in one embodiment, at least one direct media interface (DMI) 1016 interface and one or more PCIe TMInterface 1014. The display engine and these interfaces are usually connected via PCIe TM The bridge 1018 is coupled to the memory. In addition, to provide communication between other agents, such as additional processors or other circuits, one or more other interfaces (e.g., QuickPath Interconnect (QPI) fabric).

[0090] Next go to Fig.11 , depicting an embodiment of a system on chip (SOC) design according to the present invention. As a specific illustrative example, the SOC 1100 is included in a user equipment (UE). In one embodiment, UE refers to any device that an end user wants to use to communicate, such as a handheld phone, a smart phone, a tablet, an ultra-thin notebook, a notebook with a broadband adapter, or any other similar communication device. The UE is typically connected to a base station or node, which may essentially correspond to a mobile station (MS) in a GSM network.

[0091] Here, SOC 1100 includes two cores - 1106 and 1107. Similar to the above discussion, cores 1106 and 1107 may conform to an instruction set architecture, such as based on Architecture Core TM , Advanced Micro Devices, Inc. (AMD) processors, MIPS-based processors, ARM-based processor designs, or their customers, and their licensees or adopters. Cores 1106 and 1107 are coupled to cache control 1108, which is associated with bus interface unit 1109 and L2 cache 1110 to communicate with other parts of system 1100. Interconnect 1110 includes an on-chip interconnect, such as IOSF, AMBA, or other interconnects as described above, which potentially implements one or more aspects of the described invention.

[0092] The interface 1110 provides a communication channel to other components, such as a subscriber identification module (SIM) 1130 for interfacing with a SIM card, a boot ROM 1135 for holding boot code to be executed by the cores 1106 and 1107 to initialize and boot the SOC 1100, an SDRAM controller 1140 for interfacing with external memory (e.g., DRAM 1160), a flash controller 1145 for interfacing with non-volatile memory (e.g., flash memory 1165), a peripheral control 1150 (e.g., a serial peripheral interface) for interfacing with peripheral devices, a video codec 1120 and a video interface 1125 for displaying and receiving input (e.g., touch-enabled input), a GPU 1115 for performing graphics-related calculations, etc. Any of these interfaces may include aspects of the invention described herein.

[0093] In addition, the system shows peripheral devices for communication, such as Bluetooth module 1170, 3G modem 1175, GPS 1185 and WiFi 1185. Note that, as mentioned above, the UE includes a radio for communication. As a result, these peripheral communication modules are not all required. However, in the UE, some form of radio for external communication will be included.

[0094] Reference now Fig.12 , which is a block diagram of a second system 1200 according to an embodiment of the present invention. Fig.12 As shown, multiprocessor system 1200 is a point-to-point interconnect system and includes a first processor 1270 and a second processor 1280 coupled via a point-to-point interconnect 1250. Each of processors 1270 and 1280 can be a certain version of a processor. In one embodiment, 1252 and 1254 are part of a serial point-to-point coherent interconnect structure, such as Intel's Quick Path Interconnect (QPI) architecture. As a result, the present invention can be implemented within the QPI architecture.

[0095] Although shown with only two processors 1270, 1280, it should be understood that the scope of the present invention is not limited in this regard. In other embodiments, one or more additional processors may be present in a given processor.

[0096] The processors 1270 and 1280 are shown to include integrated memory controller units 1272 and 1282, respectively. The processor 1270 also includes point-to-point (PP) interfaces 1276 and 1278 as part of its bus controller unit; similarly, the second processor 1280 includes PP interfaces 1286 and 1288. The processors 1270, 1280 can exchange information via the point-to-point (PP) interface 1250 using PP interface circuits 1278, 1288. Fig.12 As shown, IMCs 1272 and 1282 couple the processors to respective memories, namely, memory 1232 and memory 1234, which may be portions of main memory locally connected to the respective processors.

[0097] Processors 1270, 1280 each exchange information with chipset 1290 via respective PP interfaces 1252, 1254 using point-to-point interface circuits 1276, 1294, 1286, 1298. Chipset 1290 also exchanges information with high-performance graphics circuit 1238 along high-performance graphics interconnect 1239 via interface circuit 1292.

[0098] A shared cache (not shown) may be included in the processor or external to both processors; then connected to the processors via the PP interconnect so that if the processors are placed in a low power mode, local cache information of either or both processors may be stored in the shared cache.

[0099] Chipset 1290 may be coupled to first bus 1216 via interface 1296. In one embodiment, first bus 1216 may be a peripheral component interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I / O interconnect bus, but the scope of the present invention is not limited in this regard.

[0100] like Fig.12 As shown, various I / O devices 1214 are coupled to first bus 1216, and a bus bridge 1218 that couples first bus 1216 to a second bus 1220. In one embodiment, second bus 1220 comprises a low pin count (LPC) bus. In one embodiment, various devices are coupled to second bus 1220 including, for example, a keyboard and / or mouse 1222, communication devices 1227, and a storage unit 1228, such as a disk drive or other mass storage device, which generally includes instructions / code and data 1230. Additionally, an audio I / O 1224 is shown coupled to second bus 1220. Note that other architectures are possible in which the included components and interconnect architectures vary. For example, instead of Fig.12 Instead of a point-to-point architecture, the system may implement a multi-drop bus or other such architecture.

[0101] While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations that fall within the true spirit and scope of the present invention.

[0102] The design may go through various stages, from creation to simulation to manufacturing. Data representing the design may represent the design in a variety of ways. First, as useful in simulation, the hardware may be represented using a hardware description language or another functional description language. In addition, a circuit-level model with logic and / or transistor gates may be produced at a certain stage of the design process. In addition, most designs at a certain stage reach the level of data representing the physical arrangement of each device in the hardware model. In the case of using conventional semiconductor manufacturing technology, the data representing the hardware model may be data specifying the presence or absence of each feature on different mask layers of a mask for producing an integrated circuit. In any representation of the design, the data may be stored in any form of a machine-readable medium. A memory or magnetic or optical storage device, such as an optical disc, may be a machine-readable medium that stores information transmitted via light or radio waves modulated or otherwise generated to transmit the information. When an electrical carrier indicating or carrying a code or design is transmitted, a new copy is made within the scope of copying, buffering, or retransmission of the electrical signal being performed. Therefore, a communication provider or a network provider may store, at least temporarily, an object of a technology that specifically implements an embodiment of the present invention, such as information encoded into a carrier, on a tangible machine-readable medium.

[0103] As used herein, a module refers to any combination of hardware, software, and / or firmware. As an example, a module includes hardware, such as a microcontroller, which is associated with a non-transitory medium to store code suitable for execution by the microcontroller. Therefore, in one embodiment, a reference to a module refers to hardware specifically configured to identify and / or execute code stored in a non-transitory medium. In addition, in another embodiment, the use of a module refers to a non-transitory medium including code specifically suitable for execution by a microcontroller to implement a predetermined operation. And, it can be deduced that in other embodiments, the term module (in this example) may refer to a combination of a microcontroller and a non-transitory medium. Often, the module boundaries separated in the diagram are usually variable and may overlap. For example, a first module and a second module may share hardware, software, firmware, or a combination thereof, while possibly maintaining some independent hardware, software, or firmware. In one embodiment, the use of the term logic includes hardware, such as transistors, registers, or other hardware, such as programmable logic devices.

[0104] In one embodiment, the use of the phrase 'for' or 'configured for' refers to a device, hardware, logic or element that is arranged, put together, manufactured, offered for sale, imported and / or designed to perform a specified or determined task. In this example, a non-operating device or element thereof, if designed, coupled and / or interconnected to perform the specified task, is still 'configured for' to perform the specified task. As a purely illustrative example, a logic gate can provide 0 or 1 during operation. However, a logic gate that is 'configured for' to provide a clock enable signal does not include every possible logic gate that can provide 1 or 0. Instead, a logic gate is a logic gate coupled in a way that a 1 or 0 output enables the clock during operation. Note again that the use of the term 'configured for' does not require operation, but focuses on the potential state of the device, hardware and / or element, where the device, hardware and / or element is designed to perform a specific task when the device, hardware and / or element is operated in the potential state.

[0105] Additionally, in one embodiment, the use of the phrases "capable of..." and / or "operable to..." refers to a device, logic, hardware, and / or element designed in a manner that enables the use of a device, logic, hardware, and / or element in a specified manner. As mentioned above, the use of to, capable of, or operable in one embodiment refers to a potential state of a device, logic, hardware, and / or element, wherein the device, logic, hardware, and / or element is not operating, but is designed in a manner that enables the use of the device in a specified manner.

[0106] As used herein, value includes any known representation of a number, state, logic state or binary logic state. Often, the use of logic level, logic value or logic value is also referred to as 1 and 0, which simply represents a binary logic state. For example, 1 refers to a high logic level, and 0 refers to a low logic level. In one embodiment, a storage unit, such as a transistor or a flash memory cell, may be able to store a single logic value or multiple logic values. However, other representations of values ​​in a computer system have been used. For example, the decimal number ten can also be represented as a binary value 1010 and a hexadecimal letter A. Therefore, value includes any representation of information that can be stored in a computer system.

[0107] Moreover, a state may be represented by a value or a portion of a value. As an example, a first value such as a logical one may represent a default or initial state, while a second value such as a logical zero may represent a non-default state. Additionally, in one embodiment, the terms reset and set refer to a default value or state and an updated value or state, respectively. For example, a default value may include a high logic value, i.e., reset, while an updated value may include a low logic value, i.e., set. Note that any combination of values ​​may be used to represent any number of states.

[0108] Embodiments of the methods, hardware, software, firmware or code described above may be implemented via instructions or code that can be executed by a processing element and stored on a machine-accessible, machine-readable, computer-accessible or computer-readable medium. Non-transitory machine-accessible / readable media include any mechanism that provides (i.e., stores and / or transmits) information in a form that can be read by a machine such as a computer or electronic system. For example, non-transitory machine-accessible media include random access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; magnetic or optical storage media; flash memory devices; electrical storage devices; optical storage devices; acoustic storage devices; other forms of storage devices for storing information received from transient (propagating) signals (e.g., carrier waves, infrared signals, digital signals); etc., which should be distinguished from non-transitory media from which information can be received.

[0109] Instructions for programming logic to perform embodiments of the present invention can be stored in a memory in the system, such as a DRAM, cache, flash memory or other storage device. In addition, instructions can be distributed via a network or by other computer-readable media. Therefore, a machine-readable medium may include any mechanism for storing or sending information in a form that a machine (e.g., a computer) can read, but is not limited to a floppy disk, an optical disk, a compressed disk, a read-only memory (CD-ROM) and a magneto-optical disk, a read-only memory (ROM), a random access memory (RAM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic card or an optical card, a flash memory, or a tangible, machine-readable storage device for sending information on the Internet via electrical, optical, acoustic or other forms of propagation signals (e.g., carrier waves, infrared signals, digital signals, etc.). Therefore, a computer-readable medium includes any type of tangible machine-readable medium suitable for storing or sending electronic instructions or information in a form that can be read by a machine (e.g., a computer).

[0110] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0111] In the foregoing description, detailed descriptions have been given with reference to specific exemplary embodiments. However, it will be apparent that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure as set forth in the appended claims. The description and drawings are therefore to be considered in an illustrative rather than a restrictive sense. Furthermore, the foregoing use of embodiments and other exemplary language does not necessarily all refer to the same embodiment or the same example, but may refer to different and unique embodiments as well as possibly the same embodiment.

[0112] The following paragraphs provide examples of the various embodiments disclosed herein.

[0113] Example 1 is an apparatus implemented at least in part in hardware, the apparatus comprising hardware logic for: receiving a request to access one or more registers of a hardware device; determining that the request comprises a request to access one or more Peripheral Component Interconnect Express (PCIe) specific registers; and responding to the request without providing information associated with the one or more PCIe specific registers. The apparatus comprises system-on-chip emulation hardware or device emulation hardware.

[0114] Example 2 may include the subject matter of Example 1, further comprising logic for: determining that the request comprises a read request to read one or more PCIe registers; and wherein the logic responds to the read request by sending a bit string without a PCIe specific value.

[0115] Example 3 may include the subject matter of any of Examples 1 or 2, further comprising logic to: determine that the request comprises a write request to write to one or more PCIe registers; and wherein the logic discards the write request.

[0116] Example 4 may include the subject matter of any of Examples 1-3, further comprising logic for: receiving a response message from an endpoint device in response to the request; determining that the response message includes PCIe specific information; and modifying or discarding the PCIe specific information before sending the response message.

[0117] Example 5 may include the subject matter of any of Examples 1-4, further comprising logic to: receive a PCIe specific message from an endpoint device; and reroute the PCIe specific message to an event handler.

[0118] Example 6 may include the subject matter of Example 5, wherein the PCIe specific message includes a PCIe error message, and wherein the logic is to forward the PCIe error message to a PCIe error handler.

[0119] Example 7 may include the subject matter of any of Examples 1-6, further comprising logic for: determining that the request message includes a request to access a PCIe specific register of an endpoint device and a request to access a non-PCIe specific register of the endpoint device; sending the request to access the non-PCIe specific register to the endpoint device; and hiding the request to access the PCIe specific register.

[0120] Example 8 may include the subject matter of any of Examples 1-7, wherein the device resides upstream of a PCIe-compliant root complex.

[0121] Example 9 may include the subject matter of any of Examples 1-8, wherein the apparatus resides on a PCIe-compliant endpoint device.

[0122] Example 10 may include the subject matter of any of Examples 1-7, wherein the PCIe specific register is a register associated with one or more of a PCIe compliant root complex, a PCIe compliant root complex controller, or a PCIe port.

[0123] Example 11 is a method performed by a simulated hardware element, the method comprising: receiving a request to access one or more registers of a hardware device; determining that the request comprises a request to access one or more Peripheral Component Interconnect Express (PCIe) specific registers; and responding to the request without providing information associated with the one or more PCIe specific registers.

[0124] Example 12 may include the subject matter of Example 11, further comprising: determining that the request comprises a read request to read one or more PCIe registers; and sending the bit string without the register specific value.

[0125] Example 13 may include the subject matter of any of Examples 11-12, further comprising: determining that the request comprises a write request to write to one or more PCIe registers; and discarding the write request.

[0126] Example 14 may include the subject matter of any of Examples 11-13, and may further include: receiving a response message from an endpoint device in response to the request; determining that the response message includes PCIe specific information; and modifying or discarding the PCIe specific information before sending the response message.

[0127] Example 15 may include the subject matter of any of Examples 11-14, further comprising: receiving a PCIe specific message from an endpoint device; and rerouting the PCIe specific message to an event handler.

[0128] Example 16 may include the subject matter of Example 15, wherein the PCIe specific message includes a PCIe error message, and the method further comprises forwarding the PCIe error message to a PCIe error handler.

[0129] Example 17 may include the subject matter of any of Examples 11-16, further comprising: determining that the request message includes a request to access a PCIe specific register of an endpoint device and a request to access a non-PCIe specific register of the endpoint device; sending the request to access the non-PCIe specific register to the endpoint device; and hiding the request to access the PCIe specific register.

[0130] Example 18 may include the subject matter of any of Examples 11-17, wherein the PCIe specific register is a register associated with one or more of a PCIe compliant root complex, a PCIe compliant root complex controller, or a PCIe port.

[0131] Example 19 is a host system comprising: a processor running an operating system; a root complex compliant with Peripheral Component Interconnect Express (PCIe), the PCIe compliant root complex; and emulation hardware. The emulation hardware includes logic for: receiving a register access request from the operating system; determining one or more PCIe specific registers in the request message; and hiding the PCIe specific registers from the operating system.

[0132] Example 20 may include the subject matter of Example 19, further comprising a PCIe compliant port, the emulation hardware comprising logic to hide PCIe specific registers associated with the PCIe compliant port from the operating system.

[0133] Example 21 may include the subject matter of any of Examples 19-20, further comprising a PCIe-compliant endpoint device, wherein the emulation hardware is used to hide PCIe-specific registers associated with the PCIe-compliant endpoint device from the operating system.

[0134] Example 22 may include the subject matter of any of Examples 19-21, wherein the emulation hardware comprises logic to hide PCIe specific registers based on a type of register access identified from the register access request.

[0135] Example 23 may include the subject matter of Example 22, wherein the emulation hardware includes logic for discarding write requests to PCIe specific registers received from the operating system and providing null data in response to read requests to PCIe specific registers received from the operating system.

[0136] Example 24 may include the subject matter of example claim 22, wherein the emulation hardware includes logic for modifying PCIe specific register information received in response to a register access request by creating modified register information that does not conform to the PCIe protocol, and sending the modified register information to the operating system.

[0137] Example 25 may include the subject matter of any of Examples 19-24, further including a PCIe-compliant event handler implemented at least in part in hardware, and wherein: the emulated hardware includes logic for: receiving one or more PCIe-specific messages from a PCIe-compliant connected device; and rerouting the one or more PCIe-specific messages to the PCIe-compliant event handler.

Claims

1. An apparatus implemented at least in part in hardware, the apparatus comprising hardware logic for: receiving a request message for accessing one or more registers of a hardware device; determining that the request message includes a request to access one or more Peripheral Component Interconnect Express (PCIe) specific registers, the specific registers including at least one of: a PCIe capability register, a PCI Express extended capability register, a device / port type register, a link-related register, a link power management-related register, and a multi-function virtual channel capability register; as well as Responding to the request message without providing information associated with the one or more PCIe specific registers includes at least one of the following: determining that the request message comprises a read request to read one or more PCIe registers; and responding to the read request by sending a bit string without a PCIe specific register value; determining that the request message includes a write request to write one or more PCIe specific registers; discarding the write request; receiving a response message from an endpoint device in response to the request message; Determining that the response message includes PCIe specific information; and modifying or discarding the PCIe specific information before sending the response message; Receive PCIe specific messages from endpoint devices; and rerouting the PCIe specific message to an event handler; Determining that the request message includes a request to access a PCIe specific register of an endpoint device and a request to access a non-PCIe specific register of the endpoint device; Sending the request message for accessing the non-PCIe specific register to the endpoint device; As well as hiding the PCIe specific registers.

2. The device according to claim 1, wherein: The PCIe specific message includes a PCIe error message, and the logic is to forward the PCIe error message to a PCIe error handler.

3. The device according to claim 1 or 2, wherein: The device resides upstream of a PCIe compliant root complex.

4. The device according to claim 1 or 2, wherein: The means resides on a PCIe compliant endpoint device.

5. The device according to claim 1 or 2, wherein: The PCIe specific registers are registers associated with one or more of a PCIe compliant root complex, a PCIe compliant root complex controller, or a PCIe port.

6. A method performed by a simulated hardware element, the method comprising: receiving a request message for accessing one or more registers of a hardware device; determining that the request message includes a request to access one or more Peripheral Component Interconnect Express (PCIe) specific registers, the specific registers including at least one of: a PCIe capability register, a PCI Express extended capability register, a device / port type register, a link-related register, a link power management-related register, and a multi-function virtual channel capability register; as well as Responding to the request message without providing information associated with the one or more PCIe specific registers includes at least one of the following: determining that the request message comprises a read request to read one or more PCIe registers; and sending a bit string without a register specific value; determining that the request message includes a write request to write one or more PCIe registers; and discarding the write request; receiving a response message from an endpoint device in response to the request message; Determining that the response message includes PCIe specific information; and modifying or discarding the PCIe specific information before sending the response message; Receive PCIe specific messages from endpoint devices; and rerouting the PCIe specific message to an event handler; Determining that the request message includes a request to access a PCIe specific register of an endpoint device and a request to access a non-PCIe specific register of the endpoint device; Sending the request message for accessing the non-PCIe specific register to the endpoint device; And abandon sending the request to access the PCIe specific register.

7. The method of claim 6, wherein: The PCIe specific message includes a PCIe error message, and the method further includes forwarding the PCIe error message to a PCIe error handler.

8. The method of claim 6 or 7, further comprising generating a type 0 configuration register access message, the type 0 configuration being configured for a small form factor endpoint device; and forwarding the type 0 configuration register to the small form factor endpoint device across a PCIe compliant link.

9. A host system, comprising: A processor that runs the operating system; a Peripheral Component Interconnect Express (PCIe) compliant root complex, the PCIe compliant root complex; as well as Emulate hardware, including logic, for: receiving a register access request message from the operating system; Determine one or more PCIe specific registers in the request message, the specific registers comprising at least one of the following: a PCIe capability register, a PCI Express extended capability register, a device / port type register, a link-related register, a link power management-related register, and a multi-function virtual channel capability register; as well as Hiding the PCIe specific registers from the operating system includes responding to the request message without providing information associated with the one or more PCIe specific registers, including at least one of the following: hiding PCIe specific registers associated with a PCIe compliant port from the operating system; hiding PCIe specific registers associated with a PCIe compliant endpoint device from the operating system; hiding PCIe specific registers based on a type of register access identified from the register access request message; receiving one or more PCIe specific messages from a PCIe compliant connected device; and rerouting the one or more PCIe specific messages to a PCIe compliant event handler implemented at least in part in hardware.

10. The host system of claim 9, wherein: The emulation hardware includes logic to discard write requests to PCIe specific registers received from the operating system and to provide null data in response to read requests to PCIe specific registers received from the operating system.

11. The host system of claim 9, wherein: The emulation hardware includes logic to modify PCIe specific register information received in response to a register access request message by creating modified register information that does not conform to the PCIe protocol, and to send the modified register information to the operating system.

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