Printed circuit board, semiconductor package and manufacturing method

Abstract

The present application provides a semiconductor package and a printed circuit board. The semiconductor package may include: a substrate and a semiconductor chip on the substrate. A first molded portion may cover the semiconductor chip and may include a first sidewall and a second sidewall opposite to each other. A second molded portion may extend on the substrate along the first sidewall and along the second sidewall, wherein the first molded portion may include a non-conductive material and the second molded portion may include a conductive material.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2017-0138134 filed on October 24, 2017, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a printed circuit board (PCB), a semiconductor package, and a method of manufacturing the semiconductor package. Background Art

[0004] As mobile devices (eg, smartphones) become smaller, lighter, and higher performance, semiconductor packages may become thinner and more highly integrated. Therefore, there is an increasing demand for thin substrates.

[0005] However, thin substrates can lead to process defects. For example, due to reduced stiffness, thin substrates can bend or crack during the process of manufacturing semiconductor packages. Jigs or fixtures can be used to compensate for the reduction in substrate stiffness. However, this approach can introduce new equipment and processes.

[0006] Furthermore, as semiconductor packages become thinner and more highly integrated, electromagnetic interference (EMI) may increase. Summary of the invention

[0007] In some embodiments, a semiconductor package may include a substrate and a semiconductor chip on the substrate. A first molding portion may cover the semiconductor chip and may include a first sidewall and a second sidewall opposite to each other. A second molding portion may extend on the substrate along the first sidewall and along the second sidewall, wherein the first molding portion may include a non-conductive material and the second molding portion may include a conductive material.

[0008] In some embodiments, a semiconductor package may include a substrate and a semiconductor chip on the substrate. A first molding portion may be on the substrate and may cover the semiconductor chip. A second molding portion may be on the substrate and may extend along a sidewall of the first molding portion. A third molding portion may cover an uppermost surface of the first molding portion and an uppermost surface of the second molding portion, wherein the second molding portion and the third molding portion may include a conductive epoxy molding compound.

[0009] In some embodiments, a printed circuit board (PCB) may include a substrate including a first mounting area and a second mounting area adjacent to each other along a first direction, wherein the first mounting area and the second mounting area are configured to mount an integrated circuit thereon. A molding structure may be on the substrate and may include a conductive material, wherein the molding structure may include a peripheral portion and a first strip, the peripheral portion extending along an edge of the substrate, the first strip separating the first mounting area and the second mounting area. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] These and / or other aspects will become apparent and more easily understood from the following description of embodiments in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a schematic top view of a PCB according to an embodiment;

[0012] Figure 2 It is along Figure 1 A schematic cross-sectional view taken along line AA';

[0013] Figure 3 It is along Figure 1 A schematic cross-sectional view taken along line BB';

[0014] Figure 4 is a schematic top view of a PCB according to an embodiment;

[0015] Figure 5 It is along Figure 4 A schematic cross-sectional view taken along line CC';

[0016] Figure 6 It is along Figure 4 A schematic cross-sectional view taken along line D-D';

[0017] 7A to 7C is a schematic top view of a semiconductor package according to an embodiment;

[0018] Figure 8 It is along Fig. 7A A schematic cross-sectional view taken along line EE';

[0019] Fig. 9 is a schematic top view of a semiconductor package according to an embodiment;

[0020] Fig.10 It is along Fig. 9 A schematic cross-sectional view taken along line F-F';

[0021] Fig.11 is a schematic top view of a semiconductor package according to an embodiment;

[0022] Fig.12 It is along Fig.11 A schematic cross-sectional view taken along line G-G';

[0023] Fig.13 is a schematic top view of a semiconductor package according to an embodiment; and

[0024] Figures 14 to 25 is a diagram illustrating a method of manufacturing a semiconductor package according to an embodiment. DETAILED DESCRIPTION

[0025] Now refer to Figures 1 to 6 A printed circuit board (PCB) according to an embodiment is described.

[0026] Figure 1 is a schematic top view of a PCB according to an embodiment. Figure 2 It is along Figure 1 Schematic cross-sectional view taken along line AA'. Figure 3 It is along Figure 1 Schematic cross-sectional view taken along line BB'.

[0027] refer to Figures 1 to 3 , the PCB according to the embodiment includes a substrate 100 and a molding structure 220S.

[0028] The substrate 100 may be a substrate of a package. For example, the substrate 100 may be a thin PCB. The thickness of the substrate 100 may be, for example, 0.17 mm or less. The substrate 100 may be a single layer or a multilayer.

[0029] The substrate 100 may include a plurality of mounting areas 120. Figure 1 In the embodiment, the mounting areas 120 are arranged in a checkerboard pattern. However, the present disclosure is not limited thereto.

[0030] Each of the mounting regions 120 may be a semiconductor chip 300 (see FIG. Figure 8 ). For example, each of the mounting regions 120 may include a circuit pattern. The circuit pattern of each of the mounting regions 120 may be configured to be electrically connected to the semiconductor chip 300.

[0031] The mounting area 120 may include a first mounting area 121 , a second mounting area 122 , and a third mounting area 123 adjacent to each other.

[0032] For example, Figure 1 As shown, the first mounting area 121 and the second mounting area 122 may be disposed adjacent to each other along the first direction X. However, the first mounting area 121 and the second mounting area 122 may be electrically isolated from each other.

[0033] In addition, for example, Figure 1 As shown, the first mounting area 121 and the third mounting area 123 may be disposed adjacent to each other along a second direction Y intersecting the first direction X. However, the first mounting area 121 and the third mounting area 123 may be electrically isolated from each other.

[0034] In some embodiments, the third mounting area 123 may be an outermost mounting area among the mounting areas 120. For example, the third mounting area 123 may be a mounting area among the mounting areas 120 that is closest to an edge of the substrate 100.

[0035] In addition, the substrate 100 may include a first bonding pad 102, a second bonding pad 104, and a grounding pad 106. Each of the first bonding pad 102, the second bonding pad 104, and the grounding pad 106 may be one of the same plurality. In addition, the first bonding pad 102, the second bonding pad 104, and the grounding pad 106 may each be formed as a conductor.

[0036] For example, the first bonding pad 102 may be formed in the upper portion of the substrate 100. The first bonding pad 102 may be connected to a circuit (eg, a circuit pattern) formed on the substrate 100. In addition, the first bonding pad 102 may be connected to a bonding wire 306 (see FIG. 1 ) to be described later. Figure 8 That is, the first bonding pad 102 may be a portion through which the circuit pattern of the substrate 100 is connected to the outside. Therefore, the substrate 100 may be electrically connected to, for example, a semiconductor chip through the first bonding pad 102.

[0037] For example, the second bonding pad 104 may be formed in the lower portion of the substrate 100. Similar to the first bonding pad 102, the second bonding pad 104 may be connected to a circuit (e.g., a circuit pattern) formed on the substrate 100. In addition, the second bonding pad 104 may be connected to a solder ball 110 (see FIG. 1 ) to be described later. Figure 8 That is, the second bonding pad 104 may be a portion through which the circuit pattern of the substrate 100 is connected to the outside.

[0038] For example, a ground pad 106 may be formed in an upper portion of the substrate 100. The ground pad 106 may be electrically connected to a ground line within the substrate 100. However, in some embodiments, the ground pad 106 may be omitted.

[0039] The molding structure 220S may be disposed on the substrate 100. The molding structure 220S may extend from the upper surface of the substrate 100 in a third direction Z intersecting the first direction X and the second direction Y.

[0040] The mold structure 220S according to the embodiment may include a peripheral portion 222 and a plurality of first bars 224 .

[0041] The peripheral portion 222 of the mold structure 220S may extend along the edge of the substrate 100. For example, when the substrate 100 is rectangular, the peripheral portion 222 of the mold structure 220S may have a shape extending along the edge of the rectangular shape, such as Figure 1 shown.

[0042] In some embodiments, all of the mounting regions 120 may be disposed within the peripheral portion 222. For example, the peripheral portion 222 of the molded structure 220S may extend along the periphery of the outermost mounting region among the mounting regions 120. Figure 1 and Figure 3 As shown, the peripheral portion 222 may be adjacent to the third mounting region 123 which is the outermost mounting region among the mounting regions 120 .

[0043] In some embodiments, some of the mounting areas 120 may be disposed outside of the peripheral portion 222 .

[0044] The first strip 224 of the molded structure 220S may separate at least some of the mounting areas 120. The first strip 224 of the molded structure 220S may extend within the peripheral portion 222. For example, Figure 1 As shown, the first strip 224 may extend along the second direction Y within the peripheral portion 222 to separate at least some of the mounting areas 120. Figure 1 and Figure 2 As shown, the first strip 224 may separate the first mounting area 121 and the second mounting area 122 from each other.

[0045] The first strip 224 may be connected to the peripheral portion 222. In addition, the first strip 224 may extend from the peripheral portion 222 along the second direction Y. For example, the first strip 224 may be adjacent to all of the mounting areas 120 and extend along the second direction Y.

[0046] In some embodiments, the molding structure 220S may be spaced apart from the edge of the substrate 100. That is, the molding structure 220S may not be formed on the outermost periphery of the substrate 100. Figure 1 As shown, an edge of the peripheral portion 222 of the mold structure 220S may be spaced apart from an edge of the substrate 100 .

[0047] In some embodiments, the mold structure 220S may contact the ground pad 106. For example, Figure 2 and Figure 3 As shown, the peripheral portion 222 and the first strip 224 may be formed on the ground pad 106. Therefore, the ground pad 106 may provide a ground voltage to the mold structure 220S. Figure 2In the embodiment, the width of the ground pad 106 is equal to the width of the first strip 224. However, the present disclosure is not limited thereto. For example, the width of the ground pad 106 may be greater than or less than the width of the first strip 224.

[0048] The molding structure 220S may include, but is not limited to, epoxy molding compound (EMC).

[0049] In some embodiments, the molded structure 220S may include a conductive material. For example, the molded structure 220S may include a conductive EMC. The conductive EMC may include a conductive filler. The conductive filler may include, for example, ferrite. For example, the conductive filler may include various known conductive fillers. For example, the conductive filler may include at least one of a metal-based conductive filler, a carbon-based conductive filler, a polymer-based conductive filler, and a combination of these fillers, and the metal-based conductive filler includes Ag, Cu, Ni, ZnO, SnO 2 , Al and stainless steel, carbon-based conductive fillers include acetylene black, channel black, pitch-based / polyacrylonitrile-based carbon fibers and graphite, and polymer-based conductive fillers include polyaniline, polypyrrole and polythiophene.

[0050] In some embodiments, the molded structure 220S may include 50% by weight or more of the conductive filler based on 100% by weight of the conductive EMC. For example, the molded structure 220S may include 85% to 95% by weight of the conductive filler based on 100% by weight of the conductive EMC. In another embodiment, the molded structure 220S may include an amount of conductive material that provides sufficient EMI shielding for an integrated circuit within a semiconductor package.

[0051] As the inventors understand, a thin substrate may lead to process defects. For example, due to reduced hardness, a thin substrate may bend or crack during the process of manufacturing a semiconductor package. However, the PCB according to the embodiment can enhance the hardness of the substrate by using the molding structure 220S. For example, during assembly or transportation, the molding structure 220S can support the substrate 100 to enhance the hardness of the substrate 100.

[0052] A jig or a fixture may be used to compensate for the reduction in substrate hardness. However, this method may introduce new equipment and processes. On the other hand, since the molded structure 220S according to the embodiment includes an EMC, existing equipment and processes may be used without cracking or bending the thin substrate. For example, the same method as used to manufacture the first molded portion 210 (see Figure 8 ) is used to manufacture the mold structure 220S according to the embodiment. Therefore, the PCB according to the embodiment can reduce the manufacturing cost of the semiconductor package.

[0053] In addition, since the molding structure 220S according to the embodiment is spaced apart from the edge of the substrate 100, an area for processing the substrate 100 can be provided. For example, a jig used in a process of manufacturing a semiconductor package can fix the PCB according to the embodiment by using the edge of the substrate 100 on which the molding structure 220S is not formed.

[0054] Figure 4 is a schematic top view of a PCB according to an embodiment. Figure 5 It is along Figure 4 Schematic cross-sectional view taken along line CC'. Figure 6 It is along Figure 4 For ease of explanation, the schematic cross-sectional view of the line D-D' is shown in FIG. Figures 1 to 3 Description of elements that are the same as those described above will be briefly given or may be omitted.

[0055] refer to Figures 4 to 6 , the molded structure 220S according to the embodiment further includes a plurality of second strips 226 .

[0056] The second strip 226 of the mold structure 220S may separate at least some of the plurality of mounting regions 120. The second strip 226 of the mold structure 220S may extend within the peripheral portion 222. For example, Figure 4 As shown, the second strip 226 extends along the first direction X within the peripheral portion 222 to separate at least some of the mounting areas 120. Figure 4 and Figure 6 As shown, the second bar 226 may separate the first mounting area 121 and the third mounting area 123 from each other.

[0057] The second strip 226 may be connected to the peripheral portion 222. The second strip 226 may extend from the peripheral portion 222 along the first direction X. For example, the second strip 226 may be adjacent to all of the mounting areas 120 and extend along the first direction X.

[0058] Since the mounting regions 120 may be arranged in a checkerboard pattern, the molding structure 220S may be formed in a lattice pattern, for example. Therefore, the mounting regions 120 may be separated from each other by the molding structure 220S.

[0059] In some embodiments, the mold structure 220S may contact the ground pad 106. For example, Figure 5 and Figure 6 As shown, the peripheral portion 222, the first strip 224, and the second strip 226 may be formed on the ground pad 106. Therefore, the ground pad 106 may provide a ground voltage to the mold structure 220S. Figure 6In the embodiment, the width of the ground pad 106 is equal to the width of the second strip 226. However, the present disclosure is not limited thereto. For example, the width of the ground pad 106 may be greater than or less than the width of the second strip 226.

[0060] Now refer to FIG. 7A to FIG. 13 A semiconductor package according to an embodiment is described.

[0061] 7A to 7C are various schematic top views of semiconductor packages according to embodiments. Figure 8 It is along Fig. 7A For ease of explanation, the schematic cross-sectional view of the line EE' is shown in FIG. Figures 1 to 6 Description of elements that are the same as those described above will be briefly given or may be omitted.

[0062] refer to Fig. 7A and Figure 8 , a semiconductor package according to an embodiment includes a substrate 100 , a semiconductor chip 300 , bonding wires 306 , solder balls 110 , a first molding portion 210 , and a second molding portion 220 .

[0063] The semiconductor chip 300 may be disposed on the substrate 100. For example, the semiconductor chip 300 may be mounted in the mounting region 120 (see FIG. Figure 1 The semiconductor chip 300 may be, but is not limited to, a logic device (eg, a microprocessor).

[0064] The semiconductor chip 300 may have a structure in which a plurality of chips are stacked. For example, the semiconductor chip 300 may include a lower chip 302b and an upper chip 302u stacked on the lower chip 302b. Figure 8 , a structure in which only two chips are stacked is shown, but the semiconductor chip 300 may have a structure in which three or more chips are stacked.

[0065] The lower chip 302b may be mounted on the substrate 100 through the lower attaching portion 304b. The lower attaching portion 304b may mount the lower chip 302b on the substrate 100 by using an adhesive medium.

[0066] The upper chip 302u may be mounted on the lower chip 302b through the upper attaching portion 304u. Similar to the lower attaching portion 304b, the upper attaching portion 304u may mount the upper chip 302u on the lower chip 302b by using an adhesive medium.

[0067] Each of the lower attachment portion 304b and the upper attachment portion 304u may include, but is not limited to, liquid epoxy, adhesive tape, or a conductive medium.

[0068] In some embodiments, the semiconductor chip 300 may be mounted on the substrate 100 by flip-chip bonding. Although not shown in the drawings, for example, a plurality of conductive chip bumps may be interposed between the substrate 100 and the semiconductor chip 300. The conductive chip bumps may be formed by, for example, a soldering process.

[0069] The bonding wires 306 may electrically connect the substrate 100 and the semiconductor chip 300. For example, the bonding wires 306 may be connected to the first bonding pads 102 of the substrate 100. However, the substrate 100 may also be electrically connected to the semiconductor chip 300 through, for example, a bonding ribbon.

[0070] The solder balls 110 may be connected to the substrate 100. For example, the solder balls 110 may be connected to the second bonding pads 104 of the substrate 100. Therefore, the substrate 100 may be electrically connected to another substrate or the like through the solder balls 110. For example, the substrate 100 may be electrically connected to a module board or a main circuit board through the solder balls 110.

[0071] The first molding portion 210 may cover the semiconductor chip 300 . Therefore, the semiconductor chip 300 may be sealed by the first molding portion 210 .

[0072] The first molded portion 210 may include a first side wall S1, a second side wall S2, a third side wall S3, and a fourth side wall S4. The first side wall S1 and the second side wall S2 may be opposite side walls of the first molded portion 210. The third side wall S3 of the first molded portion 210 may be a side wall connecting the first side wall S1 and the second side wall S2. The fourth side wall S4 of the first molded portion 210 may be a side wall facing the third side wall S3.

[0073] For example, the first sidewall S1 and the second sidewall S2 may be two sidewalls of the first molded portion 210 extending along the second direction Y. The third sidewall S3 may be a sidewall of the first molded portion 210 extending along the first direction X. The fourth sidewall S4 may be another sidewall of the first molded portion 210 extending along the first direction X. For example, the first sidewall S1, the second sidewall S2, the third sidewall S3, and the fourth sidewall S4 may be sidewalls of the first molded portion 210 shaped like a rectangular parallelepiped.

[0074] The first molded portion 210 may include a non-conductive material. The first molded portion 210 may include, for example, a non-conductive EMC including a non-conductive filler. The non-conductive filler may include, but is not limited to, silicon dioxide.

[0075] The second molding portion 220 may extend on the substrate 100 along at least some of the sidewalls of the first molding portion 210. Thus, the second molding portion 220 may surround at least a portion of the semiconductor chip 300. For example, Fig. 7AAs shown, the second molded portion 220 may extend along the first sidewall S1 and the second sidewall S2 of the first molded portion 210. However, in some embodiments, the second molded portion 220 may not extend along the third sidewall S3 and the fourth sidewall S4 of the first molded portion 210.

[0076] like Figure 8 As shown, the lower surface of the second molding portion 220 may contact the upper surface of the substrate 100. Figure 8 In the embodiment, the upper surface of the second molded part 220 is located in the same plane as the upper surface of the first molded part 210. However, the present disclosure is not limited thereto. For example, the upper surface of the second molded part 220 may be higher or lower than the upper surface of the first molded part 210.

[0077] In some embodiments, the second molded portion 220 may contact the ground pad 106 of the substrate 100. Therefore, the second molded portion 220 may be grounded through the ground pad 106.

[0078] A semiconductor package according to an embodiment may be used Figures 1 to 6 For example, a semiconductor package can be manufactured using one of the PCBs. Figures 1 to 6 A plurality of semiconductor packages adjacent to each other may be manufactured on one of the PCBs. Then, the semiconductor packages adjacent to each other may be cut to produce FIG. 7A to FIG. 8 The semiconductor package, such as reference Figures 14 to 25 described in further detail.

[0079] For example, you can use Figures 1 to 3 PCB Manufacturing Fig. 7A and Figure 8 In this case, the second molding portion 220 may be Figure 1 For example, the second molded portion 220 on each of the first sidewall S1 and the second sidewall S2 may be a portion of the first strip 224 .

[0080] refer to Figure 7B and Figure 8 , the second molding portion 220 according to the embodiment may further extend along the third side wall S3.

[0081] For example, Figure 7B As shown, the second molded portion 220 may extend along the first sidewall S1, the second sidewall S2, and the third sidewall S3 of the first molded portion 210. However, in some embodiments, the second molded portion 220 may not extend along the fourth sidewall S4 of the first molded portion 210.

[0082] A semiconductor package according to an embodiment may be used Figures 1 to 6 A semiconductor package is manufactured on one of the PCBs.

[0083] For example, you can use Figures 1 to 3 PCB Manufacturing Figure 7B and Figure 8 In this case, the second molding portion 220 may be Figure 1 For example, the second molded portion 220 on each of the first sidewall S1 and the second sidewall S2 may be a portion of the first strip 224. For example, the second molded portion 220 on the third sidewall S3 may be a portion of the peripheral portion 222.

[0084] refer to Figure 7C and Figure 8 , the second molding portion 220 according to the embodiment may further extend along the fourth side wall S4.

[0085] For example, Figure 7C As shown, the second molding portion 220 may extend along the first sidewall S1 , the second sidewall S2 , the third sidewall S3 , and the fourth sidewall S4 of the first molding portion 210 .

[0086] A semiconductor package according to an embodiment may be used Figures 1 to 6 A semiconductor package is manufactured on one of the PCBs.

[0087] For example, you can use Figures 4 to 6 PCB Manufacturing Figure 7C and Figure 8 In this case, the second molding portion 220 may be Figure 4 For example, the second molded portion 220 on each of the first sidewall S1 and the second sidewall S2 may be a portion of the first strip 224. For example, the second molded portion 220 on each of the third sidewall S3 and the fourth sidewall S4 may be a portion of the second strip 226. Alternatively, the second molded portion 220 on the first sidewall S1, the second sidewall S2, the third sidewall S3, or the fourth sidewall S4 may be a portion of the peripheral portion 222.

[0088] Fig. 9 is a schematic top view of a semiconductor package according to an embodiment. Fig.10 It is along Fig. 9 For ease of explanation, the schematic cross-sectional view of the line F-F' is shown in FIG. Figures 1 to 8 Description of elements that are the same as those described above will be briefly given or may be omitted.

[0089] refer to Fig. 9 and Fig.10, the first molding part 210 according to the embodiment may cover the upper surface of the second molding part 220. For example, the uppermost surface of the first molding part 210 may be higher than the uppermost surface of the second molding part 220.

[0090] exist Fig. 9 and Fig.10 In the embodiment, the first molded part 210 covers the entire upper surface of the second molded part 220. However, the present disclosure is not limited thereto. For example, the first molded part 210 may cover a portion of the upper surface of the second molded part 220.

[0091] Fig.11 is a schematic top view of a semiconductor package according to an embodiment. Fig.12 It is along Fig.11 For ease of explanation, the schematic cross-sectional view of the line G-G' is shown in FIG. Figures 1 to 8 Description of elements that are the same as those described above will be briefly given or may be omitted.

[0092] refer to Fig.11 and Fig.12 , the semiconductor package according to the embodiment further includes a third molding portion 230 .

[0093] The third molded portion 230 may be disposed on the first molded portion 210 and the second molded portion 220. Therefore, the third molded portion 230 may contact the second molded portion 220. When the second molded portion 220 is grounded as described above, the third molded portion 230 may also be grounded.

[0094] exist Fig.11 and Fig.12 , the third molded portion 230 completely covers the upper surface of the first molded portion 210 and the upper surface of the second molded portion 220. However, the present disclosure is not limited thereto. For example, the third molded portion 230 may cover a portion of the upper surface of the second molded portion 220. However, the third molded portion 230 may completely cover the upper surface of the first molded portion 210.

[0095] The third molded portion 230 may include, but is not limited to, EMC.

[0096] In some embodiments, the third molded portion 230 may include a conductive material. For example, the third molded portion 230 may include a conductive EMC. The conductive EMC may include a conductive filler. The conductive filler may include, for example, ferrite. However, the conductive filler may include various known conductive fillers. For example, the conductive filler may include at least one of a metal-based conductive filler, a carbon-based conductive filler, a polymer-based conductive filler, and a combination of these fillers, and the metal-based conductive filler includes Ag, Cu, Ni, ZnO, SnO 2, Al and stainless steel, carbon-based conductive fillers include acetylene black, channel black, pitch-based / polyacrylonitrile-based carbon fibers and graphite, and polymer-based conductive fillers include polyaniline, polypyrrole and polythiophene.

[0097] In some embodiments, the third molded portion 230 may include 50% by weight or more of the conductive filler based on 100% by weight of the conductive EMC. For example, the third molded portion 230 may include 85% to 95% by weight of the conductive filler based on 100% by weight of the conductive EMC.

[0098] In some embodiments, third molded portion 230 may include the same material as second molded portion 220. For example, third molded portion 230 may include a different type of conductive filler than that of second molded portion 220 or may include a different content of conductive filler than second molded portion 220.

[0099] Fig.13 is a schematic top view of a semiconductor package according to an embodiment. Figures 1 to 8 Description of elements that are the same as those described above will be briefly given or may be omitted.

[0100] refer to Fig.13 , a semiconductor package according to an embodiment may include a plurality of sub-semiconductor chips.

[0101] For example, the first sub-semiconductor chip 300a and the second sub-semiconductor chip 300b may be disposed on the substrate 100. Each of the first sub-semiconductor chip 300a and the second sub-semiconductor chip 300b may correspond to FIG. 7A to FIG. 8 A semiconductor chip 300 is provided.

[0102] The first molding part 210 may cover the first and second sub-semiconductor chips 300a and 300b. Therefore, the first and second sub-semiconductor chips 300a and 300b may be sealed by the first molding part 210. The second molding part 220 may surround at least a portion of the first and second sub-semiconductor chips 300a and 300b.

[0103] As semiconductor packages become thinner and more highly integrated, the hardness of the semiconductor packages may be reduced. For example, as semiconductor packages become thinner, the bending of the semiconductor packages may be increased. However, the hardness of the semiconductor package according to the embodiment may be enhanced using the second molding part 220. For example, the second molding part 220 may support the substrate 100 and the first molding part 210 to enhance the hardness of the semiconductor package according to the embodiment.

[0104] In addition, as semiconductor packages become thinner and more highly integrated, electromagnetic interference (EMI) will be more severe. However, the semiconductor package according to the embodiment can prevent EMI by using the second molding part 220. For example, the second molding part 220 including the conductive material can be grounded by contacting the grounding pad 106 of the substrate 100. The grounded second molding part 220 can surround the semiconductor chip 300 and reduce the EMI effect on the semiconductor chip 300.

[0105] In some embodiments, the grounded third molding portion 230 may completely surround the semiconductor chip 300 together with the second molding portion 220 and minimize the influence of EMI on the semiconductor chip 300 .

[0106] Now refer to Figures 14 to 25 A method of manufacturing a semiconductor package according to an embodiment is described.

[0107] Figures 14 to 25 is a diagram showing steps of a method for manufacturing a semiconductor package according to an embodiment. Figures 1 to 13 Description of elements that are the same as those described above will be briefly given or may be omitted.

[0108] refer to Fig.14 and Fig.15 , providing a substrate 100 including a plurality of mounting areas 120. For reference, Fig.15 It is along Fig.14 A cross-sectional view taken along line A1-A1'.

[0109] The mounting area 120 may include a first mounting area 121 and a second mounting area 122 adjacent to each other along the first direction X.

[0110] The substrate 100 may include a first bonding pad 102, a second bonding pad 104, and a grounding pad 106. Each of the first bonding pad 102, the second bonding pad 104, and the grounding pad 106 may be formed in plural. In addition, the first bonding pad 102, the second bonding pad 104, and the grounding pad 106 may each be formed as a conductor.

[0111] refer to FIG. 16A to FIG. 17 , a molding structure 220S is formed on the substrate 100. For reference, Fig.17 It is along Fig.16A and Fig. 16B A cross-sectional view taken along line A2-A2'.

[0112] The molded structure 220S may be formed into various shapes. Fig.16A As shown, a molded structure 220S including a peripheral portion 222 and a first strip 224 can be formed. Figures 1 to 3PCB.

[0113] Alternatively, if Fig. 16B As shown, a molded structure 220S including a peripheral portion 222, a first strip 224, and a second strip 226 can be formed. Figures 4 to 6 PCB.

[0114] For ease of explanation, the molded structure 220S will be described below as including a peripheral portion 222 , a first strip 224 , and a second strip 226 .

[0115] The molded structure 220S may include, for example, EMC. The molded structure 220S may be formed by at least one of, for example, dispensing, film attachment, transfer molding, and compression molding. However, the molded structure 220S may also be formed by various methods of forming a molded part including EMC.

[0116] In some embodiments, the mold structure 220S may include a conductive material. For example, the mold structure 220S may include a conductive EMC.

[0117] In some embodiments, the molding structure 220S may be formed to contact the ground pad 106 of the substrate 100 .

[0118] refer to Fig.18 and Fig.19 , a plurality of semiconductor chips 300 are formed on a substrate 100. For reference, Fig.19 It is along Fig.18 A cross-sectional view taken along line A3-A3'.

[0119] The semiconductor chips 300 may be formed on the respective mounting regions 120 , respectively. For example, the first semiconductor chip 310 may be formed on the first mounting region 121 , and the second semiconductor chip 320 may be formed on the second mounting region 122 .

[0120] Each of the semiconductor chips 300 may have a structure in which a plurality of chips are stacked. Fig.19 In the embodiment, each of the first semiconductor chip 310 and the second semiconductor chip 320 has a structure in which only two chips are stacked. However, each of the first semiconductor chip 310 and the second semiconductor chip 320 may have a structure in which three or more chips are stacked.

[0121] Since the mold structure 220S may separate at least some of the mounting region 120, at least some of the semiconductor chips 300 may be separated by the mold structure 220S. For example, the first semiconductor chip 310 and the second semiconductor chip 320 may be separated by the mold structure 220S.

[0122] refer to Fig. 20and Fig.21 , a first molding portion 210 is formed on the substrate 100 and the molding structure 220S. For reference, Fig.21 It is along Fig. 20 A cross-sectional view taken along line A4-A4'.

[0123] The first molding portion 210 may be formed to cover the semiconductor chip 300. For example, the first molding portion 210 may be formed to cover the first semiconductor chip 310 and the second semiconductor chip 320.

[0124] In addition, the first molding portion 210 may be formed to cover the molding structure 220S. Therefore, the uppermost surface of the first molding portion 210 may be higher than the uppermost surface of the molding structure 220S.

[0125] The first molded portion 210 may include, for example, a non-conductive EMC. The first molded portion 210 may be formed by at least one of the following: for example, dispensing, film attachment, transfer molding, and compression molding. However, the first molded portion 210 may also be formed by various methods of forming a molded part including an EMC.

[0126] In some embodiments, the first molding portion 210 may be formed in the same manner as the molding structure 220S. Therefore, the manufacturing cost of the semiconductor package according to the embodiment may be reduced.

[0127] refer to Fig. 22 and Fig.23 , so that the upper surface of the molded structure 220S and the upper surface of the first molded part 210 are planarized. For reference, Fig.23 It is along Fig. 22 A cross-sectional view taken along line A5-A5'.

[0128] The upper surface of the molding structure 220S and the upper surface of the first molding portion 210 may be planarized by, for example, chemical mechanical polishing (CMP).

[0129] Therefore, the upper surface of the molding structure 220S and the upper surface of the first molding portion 210 may be located in the same plane. As used herein, the term "same" refers not only to being completely identical but also to having a slight difference that may occur due to a process margin or the like.

[0130] In addition, the first molded portion 210 may be divided into a plurality of encapsulated portions by the molded structure 220S. For example, the first molded portion 210 may include a first encapsulated portion 210a and a second encapsulated portion 210b separated by the molded structure 220S. Fig.23As shown, the first encapsulation portion 210 a may be a portion of the first molding portion 210 covering the first semiconductor chip 310 , and the second encapsulation portion 210 b may be a portion of the first molding portion 210 covering the second semiconductor chip 320 .

[0131] In some embodiments, planarization of the upper surface of the molding structure 220S and the upper surface of the first molding portion 210 may be omitted.

[0132] refer to Fig.24 and Fig.25 , a third molding part 230 is formed on the molding structure 220S and the first molding part 210. For reference, Fig.25 It is along Fig.23 A cross-sectional view taken along line A6-A6'.

[0133] The third molding portion 230 may be formed to cover the upper surface of the molding structure 220S and the upper surface of the first molding portion 210. Therefore, the third molding portion 230 may contact the molding structure 220S.

[0134] In some embodiments, the third molding portion 230 may include a conductive material. For example, the third molding portion 230 may include a conductive EMC.

[0135] However, in some embodiments, forming the third molding portion 230 on the molding structure 220S and the first molding portion 210 may be omitted.

[0136] Therefore, you can use Figures 1 to 3 PCB or Figures 4 to 6 The PCB forms a plurality of semiconductor packages adjacent to each other.

[0137] Then, the semiconductor packages adjacent to each other may be diced into individual semiconductor packages.

[0138] For example, when using Figures 1 to 3 In the method for manufacturing a semiconductor package using a PCB, the semiconductor packages adjacent to each other may be cut around the first semiconductor chip 310 to produce Fig. 7A and Figure 8 semiconductor packages.

[0139] For example, when using Figures 4 to 6 In the method for manufacturing a semiconductor package using a PCB, the semiconductor packages adjacent to each other may be cut around the first semiconductor chip 310 to produce Figure 7C and Figure 8 semiconductor packages.

[0140] For example, you can Fig.24 and Fig.25 The first semiconductor chip 310 cuts the semiconductor packages adjacent to each other to produce Fig.11 and Fig.12 semiconductor packages.

[0141] Although the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made thereto without departing from the spirit and scope of the inventive concept as defined in the appended claims. It is therefore desired that the present embodiments be considered in all respects as illustrative rather than restrictive, with reference to the appended claims rather than the foregoing description to indicate the scope of the invention.

Claims

1. A semiconductor package, include: substrate; a semiconductor chip on the substrate; a first molding portion covering the semiconductor chip and including a first side wall and a second side wall opposite to each other; and a second molded portion extending on the substrate along the first side wall and the second side wall, and a third molded portion, which is located on the first molded portion and on the second molded portion and includes a conductive material, wherein the first molded portion comprises a non-conductive material and the second molded portion comprises a conductive epoxy molding compound, wherein the second molded portion includes 85% to 95% by weight of a conductive filler based on 100% by weight of the conductive epoxy molding compound, and The third molded portion includes a conductive filler having a different content from that of the second molded portion.

2. The semiconductor package according to claim 1, in, The first molding portion further includes a third sidewall connecting the first sidewall and the second sidewall, and the second molding portion extends on the substrate along the third sidewall.

3. The semiconductor package according to claim 2, in, The first molding portion further includes a fourth sidewall opposite to the third sidewall, and the second molding portion extends on the substrate along the fourth sidewall.

4. The semiconductor package according to claim 1, in, The substrate includes a ground pad, and the second molded portion electrically contacts the ground pad.

5. The semiconductor package according to claim 1, in, The first molded portion covers an uppermost surface of the second molded portion.

6. The semiconductor package according to claim 1, in, The third molding portion covers an uppermost surface of the first molding portion and an uppermost surface of the second molding portion.

7. The semiconductor package according to claim 1, in, The conductive epoxy molding compound includes an amount of conductive material to provide sufficient electromagnetic interference shielding for an integrated circuit in the semiconductor package.

8. A semiconductor package, include: substrate; a semiconductor chip on the substrate; a first molding portion on the substrate, covering the semiconductor chip; a second molded portion on the substrate extending along a sidewall of the first molded portion; and a third molded portion covering the uppermost surface of the first molded portion and the uppermost surface of the second molded portion, wherein the second molded portion and the third molded portion include conductive epoxy molding compound, wherein each of the second molded portion and the third molded portion includes 85% to 95% by weight of a conductive filler based on 100% by weight of the conductive epoxy molding compound, and The third molded portion includes a conductive filler having a different content from that of the second molded portion.

9. The semiconductor package according to claim 8, in, The first molded portion has a rectangular parallelepiped shape.

10. The semiconductor package according to claim 9, in, The substrate includes a grounding pad, the second molded portion contacts the grounding pad, and the third molded portion contacts the second molded portion.

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