Image sensor and method for manufacturing the same

Abstract

An image sensor includes a photosensitive element, a storage element and a driving circuit. The storage element is adjacent to the photosensitive element and includes a storage node, a gate dielectric layer, a storage gate electrode, an etch stop layer, a shielding layer, and a protective layer. The gate dielectric layer is located on the storage node. The storage gate electrode is located on the gate dielectric layer. The etch stop layer covers the gate dielectric layer and the storage gate electrode. The shielding layer is located on the storage gate electrode. The protective layer is sandwiched between the etch stop layer and the shielding layer. The driving circuit is adjacent to the storage element.

Description

Technical Field

[0001] The embodiments of the present invention relate to an image sensor. More specifically, the embodiments of the present invention relate to an image sensor with a protective layer. Background Art

[0002] In order to capture fast-moving objects, it is preferred to use an image sensor with a global shutter. A global shutter is often implemented by placing a storage element in each pixel of the image sensor array in addition to the photodiode and readout circuitry. The storage element is configured to temporarily store photogenerated charge, thereby enabling each row of the image sensor array to be exposed at the same time. Summary of the invention

[0003] An image sensor includes a photosensitive element, a storage element, and a driving circuit. The storage element is adjacent to the photosensitive element. The storage element includes a storage node, a gate dielectric layer, a storage gate electrode, an etch stop layer, a shielding layer, and a protective layer. The gate dielectric layer is located on the storage node. The storage gate electrode is located on the gate dielectric layer. The etch stop layer covers the gate dielectric layer and the storage gate electrode. The shielding layer is located on the storage gate electrode. The protective layer is sandwiched between the etch stop layer and the shielding layer. The driving circuit is adjacent to the storage element. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0005] Figure 1 is a schematic diagram illustrating an image sensor according to some embodiments of the present disclosure.

[0006] Figure 2 yes Figure 1 A schematic top view of a storage element is shown.

[0007] FIG. 3A to FIG. 3O is a diagram showing various stages in a method of manufacturing a memory element. Figure 2 A schematic cross-sectional view along line AA' is shown.

[0008] Figure 4 is the storage element along Figure 2 Schematic cross-sectional view along line BB' is shown.

[0009] Description of Figure Numbers

[0010] 10: Image Sensor

[0011] 100: Substrate

[0012] 102a, 102b: first doping region

[0013] 104a, 104b: second doping region

[0014] 110: Storage node

[0015] 200: Gate dielectric layer

[0016] 300: Etch stop layer

[0017] 400: Dielectric layer

[0018] 402, 402a, 402b: first dielectric layer

[0019] 404: Second dielectric layer

[0020] 500, 500a: Termination layer

[0021] 600: Protective material layer

[0022] 600a: Protective layer

[0023] 700: Shielding material layer

[0024] 700a: Shielding layer

[0025] 800: Conductive contact

[0026] 900: Inner connection structure

[0027] 902: Internal conductive pattern

[0028] 904: Interconnect dielectric layer

[0029] B 700a : Bottom surface

[0030] DC: driving circuit

[0031] FD: Floating Diffusion

[0032] OP1: Opening

[0033] OP2: Contact opening

[0034] PD: Photosensitive element

[0035] Pixout: Image Data

[0036] RS: Row select transistor

[0037] RST: Reset transistor

[0038] SD: Storage Component

[0039] SF: Source follower transistor

[0040] SG: Storage gate electrode

[0041] SHG: Shutter Gate Transistor

[0042] SW 700a : Sidewall

[0043] T 700a : Top surface

[0044] TG1: First transfer gate transistor

[0045] TG2: Second transfer gate transistor

[0046] V aa :Voltage

[0047] V cc : Reference voltage

[0048] V pix :Voltage DETAILED DESCRIPTION

[0049] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the sake of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0050] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship between one component or feature and another (other) component or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0051] Figure 1is a schematic diagram showing an image sensor 10 according to some embodiments of the present disclosure. Figure 1 The image sensor 10 includes a shutter gate transistor SHG, a photosensitive element PD, a first transfer gate transistor TG1, a storage element SD, and a driving circuit DC. In some embodiments, the image sensor 10 may be referred to as a complementary metal-oxide-semiconductor (CMOS) image sensor. In some embodiments, the image sensor 10 may include a global shutter. It should be noted that Figure 1 The components shown may constitute one pixel unit of the image sensor 10. In other words, for the sake of simplicity, only one pixel unit is shown as a representative. It should be understood that the image sensor 10 may include a pixel array composed of a plurality of pixel units.

[0052] In some embodiments, the photosensitive element PD may be a photodiode. For example, the photosensitive element PD may be formed by a PN junction (P-N junction) formed by the first doping region 102a and the second doping region 104a. In some embodiments, the first doping region 102a may be doped with an n-type dopant, and the second doping region 104a may be doped with a p-type dopant. However, this is not a limitation in the present disclosure. In some alternative embodiments, the dopant in the first doping region 102a and the dopant in the second doping region 104a may be interchangeable depending on the conductivity type of the substrate. When incident light is irradiated, the photosensitive element PD is capable of accumulating an image charge in response to the incident light. It should be noted that the photodiode is only used as an exemplary illustration of the photosensitive element PD, and the present disclosure is not limited thereto. Other suitable photosensitive elements may also be used, as long as the element is capable of accumulating an image charge when incident light is irradiated.

[0053] The shutter gate transistor SHG is coupled to the photosensitive element PD. In some embodiments, the source or drain of the shutter gate transistor SHG is coupled to a voltage V aa The first transfer gate transistor TG1 is located between the photosensitive element PD and the storage element SD. In some embodiments, the first transfer gate transistor TG1 is capable of controlling the transfer of the image charge accumulated in the photosensitive element PD to the storage element SD. For example, during the operation of the image sensor 10, the first transfer gate transistor TG1 is capable of receiving a transfer signal and performing the transfer of the image charge accumulated in the photosensitive element PD to the storage element SD based on the transfer signal.

[0054] The storage element SD is coupled to the first transfer gate transistor TG1 and the photosensitive element PD to receive the image charges accumulated in the photosensitive element PD and store the received image charges in a depletion region. Figure 1 As shown, the storage element SD may be adjacent to the photosensitive element PD. In some embodiments, the storage element SD includes a first doping region 102b, a second doping region 104b, and a storage gate electrode SG. In some embodiments, the image charge is stored in the first doping region 102b, the second doping region 104b, and a substrate (e.g., Figure 3A The first doping region 102b of the storage element SD and the first doping region 102a of the photosensitive element PD can be formed simultaneously in the same step. Similarly, the second doping region 104b of the storage element SD and the second doping region 104a of the photosensitive element PD can also be formed simultaneously in the same step. However, the present disclosure is not limited to this. In some alternative embodiments, the first doping regions 102a, 102b and the second doping regions 104a, 104b can be formed separately in different steps. Figure 2 , FIG. 3A to FIG. 3O ,and Figure 4 The structure of the storage element SD is described in more detail.

[0055] The driving circuit DC is disposed adjacent to the storage element SD. The driving circuit DC includes a second transfer gate transistor TG2, a floating diffusion FD, a reset transistor RST, a source follower transistor SF, and a row select transistor RS. In some embodiments, the second transfer gate transistor TG2 is coupled to the output of the storage element SD. Similar to the first transfer gate transistor TG1, the second transfer gate transistor TG2 also provides a function of selectively transferring the image charge accumulated in the storage element SD to the floating diffusion FD. In some embodiments, the second transfer gate transistor TG2 and the storage gate electrode SG can be actuated together to transfer the image charge stored in the storage element SD to the floating diffusion FD. For example, a bias voltage can be applied to the storage gate electrode SG and the gate of the second transfer gate transistor TG2 to generate an electric field, thereby forming a channel for charge movement. In some embodiments, due to the generated electric field, charges stored in the first doping region 102 b, the second doping region 104 b, and the substrate below the second doping region 104 b are pulled out from the first doping region 102 b and the second doping region 104 b and enter the channel of the second transfer gate transistor TG2 adjacent to the storage element SD. These charges can then pass through the channel of the second transfer gate transistor TG2 and reach the floating diffusion region FD. In some embodiments, the drain of the second transfer gate transistor TG2 can serve as the drain of the storage element SD.

[0056] In some embodiments, the floating diffusion region FD is referred to as a readout node. The floating diffusion region FD is, for example, a lightly doped n-type region formed at least partially within a p-well. In some embodiments, the floating diffusion region FD can be used as a capacitor for storing image charges.

[0057] like Figure 1 As shown, the reset transistor RST is coupled to the floating diffusion region FD and the voltage V pix , to selectively reset the image charge in the floating diffusion region FD. For example, the reset transistor RST can discharge or charge the floating diffusion region FD to a preset voltage in response to the reset signal. The source follower transistor SF is coupled to the floating diffusion region FD and the voltage V aaIn some embodiments, the source follower transistor SF can provide a high impedance output. For example, the source follower transistor SF can be an amplifier transistor that amplifies the signal of the floating diffusion region FD for a readout operation. The row select transistor RS is coupled to the source follower transistor SF. In some embodiments, the other end of the row select transistor RS can be coupled to a readout column line (not shown) to selectively output the image data Pixout.

[0058] Since the driving circuit DC performs a readout function, in some embodiments, the driving circuit DC may be referred to as a readout circuit. Figure 1 The diagram of image sensor 10 shown is only an example, and the present disclosure is not limited thereto. In some alternative embodiments, image sensor 10 may have a different circuit design. For example, in some embodiments, first transfer gate transistor TG1 may be omitted. In some alternative embodiments, the layout of components in driver circuit DC may be changed according to circuit requirements. For example, driver circuit DC is depicted as Figure 1 The illustrated embodiment is a four transistor (4T) circuit system. However, in some alternative embodiments, the driver circuit DC may be a 3-transistor circuit system, a 5-transistor circuit system, or any other suitable circuit system.

[0059] The operation of the image sensor 10 will be briefly described below. In order to prevent the signal to be received from being mixed with the previously received signal, a reset procedure is first performed. During the reset procedure, a reference voltage V is applied to the reset transistor RST. cc To turn on the reset transistor RST, and the voltage V pix becomes the reference voltage V cc In some embodiments, the reference voltage V cc It can be 3.3V. Then, through the reset transistor RST and the voltage V pix Pull the potential of the floating diffusion region FD to the reference voltage V cc At the same time, the storage gate electrode SG and the second transfer gate transistor TG2 are turned on, so that the high reference voltage V cc The charge previously stored in the storage element SD can be exhausted, thereby resetting the storage element SD. In some embodiments, the photosensitive element PD is exhausted together with the storage element SD. For example, the voltage V aa Set as reference voltage V cc, and the shutter gate transistor SHG can be turned on to deplete the charge previously accumulated in the photosensitive element PD. It should be noted that during this stage, the first transfer gate transistor TG1 is turned off. After ensuring that the storage element SD is reset and the photosensitive element PD is depleted, the shutter gate transistor SHG, the first transfer gate transistor TG1, and the second transfer gate transistor TG2 are turned off. When incident light is irradiated, the image charge is trapped in the photosensitive element PD. In order to access the image charge accumulated in the photosensitive element PD, the first transfer gate transistor TG1 and the storage gate electrode SG are turned on so that the image charge accumulated in the photosensitive element PD is transferred to the storage element SD. In order to access the image charge stored in the storage element SD, the storage gate electrode SG and the second transfer gate transistor TG2 are turned on to transfer the image charge from the depletion area of ​​the storage element SD to the floating diffusion area FD. Subsequently, the source follower transistor SF is turned on to amplify the signal of the floating diffusion area FD for a read operation, and the row selection transistor RS is turned on to selectively output the image data Pixout.

[0060] Figure 2 yes Figure 1 A schematic top view of a storage element SD is shown. FIG. 3A to FIG. 3O The various stages in the method for manufacturing the storage element SD are shown in FIG. Figure 2 A schematic cross-sectional view of the line AA' is shown. Figure 3A , providing a substrate 100. In some embodiments, the substrate 100 is a semiconductor substrate. For example, the substrate 100 may be made of: a suitable elemental semiconductor, such as crystalline silicon, diamond, or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, the substrate 100 may be a p-type substrate. However, the present disclosure is not limited thereto. In some alternative embodiments, an n-type substrate may be used as the substrate 100.

[0061] Then, a storage node 110 is formed in the substrate 100. In some embodiments, the storage node 110 is composed of a first doped region 102b and a second doped region 104b. The first doped region 102b can be formed by doping the substrate 100 with a first type of dopant, and the second doped region 104b can be formed by doping the substrate 100 located above the first doped region 102b with a second type of dopant. The first type of dopant is different from the second type of dopant. For example, when the substrate 100 is a p-type substrate, the first doped region 102b can be doped with an n-type dopant (such as phosphorus or arsenic), and the second doped region 104b can be doped with a p-type dopant (such as boron or BF2) to form a PN junction between the first doped region 102b and the second doped region 104b. Similarly, when the substrate 100 is an n-type substrate, the first doping region 102b may be doped with a p-type dopant, and the second doping region 104b may be doped with an n-type dopant to form a PN junction between the first doping region 102b and the second doping region 104b. In some embodiments, the dopant may be doped into the first doping region 102b and the second doping region 104b by an ion implantation process. As described above, the first doping region 102a and the second doping region 104a of the photosensitive element PD may be formed in a manner similar to that of the first doping region 102b and the second doping region 104b. Therefore, although not shown, it should be understood that the photosensitive element PD is located within the substrate 100. In some embodiments, the photosensitive element PD (shown in Figure 1 ) can serve as the source of the storage element SD.

[0062] Reference Figure 3B, forming a gate dielectric layer 200 to cover the substrate 100. In some embodiments, the gate dielectric layer 200 may include silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material. A high-k dielectric material is generally a dielectric material having a dielectric constant greater than 4. In some embodiments, the high-k dielectric material may include a metal oxide. Examples of metal oxides for high-k dielectric materials include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and / or mixtures thereof. In some embodiments, the gate dielectric layer 200 may be formed using a suitable process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal oxidation, UV-ozone oxidation, or a combination thereof.

[0063] Reference Figure 3C , a storage gate electrode SG is formed on the gate dielectric layer 200. In some embodiments, the storage gate electrode SG is formed above the storage node 110. For example, a vertical projection of the storage gate electrode SG may overlap with the storage node 110. In some embodiments, the storage gate electrode SG may include a single-layer structure or a multi-layer structure. In some embodiments, the storage gate electrode SG includes a silicon-containing material, such as polycrystalline silicon, amorphous silicon, or a combination thereof. The storage gate electrode SG may be formed using a suitable process such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, plating, or a combination thereof.

[0064] Reference Figure 3D , an etch stop layer 300 is formed on the gate dielectric layer 200 and the storage gate electrode SG. In some embodiments, the etch stop layer 300 comprises silicon nitride, carbon-doped silicon nitride, or a combination thereof. In some embodiments, the etch stop layer 300 may be referred to as a contact etch stop layer (CESL). The etch stop layer 300 may be deposited by, for example, chemical vapor deposition, high density plasma (HDP) chemical vapor deposition, sub-atmospheric CVD (SACVD), molecular layer deposition (MLD), or other suitable methods.

[0065] Reference Figure 3E, forming a first dielectric layer 402 on the etch stop layer 300. In some embodiments, the first dielectric layer 402 may be formed in a conformal manner. In some embodiments, the first dielectric layer 402 may be referred to as an interlayer dielectric layer (ILD). The first dielectric layer 402 may include silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), spin-on glass (SOG), fluorinated silica glass (FSG), carbon-doped silicon oxide (e.g., SiCOH), polyimide, and / or combinations thereof. In some other embodiments, the first dielectric layer 402 includes a low dielectric constant dielectric material. A low dielectric constant dielectric material is generally a dielectric material having a dielectric constant lower than 3.9. Examples of low dielectric constant dielectric materials include (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, Amorphous Fluorinated Carbon, Parylene, bis-benzocyclobutenes (BCB), Flare, (Dow Chemical, Midland, Mich.), hydrogen silsesquioxane (HSQ), or fluorinated silicon oxide (SiOF), and / or combinations thereof. In some embodiments, the first dielectric layer 402 is formed to a suitable thickness by flowable chemical vapor deposition (FCVD), chemical vapor deposition, high density plasma chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, spin coating, sputtering, or other suitable methods.

[0066] Reference Figure 3F , reducing the thickness of the first dielectric layer 402 to form a first dielectric layer 402a. In some embodiments, a portion of the first dielectric layer 402 is removed by a chemical mechanical polishing (CMP) process, an etching process, or other suitable processes.

[0067] Reference Figure 3G, forming a termination layer 500 to cover the first dielectric layer 402a. In some embodiments, the termination layer 500 may be an antireflection layer. The termination layer 500 may be made of, for example, silicon nitride, boron nitride, titanium nitride, or other nitride materials. In some embodiments, the termination layer 500 may be formed by chemical vapor deposition, plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition, physical vapor deposition, or a combination thereof.

[0068] Reference Figure 3H , a portion of the termination layer 500 and a portion of the first dielectric layer 402a are removed to form the termination layer 500a and the first dielectric layer 402b having the opening OP1 therein. The opening OP1 may be formed by patterning the termination layer 500 and the first dielectric layer 402a. In some embodiments, the patterning process may include a photolithography process and an etching process. Figure 3H As shown, the opening OP1 exposes at least a portion of the etch stop layer 300 .

[0069] Reference Fig. 3I , a protective material layer 600 is conformally formed on the stop layer 500a, the first dielectric layer 402b, and the etch stop layer 300. In some embodiments, the protective material layer 600 extends into the opening OP1 to cover the bottom surface and sidewalls of the opening OP1. In some embodiments, the protective material layer 600 comprises SiO2, SiN, or other suitable materials. In some embodiments, the thickness of the protective material layer 600 is between 100 and 200 nm. and The protective material layer 600 may be formed by chemical vapor deposition or other suitable methods.

[0070] Reference Figure 3J, a shielding material layer 700 is deposited on the protective material layer 600 to fill the opening OP1. In some embodiments, the shielding material layer 700 provides a function of shielding the previously formed element from the incident light. Therefore, in some embodiments, the shielding material layer 700 may be made of an opaque material. For example, the shielding material layer 700 may include a conductive material such as tungsten. However, the present disclosure is not limited thereto. In some alternative embodiments, other opaque metal materials may also be used. In some embodiments, the shielding material layer 700 may be formed by, for example, an electrochemical plating process, chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or a combination thereof. In some embodiments, the storage element SD may be formed together with other logic elements. In this case, the shielding material layer 700 of the storage element SD and the metal lines of the other logic elements may be formed simultaneously by the same step. In other words, the shielding material layer 700 and the metal lines of the other logic elements may be regarded as the same layer. It should be noted that since the shielding material layer 700 provides a function of shielding other elements from the incident light, it is different from the metal lines of other logic elements. The shielding material layer 700 is not electrically connected to other conductive elements in the storage device SD. For example, the shielding material layer 700 may be grounded.

[0071] Reference Figure 3K , remove the stop layer 500a, a portion of the protective material layer 600, and a portion of the shielding material layer 700 to form the protective layer 600a and the shielding layer 700a. In some embodiments, the removal of the stop layer 500a, the portion of the protective material layer 600, and the portion of the shielding material layer 700 may be achieved by a chemical mechanical polishing process, an etching process, or other suitable processes. Figure 3K As shown, a portion of the protection layer 600a is sandwiched between the shielding layer 700a and the etch stop layer 300, and another portion of the protection layer 600a is sandwiched between the shielding layer 700a and the first dielectric layer 402b, so that the protection layer 600a wraps around the shielding layer 700a. For example, the protection layer 600a can completely cover the bottom surface B of the shielding layer 700a. 700a And side wall SW 700a On the other hand, the protective layer 600a may expose the top surface T of the shielding layer 700a. 700a In some embodiments, the thickness of the protective layer 600a is between and In some embodiments, the etch stop layer 300 is sandwiched between the protection layer 600a and the storage gate electrode SG, between the protection layer 600a and the gate dielectric layer 200, between the first dielectric layer 402b and the gate dielectric layer 200, and between the first dielectric layer 402b and the storage gate electrode SG. It should be noted that since the etch stop layer 300 and the protection layer 600a are formed at different stages and have different profiles, the two layers are considered to be two different layers. In some embodiments, during the step of forming the opening OP1 (e.g., Figure 3H As shown in FIG. 1 , the etchant may damage / consume a portion of the etch stop layer 300, thereby causing the thickness of the etch stop layer 300 to decrease. However, sufficient isolation between the storage gate electrode SG and the shielding layer 700a is key to ensuring the reliability of the storage element SD. For example, when the minimum distance between the storage gate electrode SG and the shielding layer 700a is too small (e.g., less than 20 nm), the breakdown voltage (V bd ) will drop dramatically, causing V bd In other words, when the storage gate electrode SG is not sufficiently isolated from the shielding layer 700a, the device life of the storage element SD will be shortened. By forming the protective layer 600a on the etching stop layer 300, the protective layer 600a can compensate for the formation of Figure 3H That is, the protection layer 600a together with the etch stop layer 300 can provide sufficient isolation between the storage gate electrode SG and the shielding layer 700a, thereby ensuring a longer life of the storage element SD.

[0072] Reference Figure 3L , a second dielectric layer 404 is formed on the first dielectric layer 402b, the protective layer 600a, and the shielding layer 700a. Similar to the first dielectric layer 402b, the second dielectric layer 404 may also be referred to as an interlayer dielectric layer. In some embodiments, the first dielectric layer 402b and the second dielectric layer 404 may be collectively referred to as a single dielectric layer 400. In some embodiments, the second dielectric layer 404 and the first dielectric layer 402b may be made of the same material. However, the present disclosure is not limited to this. In some alternative embodiments, the second dielectric layer 404 and the first dielectric layer 402b may be made of different materials. For example, the second dielectric layer 404 may include silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass, borophosphosilicate glass, spin-on glass, silicon fluoride glass, carbon-doped silicon oxide (e.g., SiCOH), polyimide, and / or a combination thereof. In some other embodiments, the second dielectric layer 404 includes a low dielectric constant dielectric material. Examples of low-k dielectric materials include (Applied Materials, Santa Clara, CA), xerogel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene, Flare, (The Dow Chemical Company, Midland, Michigan), hydrogen silsesquioxane, or SiOF, and / or combinations thereof. In some embodiments, the second dielectric layer 404 is formed to a suitable thickness by flowable chemical vapor deposition, chemical vapor deposition, high density plasma chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, spin coating, sputtering, or other suitable methods.

[0073] Reference Figure 3M , forming a contact opening OP2 penetrating the second dielectric layer 404, the first dielectric layer 402b and the etch stop layer 300. Figure 3M As shown, the contact opening OP2 exposes a portion of the storage gate electrode SG for future electrical connection. Similar to the opening OP1, the contact opening OP2 may be formed by a photolithography process and an etching process.

[0074] Reference Figure 3N , forming a conductive contact 800 to fill the contact opening OP2. In some embodiments, the conductive contact 800 can be formed in the following manner. First, a conductive material (not shown) is deposited on the second dielectric layer 404, and the conductive material is filled into the contact opening OP2. Subsequently, a portion of the conductive material outside the contact opening OP2 is removed to obtain the conductive contact 800. In some embodiments, the conductive material can be removed by a chemical mechanical polishing process, an etching process, or other suitable processes.

[0075] Reference Fig.3O, an interconnect structure 900 is formed on the second dielectric layer 404 and the conductive contact 800. At this stage, the storage element SD is substantially completed. The interconnect structure 900 includes an interconnect dielectric layer 904 and a plurality of interconnect conductive patterns 902 at least partially embedded in the interconnect dielectric layer 904. In some embodiments, the material of the interconnect dielectric layer 904 includes polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene, polybenzooxazole (PBO), or any other suitable polymer dielectric material. The interconnect dielectric layer 904 can be formed by suitable manufacturing techniques such as spin coating, chemical vapor deposition, plasma enhanced chemical vapor deposition, etc. The interconnect conductive pattern 902 can be formed in the following manner. First, the interconnect dielectric layer 904 is patterned by a photolithography process and an etching process to form a plurality of openings. Then, an interconnect conductive pattern 902 is formed on the interconnect dielectric layer 904 and is formed to extend into the opening of the interconnect dielectric layer 904. The interconnect conductive pattern 902 may be formed by, for example, electroplating, deposition, and / or photolithography and etching. In some embodiments, the material of the interconnect conductive pattern 902 includes aluminum, titanium, copper, nickel, tungsten, and / or alloys thereof. Fig.3O As shown, the conductive contact 800 contacts both the storage gate electrode SG and the interconnection conductive pattern 902, so that the storage gate electrode SG is electrically connected to the interconnection conductive pattern 902. Fig.3O A single-layer interconnect structure 900 is shown, but the present disclosure is not limited thereto. In some alternative embodiments, the interconnect structure 900 may be a multi-layer structure. For example, the interconnect structure 900 may include a plurality of interconnect dielectric layers sequentially stacked on each other and a plurality of interconnect conductive patterns 902 sandwiched between / embedded in the interconnect dielectric layers.

[0076] Figure 4 is the storage element SD along Figure 2 A schematic cross-sectional view of the line BB' shown. Figure 2 In the top view, the shielding layer 700a surrounds the conductive contact 800. Figure 2 , Fig.3O ,and Figure 4, from a top view, the shielding layer 700a substantially covers the storage gate electrode SG and the active area OD of the storage element SD. In some embodiments, the active area OD may be a region that performs the storage function of the storage element SD. For example, the active area OD of the storage element SD may include at least the first doped region 102b, the second doped region 104b, and the storage gate electrode SG. As described above, since the storage element SD is used to store the image charge received from the photosensitive element PD, the active area OD of the storage element SD is preferably not irradiated by the incident light to avoid damaging the stored image charge. By using the shielding layer 700a that substantially completely covers the active area OD and the storage element SD (except for the location where the contact opening OP2 is located), the active area OD and the storage element SD can be shielded from the incident light. Therefore, it is possible to fully prevent the image charge stored in the storage element SD from being damaged, thereby providing accurate image data for reading out. Since the shielding layer 700a provides the function of shielding the active area OD of the storage element SD from the incident light, in some embodiments, the shielding layer 700a can be electrically grounded through the substrate 100.

[0077] According to some embodiments of the present disclosure, an image sensor includes a photosensitive element, a storage element, and a driving circuit. The storage element is adjacent to the photosensitive element. The storage element includes a storage node, a gate dielectric layer, a storage gate electrode, an etch stop layer, a shielding layer, and a protective layer. The gate dielectric layer is located on the storage node. The storage gate electrode is located on the gate dielectric layer. The etch stop layer covers the gate dielectric layer and the storage gate electrode. The shielding layer is located on the storage gate electrode. The protective layer is sandwiched between the etch stop layer and the shielding layer. The driving circuit is adjacent to the storage element.

[0078] According to some embodiments of the present disclosure, the storage element further includes a dielectric layer located on the shielding layer.

[0079] According to some embodiments of the present disclosure, the image sensor further comprises an interconnect structure and a conductive contact, wherein the interconnect structure is disposed on the dielectric layer, and the conductive contact penetrates the dielectric layer and the etch stop layer to electrically connect the interconnect structure with the storage gate electrode.

[0080] According to some embodiments of the present disclosure, the storage node includes a PN junction.

[0081] According to some embodiments of the present disclosure, the shielding layer is electrically grounded.

[0082] According to some embodiments of the present disclosure, the thickness of the protective layer is between and between.

[0083] According to some embodiments of the present disclosure, the material of the protective layer includes SiO 2 or SiN.

[0084] According to some alternative embodiments of the present disclosure, an image sensor includes a storage element, a photosensitive element, and a driving circuit. The storage element includes a substrate, a PN junction, a gate dielectric layer, a storage gate electrode, a shielding layer, a protective layer, and a dielectric layer. The PN junction is located in the substrate. The gate dielectric layer is located on the substrate. The storage gate electrode is located on the gate dielectric layer. The shielding layer is located on the storage gate electrode. The protective layer covers the bottom surface and sidewalls of the shielding layer. The dielectric layer is located on the shielding layer. The photosensitive element is adjacent to the storage element, and the photosensitive element is located in the substrate. The driving circuit is adjacent to the storage element.

[0085] According to some embodiments of the present disclosure, the storage element further comprises an etch stop layer. The etch stop layer is sandwiched between the protection layer and the storage gate electrode, the etch stop layer is sandwiched between the protection layer and the gate dielectric layer, the etch stop layer is sandwiched between the dielectric layer and the gate dielectric layer, and the etch stop layer is sandwiched between the dielectric layer and the storage gate electrode.

[0086] According to some embodiments of the present disclosure, the image sensor further comprises an interconnect structure and a conductive contact, wherein the interconnect structure is disposed on the dielectric layer, and the conductive contact penetrates the dielectric layer and the etch stop layer to electrically connect the interconnect structure and the storage gate electrode.

[0087] According to some embodiments of the present disclosure, the shielding layer surrounds the conductive contact.

[0088] According to some embodiments of the present disclosure, the shielding layer is electrically grounded through the substrate.

[0089] According to some embodiments of the present disclosure, the thickness of the protective layer is between and between.

[0090] According to some embodiments of the present disclosure, the material of the protective layer includes SiO 2 or SiN.

[0091] According to some embodiments of the present disclosure, a method for manufacturing an image sensor includes at least the following steps. A substrate is provided. A storage node is formed in the substrate. A gate dielectric layer is formed on the substrate. A storage gate electrode, an etch stop layer, and a first dielectric layer are sequentially formed on the gate dielectric layer. A stop layer is formed on the first dielectric layer. A portion of the stop layer and a portion of the first dielectric layer are removed to form an opening. The opening exposes at least a portion of the etch stop layer. A protective layer is formed on the etch stop layer and the first dielectric layer. A shielding layer is formed on the protective layer so that the protective layer covers the bottom surface and sidewalls of the shielding layer. A second dielectric layer is formed on the shielding layer.

[0092] According to some embodiments of the present disclosure, the method for manufacturing an image sensor further includes the following steps: forming a contact opening penetrating the second dielectric layer, the first dielectric layer, and the etch stop layer; forming a conductive contact in the contact opening; and forming an interconnect structure on the second dielectric layer, so that the interconnect structure is electrically connected to the storage gate electrode through the conductive contact.

[0093] According to some embodiments of the present disclosure, the step of forming the storage node in the substrate includes at least the following steps: doping the substrate with a first type of dopant to form a first doped region; doping the substrate above the first doped region with a second type of dopant to form a second doped region, wherein the first type of dopant is different from the second type of dopant.

[0094] According to some embodiments of the present disclosure, the step of forming the shielding layer includes at least the following steps: depositing a shielding material layer to fill the opening; removing a portion of the shielding material layer and the termination layer to form the shielding layer.

[0095] According to some embodiments of the present disclosure, the thickness of the protective layer is between and between.

[0096] According to some embodiments of the present disclosure, the material of the protective layer includes SiO 2 or SiN.

[0097] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of the present disclosure.

Claims

1. An image sensor, characterized in that: include: Photosensitive element; A storage element, adjacent to the photosensitive element, and comprising: Storage nodes; A gate dielectric layer, located on the storage node; A storage gate electrode, located on the gate dielectric layer; An etch stop layer, covering the gate dielectric layer and the storage gate electrode; a shielding layer, located on the storage gate electrode; and a protective layer sandwiched between the etch stop layer and the shielding layer, wherein a top surface of the protective layer is coplanar with a top surface of the shielding layer; and The driving circuit is adjacent to the storage element. 2 . The image sensor of claim 1 , wherein the storage element further comprises a dielectric layer located on the shielding layer.

3. The image sensor according to claim 2, further comprising: An interconnect structure, disposed on the dielectric layer; as well as A conductive contact penetrates the dielectric layer and the etch stop layer to electrically connect the interconnect structure and the storage gate electrode. The image sensor according to claim 1 , wherein the storage node comprises a PN junction. The image sensor of claim 1 , wherein the shielding layer is electrically grounded.

6. The image sensor according to claim 1, wherein the thickness of the protective layer is between and between. 7 . The image sensor according to claim 1 , wherein a material of the protection layer comprises SiO 2 or SiN.

8. An image sensor, characterized in that: include: Storage elements, including: substrate; A PN junction is located in the substrate; a gate dielectric layer, located on the substrate; A storage gate electrode, located on the gate dielectric layer; A shielding layer, located on the storage gate electrode; a protective layer covering the bottom surface and side walls of the shielding layer, wherein the top surface of the protective layer is coplanar with the top surface of the shielding layer; and a dielectric layer, located on the shielding layer; a photosensitive element adjacent to the storage element, wherein the photosensitive element is located within the substrate; and The driving circuit is adjacent to the storage element.

9. The image sensor of claim 8, wherein the storage element further comprises an etch stop layer, the etch stop layer being sandwiched between the protective layer and the storage gate electrode, the etch stop layer being sandwiched between the protective layer and the gate dielectric layer, the etch stop layer being sandwiched between the dielectric layer and the gate dielectric layer, and the etch stop layer being sandwiched between the dielectric layer and the storage gate electrode.

10. The image sensor according to claim 9, further comprising: An interconnect structure, disposed on the dielectric layer; as well as A conductive contact penetrates the dielectric layer and the etch stop layer to electrically connect the interconnect structure and the storage gate electrode. The image sensor of claim 10 , wherein the shielding layer surrounds the conductive contact.

12. The image sensor of claim 8, wherein the shielding layer is electrically grounded through the substrate.

13. The image sensor according to claim 8, wherein the thickness of the protective layer is between and between. 14 . The image sensor according to claim 8 , wherein a material of the protection layer comprises SiO 2 or SiN.

15. A method for manufacturing an image sensor, characterized in that: include: forming a storage node in a substrate; forming a gate dielectric layer, a storage gate electrode, and a first dielectric layer in sequence on the substrate; removing a portion of the first dielectric layer to form an opening; Filling the opening with a protection layer and a shielding layer in sequence, wherein the protection layer laterally surrounds the shielding layer, a top surface of the protection layer is coplanar with a top surface of the shielding layer, and at least a portion of the protection layer is located between the storage gate electrode and the shielding layer; and A second dielectric layer is formed on the shielding layer. 16 . The method of manufacturing an image sensor according to claim 15 , further comprising conformally forming an etch stop layer on the gate dielectric layer and the storage gate electrode, wherein at least a portion of the protection layer is sandwiched between the etch stop layer and the shielding layer. 17 . The method of manufacturing an image sensor according to claim 15 , further comprising forming a termination layer on the first dielectric layer, wherein the opening is formed by removing a portion of the first dielectric layer and a portion of the termination layer.

18. The method for manufacturing an image sensor according to claim 17, wherein the step of filling the shielding layer in the opening comprises: depositing a layer of shielding material on the protective layer in the opening; as well as A portion of the shielding material layer and the termination layer are removed to form the shielding layer.

19. The method for manufacturing an image sensor according to claim 15, further comprising: forming a contact opening penetrating the second dielectric layer and the first dielectric layer; forming a conductive contact in the contact opening; as well as An interconnect structure is formed on the second dielectric layer such that the interconnect structure is electrically connected to the storage gate electrode through the conductive contact.

20. The method of manufacturing an image sensor according to claim 15, wherein the step of forming the storage node in the substrate comprises: doping the substrate with a first type of dopant to form a first doped region; as well as The substrate above the first doped region is doped with a second type of dopant to form a second doped region, wherein the first type of dopant is different from the second type of dopant.

21. A method for manufacturing an image sensor, characterized in that: include: providing a substrate; forming a storage node in the substrate; forming a gate dielectric layer on the substrate; forming a storage gate electrode, an etch stop layer, and a first dielectric layer in sequence on the gate dielectric layer; forming a termination layer on the first dielectric layer; removing a portion of the stop layer and a portion of the first dielectric layer to form an opening, wherein the opening exposes at least a portion of the etch stop layer; forming a protective layer on the etch stop layer and the first dielectric layer; forming a shielding layer on the protective layer, so that the protective layer covers the bottom surface and side walls of the shielding layer, and the top surface of the protective layer is coplanar with the top surface of the shielding layer; as well as A second dielectric layer is formed on the shielding layer.

22. The method for manufacturing an image sensor according to claim 21, further comprising: forming a contact opening penetrating the second dielectric layer, the first dielectric layer and the etch stop layer; forming a conductive contact in the contact opening; as well as An interconnect structure is formed on the second dielectric layer such that the interconnect structure is electrically connected to the storage gate electrode through the conductive contact.

23. The method of manufacturing an image sensor according to claim 21, wherein the step of forming the storage node in the substrate comprises: doping the substrate with a first type of dopant to form a first doped region; as well as The substrate above the first doped region is doped with a second type of dopant to form a second doped region, wherein the first type of dopant is different from the second type of dopant.

24. The method for manufacturing an image sensor according to claim 21, wherein the step of forming the shielding layer comprises: depositing a layer of shielding material to fill the opening; as well as A portion of the shielding material layer and the termination layer are removed to form the shielding layer.

25. The method for manufacturing an image sensor according to claim 21, wherein the thickness of the protective layer is between and between. 26 . The method of manufacturing an image sensor according to claim 21 , wherein a material of the protection layer comprises SiO 2 or SiN.

27. A method for manufacturing an image sensor, characterized in that: include: forming a photosensitive element in a substrate; as well as A storage element is formed adjacent to the photosensitive element, comprising: forming a PN junction in the substrate; forming a gate dielectric layer, a storage gate electrode, and a first dielectric layer in sequence on the substrate; removing a portion of the first dielectric layer to form an opening; Filling a protective layer in the opening to cover the sidewalls and bottom surface of the opening; depositing a shielding layer on the protective layer to fill the opening, wherein a top surface of the protective layer is coplanar with a top surface of the shielding layer; and A second dielectric layer is formed on the shielding layer.

28. The method of manufacturing an image sensor according to claim 27, further comprising conformally forming an etch stop layer on the gate dielectric layer and the storage gate electrode, wherein at least a portion of the protection layer is sandwiched between the etch stop layer and the shielding layer. 29 . The method of manufacturing an image sensor according to claim 27 , further comprising forming a termination layer on the first dielectric layer, wherein the opening is formed by removing a portion of the first dielectric layer and a portion of the termination layer.

30. The method of manufacturing an image sensor according to claim 29, wherein the step of depositing the shielding layer comprises: depositing a layer of shielding material on the protective layer in the opening; as well as A portion of the shielding material layer and the termination layer are removed to form the shielding layer.

31. The method of manufacturing an image sensor according to claim 27, further comprising: forming a contact opening penetrating the second dielectric layer and the first dielectric layer; forming a conductive contact in the contact opening; as well as An interconnect structure is formed on the second dielectric layer such that the interconnect structure is electrically connected to the storage gate electrode through the conductive contact.

32. The method for manufacturing an image sensor according to claim 27, wherein the step of forming the PN junction in the substrate comprises: doping the substrate with a first type of dopant to form a first doped region; as well as The substrate above the first doped region is doped with a second type of dopant to form a second doped region, wherein the first type of dopant is different from the second type of dopant.

33. The method of manufacturing an image sensor according to claim 32, wherein the step of forming the photosensitive element in the substrate comprises: doping the substrate with the first type of dopant to form a third doped region; as well as The substrate above the third doped region is doped with the second type of dopant to form a fourth doped region, wherein the first type of dopant is different from the second type of dopant.

34. The method for manufacturing an image sensor according to claim 33, wherein the third doping region of the photosensitive element and the first doping region of the PN junction are formed simultaneously, and the fourth doping region of the photosensitive element and the second doping region of the PN junction are formed simultaneously.

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