Phase detector circuit and method for estimating phase

Abstract

The present application relates to a phase detector circuit and a method for estimating phase. The phase detector circuit includes: an oscillator circuit; an edge detection and correction circuit; a sampler circuit; and an adder circuit. The oscillator circuit is configured to provide a sawtooth oscillator signal. The edge detection and correction circuit is configured to receive an in-phase signal and a quadrature signal, provide an edge detection signal during each edge of the in-phase signal and the quadrature signal, and provide an edge correction signal based on whether the edge is in the in-phase signal or in the quadrature signal and whether the edge is a rising edge or a falling edge. The sampler circuit is configured to sample the sawtooth oscillator signal in response to the edge detection signal. The adder circuit is configured to subtract the edge correction signal from the sampled sawtooth oscillator signal to provide a phase estimation signal.

Description

[0001] Related Applications

[0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 62 / 581,890, filed on November 6, 2017, which is incorporated herein by reference in its entirety. Field of the Invention

[0003] The present disclosure relates to systems and methods for measuring the phase of a signal. Background Art

[0004] The phase of a signal provides valuable information that may be useful in several applications. For example, the phase of a wireless communication signal received at multiple antennas can be used to determine the angle of arrival of the wireless communication signal, which indicates a direction from which the wireless communication signal is transmitted relative to the receiver transmission. Conventional systems and methods for measuring the phase of wireless communication signals rely on high linearity receivers. However, high linearity receivers are costly in terms of expense and power consumption. Therefore, phase measurements and therefore angle of arrival estimates are not available for low-cost and low-power applications such as Internet of Things (IoT) devices. In view of the above, there is a need for systems and methods for measuring the phase of wireless receive signals suitable for nonlinear (e.g., hard limiting) receiver architectures. Summary of the invention

[0005] In one embodiment, a phase detector circuit includes: an oscillator circuit; an edge detection and correction circuit; a sampler circuit; and an adder circuit. The oscillator circuit is configured to provide a sawtooth oscillator signal. The edge detection and correction circuit is configured to receive an in-phase signal and a quadrature signal, provide an edge detection signal during each edge of the in-phase signal and the quadrature signal, and provide an edge correction signal based on whether the edge is in the in-phase signal or in the quadrature signal and whether the edge is a rising edge or a falling edge. The sampler circuit is coupled to the oscillator circuit and the edge detection and correction circuit. The sampler circuit is configured to sample the sawtooth oscillator signal in response to the edge detection signal. The adder circuit is coupled to the sampler circuit and the edge detection and correction circuit. The adder circuit is configured to subtract the edge correction signal from the sampled sawtooth oscillator signal to provide a phase estimation signal. By providing the phase estimate signal based on the edges of the in-phase signal and the quadrature signal, the phase estimate signal may provide repeatedly accurate phase measurements even when the in-phase signal and the quadrature signal are components of a hard-limited wireless communication signal.

[0006] Those skilled in the art will appreciate the scope of the present disclosure and recognize additional aspects of the present disclosure after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the disclosure, and together with the description, serve to explain the principles of the disclosure.

[0008] Figure 1 A phase detector circuit according to one embodiment of the present disclosure is shown.

[0009] Figure 2 is a graph illustrating the operation of a phase detector circuit according to one embodiment of the present disclosure.

[0010] Figure 3 is a flow chart illustrating a method for estimating the phase of a signal according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0011] The embodiments set forth below represent the necessary information that enables those skilled in the art to practice the embodiments, and illustrate the best mode for practicing the embodiments. After reading the following description in accordance with the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure, and will recognize the application of these concepts not specifically proposed herein. It should be understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0012] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, a first element may be named a second element, and similarly, a second element may be named a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items.

[0013] It will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element or extending "on" another element, it can be directly on another element or directly extending to another element, or there may also be an intermediate element. In contrast, when an element is referred to as being "directly on" another element or extending "directly" to another element, there is no intermediate element. Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element or extending "on" another element, it can be directly on another element or directly on another element, or there may also be an intermediate element. In contrast, when an element is referred to as being "directly on" another element or extending "directly on" another element, there is no intermediate element. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or there may be an intermediate element. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0014] Relative terms, such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical", may be used herein to describe the relationship of one element, layer or region to another element, layer or region as shown in the figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation shown in the figures.

[0015] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms as well. It will also be understood that the terms "comprises", "comprising", "includes", and / or "including" when used herein indicate the presence of stated features, integers, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups thereof.

[0016] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that the terms used herein should be interpreted as having a meaning consistent with their meanings in the context of this specification and the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined in this document.

[0017] Figure 1A phase detector circuit 10 is shown according to one embodiment of the present disclosure. The phase detector circuit 10 includes an oscillator circuit 12, a sampler circuit 14 coupled to the oscillator circuit 12, an adder circuit 16 coupled to the sampler circuit 14, an averaging circuit 18 coupled to the adder circuit 16, and an edge detection and correction circuit 20 coupled to the sampler circuit 14 and the adder circuit 16.

[0018] In operation, the oscillator circuit 12 provides a sawtooth oscillator signal OSC st , which has an input frequency signal F in The determined frequency is at a value varying between 0 and 360. The edge detection and correction circuit 20 receives the in-phase signal I in and the quadrature input signal Q in And provide edge detection signal E det and edge correction signal E corr . Edge detection signal E det Only when the in-phase signal I in and the quadrature signal Q in In response to the edge detection signal E det , the sampler circuit 14 is coupled to the sawtooth oscillator signal OSC st Sampling is performed to sample the sawtooth oscillator signal OSC st (t) is provided to the adder circuit 16. The adder circuit 16 is obtained from the sampled sawtooth oscillator signal OSC st (t) minus the edge correction signal E corr To provide a phase estimation signal PH est .

[0019] When the edge detection and correction circuit 20 detects the in-phase signal I in When the edge correction signal E corr The value of has is 180. When the edge detection and correction circuit 20 detects the in-phase signal I in At the falling edge of the edge correction signal E corr The value of has is 0. When the edge detection and correction circuit 20 detects the quadrature signal Q in When the edge correction signal E corr The value of is 270. When the edge detection and correction circuit 20 detects the quadrature signal Q in At the falling edge of the edge correction signal E corr has a value of 90.

[0020] Edge correction signal E corr The effect is that the in-phase signal I in and the quadrature signal Q in Each edge of the sawtooth oscillator signal OSC will be sampledst (t) Normalization. Take the in-phase signal I in As a reference, those skilled in the art will readily appreciate that the in-phase signal I in The rising edge of the signal will be 180 degrees out of phase, and the quadrature signal Q in The falling edge of the signal will be 270 degrees out of phase, and the quadrature signal Q in The rising edge of will be 90 degrees out of phase with this edge. Therefore, the phase estimate signal PH est Reflected in the same phase signal I in and the quadrature signal Q in A normalized estimate of the phase at each edge of .

[0021] The averaging circuit 18 includes an average adder 22, a delay 24, and a frequency divider 26. The phase estimation signal PH est is provided to an average summer 22 where the phase estimate signal is added to one or more previous phase estimates held in a delay 24. The combined phase estimate at the output of the average summer 22 is divided by the number of phase estimates to provide an average phase estimate AVG(PH est ).

[0022] Although the oscillator circuit 12, the sampler circuit 14, the adder circuit 16, the averaging circuit 18 and the edge detection and correction circuit 20 are Figure 1 Although shown as separate functional components in the drawings, those skilled in the art will readily appreciate that the functionality provided thereby may be further separated or combined into any number of different functional components, all of which are contemplated herein.

[0023] Figure 2 is a sawtooth oscillator signal OSC st , in-phase signal I in , orthogonal signal Q in and edge detection signal E det The curve graph of Figure 2 In the example, the Y axis represents the signal amplitude and the X axis represents the time. It is worth noting that the in-phase signal I in , orthogonal signal Q in and edge detection signal E det Arbitrarily placed relative to the Y axis. As shown in the figure, the sawtooth oscillator signal OSC st The value of has varies between 0 and 360. The in-phase signal I in and the quadrature signal Q in is shown as a 1-bit quantized signal, as is the phase signal I in and the quadrature signal Q in This will occur when the in-phase signal I is a component of a wireless communication signal received by a hard-limiting receiver architecture.in and the quadrature signal Q in is represented as a binary signal, where all information about its phase is contained at its edge. It is worth noting that the in-phase signal I in and the quadrature signal Q in The edge of represents the zero crossing of its non-quantized and non-limited version, which will usually be a sinusoidal signal. det is shown as the in-phase signal I in and the quadrature signal Q in provided at each edge of the .

[0024] like Figure 2 As shown, in the in-phase signal I in At the falling edge of the sawtooth oscillator signal OSC st The value is about 10. In the in-phase signal I in At the rising edge of the sawtooth oscillator signal OSC st The value is about 190. From the sawtooth oscillator signal OSC st The value of the in-phase signal I in The edge correction signal E provided by the edge detection and correction circuit 20 during the rising edge of corr ) by subtracting 180 to provide the in-phase signal I in The same value 10 is obtained during the falling edge of the quadrature signal Q in At the rising edge of the sawtooth oscillator signal OSC st The value is about 280. From the sawtooth oscillator signal OSC st The value of the in-phase signal I in The edge correction signal E provided by the edge detection and correction circuit 20 during the rising edge of corr ) minus 270 to provide the quadrature signal Q in Finally, the quadrature signal Q in At the falling edge of the sawtooth oscillator, the value of the sawtooth oscillator is about 100. st The value of the in-phase signal I in The edge correction signal E provided by the edge detection and correction circuit 20 during the falling edge of corr subtracting 90 from the value of in The same value 10 is obtained during the falling edge of the in-phase signal I in and the quadrature signal Q in The phase estimate is obtained at each edge of . Although the above example is given, so that the in-phase signal I in and the quadrature signal Q inThe phase estimate at each edge of I produces the same value, but the values ​​will generally be different. The averaging circuit 18 is therefore in and the quadrature signal Q in It is important to average the differences between the phase estimates at each edge of , so that the average phase estimate signal AVG(PH est ) more accurately reflects the in-phase signal I in and the quadrature signal Q in The actual phase of the wireless communication signal.

[0025] Although the phase detector circuit 10 can be operated to detect the in-phase signal I in and the quadrature signal Q in Sampling is performed to provide an average phase estimate signal AVG(PH) for any number of its edges. est ), but in one embodiment, the in-phase signal I in and the quadrature signal Q in At least four phase estimation signals PH of at least four edges of est The average is calculated to provide an average phase estimate signal AVG(PH est ).

[0026] As discussed above, the oscillator circuit 12 generates an oscillator with an input frequency F in Although the receiving input frequency F is not shown in , but the edge detection and correction circuit 20 can also operate at a frequency that determines its sampling rate. Those skilled in the art will readily appreciate that the input frequency F in should be chosen to be significantly higher than the in-phase signal I in and the quadrature signal Q in In one embodiment, the input frequency F in Should be compared with the in-phase signal I in and the quadrature signal Q in The frequency is at least two orders of magnitude higher. For example, if the in-phase signal I in and the quadrature signal Q in The frequency is 1.75MHz, so the input frequency F in can be selected as 192MHz. This means that the in-phase signal I in and the quadrature signal Q in There are 192 / 1.75 samples in each cycle of , providing a resolution of approximately 3.3 degrees per sample (360 degrees in each cycle).

[0027] The phase detector circuit 10 may be particularly useful in applications where absolute phase measurement is not required, such as for angle of arrival estimation where only the relative phase between identical wireless communication signals received at different antennas is required. Notably, the phase detector circuit 10 may be less susceptible to common system error sources than conventional phase measurement circuits. Typical system error sources in conventional phase estimation circuits include: IQ phase offset, where a deviation from the ideal 90 degree phase separation between the in-phase signal and the quadrature signal occurs; IQ imbalance, where a difference in gain exists between the in-phase signal and the quadrature signal; and DC offset in the in-phase signal and the quadrature signal.

[0028] Regarding the IQ phase offset, this will cause the in-phase signal I in and the quadrature signal Q in Different phase estimates PH are generated at the edge of est , which in turn makes the average phase estimate AVG(PH est ) displacement. However, this displacement is independent of the absolute input phase and always gives the same phase shift or offset in the measured phase. In applications where only the relative phase or phase difference between the signals is required, this fixed phase offset does not cause degradation.

[0029] Regarding IQ imbalance, this will be the case for the in-phase signal I in and the quadrature signal Q in A hard-limited receiver quantized to 1 bit (as discussed above) is insignificant since hard limiting produces only two signal levels and thus eliminates gain differences.

[0030] Regarding DC offset, although this will affect the in-phase signal I in and / or quadrature signal Q in The duty cycle of the phase shift signal AVG(PH) has an effect, but the changes are symmetrical and will therefore cancel out since both the rising and falling edges are included in the average phase estimate signal AVG(PH est )middle.

[0031] Figure 3 A method for estimating phase according to an embodiment of the present disclosure is shown. First, an in-phase signal and a quadrature signal are received (step 100). A sawtooth oscillator signal is generated (step 102). The sawtooth oscillator signal is sampled at each edge of the in-phase signal and the quadrature signal (step 104) to provide a sampled sawtooth oscillator signal. The sampled sawtooth oscillator signal (step 106) is compensated to provide a phase estimation signal based on whether the edge is on the in-phase signal or on the quadrature signal and whether the edge is a rising edge or a falling edge. Finally, the above process is repeated as many times as needed (step 108), and the multiple phase estimation signals are averaged (step 110) to provide an average phase estimation signal.

[0032] As discussed above, the value of the sawtooth oscillator signal varies between 0 and 360. Also as discussed above, compensation of the sampled sawtooth oscillator based on whether the edge is on the in-phase signal or the quadrature signal and whether the edge is a rising edge can be accomplished by: when the edge is a falling edge of the in-phase signal, the value of the sampled sawtooth oscillator signal is not changed; when the edge is a rising edge of the in-phase signal, 180 is subtracted from the sampled sawtooth oscillator signal; when the edge is a rising edge of the quadrature signal, 270 is subtracted from the sampled sawtooth oscillator signal; and when the edge is a falling edge of the quadrature signal, 90 is subtracted from the sampled sawtooth oscillator signal. The in-phase signal and the quadrature signal can be components of a wireless communication signal. In one embodiment, the wireless communication signal is hard limited, and the in-phase signal and the quadrature signal are quantized to 1-bit signals.

[0033] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the appended claims.

Claims

1. A phase detector circuit, the phase detector circuit comprising: an oscillator circuit configured to provide a sawtooth oscillator signal; An edge detection and correction circuit, the edge detection and correction circuit being configured to: Receive in-phase and quadrature signals; providing an edge detection signal during each edge of the in-phase signal and the quadrature signal; and providing an edge correction signal, wherein the edge correction signal is based on whether the edge is in the in-phase signal or in the quadrature signal and whether the edge is a rising edge or a falling edge; a sampler circuit coupled to the oscillator circuit and the edge detection and correction circuit, the sampler circuit being configured to sample the sawtooth oscillator signal in response to the edge detection signal; as well as an adder circuit coupled to the sampler circuit and the edge detection and correction circuit, the adder circuit being configured to subtract the edge correction signal from the sampled sawtooth oscillator signal so that the sampled sawtooth oscillator signal is normalized for each edge of the in-phase signal and the quadrature signal to provide a phase estimation signal.

2. The phase detector circuit of claim 1 , further comprising an averaging circuit coupled to the adder circuit and configured to receive and average a plurality of phase estimation signals to provide an average phase estimation signal.

3. The phase detector circuit of claim 1, wherein the oscillator circuit is configured to provide the sawtooth oscillator signal such that a value of the sawtooth oscillator signal varies between 0 and 360.

4. The phase detector circuit of claim 3 , wherein the edge detection and correction circuit is configured to provide the edge correction signal such that: When the edge is a falling edge of the in-phase signal, the value of the edge correction signal is 0; When the edge is a rising edge of the in-phase signal, the value of the edge correction signal is 180; When the edge is a falling edge of the quadrature signal, the value of the edge correction signal is 90; and When the edge is a rising edge of the quadrature signal, the value of the edge correction signal is 270.

5. The phase detector circuit of claim 1, wherein the in-phase signal and the quadrature signal are components of a wireless communication signal.

6. The phase detector circuit of claim 5, wherein the wireless communication signal is a hard-limited signal.

7. A method for estimating phase, the method comprising: Receive in-phase and quadrature signals through edge detection and correction circuits; Generate a sawtooth oscillator signal through an oscillator circuit; sampling the sawtooth oscillator signal at each edge of the in-phase signal and the quadrature signal by a sampler circuit coupled to the oscillator circuit and the edge detection and correction circuit; as well as compensating the sampled sawtooth oscillator signal by an adder circuit based on whether the edge is in the in-phase signal or the quadrature signal and whether the edge is a rising edge or a falling edge so that the sampled sawtooth oscillator signal is normalized for each edge of the in-phase signal and the quadrature signal to provide a phase estimate signal, wherein the adder circuit is coupled to the sampler circuit and the edge detection and correction circuit.

8. The method of claim 7, further comprising averaging a plurality of phase estimate signals by an averaging circuit to provide an average phase estimate signal, the averaging circuit being coupled to the adder circuit. 9 . The method of claim 7 , wherein generating the sawtooth oscillator signal comprises generating the sawtooth oscillator signal such that a value of the sawtooth oscillator signal varies between 0 and 360.

10. The method of claim 7, wherein compensating the sampled sawtooth oscillator signal to provide a phase estimate signal based on whether the edge is in the in-phase signal or in the quadrature signal and whether the edge is a rising edge or a falling edge comprises: When the edge is a falling edge of the in-phase signal, the value of the sampled sawtooth oscillator signal is not changed; When the edge is a rising edge of the in-phase signal, subtract 180 from the sampled sawtooth oscillator signal; When the edge is a falling edge of the quadrature signal, subtract 90 from the sampled sawtooth oscillator signal; and • When the edge is a rising edge of the quadrature signal, subtract 270 from the sampled sawtooth oscillator signal.

11. The method of claim 7, wherein the in-phase signal and the quadrature signal are components of a wireless communication signal.

12. The method of claim 11, wherein the wireless communication signal is a hard-limited signal.

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