Clock synchronization device and clock synchronization method of distributed system

Abstract

The invention belongs to the technical field of clock synchronization, and provides a clock synchronization device and a clock synchronization method of a distributed system. Wherein the distributed system comprises a master node and a plurality of slave nodes, the master node and the slave nodes are in two-way communication, and the clock synchronization device comprises a single-core optical cable, an optical switch and a double-frequency-mixing phase discriminator and is used for connecting the master node and the slave nodes; the optical switch is switched between a communication mode and a short circuit mode; when the optical switch is in a communication mode, the single-core optical cable is connected with the master node for transmitting and the slave node for receiving, or is connected with the slave node for transmitting and the master node for receiving; when the optical switch is in a short-circuit mode, the single-core optical cable is connected with transceiving of the master node or transceiving of the slave node; and the dual-mixing phase discriminator is used for measuring the phase difference between the local clock and the received data recovery clock. According to the invention, respective transmit-receive delays of the master and slave nodes and bidirectional transmission delays between the master and slave nodes can be obtained, the clock difference can be conveniently obtained according to the unidirectional transmission delays, and the synchronization precision is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of clock synchronization, and in particular to a clock synchronization device and a clock synchronization method for a distributed system. Background Art

[0002] Distributed systems are currently widely used in electromagnetic wave measurement and control. With increasing real-time requirements, time synchronization errors introduced by spatial distance in distributed systems are becoming increasingly significant. Nodes are distributed across diverse locations, with distances ranging from a few meters to hundreds of kilometers. Each node has its own internal clock source (i.e., a local clock source) that provides the operating clock for local digital circuits. Due to manufacturing variations in the crystal oscillator and PLL circuits used in these clock sources, the frequency of each node's local clock source varies. Furthermore, node startup times are completely random, and the clock source phases are independent. To ensure that all clocks in the system operate at a common frequency and phase, known as clock resonance, a single node's clock must be transmitted to all nodes as a reference. This introduces another problem: transmission delay due to spatial distance. For example, the speed of light in optical fiber is 200,000 km / s, so every nanosecond (ns) transmits 0.2 meters. Therefore, for nodes distributed over a few kilometers, delays can be on the order of microseconds (us). For systems like LiDAR, which have a transmission window of only nanoseconds, these delays must be eliminated through synchronization systems.

[0003] To eliminate this problem, the Synchronous Ethernet,PTP precision time protocol (IEEE1588) has been proposed.,PTP protocol is implemented through network packets with timestamps, such as, Figure 1 As shown in the figure, the master and slave nodes each have their own time information. The master node periodically sends synchronization messages, and the timestamp information of the sending time t1 is then sent to the slave node via a follow-up message. The receiving end of the slave node receives the synchronization message and records the local reception time t2, and receives the follow-up message to obtain t1. The slave node sends a delay request message and records the local sending time t3. The master node receives the delay request message, records the reception time t4, and replies to the slave node via a delay response message. The slave node receives the delay request response message, obtains t4, calculates the time difference between the master and slave nodes based on t1, t2, t3, and t4, and adjusts the local time to achieve synchronization.

[0004] The accuracy of the above protocol depends primarily on the accuracy of the four timestamps. However, the packet transmission delay in network communications is not fixed. The network card communication interface, operating system, and application software all affect the delay, reducing the accuracy of the timestamp. Therefore, timestamps must be processed at the network physical layer. Furthermore, Synchronous Ethernet and the PTP precision time protocol (IEEE1588) are limited by the clock period, and their synchronization accuracy cannot be better than the time period (8ns for a 125MHz Gigabit Ethernet clock). To further improve timing accuracy, a dual-mixer phase detector solution has been proposed to obtain time differences within the time period.

[0005] The above operation assumes that the communication delays from the master node to the slave node and from the slave node to the master node are identical. However, in reality, due to differences in electronic components, circuit boards, ambient temperature, and other factors, the two are not exactly the same. Therefore, to further improve the accuracy of synchronization time, a method that can account for the influence of asymmetric factors is needed. Summary of the Invention

[0006] In response to the defects in the prior art, the present invention provides a clock synchronization device and a clock synchronization method for a distributed system to solve the problem of asymmetric communication delay between the transmitting end of the master node and the receiving end of the slave node, and between the sending end of the slave node and the receiving end of the master node in the current distributed system clock synchronization.

[0007] In a first aspect, the present invention provides a clock synchronization device for a distributed system, wherein the distributed system includes a master node and a plurality of slave nodes, and the master node and the slave nodes communicate with each other bidirectionally. The clock synchronization device includes:

[0008] Single-core optical cable, used to connect the master node and the slave node;

[0009] An optical switch, the optical switch being switchable between a communication mode and a shorting mode; when the optical switch is in the communication mode, a single-core optical cable connects a transmitting end of the master node and a receiving end of the slave node, or connects a transmitting end of the slave node and a receiving end of the master node; when the optical switch is in the shorting mode, the single-core optical cable connects a receiving end and a transmitting end of the master node, or connects a receiving end and a transmitting end of the slave node;

[0010] A dual-mixer phase detector is provided at the master node and the slave node respectively, and is used to measure the phase difference between the local clock of the master node / slave node and the received data recovery clock; wherein the data recovery clock is the local clock of the slave node / master node extracted by the master node / slave node from the data link.

[0011] It can be seen from the above technical solution that the clock synchronization device of a distributed system provided by the present invention can switch the connection between the master and slave nodes through an optical switch, and the control device as a whole switches between the communication mode and the short-circuit mode, which can facilitate the acquisition of the respective transmission and reception delays of the master and slave nodes, and the two-way transmission delay between the master and slave nodes, so as to facilitate the subsequent acquisition of the clock difference, realize the clock synchronization of the master and slave nodes, and improve the synchronization accuracy.

[0012] Optionally, the optical switch includes a master node optical switch and a slave node optical switch.

[0013] The master node optical switch includes a master node optical switch A and a master node optical switch B, wherein the master node optical switch A is connected to the transmitting end of the master node, and the master node optical switch B is connected to the receiving end of the master node;

[0014] The slave node optical switch includes a slave node optical switch A and a slave node optical switch B, wherein the slave node optical switch A is connected to the transmitting end of the slave node, and the slave node optical switch B is connected to the receiving end of the slave node;

[0015] When the optical switch is in the communication mode, the transmitting end of the master node and the receiving end of the slave node are connected through the master node switch A and the slave node switch B, or the transmitting end of the slave node and the receiving end of the master node are connected through the slave node switch A and the master node switch B;

[0016] When the optical switch is in short-circuit mode, the transmitting end and the receiving end of the master node are connected through the master node switch A and the master node switch B, and / or the transmitting end and the receiving end of the slave node are connected through the slave node switch A and the slave node switch B.

[0017] In a second aspect, the present invention provides a clock synchronization method, based on a clock synchronization device for a distributed system provided by any possible implementation of the first aspect, comprising:

[0018] Get the delay correction value Delay_mt of the master and slave nodes cor 、Delay_sr cor 、Delay_st cor 、Delay_mr cor The correction value is determined based on the pre-acquired Delay_mt', Delay_sr', Delay_st', Delay_mr' and the correction coefficient, where Delay_mt represents the sending delay of the master node, Delay_sr represents the receiving delay of the slave node, Delay_st represents the sending delay of the slave node, and Delay_mr represents the receiving delay of the master node. The subscript cor represents the correction value of the delay, and the superscript ' represents the value obtained by the clock synchronization device in a calibration environment.

[0019] According to the delay correction value Delay_mtcor 、Delay_sr cor 、Delay_st cor 、Delay_mr cor , obtain the clock difference ΔT;

[0020] The slave node is controlled to compensate the clock difference ΔT to complete the clock synchronization of the master node and the slave node.

[0021] It can be seen from the above technical solution that the present invention corrects the delay between the receiving end and the transmitting end of the master and slave nodes measured during use by using the calibration value measured in the calibration environment, thereby reducing the impact of the ambient temperature on the delay and reducing the error of clock synchronization.

[0022] Optionally, a method for obtaining the delays Delay_mt', Delay_sr', Delay_st', and Delay_mr' sent by the receiving end of the master and slave nodes includes:

[0023] Controlling the clock synchronization device to be in a communication mode under a calibration environment, obtaining timestamps t1', t2', t3', t4' and a local time difference ΔT'; wherein t2'-t1'=Delay_mt'+Delay_λ1'+Delay_sr'+ΔT', t4'-t3'=Delay_st'+Delay_λ2'+Delay_mr'-ΔT', t1' is the local sending time of the master node, t2' is the local receiving time of the slave node, t3' is the local sending time of the slave node, t4' is the local receiving time of the master node, Delay_λ1' and Delay_λ2' are the optical fiber delays from the transmitting end of the master node to the receiving end of the slave node and the optical fiber delays from the transmitting end of the slave node to the receiving end of the master node, respectively;

[0024] Control the clock synchronization device to be in short-circuit mode under a calibration environment, and obtain the master node receiving and sending delay D0' and the slave node receiving and sending delay D1'; wherein D0'=Delay_mt'+Delay_mr', D1'=Delay_st'+Delay_sr';

[0025] Delay_mt', Delay_sr', Delay_st', and Delay_sr' are calculated.

[0026] Optionally, the fiber delay Delay_λ1 from the transmitting end of the master node to the receiving end of the slave node and the fiber delay Delay_λ2 from the transmitting end of the slave node to the receiving end of the master node are determined according to the length of the single-core optical cable and the refractive index λ1 of the single-core optical cable from the master node to the slave node and the refractive index λ2 from the slave node to the master node.

[0027] From the above technical solution, it can be seen that by considering the different refractive indices of bidirectional optical fiber transmission, the optical fiber delays Delay_λ1 and Delay_λ2 are obtained respectively, which reduces the impact of bidirectional asymmetry of optical fiber transmission on delay and improves the accuracy of clock synchronization.

[0028] Optionally, Delay_mt cor 、Delay_mr cor 、Delay_st cor 、Delay_sr cor Methods for obtaining include:

[0029] Control the synchronous clock device to be in a short-circuit mode, and obtain the master node receiving and sending delay D0 and the slave node receiving and sending delay D1;

[0030] Get the master node correction coefficient k m and the slave node correction factor k s ;k m =D0 / D0',k s =D1 / D1';

[0031] According to the correction coefficient, calculate the correction delay; Delay_mt cor =Delay_mt'·k m , Delay_mr cor =Delay_mr'·k m ;Delay_st cor =Delay_st'·k s , Delay_sr cor =Delay_sr'·k s .

[0032] Optionally, the master node receiving and sending delay D0, the slave node receiving and sending delay D1, the time difference t2-t1, and the time difference t4-t3 are all calculated based on the phase difference collected by the dual-mixer phase detector.

[0033] By adopting the above technical solution, this application has the following beneficial effects:

[0034] The present invention provides a clock synchronization device for a distributed system. The device can switch the connection between the master and slave nodes through an optical switch, and control the entire device to switch between communication mode and short-circuit mode. This facilitates obtaining the transmission and reception delays of the master and slave nodes, as well as the two-way transmission delay between the master and slave nodes. This facilitates the subsequent acquisition of the clock difference, achieving master and slave node clock synchronization and improving synchronization accuracy.

[0035] The present invention takes into account the problem of inconsistent two-way transmission between the master node and the slave node, and calculates the master node to the slave node and the slave node to the master node respectively; then, by calculating the calibration value measured in the calibration environment, the receiving end transmission delay of the master and slave nodes measured during use is corrected, thereby reducing the influence of the ambient temperature on the delay and reducing the error of clock synchronization. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly describes the drawings required for the specific embodiments or the description of the prior art. Similar elements or parts are generally identified by similar reference numerals throughout the drawings. Elements or parts in the drawings are not necessarily drawn to scale.

[0037] Figure 1 A schematic diagram of the PTP protocol involved in background technology is shown;

[0038] Figure 2 A schematic diagram of a clock synchronization device for a distributed system provided by an embodiment of the present invention is shown;

[0039] Figure 3 A flowchart of a clock synchronization method provided by an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0040] The following embodiments of the technical solution of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention and are therefore only examples and are not intended to limit the scope of protection of the present invention.

[0041] It should be noted that, unless otherwise specified, the technical or scientific terms used in this application should have the common meanings understood by those skilled in the art to which the present invention belongs.

[0042] In accordance with Figure 1 The timestamps t1, t2, t3, and t4 shown are used to calculate the time difference between the master and slave nodes. When synchronization is achieved, the calculation method is as follows:

[0043] Link delay from master node to slave node:

[0044] delay = (t4-t3+t2-t1) / 2 (1)

[0045] Time difference between master and slave nodes:

[0046] offset = t2-t1-delay = (t2-t1+t3-t4) / 2 (2)

[0047] However, this depends on the accuracy of the four timestamps t1, t2, t3, and t4, and the communication delays from the master node to the slave node and from the slave node to the master node must be the same, otherwise the accuracy cannot be guaranteed. On this basis, the present invention proposes a clock synchronization device and clock synchronization method for a distributed system.

[0048] Example 1

[0049] This embodiment provides a clock synchronization device for a distributed system, wherein the distributed system used includes a master node and several slave nodes, and the master node and the slave nodes communicate with each other in a bidirectional manner. Figure 2 As shown, the clock synchronization device includes a single-core optical cable, an optical switch and a dual-frequency phase detector. The single-core optical cable is used to connect the master node and the slave node; the optical switch switches between a communication mode and a short-circuit mode; when the optical switch is in the communication mode, the single-core optical cable connects the transmitter of the master node and the receiver of the slave node, or connects the transmitter of the slave node and the receiver of the master node; when the optical switch is in the short-circuit mode, the single-core optical cable connects the receiver and transmitter of the master node, or connects the receiver and transmitter of the slave node; the dual-frequency phase detector is respectively provided at the master node and the slave node, and is used to measure the phase difference between the local clock of the master node / slave node and the received data recovery clock; wherein the data recovery clock is the local clock of the slave node / master node extracted by the master node / slave node from the data link.

[0050] Based on this, the connection between the master and slave nodes can be switched through an optical switch, and the control device as a whole can be switched between communication mode and short-circuit mode, so as to facilitate the acquisition of the respective transmission and reception delays of the master and slave nodes; on this basis, by determining the length of a single-core optical cable, it is also convenient to subsequently obtain the optical fiber delay from the transmitting end of the master node to the receiving end of the slave node, and from the transmitting end of the slave node to the receiving end of the master node in a calibration environment, so as to facilitate the subsequent compensation of the clock difference, thereby improving the accuracy of clock synchronization.

[0051] Specifically, a distributed system consists of a master node and n slave nodes. The master node communicates bidirectionally with each slave node via a high-speed serial bus (SerDes). The SerDes communication interface only has a data line, not a clock line. The receiver extracts the data clock from the data link using a CDR circuit. The extracted clock frequency error has good long-term accuracy. The slave node's local clock tracks the data clock using DDMTD to ensure that the two frequencies are consistent. However, in real applications, the phase difference between the two may vary due to environmental factors such as temperature changes and power supply voltage fluctuations.

[0052] The clock sent by the serdes of the slave node still uses the clock extracted from the data link just received.

[0053] Specifically, the optical switch includes a master node optical switch and a slave node optical switch.

[0054] The master node optical switch includes a master node optical switch A and a master node optical switch B, wherein the master node optical switch A is connected to the transmitting end of the master node, and the master node optical switch B is connected to the receiving end of the master node;

[0055] The slave node optical switch includes a slave node optical switch A and a slave node optical switch B, wherein the slave node optical switch A is connected to a transmitting end of the slave node, and the slave node optical switch B is connected to a receiving end of the slave node;

[0056] When the optical switch is in communication mode, transmission and reception are realized between the master node and the slave node. The transmitting end of the master node and the receiving end of the slave node are connected through the master node switch A and the slave node switch B, or the transmitting end of the slave node and the receiving end of the master node are connected through the slave node switch A and the master node switch B.

[0057] When the optical switch is in short-circuit mode, the master / slave node's own transmission and reception delay can be obtained, that is, the transmission and reception delay from the master node's transmitter to the master node's receiver, or from the slave node's transmitter to the slave node's receiver. In this case, the master node's transmitter and receiver are connected through master node switches A and B, and / or the slave node's transmitter and receiver are connected through slave node switches A and B.

[0058] In practice, the slave node passes the output voltage of the dual-mixer phase detector through a low-pass filter (LP) and then feeds it into a voltage-controlled oscillator (VCO) that generates the local clock, forming a phase-locked loop (PLL) circuit that adjusts and locks the slave node's clock phase. The master node passes the output voltage of the dual-mixer phase detector through a low-pass filter (LP) and then feeds it into an ADC to obtain digital information representing the phase difference. Phase difference, delay, and other information are transmitted between the master and slave nodes via a data communication link.

[0059] Example 2

[0060] The transmission delay between the master and slave nodes is Delay_mt when the master node sends data, Delay_mr when the master node receives data, Delay_st when the slave node sends data, and Delay_sr when the slave node receives data. Assuming that the master node sends data to the slave node via a single-core optical cable using a laser with wavelength λ1, the delay of the optical signal in the single-core optical cable is Delay_λ1. Conversely, the slave node sends data to the master node using wavelength λ2, with a delay of Delay_λ2. In addition, assume that the local time difference between the master node and the slave node is ΔT, that is, the time difference between the local times of the two nodes is obtained at the same time. Therefore, for example Figure 1In the PTP synchronization mechanism shown, t2-t1=Delay_mt+Delay_λ1+Delay_sr+ΔT, and t4-t3=Delay_st+Delay_λ2+Delay_mr-ΔT. At this point, as long as Delay_mt+Delay_sr, Delay_λ1, or Delay_st+Delay_mr, Delay_λ2 is known, ΔT can be obtained.

[0061] For the above method of calculating ΔT, the required Delay_mt+Delay_sr and Delay_st+Delay_mr can be obtained through calibration. That is, the master node and the slave node are connected to an optical fiber of known length, and t1, t2, t3, and t4 are recorded. The local times of both nodes are simultaneously collected to obtain the time difference ΔT in advance. When the optical fiber length and laser wavelength are known, Delay_λ1 and Delay_λ2 are obtained, and thus Delay_mt+Delay_sr and Delay_st+Delay_mr are obtained.

[0062] Ideally, if the ambient temperature and other environmental factors of the master and slave nodes are consistent with the calibration environment, Delay_mt + Delay_sr and Delay_st + Delay_mr are very close to the calibration values. Even if the fiber lengths are different, because the laser wavelengths λ1 and λ2 are known, the speed of light within the fiber is correlated, and Delay_λ1 and Delay_λ2 are also correlated. Formula (1) eliminates ΔT, and Delay_λ1 and Delay_λ2 can be calculated.

[0063] However, in actual use, the ambient temperature of the master and slave nodes may not be consistent with the calibration environment, resulting in errors in the above calculation method. To address the inconsistency caused by ambient temperature, this embodiment obtains the calibrated transmit and receive delays in the calibration environment and, based on a real-time calibration method, calculates the corrected transmit and receive delays using a correction coefficient to reduce clock synchronization errors.

[0064] like Figure 3 As shown, this embodiment provides a clock synchronization method, based on the clock synchronization device of the distributed system provided in Example 1, including:

[0065] S100. Control the clock synchronization device to be in a communication mode under a calibration environment, and obtain the time difference t2-t1 or the time difference t4-t3.

[0066] S200. Obtain the delay correction value Delay_mt of the master and slave nodes cor 、Delay_sr cor 、Delay_st cor 、Delay_mrcor ; The correction value is determined based on the pre-acquired calibration values Delay_mt', Delay_sr', Delay_st', Delay_mr' and the correction coefficient, Delay_mt represents the sending delay of the master node, Delay_sr represents the receiving delay of the slave node, Delay_st represents the sending delay of the slave node, Delay_mr represents the receiving delay of the master node, the subscript cor represents the correction value of the delay, and the superscript ' represents the value obtained by the clock synchronization device under the calibration environment.

[0067] When the clock synchronization device is in short-circuit mode, the transmitter of the master / slave node sends data to the receiver, and the master node transmission and reception delay D0 = Delay_mt + Delay_mr, and the slave node receiving end transmission delay D1 = Delay_st + Delay_sr; on this basis, the clock synchronization device is controlled to the communication mode, and the following can be obtained: Figure 1 The four timestamps shown are t1, t2, t3, and t4. The calibration values are obtained in a calibration environment, that is, the master and slave nodes are in the same temperature environment, and the length of the single-core optical cable of the clock synchronization device is selected to be 1 meter.

[0068] The master node transceiver delay D0 is the delay from the master node's transmitter to the receiver, and the slave node transceiver delay D1 is the delay from the slave node's transmitter to the receiver.

[0069] It's important to understand that the master and slave node's transmit and receive delays (Delay_mt', Delay_sr', Delay_st', and Delay_mr') in step S100 serve as baseline values for calibrating the distributed system in practice. These values are obtained by pre-conditioning the master and slave nodes under the same temperature and with a known single-core fiber optic cable length. Correction values for the master and slave node's transmit and receive delays require determining the corrective factors for Delay_mt', Delay_sr', Delay_st', and Delay_mr', respectively.

[0070] First, the method for obtaining the sending and receiving delays Delay_mt', Delay_sr', Delay_st', and Delay_mr' of the master and slave nodes includes:

[0071] S211. Control the clock synchronization device to be in communication mode under the calibration environment, and obtain timestamps t1', t2', t3', t4' and the local time difference ΔT'; where t2'-t1'=Delay_mt'+Delay_λ1'+Delay_sr'+ΔT', t4'-t3'=Delay_st'+Delay_λ2'+Delay_mr'-ΔT', t1' is the local sending time of the master node, t2' is the local receiving time of the slave node, t3' is the local sending time of the slave node, t4' is the local receiving time of the master node, Delay_λ1' and Delay_λ2' are the optical fiber delay from the transmitting end of the master node to the receiving end of the slave node, and the optical fiber delay from the transmitting end of the slave node to the receiving end of the master node, respectively;

[0072] Where t2'-t1'=Delay_mt'+Delay_λ1'+Delay_sr'+ΔT', t4'-t3'=Delay_st'+Delay_λ2'+Delay_mr'-ΔT', Delay_λ1' and Delay_λ2' are the fiber delay from the transmitter of the master node to the receiver of the slave node and the fiber delay from the slave node to the master node, respectively.

[0073] S212. Control the clock synchronization device to be in short-circuit mode in the calibration environment, and obtain the master node receiving and sending delay D0' and the slave node receiving end sending delay D1'; wherein D0'=Delay_mt'+Delay_mr', D1'=Delay_st'+Delay_sr'.

[0074] S213. Combine the above formulas to calculate Delay_mt', Delay_sr', Delay_st', and Delay_sr'.

[0075] Among them, the optical fiber delay Delay_λ1 from the transmitting end of the master node to the receiving end of the slave node and the optical fiber delay Delay_λ2 from the transmitting end of the slave node to the receiving end of the master node are determined according to the length of the single-core optical cable and the refractive index λ1 from the master node to the slave node and the refractive index λ2 from the slave node to the master node in the single-core optical cable, wherein the refractive indices λ1 and λ2 can be obtained by looking up the table. The refractive indices λ1 and λ2 are related to their own properties and the incident angle during bidirectional transmission of the signal, and can be calculated by those skilled in the art.

[0076] Then, based on the obtained Delay_mt', Delay_sr', Delay_st', and Delay_sr', the value Delay_mt is corrected. cor 、Delay_mr cor 、Delay_st cor 、Delay_sr corMethods for obtaining include:

[0077] S221. Control the synchronous clock device in short-circuit mode, obtain the master node transceiver delay D0 and the slave node transceiver delay D1;

[0078] S222. Get the master node correction coefficient k m and the slave node correction factor k s ;k m =D0 / D0',k s =D1 / D1';

[0079] S223. Calculate the correction delay according to the correction coefficient; Delay_mt cor =Delay_mt'·k m ,

[0080] Delay_mr cor =Delay_mr'·k m ;Delay_st cor =Delay_st'·k s , Delay_sr cor =Delay_sr'·k s .

[0081] The delay effect caused by the ambient temperature can be overcome by using correction coefficients in steps S121-S123, which can eliminate the problem of inconsistent two-way transmission delay between the master node and the slave node caused by the different ambient temperatures between the master node and the slave node, thereby improving synchronization accuracy.

[0082] S300. Correct the delay value Delay_mt according to the transmission and reception delay cor 、Delay_sr cor 、Delay_st cor 、Delay_mr cor , and obtain the clock difference ΔT. By substituting the correction value into the above formula, the clock difference ΔT can be calculated.

[0083] Specifically, the delay correction value is substituted into t2-t1 or t4-t3 obtained in step S100: t2-t1 = Delay_mt + Delay_λ1 + Delay_sr + ΔT, and t4-t3 = Delay_st + Delay_λ2 + Delay_mr - ΔT. Delay_λ1 or Delay_λ2 can be calculated based on the refractive index of the optical fiber according to the laser wavelength and then the optical fiber length; Delay_mt, Delay_sr, Delay_st, and Delay_mr directly use the transmit and receive delay correction value Delay_mt. cor 、Delay_srcor 、Delay_st cor 、Delay_mr cor Substitute in. Furthermore, if Delay_mt+Delay_sr and Delay_λ1 are known, or if Delay_st+Delay_mr and Delay_λ2 are known, the clock difference ΔT can be obtained.

[0084] S400. Control the slave node to compensate for the clock difference ΔT, thereby completing clock synchronization between the master node and the slave node. The local clock of the slave node compensates for the clock difference ΔT, thereby completing clock synchronization between the master and slave nodes.

[0085] In one embodiment, the master node receiving and sending delay D0, the slave node receiving and sending delay D1, the time difference t2-t1, and the time difference t4-t3 are all calculated based on the phase difference collected by the dual-mixer phase detector.

[0086] Table 1

[0087]

[0088] The following uses the specific data shown in Table 1 as an example to illustrate the method in this embodiment. Assume that the master node sends at the local time Tm=0, that is, the timestamp t1 is 0; the slave node receives at the local time Ts2=4.25, that is, the timestamp t2 is 4.25, and the dual-mixer phase detector can convert t2-t1=4.25 by collecting the phase difference, or the dual-mixer phase detector can convert t4-t3=1.75 by collecting the phase difference. According to the formula t2-t1=Delay_mt+Delay_λ1+Delay_sr+ΔT or t4-t3=Delay_st+Delay_λ2+Delay_mr-ΔT, Delay_mt, Delay_sr, Delay_st, and Delay_mr directly use the transmit and receive delay correction value Delay_mt cor 、Delay_sr cor 、Delay_st cor 、Delay_mr cor Substitute Delay_λ1 or Delay_λ2 for the refractive index obtained from the laser wavelength and then calculated from the length of the single-core optical cable. Ultimately, the clock difference ΔT is determined to be 1.25s, controlling the slave node to compensate for the clock difference.

[0089] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A clock synchronization device for a distributed system, characterized in that: The distributed system includes a master node and several slave nodes, and the master node and the slave nodes communicate with each other in a two-way manner. The clock synchronization device includes: Single-core optical cable, used to connect the master node and the slave node; An optical switch, the optical switch being switchable between a communication mode and a shorting mode; when the optical switch is in the communication mode, a single-core optical cable connects a transmitting end of the master node and a receiving end of the slave node, or connects a transmitting end of the slave node and a receiving end of the master node; when the optical switch is in the shorting mode, the single-core optical cable connects a receiving end and a transmitting end of the master node, or connects a receiving end and a transmitting end of the slave node; A dual-mixer phase detector is provided at the master node and the slave node respectively, and is used to measure the phase difference between the local clock of the master node / slave node and the received data recovery clock; wherein the data recovery clock is the local clock of the slave node / master node extracted by the master node / slave node from the data link.

2. The clock synchronization device according to claim 1, wherein: The optical switch includes a master node optical switch and a slave node optical switch. The master node optical switch includes a master node optical switch A and a master node optical switch B, wherein the master node optical switch A is connected to the transmitting end of the master node, and the master node optical switch B is connected to the receiving end of the master node; The slave node optical switch includes a slave node optical switch A and a slave node optical switch B, wherein the slave node optical switch A is connected to the transmitting end of the slave node, and the slave node optical switch B is connected to the receiving end of the slave node; When the optical switch is in the communication mode, the transmitting end of the master node and the receiving end of the slave node are connected through the master node switch A and the slave node switch B, or the transmitting end of the slave node and the receiving end of the master node are connected through the slave node switch A and the master node switch B; When the optical switch is in short-circuit mode, the transmitting end and the receiving end of the master node are connected through the master node switch A and the master node switch B, and / or the transmitting end and the receiving end of the slave node are connected through the slave node switch A and the slave node switch B.

3. A distributed system clock synchronization method, characterized in that: The clock synchronization device according to any one of claims 1 to 2, comprising: Controlling the clock synchronization device to be in a communication mode under a calibration environment to obtain a time difference t2-t1 or a time difference t4-t3; Get the delay correction value Delay_mt of the master and slave nodes cor 、Delay_sr cor 、Delay_st cor 、Delay_mr cor The correction value is determined based on the pre-acquired Delay_mt', Delay_sr', Delay_st', Delay_mr' and the correction coefficient, where Delay_mt represents the sending delay of the master node, Delay_sr represents the receiving delay of the slave node, Delay_st represents the sending delay of the slave node, and Delay_mr represents the receiving delay of the master node. The subscript cor represents the correction value of the delay, and the superscript ' represents the value obtained by the clock synchronization device in a calibration environment. According to the delay correction value Delay_mt cor 、Delay_sr cor 、Delay_st cor 、Delay_mr cor , obtain the clock difference ΔT; The slave node is controlled to compensate the clock difference ΔT to complete the clock synchronization of the master node and the slave node.

4. The method according to claim 3, characterized in that The method for obtaining the sending and receiving delays Delay_mt', Delay_sr', Delay_st', and Delay_mr' of the master and slave nodes includes: Controlling the clock synchronization device to be in a communication mode under a calibration environment, obtaining timestamps t1', t2', t3', t4' and a local time difference ΔT'; wherein t2'-t1'=Delay_mt'+Delay_λ1'+Delay_sr'+ΔT', t4'-t3'=Delay_st'+Delay_λ2'+Delay_mr'-ΔT', t1' is the local sending time of the master node, t2' is the local receiving time of the slave node, t3' is the local sending time of the slave node, t4' is the local receiving time of the master node, Delay_λ1' and Delay_λ2' are the optical fiber delays from the transmitting end of the master node to the receiving end of the slave node and the optical fiber delays from the transmitting end of the slave node to the receiving end of the master node, respectively; Control the clock synchronization device to be in short-circuit mode under a calibration environment, and obtain the master node receiving and sending delay D0' and the slave node receiving and sending delay D1'; wherein D0'=Delay_mt'+Delay_mr', D1'=Delay_st'+Delay_sr'; Delay_mt', Delay_sr', Delay_st', and Delay_sr' are calculated.

5. The method according to claim 4, characterized in that The fiber delay Delay_λ1 from the transmitting end of the master node to the receiving end of the slave node and the fiber delay Delay_λ2 from the transmitting end of the slave node to the receiving end of the master node are determined according to the length of the single-core optical cable and the refractive index λ1 from the master node to the slave node and the refractive index λ2 from the slave node to the master node in the single-core optical cable.

6. The method according to claim 4, characterized in that Delay_mt cor 、Delay_mr cor 、Delay_st cor 、Delay_sr cor Methods for obtaining include: Control the synchronous clock device to be in a short-circuit mode, and obtain the master node receiving and sending delay D0 and the slave node receiving and sending delay D1; Get the master node correction coefficient k m and the slave node correction factor k s ;k m =D0 / D0',k s =D1 / D1'; According to the correction coefficient, calculate the correction delay; Delay_mt cor =Delay_mt'·k m , Delay_mr cor =Delay_mr'·k m ;Delay_st cor =Delay_st'·k s , Delay_sr cor =Delay_sr'·k s .

7. The method according to claim 6, characterized in that The master node receiving and sending delay D0, the slave node receiving and sending delay D1, the time difference t2-t1, and the time difference t4-t3 are all calculated based on the phase difference collected by the dual-mixer phase detector.

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