Semiconductor structure

Abstract

The present invention is a semiconductor structure. The epitaxial structure of a fin field-effect transistor device includes a substrate, a fin structure having two fins, inner fin spacers and outer fin spacers formed along the sidewalls of the fins, and an isolation region formed around the fins. The fin field-effect transistor device also includes a gate structure formed on the fin structure, and an epitaxial structure formed on the fin structure in the source / drain regions. The method of forming the epitaxial structure is to combine the fins with at least one epitaxial semiconductor layer and includes air gaps. The volume of the air gaps depends on the height and the separation distance of the inner fin spacers.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to integrated circuit devices, and more particularly to fin field effect transistor devices. Background Art

[0002] The integrated circuit industry has experienced exponential growth. Technical advancements in integrated circuit materials and design have enabled each generation of integrated circuits to have smaller and more complex circuits than the previous generation. As integrated circuits have evolved, the functional density (e.g., the number of interconnect devices per unit chip area) has generally increased as the geometric dimensions (e.g., the smallest feature or line that can be produced by a process) have shrunk. Shrinking the dimensions is beneficial for increasing production capacity and reducing related costs.

[0003] Shrinking the dimensions also increases the complexity of the processes and manufacturing of integrated circuits. To achieve these advancements, similar developments are also required in the processes and manufacturing of integrated circuits. For example, three-dimensional fin field effect transistors have replaced planar transistors. Although existing fin field effect transistor devices and their manufacturing methods have served their development purposes, they cannot fully meet all aspects of the requirements. For example, the viable processes of fin field effect transistor technology are moving towards smaller structural dimensions (e.g., 32 nm, 28 nm, 20 nm, or smaller), and the approach of improving the source / drain epitaxial structure characteristics faces challenges in designing and manufacturing the devices. Summary of the Invention

[0004] A semiconductor structure provided by an embodiment of the present disclosure includes: a fin structure having a first fin and a second fin formed on a semiconductor substrate; a plurality of inner fin spacers formed along the inner sidewalls of the first fin and the second fin, wherein the inner fin spacers have a height H i ; a plurality of outer fin spacers formed along the outer sidewalls of the first fin and the second fin, wherein the outer fin spacers have a height H o , and the height H o is substantially smaller than the height H i ; and an epitaxial structure formed on the first fin and the second fin, wherein the epitaxial structure encloses an air gap formed by the inner spacers, and the air gap has at least one width, wherein the width is the separation distance between the opposing sidewalls of the inner fin spacers. Brief Description of the Drawings

[0005] Figure 1 is a flowchart of an exemplary method for manufacturing a semiconductor structure including fin field effect transistors in various embodiments of the present disclosure.

[0006] Figure 2A and Figure 2B is a flowchart of an exemplary method for manufacturing a semiconductor structure in various embodiments of the present disclosure.

[0007] Figure 3 is a three - dimensional perspective view of a semiconductor structure in various embodiments of the present disclosure.

[0008] Figure 4A 、 Figure 5A 、 Figure 6A 、 Figure 8A and Figure 9A are partial cross - sectional views of the semiconductor structure along the section line AA shown in Figure 3 in various embodiments of the present disclosure.

[0009] Figure 4B 、 Figure 5B 、 Figure 6B 、 Figure 7 、 Figure 8B 、 Figure 9B 、 Figure 10 、 Figure 11 and Figure 12 are partial cross - sectional views of the semiconductor structure along the section line BB shown in Figure 3 in various embodiments of the present disclosure.

[0010] Among them, the reference numerals are explained as follows:

[0011] Section lines AA, BB

[0012] d Difference

[0013] H a 、H f 、H i 、H o Height

[0014] P Pitch

[0015] w Width

[0016] 100 Method

[0017] 110, 120, 130, 132, 134, 140, 142, 144, 146, 148, 150, 160 Steps

[0018] 200, 300, 400 Semiconductor structures

[0019] 210 Semiconductor substrate

[0020] 220 Fin structure

[0021] 222 Fin

[0022] 230 Isolation region

[0023] 240 Gate structure

[0024] 242 Interface layer

[0025] 244 Gate dielectric layer

[0026] 246 Gate layer

[0027] 248 Hard mask layer

[0028] 250 Dielectric layer

[0029] 310 Sidewall spacer material layer

[0030] 320 Inner fin spacer

[0031] 330 Outer fin spacer

[0032] 340 Material layer

[0033] 410 Trench

[0034] 420 First epitaxial layer

[0035] 430 Second epitaxial layer

[0036] 430A, 430B Inner crystal planes

[0037] 430C, 430D, 430E, 430F, 430G Outer crystal planes

[0038] 440 Third epitaxial layer

[0039] 442, 444, 446 Thickness

[0040] 450 Air gap

[0041] 460 Epitaxial structure Detailed implementation manners

[0042] The following disclosure provides many different embodiments or examples for implementing different structures of the present disclosure. The following embodiments of specific components and arrangements are used to simplify the present disclosure rather than limit the present disclosure. For example, the description of forming a first component on a second component includes both direct contact between the two, or there are other additional components between the two rather than direct contact.

[0043] In addition, in various examples of the present disclosure, repeated reference numerals may be used, but these repetitions are only for simplifying and clarifying the description, and do not represent that there is the same corresponding relationship between the units with the same reference numerals in different embodiments and / or arrangements. In addition, descriptions such as a structure in the embodiments of the present disclosure being formed on another structure, connected to another structure, and / or coupled to another structure, etc., may include embodiments where the structures are in direct contact with each other, and may also include embodiments where there is an additional structure (i.e., not in direct contact) between the structures. In addition, spatial relative terms such as "lower side", "upper side", "horizontal", "vertical", "thereon", "above", "thereunder", "below", "up", "down", "top", "bottom", similar terms, or derivative terms (such as "horizontally", "downward", "upward", or similar terms) may be used to simplify the relative relationship between one element and another element in the drawings. The spatial relative terms may extend to elements used in other directions, rather than being limited to the directions shown in the drawings. In addition, if there are terms such as "about", "approximate", or similar terms before a numerical value or numerical range in the description, they cover the numerical values within a reasonable range, such as within + / - 10% of the stated numerical value, or other numerical values understood by those skilled in the art. For example, the term "about 5 nm" covers the range from 4.5 nm to 5.5 nm.

[0044] Embodiments of the present disclosure are generally related to integrated circuit devices, and more particularly to fin field effect transistor devices. For example, fin field effect transistor devices include p-type metal oxide semiconductor fin field effect transistor devices and n-type metal oxide semiconductor fin field effect transistor devices. The following description continues to use fin field effect transistors as an example to illustrate various embodiments of the present disclosure. However, it should be understood that the embodiments of the present disclosure are not limited to a specific type of device.

[0045] Figure 1 FIG. 7 is a flowchart of a method 100 for fabricating a fin field effect transistor device in some embodiments of the present disclosure. The initial step 110 of method 100 includes forming a semiconductor structure 200. As Figure 3 shown in the embodiment, the semiconductor structure 200 includes a semiconductor substrate 210 and a fin structure 220. The fin structure 200 includes two fins 222, which are separated by an isolation region 230. The semiconductor structure 200 also includes a gate structure 240, which has multiple material layers such as a dielectric layer, a gate layer 246, and a hard mask layer 248. It should be understood that the semiconductor structure 200 of the embodiments of the present disclosure may also have additional devices and structures and any variations. It should also be understood that Figure 3 the semiconductor structure 200 shown is only used to illustrate method 100, rather than limiting the embodiments of the present disclosure.

[0046] Steps 110, 120, 130 (including steps 132 and 134), 140 (including steps 142, 144, 146, and 148), 150, and 160 of the process of method 100 will be described with reference to cross-sectional views of semiconductor structure 200, and the cross-sectional views are along cutting line AA of one of fins 222 or along cutting line BB of the source / drain of fins 222.

[0047] As Figure 3 shown, semiconductor substrate 210 includes a crystalline material, which generally has a regular atomic structure or crystalline structure. In some embodiments, semiconductor substrate 210 includes a semiconductor element with a crystalline structure, such as silicon. In other or additional embodiments, semiconductor substrate 210 includes another semiconductor element such as germanium; a semiconductor compound such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; a semiconductor alloy such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide indium; or a combination of the above. On the other hand, semiconductor substrate 210 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator substrate, a silicon-germanium-on-insulator substrate, or a germanium-on-insulator substrate. The manufacturing method of the semiconductor-on-insulator substrate can adopt oxygen implantation isolation, wafer bonding, and / or other suitable methods.

[0048] In some embodiments, the step of forming fin structure 220 (such as fin 222) also forms isolation region 230. As Figure 4B shown, each fin formed in the embodiments provided herein has a height H f , which is measured from the upper surface of isolation region 230 to the upper surface of the fin. In some embodiments, height H f is between about 30 nm and about 200 nm. In some embodiments, isolation region 230 includes silicon oxide, silicon nitride, silicon oxynitride, air gap, other suitable dielectric materials, or a combination of the above. Isolation region 230 can include different structures, such as a shallow trench isolation structure, a deep trench isolation structure, and / or a local oxidation of silicon structure.

[0049] The method for forming the fin structure 220 and the isolation region 230 can be any suitable process. In an illustrative embodiment, the process may include the following steps: performing a photolithography process to form a patterned photoresist layer on the semiconductor substrate 210, and transferring the pattern to a hard mask layer (not shown), and the transfer method can be an etching process. Then, an etching process such as a dry etching and / or wet etching process is performed to etch the semiconductor substrate 210 not covered by the patterned hard mask layer to form trenches in the semiconductor substrate 210. Then, one or more dielectric materials are deposited to fill the trenches, and an isolation region can be formed, and the deposition process can be a chemical vapor deposition process and / or a spin-on glass process. Part of the trenches can be filled, and the substrate remaining between the trenches forms fins 222. One or more photolithography processes (including double patterning or multiple patterning processes) are used to pattern the hard mask layer. Generally, the double patterning or multiple patterning process combines photolithography and self-alignment processes, and the formed pattern pitch is smaller than the pattern pitch that can be produced by using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on the semiconductor substrate 210, and the sacrificial layer is patterned by a photolithography process. A self-alignment process is used to form spacers along the patterned sacrificial layer. Then, the sacrificial layer is removed, and the remaining spacers (or cores) are transformed into a patterned hard mask layer.

[0050] On the other hand, the method for forming the fins 222 and the isolation region 230 can be the following process: depositing an insulating material on the semiconductor substrate 210 to completely fill the trenches; planarizing the upper surface of the filled trenches to remove any excess insulating material (such as by using a grinding process such as chemical mechanical polishing / planarization process); and selectively epitaxially growing one or more semiconductor material layers on the exposed semiconductor substrate 210 to form fins 222, and the isolation region 230 is located between the fins 222. For example, the epitaxial semiconductor material can be silicon, germanium, silicon germanium, other suitable materials, or a combination of the above. In some embodiments, what is filled in the trenches can be a multi-layer structure, such as a thermal oxide liner layer filled with silicon nitride or silicon oxide. In summary, the fins formed by the embodiments provided herein can include the same material as the semiconductor substrate 210, or instead include one or more semiconductor materials epitaxially grown on the semiconductor substrate 210.

[0051] In some embodiments, the lithography process includes a pre-exposure baking process on a photoresist layer formed on a hard mask layer on a semiconductor substrate 210, an exposure process using a mask, a post-exposure baking process on the photoresist layer, and a development process to form a patterned photoresist layer. During the exposure process, the photoresist layer is exposed to a radiation beam such as ultraviolet light, deep ultraviolet light, or extreme ultraviolet light, where the mask blocks, is penetrated by, and / or reflects the radiation to the photoresist layer, depending on the mask pattern and / or mask type (such as a binary intensity mask, a phase shift mask, or an extreme ultraviolet mask), so that the image transferred to the photoresist layer corresponds to the mask pattern. Since the photoresist layer is sensitive to the radiation energy, chemical changes occur in the exposed portion of the photoresist layer, and the development process can be used to remove the exposed or unexposed portion of the photoresist layer, depending on the characteristics of the photoresist layer and / or the developer solution used during the development process. In some embodiments, the lithography process uses techniques such as laser patterning, electron beam patterning, and / or ion beam patterning to directly form a pattern on the photoresist layer without using a mask.

[0052] After development, the pattern on the photoresist layer is transferred to the hard mask layer, and then one or more etching processes are performed using the patterned hard mask layer to form trenches in the semiconductor substrate 210. The hard mask layer includes any suitable material, such as silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, spin-on glass, low dielectric constant film, tetraethylorthosilicate oxide, plasma-enhanced chemical vapor deposition oxide, high aspect ratio process-formed oxide, or other suitable materials, and it can be formed by suitable methods such as thermal oxidation, chemical vapor deposition, high-density plasma chemical vapor deposition, physical vapor deposition, atomic layer deposition, other suitable methods, or a combination of the above. Exemplary etching processes can include dry etching processes, wet etching processes, other suitable etching processes, or a combination of the above. In some embodiments, a reactive ion etching process is performed. After the etching process, the patterned photoresist layer and the hard mask layer can be removed from the semiconductor substrate 210, and the removal method can be a stripping process and / or plasma ashing.

[0053] In an embodiment, the semiconductor structure 200 also includes two gate structures 240 formed on the semiconductor substrate 210. It should be understood that additional gate structures similar to the gate structures 240 described herein can also be formed on the fins 222 and be parallel to the gate structures 240. Each gate structure 240 conforms to the top and sidewall portions of the fin 222, such as conforming to three sides of the fin 222 in the channel region shown here.

[0054] As Figure 4AIn the illustrated embodiment, the gate structure 240 in the semiconductor structure 200 includes a dielectric layer 250, a gate layer 246, and a hard mask layer 248. It should be understood that the gate structure 240 may include additional layers such as a capping layer, a diffusion barrier layer, a dielectric layer, a conductive layer, other suitable layers, and / or combinations thereof. For example, the dielectric layer 250 may include an interface layer 242 and a gate dielectric layer 244. The interface layer 242 is formed on the isolation region 230 and the fin structure 220. The interface layer 242 may be formed to any suitable thickness by any suitable process. Exemplary interface layers include silicon oxide (such as thermal oxide or chemical oxide) and / or silicon oxynitride.

[0055] The gate dielectric layer 244 is formed on the interface layer 242 and includes a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, aluminum oxide, hafnium-aluminum oxide alloy, other suitable high-k dielectric materials, and / or combinations thereof.

[0056] The gate layer 246 is formed on the dielectric layer 250 and includes any suitable material such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, titanium nitride, tungsten nitride, titanium aluminum, titanium aluminum nitride, tantalum carbonitride, tantalum carbide, tantalum silicon nitride, a metal alloy, other suitable materials, and / or combinations thereof.

[0057] The method of forming the hard mask layer 248 on the gate layer 246 may be any suitable process. The hard mask layer 248 includes any suitable material, such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, spin-on glass, a low-k film, tetraethyl orthosilicate oxide, plasma-enhanced chemical vapor deposition oxide, oxide formed by a high aspect ratio process, and / or other suitable materials.

[0058] Each layer of the gate structure 240 provided herein can be formed by any suitable process. For example, the formation method of each material layer includes deposition, photolithographic patterning, and etching processes. For example, the deposition process includes chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metalorganic chemical vapor deposition, remote plasma chemical vapor deposition, plasma-enhanced chemical vapor deposition, electroplating, other suitable methods, and / or combinations of the above. The photolithographic patterning process includes applying photoresist (such as spin coating), soft baking, aligning a mask, exposure, post-exposure baking, developing the photoresist, rinsing, drying (such as hard baking), other suitable processes, and / or combinations of the above. In other embodiments, a photolithographic exposure process is implemented or other suitable methods such as maskless lithography, electron beam writing, ion beam writing, and / or nanoimprinting are used to pattern the photoresist layer. The etching process can include a dry etching process, a wet etching process, other suitable etching processes, or combinations of the above. In some embodiments, a reactive ion etching process is performed.

[0059] In some embodiments, the formed gate structure 240 is a dummy gate structure. After performing a high thermal budget process, part of the dummy gate structure will be replaced with a high-k dielectric layer and a metal gate structure. In some embodiments, the dummy gate structure includes a dummy dielectric layer (similar to the aforementioned dielectric layer 250), a dummy gate layer (including polysilicon and / or other suitable materials), a hard mask layer (similar to the aforementioned hard mask layer 248), and any other suitable material layers (such as a capping layer, a diffusion barrier layer, a dielectric layer, a conductive layer, other suitable layers, and / or combinations of the above).

[0060] Returning to Figure 1 , step 120 of method 100 forms a sidewall material layer 310 on the semiconductor structure 200. As Figure 5A and 5B shown, a sidewall spacer material layer 310 is formed on the gate structure 240 and the fin structure 220 to form an adjusted semiconductor structure 300. The sidewall spacer material layer 310 generally includes a dielectric material, such as silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, or combinations of the above. The formation method of the sidewall spacer material layer 310 can be any suitable process. In an embodiment, the formation method of the sidewall spacer material layer 310 is to perform one or more processes to deposit a dielectric material on the gate structure 240 and the fins 222. For example, the deposition process can be implemented by chemical vapor deposition, high-density plasma chemical vapor deposition, physical vapor deposition, atomic layer deposition, other suitable methods, or combinations of the above.

[0061] Still as Figure 1 shown in method 100, step 130 or 140 forms Figure 6BThe inner fin spacer 320 and the outer fin spacer 330 shown. Generally, anisotropically re-etching the sidewall spacer material layer 310 can form gate spacers ( Figure 6A ) along the sidewalls of the gate structure 240( Figure 6A ), and form the inner fin spacer 320 and the outer fin spacer 330 ( Figure 6B ) along the sidewalls of each fin 222. In some embodiments, the re-etching process can include multiple steps of etching to achieve the etching selectivity, flexibility, and desired control used in the etching.

[0062] As Figure 2A shown, step 132 at the beginning of step 130 performs a main etching process on the sidewall spacer material layer 310. In some embodiments, the main etching process includes a dry etching process. Exemplary dry etchant gases include one or more of carbon monoxide, carbon dioxide, fluoromethane, sulfur dioxide, methane, argon, carbon tetrafluoride, hydrogen bromide, oxygen, nitrogen trifluoride, sulfur hexafluoride, and helium. To achieve anisotropic etching, the dry etching process can also employ the mechanism of deep reactive ion etching. On the other hand, the main etching process can also employ a wet etching process. For example, the wet etching solution includes tetramethylammonium hydroxide, a solution of hydrofluoric acid, nitric acid, and acetic acid, or other suitable solutions.

[0063] Step 134 of step 130 performs over-etching on the sidewall spacer material layer 310. Exemplary dry etching gases used in the over-etching process include one or more of fluoromethane, oxygen, and methane. In some embodiments, the etching rate of the sidewall spacer material layer 310 on the inner sidewall of the fin 222 is lower than the etching rate of the sidewall spacer material layer 310 on the outer sidewall of the fin 222. In this way, the amount of re-etching of the inner fin spacer 320 is less than that of the outer sidewall spacer 330. The above difference in etching rate may result from the fact that there is less etchant gas that can react with the spacer material in the space between the fins 222 than the etchant gas that can react with the spacer material outside the fins 222. In this way, the etching rate of the inner fin spacer 320 is slower than the etching rate of the outer fin spacer 330. The etching process of step 134 can also adjust one or more etching parameters such as etching temperature, etching pressure, source power, radio frequency bias, radio frequency bias power, etchant flow rate, or other suitable parameters. In an embodiment, the bias of the etching process of step 134 can be reduced to less than about 300V to achieve the desired etching result. In addition, step 134 can also employ a high-voltage bias pulse to precisely control the re-etching process so that the amount of re-etching of the inner fin spacer 320 is lower than that of the outer fin spacer 330.

[0064] As Figure 2BIn other embodiments shown, step 142 of the main etching process is performed after step 120, followed by step 144 of the over-etching process, which are similar to the aforementioned steps 132 and 134 respectively. Then, in step 146 of step 140, a material layer 340 is deposited on the fin structure 220, such that the material layer 340 completely fills the space between the fins 222 and is adjacent to the fins 222, as Figure 7 shown. In some embodiments, the material layer 340 comprises a polymeric material, such as a polymer of methane or fluorinated methane delivered in an inert carrier gas (such as argon or nitrogen). In other embodiments, the material layer 340 may comprise a dielectric material such as silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, other suitable materials, or a combination of the above, such that the material layer 340 is different from the sidewall spacer material layer 310. For example, the deposition process may employ chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metalorganic chemical vapor deposition, remote plasma chemical vapor deposition, plasma-enhanced chemical vapor deposition, electroplating, other suitable methods, and / or a combination of the above.

[0065] After depositing the material layer 340, in step 148 of step 140, one or more etchant gases as described in step 132 are used to anisotropically etch back the material layer 340 and the sidewall spacer material layer 310. In some embodiments, when etching back the sidewall spacer material layer 310, the applied bias voltage is between about 1 V and about 800 V. In an embodiment, the bias voltage may be less than about 300 V to precisely control the etch-back process. Similar to the foregoing of the etching process in step 134, the high-voltage bias pulse used in step 134 can precisely control the over-etching process, such that the etch-back amount of the inner fin spacer 320 is less than that of the outer fin spacer 330. In some embodiments, after completing step 148, the material layer 340 is completely removed and the sidewall spacer material layer 310 is partially etched, thereby forming the inner fin spacer 320 and the outer fin spacer 330 on the sidewalls of the fins 222, as Figure 6B shown. In many embodiments, similar to the foregoing reasons described in conjunction with step 134, the additional material layer 340 further limits the amount of reaction of the etchant gas with the sidewall spacer material layer 310, thus reducing the etching rate of the inner fin spacer 320 (compared to the etching rate of the outer fin spacer).

[0066] In summary, the etching amounts provided by steps 130 and 140 can be controlled to achieve height H i and height H o , where height H i is greater than height H o , as Figure 6BAs shown. In some embodiments, one or more etching parameters can be adjusted together or separately to control the amount of etching, so that the inner fin spacers and the outer fin spacers reach the desired relative height. It should be understood that the height H is measured from the lower surface to the upper surface of the individual fin spacers i and the height H o , and the lower surface of the inner fin spacer 320 is coplanar with the lower surface of the outer fin spacer 330. In an embodiment, the lower surfaces of the inner fin spacer 320 and the outer fin spacer 330 physically contact the upper surface of the isolation region 230 surrounding the fin structure 220. In some embodiments, the height H i is greater than or equal to half of the height H f . In some embodiments, the inner fin spacers 320 and the outer fin spacers 330 can also be described by a pitch P, which is the separation distance between the inner fin spacers 320. In some embodiments, the pitch P is the minimum pitch that can be achieved between the fins 222 obtained by the lithography process of the prior art node. For example, in Figure 6B the embodiment shown, the height H f is between about 30 nm and about 200 nm, the pitch P is between about 0.1 nm and about 50 nm, and the height H i , the height H o , and the relationship between the height H f is as follows:

[0067] H i >>H o , and

[0068] H i >0.5H f .

[0069] Embodiments of the present disclosure consider the variation of the height H i relative to the height H o , which affects the epitaxial structure formed in the fin field effect transistor device.

[0070] Returning to Figure 1 , step 150 of method 100 recesses the fins 222 to form trenches 410, as shown in Figure 8A , 8B, as shown in FIGS. 9A and 9B. In some embodiments, the recess process includes an etching process that selectively etches the fins 222 on other structures of the semiconductor structure 300. In this embodiment, etching the source / drain regions of the fins 222 causes them to recess, and the gate structure 240 protects the channel region from etching. The etching process can be a dry etching process, a wet etching process, or a combination of the above. In some embodiments, the etching solution used in the wet etching process includes potassium hydroxide. In some embodiments, the wet etching process uses an etching solution that includes ammonium hydroxide, hydrogen peroxide, sulfuric acid, tetramethylammonium hydroxide, other suitable wet etching solutions, or a combination of the above. For example, the wet etching solution can use a solution of ammonium hydroxide and hydrogen peroxide, a solution of ammonium hydroxide, hydrogen peroxide, and water (i.e., the known ammonia-peroxide mixture), or a solution of sulfuric acid and hydrogen peroxide (i.e., the known sulfuric acid peroxide mixture). In some embodiments, the dry etching process uses an etchant gas that includes a fluorine-containing etchant gas (such as carbon tetrafluoride, sulfur hexafluoride, difluoromethane, fluoroform, and / or hexafluoroethane), an oxygen-containing gas, a chlorine-containing gas (such as chlorine, chloroform, carbon tetrachloride, and / or boron trichloride), a bromine-containing gas (such as hydrogen bromide and / or bromoform), an iodine-containing gas, helium, other suitable gases and / or plasmas, or a combination of the above. In some embodiments, the recess process uses an oxidation process. For example, the recess process can expose the fins 222 to an ozone environment to oxidize a portion of the fins 222, and then remove the oxidized portion of the fins 222 with a cleaning process and / or an etching process, as described herein.

[0071] By controlling the parameters that affect the recess process (such as the recess time, the recess process conditions, or other recess parameters), the profile of the fins 222 can be adjusted to meet the various design requirements of the final fin field-effect transistor device. For example, when the recess process includes an etching process, various process parameters such as the etchant used, the etching temperature, the etching pressure, the source power, the radio frequency bias, the radio frequency bias power, the etchant flow rate, and / or other suitable etching parameters can be adjusted to remove the desired amount of the fins 222 and / or achieve the desired profile of the fins 222.

[0072] In an embodiment, the fins 222 are etched to form trenches 410 with the same height and the same profile. Taking Figure 8A and 8B as an example, after etching the fins 222, the upper surface of the fins 222 is higher than the upper surface of the isolation region 230. Taking Figure 9A and 9B as an example, after etching the fins 222, the upper surface of the fins 222 is lower than the upper surface of the isolation region 230. In some embodiments, the sidewalls of the trenches 410 are substantially vertical and parallel to each other.

[0073] Returning to Figure 1, step 160 of method 100 forms an epitaxial structure 460 on the fin structure 220 to merge the fins 222 in the source / drain regions of the semiconductor structure 400.

[0074] As Figure 10 shown in the embodiment, the epitaxial structure 460 includes three epitaxial layers: a first epitaxial layer 420, a second epitaxial layer 430, and a third epitaxial layer 440. However, it should be understood that the epitaxial structure 460 is not limited to three epitaxial layers and may include one, two, or four epitaxial layers. The formation method of each epitaxial layer can be epitaxial growth of semiconductor material on the exposed surfaces of the recessed fins 222 and / or other epitaxial layers. For example, suitable epitaxial semiconductor materials include single-element semiconductor materials such as germanium or silicon, semiconductor compound materials such as gallium arsenide or aluminum gallium arsenide, or semiconductor alloys such as silicon germanium or gallium phosphide arsenide. For embodiments with more than one epitaxial layer, the epitaxial materials of the epitaxial layers can be the same or different. In addition, each epitaxial layer can have any suitable crystal orientation, such as <100>, <110>, or <111> crystal orientations. In Figure 10 the shown embodiment, the thickness 442 of the first epitaxial layer 420 is between about 1 nm and about 10 nm, the thickness 444 of the second epitaxial layer 430 is between about 5 nm and about 60 nm, and the thickness 446 of the third epitaxial layer 440 is between about 1 nm and about 10 nm. In one example, the ratio of thickness 442, thickness 444, and thickness 446 is about 1:5:1.

[0075] In some embodiments, the epitaxial structure 460 is a structure in the source and drain regions and can be referred to as an epitaxial source / drain structure. In some embodiments, the epitaxial structure 460 can include various dopants. For example, if an n-type metal-oxide-semiconductor fin field-effect transistor needs to be formed, the epitaxial structure 460 can include one or more epitaxial layers of silicon or silicon carbide, and the silicon or silicon carbide is doped with an n-type dopant such as arsenic, phosphorus, other n-type dopants, or a combination of the above. On the other hand, if a p-type metal-oxide-semiconductor fin field-effect transistor needs to be formed, the epitaxial structure 460 can include one or more epitaxial layers of silicon germanium, and the silicon germanium is doped with a p-type dopant such as boron, gallium, indium, other p-type dopants, or a combination of the above. Figure 10 And 11 the shown first epitaxial layer 420, second epitaxial layer 430, and third epitaxial layer 440 can include different dopants or different concentrations of the same dopant. In some embodiments, the first epitaxial layer 420, second epitaxial layer 430, and third epitaxial layer 440 include different concentrations of dopants. For example, the dopant concentration of the first epitaxial layer 420 can be less than about 1E21 atoms / cm 3 , the dopant concentration of the second epitaxial layer 430 can be between about 1E21 atoms / cm 3 and about 1E22 atoms / cm 3and the dopant concentration of the third epitaxial layer 440 can be less than about 1E21 atoms / cm 3 . In an embodiment, the ratio of the dopant concentrations among the first epitaxial layer 420, the second epitaxial layer 430, and the third epitaxial layer 440 is about 1:10:1.

[0076] Any suitable process such as an ion implantation process, a diffusion process, an in-situ doping process, or a combination of the above can be implemented to dope the epitaxial semiconductor material deposited on the recessed fin 222. In some embodiments, a selective epitaxial growth process is performed to grow an epitaxial layer of semiconductor material on the recessed fin 222, and the semiconductor material is doped during the selective epitaxial growth process (such as adding dopants to the source and drain materials of the selective epitaxial growth process) to form a doped epitaxial layer. The selective epitaxial growth process can be implemented by any deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metalorganic chemical vapor deposition, remote plasma chemical vapor deposition, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, atmospheric pressure chemical vapor deposition, vapor phase epitaxy, ultra-high vacuum chemical vapor deposition, molecular beam epitaxy, other suitable processes, or a combination of the above. The selective epitaxial growth process can use gaseous precursors (such as silicon-containing gases such as silane and / or germanium-containing gases such as germane) and / or liquid precursors, and the above precursors can react with the composition of the fin 222 to form an epitaxial silicon or epitaxial silicon-germanium layer. One or more annealing processes can be performed to activate the epitaxial structure 460. The annealing process includes rapid thermal annealing and / or laser annealing processes.

[0077] In Figure 10 and Figure 11 the illustrated embodiment, the first epitaxial layer 420, the second epitaxial layer 430, and the third epitaxial layer 440 of the epitaxial structure 460 are formed in sequence on the fin structure 220. First, the first epitaxial layer 420 is formed on the exposed upper surface of each recessed fin 222. Although the upper surface of the first epitaxial layer 420 in the figure is coplanar with the upper surface of the outer fin spacer 330, the embodiments of the present disclosure are not limited to this arrangement. For example, the upper surface of the first epitaxial layer 420 can be higher or lower than the upper surface of the outer fin spacer 330. In addition, as described above, the upper surface of the recessed fin 222 can be higher than the upper surface of the isolation region 230 (such as Figure 11 ), or lower than the upper surface of the isolation region 230 (such as Figure 10)。After forming the first epitaxial layer 420, a second epitaxial layer 430 is formed on the first epitaxial layer 420 (as a substrate material). In an embodiment, due to the direction of crystal growth of the epitaxial semiconductor in the second epitaxial layer 430, the second epitaxial layer 430 has a plurality of outer crystal planes 430C, 403D, 430E, and 430F. The outer crystal planes 430C, 430D, 430E, and 430F provide a substrate for epitaxial growth of the third epitaxial layer 440, and the third epitaxial layer 440 is conformally formed on the outer crystal planes 430C, 430D, 430E, and 430F.

[0078] When depositing the second epitaxial layer 430, an air gap 450 is formed in the epitaxial structure 460, as Figures 10 to 12 shown. The air gap 450 includes a first portion formed by the inner fin spacers 320, which has a height defined by the height Hi, and a width defined by the pitch P of the inner fin spacers. The air gap 450 also includes a second portion formed by the inner fin spacers 320 and the inner crystal planes 430A and 430B of the second epitaxial layer 430, so the second portion has a height H a . In an embodiment, the ratio between the height H a and the height H i is between about 1:3 and about 1:2, and the sum of the height H a and the height H i is between about 30% and about 80% of the height H f . In summary, the total volume of the air gap 450 is the sum of the first portion and the second portion, and is a function of the height H i , the pitch P, and / or the material used to form the second epitaxial layer 430. In an embodiment, performing steps 130 and 140 can change the amount of etch-back of the sidewall spacer material layer 310 to significantly adjust the height of the inner fin spacers 320

[0079] In an embodiment, due to the presence of the air gap 450, the second epitaxial layer 430 and the third epitaxial layer 440 can grow to have five outer crystal planes 430C, 430D, 430E, 430F, and 430G and form a C-shaped epitaxial structure. In other embodiments, the second epitaxial layer 430 and the third epitaxial layer 440 can grow to have four outer crystal planes and form a diamond-shaped epitaxial structure. In Figure 10In the exemplary embodiment shown, the second epitaxial layer 430 and the third epitaxial layer 440 include five crystal planes 430C, 430D, 430E, 430F, and 430G, and the crystal plane directly located on the fin structure 220 (such as the outer crystal plane 430E) is substantially parallel to the upper surface of the recessed fin 222. It should be understood that the widths w of the outer crystal planes may be different. For example, the width w of the outer crystal plane 430E may be smaller than the widths w of the other crystal planes of the second epitaxial layer 430. In addition, although Figure 10 and 11 the outer crystal plane 430E shown is flat, some embodiments provide that the outer crystal plane 430E may include topographical variations. For Figure 12 example, the difference d between the lowest and highest points in the topography of the outer crystal plane 430E is not 0 and is less than 5% of the thickness 444 of the second epitaxial layer 430. Although in the embodiment, the second epitaxial layer 430 and the third epitaxial layer 440 include crystal planes connected at acute angles, the embodiments of the present disclosure are not limited thereto. For example, the crystal planes may be connected by smooth or rounded angles.

[0080] To reduce the resistance-capacitance delay in an integrated circuit including a fin field-effect transistor device (such as the semiconductor structure 400 shown herein), it is necessary to increase the air gap volume (such as the volume of the air gap 450) in the epitaxial source / drain structure to increase the capacitance. The advantage of the embodiments of the present disclosure is that through the process of controlling etching described herein, the height H i can be adjusted to change the air gap volume.

[0081] Additional steps may be performed before, during, or after the method 100, and additional embodiments of the method 100 may replace, omit, or exchange some of the above steps. For example, the method 100 may also include replacing the dummy gate structure 240 with a high-k dielectric-metal gate structure after forming the epitaxial structure 460.

[0082] The semiconductor structure 400 provided herein may be included in a microprocessor, a memory, and / or other integrated circuit devices. In some embodiments, the semiconductor structure 400 may be part of an integrated circuit chip, or a system-on-chip or a part thereof, which may include a variety of passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, metal-oxide-semiconductor field-effect transistors, complementary metal-oxide-semiconductor transistors, bipolar junction transistors, laterally diffused metal-oxide-semiconductor transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations of the foregoing. Through subsequent manufacturing process steps, additional structures may be added to the semiconductor structure 400. For example, a variety of vertical interconnect structures such as contacts and / or vias and / or horizontal interconnect structures such as lines, and multi-layer interconnect structures such as metal layers and interlayer dielectrics may be formed on the semiconductor substrate 210, which are arranged to connect the various structures of the semiconductor structure 400. The various interconnect structures may employ a variety of conductive materials, such as aluminum, aluminum alloys (such as aluminum-silicon-copper alloy), copper, copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicides, other suitable metals, or combinations of the foregoing. Metal silicides may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or combinations of the foregoing.

[0083] In summary, different embodiments of the present disclosure provide an epitaxial structure and a method of fabricating the same in a fin field-effect transistor device. In one embodiment, an exemplary semiconductor structure (such as a fin field-effect transistor device) is provided, which includes fin structures having a first fin and a second fin formed on a semiconductor substrate, inner fin spacers formed along the inner sidewalls of the first fin and the second fin, outer fin spacers formed along the outer sidewalls of the first fin and the second fin, and an epitaxial structure formed on the first fin and the second fin. In some embodiments, the inner fin spacers have a height H i , the outer fin spacers have a height H o , and the height H o is substantially less than the height H i, an air gap is formed by the inner spacer of the epitaxial structure being closed, and the air gap has at least one width, where the width is the separation distance (such as pitch P) between the opposing sidewalls of the inner fin spacers. In some embodiments, the epitaxial structure includes multiple crystal planes. In an exemplary embodiment, the crystal plane directly on the upper surfaces of the first fin and the second fin is substantially parallel to the upper surfaces of the first fin and the second fin. In an exemplary embodiment, the epitaxial structure includes at least one doped epitaxial semiconductor layer. In an exemplary embodiment, the epitaxial structure includes a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer, where the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer have different dopant concentrations. In other embodiments, the first epitaxial layer grows epitaxially on the upper surfaces of the first fin and the second fin, so that the upper surface of the first epitaxial layer is coplanar with the upper surface of the outer fin spacer, and the third epitaxial layer grows conformally on the multiple crystal planes formed by the second epitaxial layer. In one embodiment, the height of a portion of the air gap above the inner fin spacer is between about 1 / 3 and about 1 / 2 of the height H i and about 1 / 2.

[0084] In another embodiment, an exemplary semiconductor structure is provided, which includes a semiconductor substrate; a fin structure including a first fin and a second fin formed on the semiconductor substrate, where inner fin spacers and outer fin spacers are perpendicular to the sidewalls along both sides of each of the first fin and the second fin, and where the inner sidewall spacer of the first fin is adjacent to the inner sidewall spacer of the second fin, and there is a pitch P between the inner sidewall spacers of the first fin and the second fin and they have a height H i , the outer sidewall spacer has a height H o , and the height H i is substantially greater than the height H o ; a gate structure formed on the fin structure; an epitaxial structure formed in the source and drain regions of the fin structure, where the epitaxial structure incorporates the first fin and the second fin and at least one epitaxial semiconductor layer, and the epitaxial semiconductor layer and the inner fin spacer form an air gap; and an isolation region formed on the semiconductor substrate to isolate the first fin and the second fin. In some embodiments, the height of the air gap is at least the height H i , and the width of the air gap is at least the pitch P. In some embodiments, the upper surfaces of the first fin and the second fin are higher than or lower than the upper surface of the isolation region. In some embodiments, the epitaxial structures in the source and drain regions are located on both sides of the gate structure. In some embodiments, the upper surface of the epitaxial structure is substantially parallel to the upper surface of the fin structure.

[0085] In another embodiment, an exemplary method is provided that includes forming a fin structure on a semiconductor substrate, and the fin structure includes a first fin and a second fin, where the first fin and the second fin have a height H f ; forming a gate structure on the fin structure, where the gate structure includes at least one dielectric layer and a gate layer; forming an inner fin spacer and an outer fin spacer along sidewalls of the first fin and the second fin, where the inner fin spacer is located between the first fin and the second fin; etching the inner fin spacer and the outer fin spacer such that the inner fin spacer has a height H i and the outer fin spacer has a height H o where the height H i is greater than the height H o and at least half of the height H f ; recessing the first fin and the second fin; and forming an epitaxial structure in a source region or a drain region by combining the recessed first fin and second fin and at least one epitaxial semiconductor layer. In some embodiments, the epitaxial semiconductor layer and the inner fin spacer form an air gap in the epitaxial structure, and the volume of the air gap is defined by the height Hi and the separation pitch P between the inner fin spacers.

[0086] In some embodiments, the step of etching the inner fin spacer and the outer fin spacer includes: depositing a material layer to fill the space between the inner fin spacers; and anisotropically etching the inner fin spacer and the outer fin spacer. In some embodiments, the step of depositing the material layer includes depositing methane or fluoromethane in an inert carrier gas. In other embodiments, the step of depositing the material layer includes depositing a dielectric material, and the dielectric material is different from the inner fin spacer and the outer fin spacer. In some embodiments, the step of forming the fin structure includes forming a plurality of isolation regions on the semiconductor substrate. In some embodiments, the step of forming the epitaxial structure in the source region or the drain region includes combining the recessed first fin and second fin and a first epitaxial semiconductor layer and a second epitaxial semiconductor layer in the source region or the drain region. In an exemplary embodiment, the first epitaxial semiconductor layer is formed on an upper surface of the recessed first fin and second fin, and the second epitaxial semiconductor layer is formed on an upper surface of the first epitaxial semiconductor layer. In some embodiments, the second epitaxial semiconductor layer includes a plurality of outer crystal planes, where the outer crystal planes directly located on the upper surface of the recessed first fin and second fin are substantially parallel to the upper surface of the recessed first fin and second fin.

[0087] The features of the above embodiments are conducive to those skilled in the art in this technical field to understand the embodiments of the present disclosure. Those skilled in the art in this technical field should understand that the embodiments of the present disclosure can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages as the above embodiments. Those skilled in the art in this technical field should also understand that these equivalent substitutions do not depart from the concept and scope of the present disclosure, and can be changed, replaced, or varied without departing from the concept and scope of the claims of the present disclosure.

Claims

1. A semiconductor structure, comprising: A fin structure having a first fin and a second fin formed on a semiconductor substrate, wherein a channel region of the first fin and the second fin has a height H f ; A plurality of inner fin spacers are formed along the inner sidewalls of the first fin and the second fin, wherein the inner fin spacers have a height H i ; A plurality of outer fin spacers are formed along the outer sidewalls of the first fin and the second fin, wherein the outer fin spacers have a height H o , and the height H o is less than the height H i ; and An epitaxial structure formed on the first fin and the second fin, wherein the epitaxial structure encloses an air gap formed by the inner fin spacers, and the air gap has at least a width P, where the width P is the separation distance between the opposing sidewalls of the inner fin spacers, and wherein the air gap comprises: A first portion between the first fin and the inner fin spacer of the second fin, wherein the first portion has a height H i ; and A second part on the first part, wherein the second part has a height H a , and the height H i and the height H a the sum of which is 30% to 80% of the height H f .

2. The semiconductor structure according to claim 1, wherein, The epitaxial structure comprises a plurality of crystal planes, wherein the crystal planes directly on the upper surfaces of the first fin and the second fin are parallel to the upper surfaces of the first fin and the second fin.

3. The semiconductor structure according to claim 1, wherein, The epitaxial structure comprises at least one doped epitaxial semiconductor layer.

4. The semiconductor structure according to claim 3, wherein, The epitaxial structure comprises a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer, wherein the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer have different dopant concentrations.

5. The semiconductor structure as claimed in claim 4, wherein, The first epitaxial layer grows epitaxially on the upper surfaces of the first fin and the second fin such that the upper surface of the first epitaxial layer is coplanar with the upper surface of the outer fin spacers.

6. The semiconductor structure according to claim 1, wherein, The height H of the second part of the air gap that is higher than the inner fin spacer a , is 1 / 3 to 1 / 2 of the height H i .

7. The semiconductor structure according to claim 1, wherein, The inner fin spacers do not physically contact the first fin and the second fin in a source / drain region.

8. A semiconductor structure, comprising: A semiconductor substrate; A fin structure includes a first fin and a second fin formed on the semiconductor substrate, wherein the channel regions of the first fin and the second fin each have a height H f , wherein a plurality of inner fin spacers and a plurality of outer fin spacers are perpendicular to the sidewalls along both sides of each of the first fin and the second fin, and wherein the inner fin spacers of the first fin are adjacent to the inner fin spacers of the second fin, and a distance P is provided between the inner fin spacers of the first fin and the second fin and they have a height H i , the outer fin spacers have a height H o , and the height H i is greater than the height H o ; A gate structure formed on the fin structure; and An epitaxial structure formed in a source region and a drain region of the fin structure, wherein the epitaxial structure incorporates the first fin and the second fin and at least one epitaxial semiconductor layer, and wherein the at least one epitaxial semiconductor layer forms an air gap with the inner fin spacers, and wherein the air gap comprises: A first portion between the first fin and the inner fin spacer of the second fin, wherein the first portion has a height H i ; and A second part on the first part, wherein the second part has a height H a , and the height H i and the height H a have a sum that is 30% to 80% of the height H f .

9. The semiconductor structure according to claim 8, wherein, The height of the air gap is at least the height H i , and the width of the air gap is at least the distance P.

10. The semiconductor structure of claim 8, further comprising a plurality of isolation regions formed on the semiconductor substrate to isolate the first fin and the second fin, wherein the upper surfaces of the first fin and the second fin are higher than the upper surfaces of the plurality of isolation regions.

11. The semiconductor structure of claim 8, further comprising a plurality of isolation regions formed on the semiconductor substrate to isolate the first fin and the second fin, wherein the upper surfaces of the first fin and the second fin are lower than the upper surfaces of the plurality of isolation regions.

12. The semiconductor structure as claimed in claim 8, wherein, The upper surface of the epitaxial structure is parallel to the upper surface of the fin structure.

13. An integrated circuit device, comprising: A first fin structure and a second fin structure are located on a substrate, wherein a channel region of each of the first fin structure and the second fin structure has a height H f , the first fin structure has an inner sidewall surface, an outer sidewall surface opposite to the inner sidewall surface, and an upper surface extending from the inner sidewall surface to the outer sidewall surface; a first inner dielectric spacer along an inner sidewall surface of the first fin structure, and the first inner dielectric spacer extends a first height H above the substrate i ; An outer dielectric spacer extends along the outer sidewall surface of the first fin structure, and the outer dielectric spacer extends a distance of a second height H above the substrate o , and the second height H o is less than the first height H i ; And An epitaxial semiconductor structure located on the first fin structure and the second fin structure, wherein the epitaxial semiconductor structure seals an air gap between the first fin structure and the second fin structure, and wherein the air gap comprises: A first portion adjacent to the inner dielectric spacer extends to a first height H i ; And A second part located on the first part, wherein the second part has a height H a , wherein a first height H i and the height H a have a sum that is 30% to 80% of the height H f .

14. The integrated circuit device according to claim 13, wherein, The epitaxial semiconductor structure comprises a first epitaxial material, a second epitaxial material, and a third epitaxial material, wherein the first epitaxial material, the second epitaxial material, and the third epitaxial material are different from each other.

15. The integrated circuit device according to claim 14, wherein, The first epitaxial material, the second epitaxial material, and the third epitaxial material comprise the same dopant, wherein the dopant concentration in the first epitaxial material and the dopant concentration in the second epitaxial material, and wherein the dopant concentration in the second epitaxial material and the dopant concentration in the third epitaxial material are different.

16. The integrated circuit device according to claim 13, wherein, The inner dielectric spacer is a first inner dielectric spacer, wherein the inner sidewall surface is a first inner sidewall surface, wherein the outer dielectric spacer is a first outer dielectric spacer, and wherein the outer sidewall surface is a first outer sidewall surface, and the integrated circuit device further comprises: A second inner dielectric spacer, along a second inner sidewall surface of the second fin structure, and the second inner dielectric spacer extends a first height H above the substrate i ; and A second outer dielectric spacer, along a second outer sidewall surface of the second fin structure, and the second outer dielectric spacer extends a distance of a second height H above the substrate o , and wherein the second outer sidewall surface of the second fin structure is opposite to the second inner sidewall surface of the second fin structure.

17. The integrated circuit device according to claim 16, wherein, The air gap extends from the first inner dielectric spacer to the second inner dielectric spacer.

18. The integrated circuit device according to claim 16, wherein, The first inner dielectric spacer has sidewall surfaces on both sides, and wherein the epitaxial semiconductor structure physically contacts one of the sidewall surfaces on both sides, and the air gap interfaces with the other of the sidewall surfaces on both sides of the first inner dielectric spacer.

19. The integrated circuit device according to claim 16, wherein, The air gap extends on the upper surface of the first inner dielectric spacer, and the upper surface of the first inner dielectric spacer is away from the substrate.

20. The integrated circuit device according to claim 13, wherein The air gap interfaces with the inner dielectric spacer.

21. A method of forming a semiconductor structure, comprising: forming a first fin and a second fin protruding from a semiconductor substrate, wherein the first fin and the second fin are defined by a fin height; forming a spacer layer on the first fin and the second fin; The spacer layer is etched to form a plurality of inner spacers and a plurality of outer spacers along both sidewalls of each of the first fin and the second fin, wherein the inner spacers are formed between the first fin and the second fin, and wherein the step of etching the spacer layer causes the inner spacers to extend higher than the outer spacers, wherein the inner spacers have a height H i ; forming a source / drain recess in each of the first fin and the second fin; and Form an epitaxial semiconductor layer in the source / drain recess, wherein the step of forming the epitaxial semiconductor layer forms an air gap with the inner spacer, and the air gap includes: a first portion between the inner spacers and a second portion on the first portion, wherein the first portion has a height H i .

22. The method for forming a semiconductor structure as described in claim 21, wherein, The step of etching the spacer layer includes: performing a main etching process to form the inner spacer and the outer spacer; and performing an over-etching process on the inner spacer and the outer spacer, such that the etching rate of the outer spacer is greater than the etching rate of the inner spacer.

23. The method for forming a semiconductor structure according to claim 21, wherein, The step of etching the spacer layer includes: performing a main etching process to form the inner spacer and the outer spacer; depositing a material layer to fill the space between the first fin and the second fin; and performing an over-etching process on the material layer, wherein the over-etching process removes a portion of the outer spacer at a rate greater than the rate of removing the inner spacer.

24. The method for forming a semiconductor structure according to claim 23, wherein, The step of depositing the material layer includes depositing in an inert carrier gas using methane or fluorinated methane.

25. The method for forming a semiconductor structure as described in claim 23, wherein, The step of depositing the material layer includes depositing a dielectric material, and the dielectric material has a different composition from the spacer layer.

26. The method for forming a semiconductor structure according to claim 21, wherein, The step of forming the epitaxial semiconductor layer merges the first fin and the second fin to create the air gap with the inner spacer.

27. The method for forming a semiconductor structure as described in claim 21, wherein, The epitaxial semiconductor layer is a first epitaxial semiconductor layer, and the method further comprises: forming a second epitaxial semiconductor layer between the first epitaxial semiconductor layer and each of the first fin and the second fin; and forming a third epitaxial semiconductor layer on the first epitaxial semiconductor layer, wherein the doping concentrations among the first epitaxial semiconductor layer, the second epitaxial semiconductor layer, and the third epitaxial semiconductor layer are different.

28. A method of forming a semiconductor structure, comprising: providing a semiconductor substrate; forming a first fin and a second fin on the semiconductor substrate; Forming a plurality of inner fin spacers and a plurality of outer fin spacers on sidewalls of the first fin and the second fin, wherein the inner fin spacers between the first fin and the second fin have a first height, and wherein the outer fin spacers opposite the inner fin spacers have a second height, and the second height is less than the first height; Forming a source / drain structure on a source / drain region of each of the first fin and the second fin, wherein the step of forming the source / drain structure creates an air gap with the inner fin spacers, the air gap including a first portion on a second portion, the second portion being between the inner fin spacers, wherein the height of the second portion is equal to the first height; And Forming a gate structure on a channel region of each of the first fin and the second fin.

29. The method for forming a semiconductor structure as described in claim 28, wherein, The steps of forming the inner fin spacers and the outer fin spacers include: Depositing a spacer layer on the first fin and the second fin; Anisotropically removing portions of the spacer layer to form the inner fin spacers and the outer fin spacers; and Selectively etching the outer fin spacers relative to the inner fin spacers.

30. The method for forming a semiconductor structure as claimed in claim 28, wherein, The steps of forming the source / drain structure include: Recessing the first fin and the second fin; Forming a first epitaxial layer of a first thickness on the recessed first fin and the recessed second fin; Forming a second epitaxial layer of a second thickness on the first epitaxial layer to merge the first fin and the second fin, thereby creating the air gap; and Forming a third epitaxial layer of a third thickness on a surface of the second epitaxial layer, wherein the second thickness is greater than the first thickness and the third thickness.

31. The method for forming a semiconductor structure as described in claim 30, wherein, The first thickness and the third thickness are similar.

32. The method for forming a semiconductor structure as described in claim 30, wherein, The step of forming the second epitaxial layer causes two oblique crystal planes to merge on the inner fin spacers, thereby defining the top of the air gap.

33. The method of forming a semiconductor structure as claimed in claim 28, wherein the first portion is defined by a crystal plane of the source / drain structure and an upper surface of the inner fin spacers.

34. The method for forming a semiconductor structure according to claim 33, wherein, The first portion of the air gap has a third height, the second portion of the air gap has a fourth height, and the fourth height is greater than the third height.

35. The method for forming a semiconductor structure as described in claim 34, wherein, The sum of the third height and the fourth height is less than the height of the first fin or the second fin.

36. A method of forming a semiconductor structure, comprising: Forming adjacent a first fin and a second fin on a semiconductor substrate, wherein the first fin and the second fin are defined by a fin height; Forming a dielectric layer on the first fin and the second fin; The dielectric layer is etched to form a plurality of opposing inner spacers and a plurality of outer spacers on sidewalls of the first fin and the second fin, wherein the inner spacers are located between the first fin and the second fin and extend higher than the outer spacers, and wherein the inner spacers have a height H i ; And A source / drain structure is formed to merge the channel regions of the first fin and the second fin, wherein the step of forming the source / drain structure forms an air gap with the inner spacer, the air gap including a first portion located on a second portion, the second portion being located between the inner spacers, and the second portion having a height H i .

37. The method for forming a semiconductor structure as described in claim 36, wherein, The steps of etching the dielectric layer include: Forming the inner spacers and the outer spacers in a first etching process; and Recessing the inner spacers and the outer spacers in a second etching process, wherein the second etching process recesses the outer spacers at a rate greater than the rate at which the inner spacers are recessed.

38. The method for forming a semiconductor structure according to claim 36, wherein, The height of the inner spacer is at least half of the fin height that defines the first fin and the second fin.

39. The method for forming a semiconductor structure as described in claim 36, wherein, The step of forming the air gap includes forming the first portion of the air gap on the upper surface of the inner spacer and forming the second portion of the air gap between the inner spacers.

40. The method for forming a semiconductor structure as claimed in claim 36, wherein, The height of the air gap is less than the fin height that defines the first fin and the second fin.

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