Etch stop layer topography for advanced integrated circuit structure fabrication

Abstract

Embodiments of the present disclosure are in the field of advanced integrated circuit structure fabrication, and in particular, the field of 10 nanometer node and smaller integrated circuit structure fabrication and resulting structures. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines in an interlayer dielectric (ILD) layer over a substrate and spaced apart by the interlayer dielectric layer. Individual conductive interconnect lines of the plurality of conductive interconnect lines have an upper surface that is lower than an upper surface of the ILD layer. An etch stop layer is on and conformal with the ILD layer and the plurality of conductive interconnect lines, the etch stop layer having a non-planar upper surface, an uppermost portion of the non-planar upper surface being above the ILD layer, and a lowermost portion of the non-planar upper surface being above the plurality of conductive interconnect lines.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 593,149, filed November 30, 2017, entitled “Advanced Integrated Circuit Structure Fabrication,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments of this disclosure are in the field of advanced integrated circuit structure manufacturing, and more specifically, in the field of 10-nanometer node and smaller integrated circuit structure manufacturing and the resulting structures. Background Technology

[0004] For decades, feature scaling in integrated circuits has been a driving force behind the ever-growing semiconductor industry. Scaling to increasingly smaller features allows for greater density of functional units within the limited footprint of a semiconductor chip. For example, shrinking transistor size allows for the integration of a larger number of memory or logic devices onto a single chip, resulting in the manufacture of products with greater capacity. However, this drive for ever-increasing capacity is not without its challenges. The need to optimize the performance of each device has become increasingly important.

[0005] Variations in conventional and currently known manufacturing processes may limit their potential for further expansion to the 10-nanometer or sub-10-nanometer node range. Therefore, manufacturing the functional components required for future technology nodes may require introducing new methods or integrating new technologies into current manufacturing processes, or replacing existing processes altogether. Attached Figure Description

[0006] FIG. 1A A cross-sectional view of the initial structure is shown after the deposition of a hard mask material layer formed on the interlayer dielectric (ILD) layer, but before its patterning.

[0007] FIG. 1B This shows the patterning of the hard mask layer by halving the spacing. FIG. 1A A cross-sectional view of the structure.

[0008] FIG. 2A This is a schematic diagram of a four-part spacing arrangement for manufacturing semiconductor fins according to an embodiment of the present disclosure.

[0009] FIG. 2B A cross-sectional view of a semiconductor fin manufactured using a pitched quartering method according to an embodiment of the present disclosure is shown.

[0010] FIG. 3Ais a schematic diagram of a fused fin pitch quartering approach for fabricating semiconductor fins according to embodiments of the present disclosure.

[0011] FIG. 3B shows a cross-sectional view of a semiconductor fin fabricated using a fused fin pitch quartering approach according to embodiments of the present disclosure.

[0012] FIG. 4A - FIG. 4C shows cross-sectional views representing various operations in a method of fabricating a plurality of semiconductor fins according to embodiments of the present disclosure.

[0013] FIG. 5A shows a cross-sectional view of a pair of semiconductor fins separated by a three-tiered trench isolation structure according to embodiments of the present disclosure.

[0014] FIG. 5B shows a cross-sectional view of another pair of semiconductor fins separated by another three-tiered trench isolation structure according to another embodiment of the present disclosure.

[0015] FIG. 6A - FIG. 6D shows cross-sectional views of various operations in fabricating a three-tiered trench isolation structure according to embodiments of the present disclosure.

[0016] FIG. 7A - FIG. 7E shows tilted three-dimensional cross-sectional views of various operations in a method of fabricating an integrated circuit structure according to embodiments of the present disclosure.

[0017] FIG. 8A - FIG. 8F shows a slightly-projected cross-sectional view taken along the a-a' axis for various operations in a method of fabricating an integrated circuit structure according to embodiments of the present disclosure. FIG. 7E

[0018] FIG. 9A shows a slightly-projected cross-sectional view taken along the a-a' axis for an integrated circuit structure including a permanent gate stack and an epitaxial source or drain region according to embodiments of the present disclosure. FIG. 7E

[0019] FIG. 9B shows a cross-sectional view taken along the b-b' axis for an integrated circuit structure including an epitaxial source or drain region and a multi-tiered trench isolation structure according to embodiments of the present disclosure. FIG. 7E

[0020] FIG. 10 shows a cross-sectional view of an integrated circuit structure taken at a source or drain location according to embodiments of the present disclosure.

[0021] FIG. 11 shows a cross-sectional view of another integrated circuit structure taken at a source or drain location according to embodiments of the present disclosure.​​​

[0022] FIG. 12A - FIG. 12D Cross-sectional views showing various operations in a method of intercepting at a source or drain location and representing fabrication of an integrated circuit structure are shown in accordance with an embodiment of the present disclosure.

[0023] FIG. 13A and FIG. 13B Plan views representing various operations in a method of patterning a fin with multiple gate spacing for forming a local isolation structure are shown in accordance with an embodiment of the present disclosure.

[0024] FIG. 14A - FIG. 14D Plan views representing various operations in a method of patterning a fin with single gate spacing for forming a local isolation structure are shown in accordance with another embodiment of the present disclosure.

[0025] FIG. 15 Cross-sectional views of an integrated circuit structure with a fin with multiple gate spacing for local isolation are shown in accordance with an embodiment of the present disclosure.

[0026] FIG. 16A Cross-sectional views of an integrated circuit structure with a fin with single gate spacing for local isolation are shown in accordance with another embodiment of the present disclosure.

[0027] FIG. 16B Cross-sectional views showing locations where a fin isolation structure can be formed to replace a gate electrode are shown in accordance with an embodiment of the present disclosure.

[0028] FIG. 17A - FIG. 17C Various depth possibilities for fin cutouts fabricated using a fin trim isolation approach are shown in accordance with an embodiment of the present disclosure.

[0029] FIG. 18 Plan views and corresponding cross-sectional views taken along the a-a' axis showing possible options for depth of a local location of a fin cutout within a fin compared to depth of a wider location are shown in accordance with an embodiment of the present disclosure.

[0030] FIG. 19A and FIG. 19B Cross-sectional views showing various operations in a method of selecting a fin end stressor location at an end of a fin with a wide cutout are shown in accordance with an embodiment of the present disclosure.

[0031] FIG. 20A and FIG. 20B Cross-sectional views showing various operations in a method of selecting a fin end stressor location at an end of a fin with a local cutout are shown in accordance with an embodiment of the present disclosure.

[0032] FIG. 21A - FIG. 21MCross-sectional views showing various operations in a method of fabricating an integrated circuit structure having differentiated fin end dielectric plugs, in accordance with an embodiment of the present disclosure.

[0033] FIG. 22A - FIG. 22D Cross-sectional views showing an exemplary structure of a PMOS fin end stressor dielectric plug, in accordance with an embodiment of the present disclosure.

[0034] FIG. 23A Cross-sectional views showing another semiconductor structure having fin end stress inducing features, in accordance with another embodiment of the present disclosure.

[0035] FIG. 23B Cross-sectional views showing another semiconductor structure having fin end stress inducing features, in accordance with another embodiment of the present disclosure.

[0036] FIG. 24A Oblique views showing a fin having uniaxial tensile stress, in accordance with an embodiment of the present disclosure.

[0037] FIG. 24B Oblique views showing a fin having uniaxial compressive stress, in accordance with an embodiment of the present disclosure.

[0038] FIG. 25A And FIG. 25B Plan views showing various operations in a method of patterning a fin having single gate spacing for forming a local isolation structure at a select gate line cut location, in accordance with an embodiment of the present disclosure.

[0039] FIG. 26A - FIG. 26C Cross-sectional views showing various possibilities for dielectric plugs for multiple cut and fin trim isolation (FTI) local fin cut locations and multiple cut only locations for structures of FIG. 25B

[0040] FIG. 27A Plan and corresponding cross-sectional views showing an integrated circuit structure having a gate line cut with a dielectric spacer with a dielectric plug extending into the gate line, in accordance with an embodiment of the present disclosure.

[0041] FIG. 27B Plan and corresponding cross-sectional views showing an integrated circuit structure having a gate line cut with a dielectric spacer with a dielectric plug extending outside of the gate line, in accordance with another embodiment of the present disclosure.

[0042] FIG. 28A - FIG. 28F ​Cross-sectional views of various operations in a method of manufacturing an integrated circuit structure having a gate line cutout with a dielectric plug according to another embodiment of the present disclosure are shown, the dielectric plug having an upper portion extending outside the dielectric spacer of the gate line and a lower portion extending into the gate line dielectric spacer.

[0043] FIG. 29A - FIG. 29C A plan view and a corresponding cross-sectional view of an integrated circuit structure having residual dummy gate material at a portion of the bottom of a permanent gate stack, according to an embodiment of the present disclosure, are shown.

[0044] FIG. 30A - FIG. 30D Cross-sectional views are shown of various operations in a method for manufacturing an integrated circuit structure having residual dummy gate material at a portion of the bottom of a permanent gate stack, according to another embodiment of the present disclosure.

[0045] FIG. 31A A cross-sectional view of a semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to an embodiment of the present disclosure is shown.

[0046] FIG. 31B A cross-sectional view of another semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to another embodiment of the present disclosure is shown.

[0047] FIG. 32A A plan view of a plurality of gate lines situated above a pair of semiconductor fins according to an embodiment of the present disclosure is shown.

[0048] FIG. 32B The following is illustrated according to an embodiment of the present disclosure. FIG. 32A A cross-sectional view taken along the a-a' axis.

[0049] FIG. 33A Cross-sectional views of an NMOS device pair and a PMOS device pair according to embodiments of the present disclosure are shown, the NMOS device pair having a differentiated voltage threshold based on modulated doping, and the PMOS device pair having a differentiated voltage threshold based on modulated doping.

[0050] FIG. 33B Cross-sectional views of an NMOS device pair and a PMOS device pair according to another embodiment of the present disclosure are shown. The NMOS device pair has a differentiated voltage threshold based on a differentiated gate electrode structure, and the PMOS device pair has a differentiated voltage threshold based on a differentiated gate electrode structure.

[0051] FIG. 34ACross-sectional views showing various operations in a method of fabricating an NMOS device having a differentiated voltage threshold based on a differentiated gate electrode structure, in accordance with an embodiment of the disclosure.

[0052] FIG. 34B Cross-sectional views showing three NMOS devices having differentiated voltage thresholds based on a differentiated gate electrode structure and modulated doping and three PMOS devices having differentiated voltage thresholds based on a differentiated gate electrode structure and modulated doping, in accordance with another embodiment of the disclosure.

[0053] FIG. 35A - FIG. 35D Cross-sectional views showing various operations in a method of fabricating an NMOS device having a differentiated voltage threshold based on a differentiated gate electrode structure, in accordance with an embodiment of the disclosure.

[0054] FIG. 36A - FIG. 36D Cross-sectional views showing various operations in a method of fabricating a PMOS device having a differentiated voltage threshold based on a differentiated gate electrode structure, in accordance with an embodiment of the disclosure.

[0055] FIG. 37 Cross-sectional views showing an integrated circuit structure having a P / N junction, in accordance with an embodiment of the disclosure.

[0056] FIG. 38A - FIG. 38H Cross-sectional views showing various operations in a method of fabricating an integrated circuit structure using a dual metal gate replacement gate process flow, in accordance with an embodiment of the disclosure.

[0057] FIG. 39A - FIG. 39H Cross-sectional views showing various operations in a method of fabricating a dual silicide based integrated circuit, in accordance with an embodiment of the disclosure.

[0058] FIG. 40A Cross-sectional views showing an integrated circuit structure having a trench contact for an NMOS device, in accordance with an embodiment of the disclosure.

[0059] FIG. 40B Cross-sectional views showing an integrated circuit structure having a trench contact for a PMOS device, in accordance with another embodiment of the disclosure.

[0060] FIG. 41A Cross-sectional views showing a semiconductor device having a conductive contact on a source or drain region, in accordance with an embodiment of the disclosure.

[0061] FIG. 41BA cross-sectional view of another semiconductor device having conductive contacts on a raised source or drain region according to an embodiment of the present disclosure is shown.

[0062] FIG. 42 A plan view of a plurality of gate lines situated above a pair of semiconductor fins according to an embodiment of the present disclosure is shown.

[0063] FIG. 43A - FIG. 43C The diagram illustrates various operations along the path of a method for manufacturing an integrated circuit structure according to embodiments of the present disclosure. FIG. 42 A cross-sectional view taken along the a-a' axis.

[0064] FIG. 44 The following diagram illustrates the edge of an integrated circuit structure according to an embodiment of the present disclosure. FIG. 42 The cross-sectional view taken along the b-b' axis.

[0065] FIG. 45A and FIG. 45B Plan view and corresponding cross-sectional view of an integrated circuit structure including a trench contact plug having a hard mask material thereon, according to embodiments of the present disclosure, are shown respectively.

[0066] FIG. 46A - FIG. 46D Cross-sectional views are shown of various operations in a method of manufacturing an integrated circuit structure including trench contact plugs having hard mask material thereon, according to embodiments of the present disclosure.

[0067] FIG. 47A A plan view of a semiconductor device having a gate contact disposed on the non-active portion of the gate electrode is shown. FIG. 47B A cross-sectional view of a nonplanar semiconductor device having a gate contact disposed on the non-active portion of the gate electrode is shown.

[0068] FIG. 48A A plan view of a semiconductor device having a gate contact via disposed on an active portion of a gate electrode, according to an embodiment of the present disclosure, is shown. FIG. 48B A cross-sectional view of a non-planar semiconductor device having a gate contact via disposed on an active portion of a gate electrode, according to an embodiment of the present disclosure, is shown.

[0069] FIG. 49A - FIG. 49D Cross-sectional views are shown illustrating various operations in a method of manufacturing a semiconductor structure having a gate contact structure disposed on an active portion of the gate, according to embodiments of the present disclosure.

[0070] FIG. 50 Plan view and corresponding cross-sectional view of an integrated circuit structure having a trench contact portion including an overlying insulating cap layer according to an embodiment of the present disclosure are shown.

[0071] FIG. 51A - FIG. 51F Cross-sectional views showing various integrated circuit structures according to embodiments of the disclosure, each having a trench contact including an overlying insulating cap layer and having a gate stack including an overlying insulating cap layer.

[0072] FIG. 52A A plan view showing another semiconductor device having a gate contact via disposed over an active portion of a gate according to another embodiment of the disclosure.

[0073] FIG. 52B A plan view showing another semiconductor device having a trench contact via coupling a pair of trench contacts according to another embodiment of the disclosure.

[0074] FIG. 53A - FIG. 53E Cross-sectional views showing various operations in a method of fabricating an integrated circuit structure with a gate stack having an overlying insulating cap layer according to embodiments of the disclosure.

[0075] FIG. 54 A schematic diagram of a pitch quartering scheme for fabricating trenches of an interconnect structure according to embodiments of the disclosure.

[0076] FIG. 55A A cross-sectional view showing a metallization layer fabricated using a pitch quartering scheme according to embodiments of the disclosure.

[0077] FIG. 55B A cross-sectional view showing a metallization layer fabricated using a pitch halving scheme over a metallization layer fabricated using a pitch quartering scheme according to embodiments of the disclosure.

[0078] FIG. 56A A cross-sectional view showing an integrated circuit structure according to embodiments of the disclosure in which a metallization layer having one metal line composition is over a metallization layer having a different metal line composition.

[0079] FIG. 56B A cross-sectional view showing an integrated circuit structure according to embodiments of the disclosure in which a metallization layer having one metal line composition is coupled to a metallization layer having a different metal line composition.

[0080] FIG. 57A - FIG. 57C A cross-sectional view showing an individual interconnect line having various liner and conductive cap structure arrangements according to embodiments of the disclosure.

[0081] FIG. 58 A cross-sectional view showing an integrated circuit structure according to embodiments of the disclosure in which four metallization layers having one metal line composition and pitch are over two metallization layers having a different metal line composition and a smaller pitch.

[0082] FIG. 59A - FIG. 59D Cross-sectional views showing various interconnects and via arrangements with bottom conductive layers are shown in accordance with embodiments of the present disclosure.

[0083] FIG. 60A - FIG. 60D Cross-sectional views showing structural arrangements for recess line topography for BEOL metallization layers are shown in accordance with embodiments of the present disclosure.

[0084] FIG. 61A - FIG. 61D Cross-sectional views showing structural arrangements for stepped line topography for BEOL metallization layers are shown in accordance with embodiments of the present disclosure.

[0085] FIG. 62A Plan views and corresponding cross-sectional views taken along the a-a' axis of a plan view of a metallization layer are shown in accordance with embodiments of the present disclosure.

[0086] FIG. 62B Cross-sectional views showing line end or plug are shown in accordance with embodiments of the present disclosure.

[0087] FIG. 62C Another cross-sectional view showing line end or plug are shown in accordance with embodiments of the present disclosure.

[0088] FIG. 63A - FIG. 63F Plan views and corresponding cross-sectional views showing various operations in a plug final processing scheme are shown in accordance with embodiments of the present disclosure.

[0089] FIG. 64A Cross-sectional views showing conductive line plugs with seams therein are shown in accordance with embodiments of the present disclosure.

[0090] FIG. 64B Cross-sectional views showing stacks of metallization layers including conductive line plugs at underlying metal line locations are shown in accordance with embodiments of the present disclosure.

[0091] FIG. 65 A first view of a cell layout for a memory cell is shown.

[0092] FIG. 66 A first view of a cell layout for a memory cell with internal node jumpers is shown in accordance with embodiments of the present disclosure.

[0093] FIG. 67 A second view of a cell layout for a memory cell is shown.

[0094] FIG. 68 A second view of a cell layout for a memory cell with internal node jumpers is shown in accordance with embodiments of the present disclosure.

[0095] FIG. 69 A third view of a cell layout for a memory cell is shown.

[0096] FIG. 70 A third view is shown of a cell layout for a memory cell with internal node jumpers according to an embodiment of the present disclosure.

[0097] FIG. 71A and FIG. 71B Bit cell layouts and schematic diagrams for a six-transistor (6T) static random access memory (SRAM) according to embodiments of the present disclosure are shown respectively.

[0098] FIG. 72 Cross-sectional views of two different layouts for the same standard cell according to embodiments of the present disclosure are shown.

[0099] FIG. 73 A plan view of four different unit arrangements specified by an even (E) or odd (O) indicator according to embodiments of the present disclosure is shown.

[0100] FIG. 74 A plan view of a block-level multigrid according to an embodiment of the present disclosure is shown.

[0101] FIG. 75 An exemplary acceptable (through) layout based on standard units with different versions is shown according to embodiments of this disclosure.

[0102] FIG. 76 An exemplary unacceptable (failure) layout based on standard units with different versions is shown according to embodiments of this disclosure.

[0103] FIG. 77 Another exemplary acceptable (through) layout based on a standard unit with a different version is shown according to an embodiment of this disclosure.

[0104] FIG. 78 Partially cut plan view and corresponding cross-sectional view of a fin-based thin-film resistor structure according to an embodiment of the present disclosure are shown, wherein the cross-sectional view is cut along the a-a' axis of the partially cut plan view.

[0105] FIG. 79 - FIG. 83 Plan views and corresponding cross-sectional views are shown representing various operations in a method for manufacturing a fin-based thin-film resistor structure according to embodiments of the present disclosure.

[0106] FIG. 84 A plan view of a fin-based thin-film resistor structure having various exemplary positions for anode or cathode electrode contacts according to embodiments of the present disclosure is shown.

[0107] FIG. 85A - FIG. 85DA plan view of various fin geometries for manufacturing fin-based precision resistors according to embodiments of the present disclosure is shown.

[0108] FIG. 86 A cross-sectional view of a photolithographic mask structure according to an embodiment of the present disclosure is shown.

[0109] FIG. 87 A computing device according to one embodiment of the present disclosure is shown.

[0110] FIG. 88 An interpolator including one or more embodiments of the present disclosure is shown.

[0111] FIG. 89 This is an isometric view of a mobile computing platform according to an embodiment of the present disclosure, which employs an IC manufactured according to one or more processes described herein or includes one or more features described herein.

[0112] FIG. 90 A cross-sectional view of a flip-chip mounted die according to an embodiment of the present disclosure is shown. Detailed Implementation

[0113] The fabrication of advanced integrated circuit structures is described. Numerous specific details, such as specific integration and material systems, are set forth in the following description to provide a thorough understanding of embodiments of this disclosure. It will be apparent to those skilled in the art that embodiments of this disclosure can be practiced without these specific details. In other instances, well-known features such as integrated circuit design layouts have not been described in detail to avoid unnecessarily obscuring embodiments of this disclosure. Furthermore, it should be recognized that the various embodiments shown in the figures are exemplary representations and are not necessarily drawn to scale.

[0114] The following detailed descriptions are merely illustrative in nature and are not intended to limit the scope of the subject matter or the application and use of such embodiments. As used herein, the term "exemplary" means "serving as an example, instance, or illustration." Any implementation described herein as exemplary should not be construed as being preferred or advantageous over other implementations. Furthermore, it is not intended to be limited by any express or implied theory presented in the foregoing technical field, background art, summary of the invention, or the following detailed descriptions.

[0115] This specification includes references to "one embodiment" or "embodiment". The appearance of the phrase "in one embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. Specific features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.

[0116] Terminology. The following paragraphs provide definitions or context for terms found in this disclosure, including the appended claims:

[0117] “Include.” This term is open-ended. As used in the appended claims, this term does not foreclose additional structure or operational steps. In other words, an implementation that includes additional structure or operational steps can be construed as having satisfied the terms of the claims.

[0118] “Configured to.” Various units or components can be described or claimed as “configured to” perform a task or tasks. In such contexts, “configured to” is used to connote structure by indicating that a unit or component includes structure (e.g., circuitry) that performs the task or tasks during operation. As such, the unit or component can be said to be configured to perform the task or tasks even when the unit or component is not currently operational (e.g., is not on or active). Reciting that a unit or component is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112, paragraph six, for that unit or component.

[0119] “First,”“second,” etc. As used herein, these terms are used as labels in reference to a noun that they directly follow, such that additional structures or operations can be performed in addition to those described by the claim.

[0120] “Coupled” - The following description refers to elements or nodes or features being “coupled” together. As used herein, “coupled” means elements or nodes or features are directly connected to one another (or directly communicate with one another) either chemically, physically or both, and not necessarily mechanically.

[0121] Also, certain terms are used throughout the following description and claims to refer to particular structures or steps. Each term can refer to a different structure or step. This is only for convenience and does not intend to limit the application. For example, words such as “upper,” “lower,” “front,” “back,” “side,” “under,” “above,” “below,” “top,” “bottom,” “out,” “in,” “vertical,” “horizontal,” and “vertical” describe the orientation of elements on the drawings as presented. Terms such as “front,” “back,” “rear,” “side,” “outboard,” and “inboard” describe the orientation of portions of elements within a consistent but arbitrary frame of reference which is for convenience not portrayed explicitly on the drawings. Such terms can include the above specifically mentioned words, actions that are derivatives of such words, and words of similar import.

[0122] “Suppress” - As used herein, suppress is used to describe reducing or minimizing an effect. When a component or feature is described as suppressing a behavior, motion, or condition, it can completely prevent the result or outcome or future state. Additionally, suppress can also refer to reducing or lessening an outcome, manifestation, or effect that might otherwise occur. Thus, when a component, element, or feature is said to suppress a result or state, it does not necessarily completely prevent or eliminate the result or state.

[0123] Embodiments described herein can relate to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first portion of integrated circuit (IC) fabrication in which individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. After the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wiring).

[0124] Embodiments described herein can relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second portion of IC fabrication in which individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., one or more metallization layers) on the wafer. BEOL includes contacts, insulating layers (dielectric), metal levels, and bonding sites for chip-to-package connections. In the BEOL portion of the fabrication phase, contacts (pads), interconnect lines, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers can be added in BEOL.

[0125] Embodiments described below can be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although exemplary processing schemes can be illustrated using FEOL processing scenarios, such approaches can also be applicable to BEOL processing. Likewise, although exemplary processing schemes can be illustrated using BEOL processing scenarios, such approaches can also be applicable to FEOL processing.

[0126] Pitch division processing and patterning schemes can be implemented to achieve embodiments described herein, or can be included as part of embodiments described herein. Pitch division patterning typically refers to pitch halving, pitch quartering, etc. Pitch division schemes can be applicable to FEOL processing, BEOL processing, or both FEOL (device) and BEOL (metallization) processing. According to one or more embodiments described herein, lithography is first implemented to print unidirectional lines (e.g., strictly unidirectional or predominantly unidirectional) with a predefined pitch. Pitch division processing is then implemented as a technique to increase line density.

[0127] In embodiments, the term "lattice structure" as used herein for fins, gate lines, metal lines, ILD lines, or hardmask lines refers to a close pitch lattice structure. In one such embodiment, the close pitch cannot be achieved directly by the selected lithography. For example, a pattern based on the selected lithography can first be formed, but the pitch can be halved with a spacer mask patterning, as is known in the art. Still further, the initial pitch can be quartered by a second round of spacer mask patterning. Thus, the lattice-like patterns described herein can have metal lines, ILD lines, or hardmask lines spaced at substantially uniform pitch and having substantially uniform width. For example, in some embodiments, the pitch varies within ten percent, the width varies within ten percent, and in some embodiments, the pitch varies within five percent, the width varies within five percent. The pattern can be fabricated by pitch halving or pitch quartering, or other pitch division means. In embodiments, the lattice is not necessarily a single pitch.

[0128] In a first example, pitch halving can be implemented to double the line density of the fabricated lattice structure. FIG. 1A A cross-sectional view of a starting structure is shown after deposition of a hardmask material layer formed on an interlayer dielectric (ILD) layer, but before patterning thereof. FIG. 1B A cross-sectional view of the structure is shown after patterning of the hardmask layer by pitch halving. FIG. 1A A cross-sectional view of the structure is shown after patterning of the hardmask layer by pitch halving.

[0129] Referring to FIG. 1A The starting structure 100 has a hardmask material layer 104 formed on an interlayer dielectric (ILD) layer 102. A patterning mask 106 is disposed over the hardmask material layer 104. The patterning mask 106 has spacers 108 formed on the sidewalls of the features (lines) of the hardmask material layer 104.

[0130] Referring to FIG. 1B The hardmask material layer 104 is patterned using pitch halving. Specifically, the patterning mask 106 is first removed. The resulting pattern of spacers 108 has doubled the density of the mask 106, or halved the pitch or features of the mask 106. The pattern of spacers 108 is transferred to the hardmask material layer 104, for example, by an etching process to form a patterned hardmask 110, as shown in FIG. IB. In one such embodiment, the patterned hardmask 110 is formed to have a lattice pattern with unidirectional lines. The lattice pattern of the patterned hardmask 110 can be a close pitch lattice pattern. For example, the close pitch can not be achievable directly by the selected lithography technique. Still further, although not shown, the initial pitch can be quartered by a second round of spacer mask patterning. Thus, the patterned hardmask 110 can have metal lines, ILD lines, or hardmask lines spaced at substantially uniform pitch and having substantially uniform width. For example, in some embodiments, the pitch varies within ten percent, the width varies within ten percent, and in some embodiments, the pitch varies within five percent, the width varies within five percent. The pattern can be fabricated by pitch halving or pitch quartering, or other pitch division means. In embodiments, the lattice is not necessarily a single pitch. FIG. 1BThe grid-like pattern of the patterned hardmask 110 can have hardmask lines that are spaced apart from one another at a constant pitch and have a constant width. The dimensions achieved can be much smaller than the critical dimensions of the lithography technology employed.

[0131] Thus, for either the front-end-of-line (FEOL) or the back-end-of-line (BEOL) or both, a uniform thickness film can be patterned using lithography and etching processes, which can involve, for example, spacer-based double patterning (SBDP) or pitch halving, or spacer-based quadruple patterning (SBQP) or pitch quartering. It should be appreciated that other pitch division approaches can also be implemented. In any case, in embodiments, the gridded layout can be fabricated by a selected lithography approach, such as 193 nm immersion lithography (193i). The pitch division can be implemented to increase the density of the lines in the gridded layout by a factor of n. The gridded layout formation using 193i lithography plus "n" times pitch division can be designated as 193i + P / n pitch division. In one such embodiment, 193 nm immersion scaling can be extended many generations with cost-efficient pitch division.

[0132] In the fabrication of integrated circuit devices, as feature sizes continue to shrink, multi-gate transistors, such as tri-gate transistors, have become more prevalent. Tri-gate transistors are typically fabricated on either a bulk silicon substrate or a silicon-on- insulator substrate. In some instances, bulk silicon substrates are preferred because they are less expensive and compatible with existing high-yield bulk silicon substrate infrastructure.

[0133] However, scaling multi-gate transistors is not without consequence. As the size of these building blocks of microelectronic circuits shrinks and as the absolute number of building blocks fabricated in a given area increases, the constraints on the semiconductor processes used to fabricate these building blocks have become overwhelming.

[0134] According to one or more embodiments of the present disclosure, a pitch quartering approach is implemented for patterning a semiconductor layer to form a semiconductor fin. In one or more embodiments, a merged fin pitch quartering approach is implemented.

[0135] FIG. 2A is a schematic diagram of a pitch quartering approach 200 for fabricating a semiconductor fin according to embodiments of the present disclosure. FIG. 2B is a cross-sectional view showing a semiconductor fin fabricated using a pitch quartering approach according to embodiments of the present disclosure.

[0136] Reference FIG. 2AAt operation (a), a photoresist layer (PR) is patterned to form photoresist features 202. The photoresist features 202 can be patterned using standard photolithography processing techniques such as 193 immersion lithography. At operation (b), a material layer such as an insulating layer or a dielectric hardmask layer is patterned using the photoresist features 202 to form first backbone (BB1) features 204. First spacer (SP1) features 206 are then formed adjacent to sidewalls of the first backbone features 204. At operation (c), the first backbone features 204 are removed to leave only the first spacer features 206. Prior to or during removal of the first backbone features 204, the first spacer features 206 can be thinned to form thinned first spacer features 206’ as shown in FIG. 2A depending on the spacing and size required for the BB2 features (208, described below), this thinning can be performed prior to or after removal of the BB1 features (204), as shown. At operation (d), the first spacer features 206 or the thinned first spacer features 206’ are used to pattern a material layer such as an insulating layer or a dielectric hardmask layer to form second backbone (BB2) features 208. Second spacer (SP2) features 210 are then formed adjacent to sidewalls of the second backbone features 208. At operation (e), the second backbone features 208 are removed to leave only the second spacer features 210. The remaining second spacer features 210 can then be used to pattern a semiconductor layer to provide a plurality of semiconductor fins having a pitch quartered size relative to the initial patterned photoresist features 202. As an example, referring to FIG. 2B , a plurality of semiconductor fins 250, such as silicon fins formed from a bulk silicon layer, are formed using the second spacer features 210 as a mask for patterning (e.g., dry or plasma etch patterning). FIG. 2B In an example, the plurality of semiconductor fins 250 all have substantially the same pitch and spacing.

[0137] It is to be appreciated that the spacing between the initial patterned photoresist features can be modified to change the structural outcome of the pitch quartering process. In an example, FIG. 3A is a schematic diagram of a fused fin pitch quartering approach 300 for fabricating semiconductor fins according to an embodiment of the present disclosure. FIG. 3B is a cross-sectional view showing a semiconductor fin fabricated using the fused fin pitch quartering approach according to an embodiment of the present disclosure.

[0138] Referring to FIG. 3AIn operation (a), a photoresist layer (PR) is patterned to form photoresist features 302. The photoresist features 302 can be patterned using standard photolithography processing techniques such as 193 immersion photolithography, but with spacings that can ultimately conflict with design rules needed to produce a uniform multiple of pitch pattern, e.g., spacings referred to as sub-design rule space. In operation (b), a layer of material such as an insulating layer or a dielectric hard mask layer is patterned using the photoresist features 302 to form first backbone (BB1) features 304. First spacer (SP1) features 306 are then formed adjacent to sidewalls of the first backbone features 304. However, unlike FIG. 2A the scheme shown in FIG. 3A , due to the tighter photoresist features 302, some of the adjacent first spacer features 306 are fused spacer features. In operation (c), the first backbone features 304 are removed to leave only the first spacer features 306. Prior to or after removing the first backbone features 304, some of the first spacer features 306 can be thinned to form thinned first spacer features 306’ as shown in FIG. 3A . In operation (d), a layer of material such as an insulating layer or a dielectric hard mask layer is patterned using the first spacer features 306 and the thinned first spacer features 306’ to form second backbone (BB2) features 308. Second spacer (SP2) features 310 are then formed adjacent to sidewalls of the second backbone features 308. However, at locations where the BB2 features 308 are fused features, e.g., at the center BB2 features 308 of , no second spacer is formed. In operation (e), the second backbone features 308 are removed to leave only the second spacer features 310. The remaining second spacer features 310 can then be used to pattern a semiconductor layer to provide a plurality of semiconductor fins having a pitch quartered size relative to the initial patterned photoresist features 302.

[0139] As an example, referring to FIG. 3B , the second spacer features 310 are used as a mask for patterning, e.g., dry or plasma etch patterning, to form a plurality of semiconductor fins 350, e.g., silicon fins formed from a bulk silicon layer. However, in the example of FIG. 3B , the plurality of semiconductor fins 350 have varying pitch and spacing. Such a fused fin spacer patterning approach can be implemented to substantially eliminate the presence of fins in certain locations of the pattern of the plurality of fins. Thus, fusing the first spacer features 306 in certain locations allows for the fabrication of six or four fins based on two first backbone features 304 that would typically produce eight fins as in conjunction with FIG. 2A and FIG. 2BThe. In one example, in a plate, the fins have a pitch that is tighter than the pitch that would normally be allowed by creating fins at a uniform pitch and then cutting away unwanted fins, although the latter approach can still be implemented according to embodiments described herein.

[0140] In an example embodiment, reference is made to FIG. 3B , an integrated circuit structure, a first plurality of semiconductor fins 352 have a longest dimension along a first direction (y, into the page). Adjacent individual semiconductor fins 353 of the first plurality of semiconductor fins 352 are spaced apart from each other in a second direction (x) orthogonal to the first direction by a first amount (SI). A second plurality of semiconductor fins 354 have a longest dimension along the first direction y. Adjacent individual semiconductor fins 355 of the second plurality of semiconductor fins 354 are spaced apart from each other in the second direction by the first amount (SI). Nearest semiconductor fins 356 and 357 of the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354, respectively, are spaced apart from each other in the second direction x by a second amount (S2). In an embodiment, the second amount S2 is greater than the first amount SI, but less than twice the first amount SI. In another embodiment, the second amount S2 exceeds twice the first amount SI.

[0141] In one embodiment, the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 comprise silicon. In one embodiment, the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 are continuous with an underlying single crystalline silicon substrate. In one embodiment, individual fins of the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 have sidewalls that taper outwardly from a top to a bottom of the individual fins of the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 along the second direction x. In one embodiment, the first plurality of semiconductor fins 352 has exactly five semiconductor fins, and the second plurality of semiconductor fins 354 has exactly five semiconductor fins.

[0142] In another example embodiment, reference is made to FIG. 3A and FIG. 3BA method of fabricating an integrated circuit structure includes forming a first primary backbone structure 304 (left BB1) and a second primary backbone structure 304 (right BB1). A primary spacer structure 306 is formed adjacent to sidewalls of the first primary backbone structure 304 (left BB1) and the second primary backbone structure 304 (right BB1). The primary spacer structure 306 between the first primary backbone structure 304 (left BB1) and the second primary backbone structure 304 (right BB1) is fused. The first primary backbone structure (left BB1) and the second primary backbone structure (right BB1) are removed and first, second, third, and fourth secondary backbone structures 308 are provided. The second and third secondary backbone structures (e.g., the middle pair of secondary backbone structures 308) are fused. A secondary spacer structure 310 is formed adjacent to sidewalls of the first, second, third, and fourth secondary backbone structures 308. The first, second, third, and fourth secondary backbone structures 308 are then removed. The semiconductor material is then patterned using the secondary spacer structure 310 to form semiconductor fins 350 in the semiconductor material.

[0143] In one embodiment, the first primary backbone structure 304 (left BB1) and the second primary backbone structure 304 (right BB1) are patterned with a sub-design rule spacing between the first primary backbone structure and the second primary backbone structure. In one embodiment, the semiconductor material includes silicon. In one embodiment, individual ones of the semiconductor fins 350 have sidewalls that taper outwardly from a top to a bottom of the individual ones of the semiconductor fins 350 along a second direction x. In one embodiment, the semiconductor fins 350 are continuous with an underlying single crystalline silicon substrate. In one embodiment, patterning the semiconductor material using the secondary spacer structure 310 includes forming a first plurality of semiconductor fins 352 having a longest dimension along a first direction y, where adjacent individual ones of the first plurality of semiconductor fins 352 are spaced apart from each other by a first amount S1 along a second direction x that is orthogonal to the first direction y. A second plurality of semiconductor fins 354 having a longest dimension along the first direction y is formed, where adjacent individual ones of the second plurality of semiconductor fins 354 are spaced apart from each other by the first amount S1 along the second direction x. Nearest semiconductor fins 356 and 357 of the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354, respectively, are spaced apart from each other by a second amount S2 along the second direction x. In embodiments, the second amount S2 is greater than the first amount S1. In one such embodiment, the second amount S2 is less than twice the first amount S1. In another such embodiment, the second amount S2 is greater than twice the first amount S1 but less than three times the first amount S1. In embodiments, as FIG. 3BAs shown in the middle, the first plurality of semiconductor fins 352 has exactly five semiconductor fins, and the second plurality of semiconductor fins 354 has exactly five semiconductor fins.

[0144] In another aspect, it is recognized that a fin trim process, in which fin removal is performed as an alternative to the merged fin approach, can trim (remove) fins during hard mask patterning or by physically removing the fins. As an example of the latter approach, FIG. 4A - FIG. 4C Cross-sectional views representing various operations in a method of fabricating a plurality of semiconductor fins according to embodiments of the present disclosure are shown.

[0145] Referring to FIG. 4A A patterned hard mask layer 402 is formed over a semiconductor layer 404, such as a bulk single crystal silicon layer. Referring to FIG. 4B Fins 406 are then formed in the semiconductor layer 404 by, for example, a dry or plasma etching process. Referring to FIG. 4C For example, selected fins 406 are removed using a masking and etching process. In the illustrated example, one of the fins 406 is removed and can leave a residual fin stub 408. In such a "fin trim last" approach, the hard mask 402 is patterned as a whole to provide a grid structure without removing or modifying individual features. The total number of fins is not modified until after the fins are fabricated.

[0146] In another aspect, a multi-layered trench isolation region can be implemented between semiconductor fins, which can be referred to as a shallow trench isolation (STI) structure. In an embodiment, a multi-layered STI structure is formed between silicon fins formed in a bulk silicon substrate to define a sub-fin region of the silicon fins.

[0147] It can be desirable to use bulk silicon for fin or tri-gate based transistors. However, it is a concern that the region (sub-fin) under the active silicon fin portion of the device (e.g., gate controlled region, or HSi) is eliminated or not under gate control. As such, if the source or drain region is at or below the HSi point, then there can be a leakage path through the sub-fin region. It can be the case that the leakage path in the sub-fin region should be controlled for the device to operate properly.

[0148] One way to address the above issues involves using a well implant operation in which the sub-fin region is heavily doped (e.g., much greater than 2E18 / cm 3 ), which cuts off the sub-fin leakage, but also results in significant doping in the fin. A halo implant is added to further increase the fin doping so that the end of the line fin is doped at a high level (e.g., greater than about 1E18 / cm 3 ).

[0149] Another approach involves doping via sub-fin doping without having to deliver the same level of doping to the HSi portion of the fin. The process can involve selectively doping the sub-fin regions of a tri-gate or FinFET transistor fabricated on a bulk silicon wafer via, for example, diffusion from a tri-gate doped glass sub-fin. For example, selective doping of the sub-fin regions of a tri-gate or FinFET transistor can mitigate sub-fin leakage while keeping the fin doping very low. A solid-state doping source (e.g., p-type and n-type doped oxides, nitrides, or carbides) is incorporated into the transistor process flow (after recessing from the fin sidewalls) to deliver well doping to the sub-fins while keeping the fin bulk relatively undoped.

[0150] Therefore, the process can include using a solid source doped layer (e.g., boron-doped oxide) deposited on the fins after fin etching. Later, after trench filling and polishing, the doped layer is recessed along with the trench fill material to define the fin height (HSi) for the device. This operation removes the doped layer from the fin sidewalls above the HSi. Thus, the doped layer exists only along the fin sidewalls in the sub-fin region, ensuring precise control over dopant placement. After drive-in annealing, the high doping is confined to the sub-fin region, rapidly transitioning to the low doping in the adjacent region of the fin above the HSi (thus forming the channel region of the transistor). Typically, borosilicate glass (BSG) is used for NMOS fin doping, while phosphosilicate (PSG) or arsenicsilicate (AsSG) layers are used for PMOS fin doping. In one example, this P-type solid dopant source layer is a BSG layer with a boron concentration in the range of approximately 0.1–10 wt%. In another example, this N-type solid-state dopant source layer is a PSG layer or an AsSG layer with phosphorus or arsenic concentrations in the range of approximately 0.1-10 wt%, respectively. A silicon nitride cap layer may be included on the doped layer, and then a silicon dioxide or silicon oxide filling material may be included on the silicon nitride cap layer.

[0151] According to another embodiment of this disclosure, for relatively thin fins (e.g., fins with a width less than about 20 nanometers), sub-fin leakage is sufficiently low, wherein an undoped or lightly doped silicon oxide or silicon dioxide film is formed directly adjacent to the fin, a silicon nitride layer is formed on the undoped or lightly doped silicon oxide or silicon dioxide film, and a silicon dioxide or silicon oxide filling material is included on the silicon nitride cap layer. It should be appreciated that such a structure can also be used to implement doping of the sub-fin region, such as halo doping.

[0152] FIG. 5A A cross-sectional view of a pair of semiconductor fins separated by a three-layer trench isolation structure according to an embodiment of the present disclosure is shown.

[0153] Referring to FIG. 5A The integrated circuit structure includes a fin 502, such as a silicon fin. The fin 502 has a lower fin portion (sub-fin) 502A and an upper fin portion 502B (Hsi). A first insulating layer 504 is directly on sidewalls of the lower fin portion 502A of the fin 502. A second insulating layer 506 is directly on the first insulating layer 504, which is directly on the sidewalls of the lower fin portion 502A of the fin 502. A dielectric fill material 508 is directly laterally adjacent to the second insulating layer 506 that is directly on the first insulating layer 504, which is directly on the sidewalls of the lower fin portion 502A of the fin 502.

[0154] In embodiments, the first insulating layer 504 is an undoped insulating layer including silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In embodiments, the first insulating layer 504 includes silicon and oxygen and no atomic species having an atomic concentration greater than 1E15 atoms per cubic centimeter. In embodiments, the first insulating layer 504 has a thickness in a range of 0.5-2 nanometers.

[0155] In embodiments, the second insulating layer 506 includes silicon and nitrogen, such as a stoichiometric Si3N4 silicon nitride insulating layer, a silicon-rich silicon nitride insulating layer, or a silicon-poor silicon nitride insulating layer. In embodiments, the second insulating layer 506 has a thickness in a range of 2-5 nanometers.

[0156] In embodiments, the dielectric fill material 508 includes silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In embodiments, a gate electrode is ultimately formed on top of and laterally adjacent to sidewalls of the upper fin portion 502B of the fin 502.

[0157] It should be appreciated that during processing, the upper fin portion of a semiconductor fin can be etched or consumed. Also, the trench isolation structure between fins can be etched to have a non-planar topography, or can be formed to have a non-planar topography at the time of manufacture. As an example, FIG. 5B A cross-sectional view of another pair of semiconductor fins separated by another three-tier trench isolation structure according to another embodiment of the disclosure is shown.

[0158] Referring to FIG. 5BThe integrated circuit structure includes a first fin 552, such as a silicon fin. The first fin 552 has a lower fin portion 552A and an upper fin portion 552B, and a shoulder feature 554 at a region between the lower fin portion 552A and the upper fin portion 552B. A second fin 562, such as a second silicon fin, has a lower fin portion 562A and an upper fin portion 562B, and a shoulder feature 564 at a region between the lower fin portion 562A and the upper fin portion 562B. A first insulating layer 574 is directly on sidewalls of the lower fin portion 552A of the first fin 552 and directly on sidewalls of the lower fin portion 562A of the second fin 562. The first insulating layer 574 has a first end portion 574A that is generally coplanar with the shoulder feature 554 of the first fin 552, and the first insulating layer 574 also has a second end portion 574B that is generally coplanar with the shoulder feature 564 of the second fin 562. A second insulating layer 576 is directly on the first insulating layer 574, which is directly on the sidewalls of the lower fin portion 552A of the first fin 552 and directly on the sidewalls of the lower fin portion 562A of the second fin 562.

[0159] A dielectric fill material 578 is laterally adjacent to the second insulating layer 576 that is directly on the first insulating layer 574, which is directly on the sidewalls of the lower fin portion 552A of the first fin 552 and directly on the sidewalls of the lower fin portion 562A of the second fin 562. In an embodiment, the dielectric fill material 578 has an upper surface 578A, where a portion of the upper surface 578A of the dielectric fill material 578 is below at least one of the shoulder features 554 of the first fin 552 and below at least one of the shoulder features 564 of the second fin 562, as shown in FIG. 5B. FIG. 5B

[0160] In an embodiment, the first insulating layer 574 is an undoped insulating layer that includes silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In an embodiment, the first insulating layer 574 includes silicon and oxygen, and does not have other atomic species with an atomic concentration greater than 1E15 atoms per cubic centimeter. In an embodiment, the first insulating layer 574 has a thickness in a range of 0.5-2 nanometers.

[0161] In an embodiment, the second insulating layer 576 includes silicon and nitrogen, such as a stoichiometric Si3N4 silicon nitride insulating layer, a silicon-rich silicon nitride insulating layer, or a silicon-poor silicon nitride insulating layer. In an embodiment, the second insulating layer 576 has a thickness in a range of 2-5 nanometers.

[0162] ​In embodiments, the dielectric fill material 578 includes silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In embodiments, the gate electrode is ultimately formed over and laterally adjacent to a top of a sidewall of the upper fin portion 552B of the first fin 552, and over and laterally adjacent to a top of a sidewall of the upper fin portion 562B of the second fin 562. The gate electrode is also over the dielectric fill material 578 between the first fin 552 and the second fin 562.

[0163] FIG. 6A - FIG. 6D Cross-sectional views showing various operations in fabricating a three-tier trench isolation structure, in accordance with embodiments of the present disclosure, are shown.

[0164] Referring to FIG. 6A , a method of fabricating an integrated circuit structure includes forming a fin 602, such as a silicon fin. A first insulating layer 604 is formed directly on and conformal to the fin 602, as shown. FIG. 6B In embodiments, the first insulating layer 604 includes silicon and oxygen, and no other atomic species having an atomic concentration greater than 1E15 atoms per cubic centimeter.

[0165] Referring to FIG. 6C , a second insulating layer 606 is formed directly on and conformal to the first insulating layer 604. In embodiments, the second insulating layer 606 includes silicon and nitrogen. A dielectric fill material 608 is formed directly on the second insulating layer 606, as shown. FIG. 6D

[0166] In embodiments, the method also involves recessing the dielectric fill material 608, the first insulating layer 604, and the second insulating layer 606 to provide the fin 602 with an exposed upper fin portion 602A (e.g., the upper fin portion 502B, 552B, or 562B of FIGS. 5A and FIG. 5B . The resulting structure can be as described in connection with FIG. 5A or FIG. 5B . In one embodiment, recessing the dielectric fill material 608, the first insulating layer 604, and the second insulating layer 606 involves using a wet etch process. In another embodiment, recessing the dielectric fill material 608, the first insulating layer 604, and the second insulating layer 606 involves using a plasma etch or dry etch process.

[0167] ​In an embodiment, the first insulating layer 604 is formed using a chemical vapor deposition process. In an embodiment, the term chemical vapor deposition process forms the second insulating layer 606. In an embodiment, the dielectric fill material 608 is formed using a spin-on process. In one such embodiment, the dielectric fill material 608 is a spin-on material and is exposed to a vapor treatment, for example, before or after a recess etch process, to provide a cured material including silicon and oxygen. In an embodiment, a gate electrode is ultimately formed over the top of and laterally adjacent to the sidewalls of the upper fin portion of the fin 602.

[0168] In another aspect, a gate sidewall spacer material can be retained over a particular trench isolation region as a protection against the trench isolation region being etched during subsequent processing operations. For example, FIG. 7A - Figure 7E illustrates a tilted three-dimensional cross-sectional view of various operations in a method of manufacturing an integrated circuit structure, in accordance with an embodiment of the present disclosure.

[0169] Referring to FIG. 7A A method of manufacturing an integrated circuit structure includes forming a fin 702, for example, a silicon fin. The fin 702 has a lower fin portion 702A and an upper fin portion 702B. An insulating structure 704 is formed directly adjacent to the sidewalls of the lower fin portion 702A of the fin 702. A gate structure 706 is formed over the upper fin portion 702B and over the insulating structure 704. In an embodiment, the gate structure is a placeholder or dummy gate structure including a sacrificial gate dielectric layer 706A, a sacrificial gate 706B, and a hardmask 706C. A dielectric material 708 is formed conformal to the upper fin portion 702B of the fin 702, conformal to the gate structure 706, and conformal to the insulating structure 704.

[0170] Referring to FIG. 7B A hardmask material 710 is formed over the dielectric material 708. In an embodiment, the hardmask material 710 is a carbon-based hardmask material formed using a spin-on process.

[0171] Referring to FIG. 7C The hardmask material 710 is recessed to form a recessed hardmask material 712 and to expose portions of the dielectric material 708 that are conformal to the upper fin portion 702B of the fin 702 and conformal to the gate structure 706. The recessed hardmask material 712 covers portions of the dielectric material 708 that are conformal to the insulating structure 704. In an embodiment, the hardmask material 710 is recessed using a wet etch process. In another embodiment, the hardmask material 710 is recessed using an ashing, dry etch, or plasma etch process.

[0172] Referring to FIG. 7DAnisotropic etching of the dielectric material 708 is performed to form a patterned dielectric material 714 along the sidewalls of the gate structure 706 as a dielectric spacer 714A, along portions of the sidewalls of the upper fin portions 702B of the fins 702, and over the insulating structure 704.

[0173] Referring FIG. 7E From FIG. 7D the recessed hardmask material 712 is removed. In embodiments, the gate structure 706 is a dummy gate structure, and subsequent processing includes replacing the gate structure 706 with a permanent gate dielectric and gate electrode stack. In embodiments, further processing includes forming an embedded source or drain structure on opposite sides of the gate structure 706, as described in more detail below.

[0174] Referring again to FIG. 7E In embodiments, the integrated circuit structure 700 includes a first fin (left 702), e.g., a first silicon fin, having a lower fin portion 702A and an upper fin portion 702B. The integrated circuit structure also includes a second fin (right 702), e.g., a second silicon fin, having a lower fin portion 702A and an upper fin portion 702B. The insulating structure 704 is directly adjacent to the sidewalls of the lower fin portion 702A of the first fin and directly adjacent to the sidewalls of the lower fin portion 702A of the second fin. The gate electrode 706 is over the upper fin portion 702B of the first fin (left 702), over the upper fin portion 702B of the second fin (right 702), and over a first portion 704A of the insulating structure 704. A first dielectric spacer 714A is along the sidewalls of the upper fin portion 702B of the first fin (left 702), and a second dielectric spacer 702C is along the sidewalls of the upper fin portion 702B of the second fin (right 702). The second dielectric spacer 714C is continuous with the first dielectric spacer 714B over a second portion 704B of the insulating structure 704 between the first fin (left 702) and the second fin (right 702).

[0175] In embodiments, the first and second dielectric spacers 714B and 714C include silicon and nitrogen, e.g., a stoichiometric Si3N4 silicon nitride material, a silicon-rich silicon nitride material, or a silicon-poor silicon nitride material.

[0176] In an embodiment, the integrated circuit structure 700 also includes an embedded source or drain structure on an opposite side of the gate electrode 706, the embedded source or drain structure having a bottom surface below a top surface of the first and second dielectric spacers 714B and 714C along sidewalls of the upper fin portions 702B of the first and second fins 702, and the source or drain structure having a top surface above the top surface of the first and second dielectric spacers 714B and 714C along the sidewalls of the upper fin portions 702B of the first and second fins 702, as described below in connection with FIG. 9B In an embodiment, the insulating structure 704 includes a first insulating layer, a second insulating layer directly on the first insulating layer, and a dielectric fill material directly on the second insulating layer laterally, as also described below in connection with FIG. 9B

[0177] FIG. 8A - FIG. 8F Slightly projected cross-sectional views along the a-a' axis of various operations in a method for fabricating an integrated circuit structure according to embodiments of the present disclosure are shown. FIG. 7E

[0178] Reference is made to FIG. 8A A method of fabricating an integrated circuit structure includes forming fins 702, such as silicon fins. The fins 702 have lower fin portions (not visible in FIG. 8A ) and upper fin portions 702B. An insulating structure 704 is formed directly adjacent to sidewalls of the lower fin portions 702A of the fins 702. A pair of gate structures 706 is formed over the upper fin portions 702B and over the insulating structure 704. It is to be appreciated that FIG. 8A - FIG. 8F The perspective view shown in

[0179] Reference is made to FIG. 8B , which corresponds to the process operations described in connection with FIG. 7A The dielectric material 708 is formed conformal to the upper fin portions 702B of the fins 702, conformal to the gate structures 706, and conformal to exposed portions of the insulating structure 704.

[0180] Reference is made to FIG. 8C , which corresponds to the process operations described in connection with FIG. 7B The hardmask material 710 is formed over the dielectric material 708. In an embodiment, the hardmask material 710 is a carbon-based hardmask material formed using a spin-on process.​​

[0181] Referring to FIG. 8D corresponding to the process operations described in conjunction with FIG. 7C The process operations described are performed to recess the hardmask material 710 to form a recessed hardmask material 712 and expose portions of the dielectric material 708 that are conformal with the upper fin portion 702B of the fin 702 and conformal with the gate structure 706. The recessed hardmask material 712 covers portions of the dielectric material 708 that are conformal with the insulating structure 704. In an embodiment, the hardmask material 710 is recessed using a wet etch process. In another embodiment, the hardmask material 710 is recessed using an ashing, dry etch, or plasma etch process.

[0182] Referring to FIG. 8E corresponding to the process operations described in conjunction with FIG. 7D The process operations described are performed to anisotropically etch the dielectric material 708 to form a patterned dielectric material 714 along the sidewalls of the gate structure 706 as portions 714A, along portions of the sidewalls of the upper fin portion 702B of the fin 702, and over the insulating structure 704.

[0183] Referring to FIG. 8F corresponding to the process operations described in conjunction with FIG. 7E The process operations described are performed to remove the recessed hardmask material 712 from the structure of FIG. 8E In an embodiment, the gate structure 706 is a dummy gate structure, and the processing includes replacing the gate structure 706 with a permanent gate dielectric and gate electrode stack. In an embodiment, the further processing includes forming an embedded source or drain structure on opposite sides of the gate structure 706, as described in more detail below.

[0184] Referring again to FIG. 8F In an embodiment, the integrated circuit structure 700 includes a fin 702, e.g., a silicon fin, having a lower fin portion 702A and an upper fin portion 702B. The upper fin portion 702B is conformal with the gate structure 706 and the lower fin portion 702A is conformal with the insulating structure 704. FIG. 8F(Not visible in the image) and the upper fin portion 702B. The insulating structure 704 is directly adjacent to the sidewall of the lower fin portion of the fin 702. The first gate electrode (left 706) is above the upper fin portion 702B and above the first portion 704A of the insulating structure 704. The second gate electrode (right 706) is above the upper fin portion 702B and above the second portion 704A' of the insulating structure 704. The first dielectric spacer (right 714A of left 706) is along the sidewall of the first gate electrode (left 706), and the second dielectric spacer (left 714A of right 706) is along the sidewall of the second gate electrode (right 706). The second dielectric spacer is continuous with the first dielectric spacer on the third portion 704A' of the insulating structure 704 between the first gate electrode (left 706) and the second gate electrode (right 706).

[0185] FIG. 9A The following diagram illustrates an integrated circuit structure comprising a permanent gate stack and an epitaxial source or drain region, according to embodiments of the present disclosure. FIG. 7E A slightly projected cross section taken along the a-a' axis. FIG. 9B This illustration shows an integrated circuit structure including epitaxial source or drain regions and multilayer trench isolation structures according to embodiments of the present disclosure. FIG. 7E The cross-sectional view taken along the b-b' axis.

[0186] refer to FIG. 9A and FIG. 9B In one embodiment, the integrated circuit structure includes an embedded source or drain structure 910 on the opposite side of the gate electrode 706. The embedded source or drain structure 910 has a bottom surface 910A below the top surface 990 of the first and second dielectric spacers 714B and 714C along the sidewalls of the upper fin portions 702B of the first and second fins 702. The embedded source or drain structure 910 has a top surface 910B above the top surface of the first and second dielectric spacers 714B and 714C along the sidewalls of the upper fin portions 702B of the first and second fins 702.

[0187] In an embodiment, the gate stack 706 is a permanent gate stack 920. In one such embodiment, the permanent gate stack 920 includes a gate dielectric layer 922, a first gate layer 924 such as a work function gate layer, and a gate fill material 926, such as... FIG. 9A As shown. In one embodiment where the permanent gate structure 920 is over the insulating structure 704, the permanent gate structure 920 is formed on a residual polysilicon portion 930, which may be a residue of a replacement gate process involving a sacrificial polysilicon gate electrode.

[0188] In an embodiment, the insulating structure 704 includes a first insulating layer 902, a second insulating layer 904 directly on the first insulating layer 902, and a dielectric fill material 906 directly on the second insulating layer 904 laterally. In one embodiment, the first insulating layer 902 is a non-doped insulating layer including silicon and oxygen. In one embodiment, the second insulating layer 904 includes silicon and nitrogen. In one embodiment, the dielectric fill material 906 includes silicon and oxygen.

[0189] In another aspect, the epitaxial embedded source or drain regions are implemented as source or drain structures for semiconductor fins. As an example, FIG. 10 A cross-sectional view of an integrated circuit structure taken at a source or drain location is shown in accordance with an embodiment of the present disclosure.

[0190] Referring to FIG. 10 , the integrated circuit structure 1000 includes P-type devices, such as P-type metal oxide semiconductor (PMOS) devices. The integrated circuit structure 1000 also includes N-type devices, such as N-type metal oxide semiconductor (NMOS) devices.

[0191] FIG. 10 The PMOS devices of include a first plurality of semiconductor fins 1002, such as silicon fins formed from a bulk silicon substrate 1001. At source or drain locations, an upper portion of the fins 1002 has been removed, and the same or different semiconductor material has been grown to form source or drain structures 1004. It should be appreciated that the source or drain structures 1004 will look the same at a cross-sectional view taken on either side of a gate electrode, e.g., they will look substantially the same on a source side as on a drain side. In an embodiment, as noted, the source or drain structures 1004 have a portion below and a portion above an upper surface of an insulating structure 1006. In an embodiment, as shown, the source or drain structures 1004 have a strong facet. In an embodiment, a conductive contact 1008 is formed on the source or drain structures 1004. However, in one such embodiment, the strong facet and the wider growth of the source or drain structures 1004 at least to some extent inhibit good coverage of the conductive contact 1008.

[0192] FIG. 10The NMOS device includes a second plurality of semiconductor fins 1052, e.g., silicon fins formed from a bulk silicon substrate 1001. At source or drain locations, an upper portion of the fins 1052 has been removed, and the same or different semiconductor material has been grown to form source or drain structures 1054. It should be appreciated that the source or drain structures 1054 will appear the same in a cross-sectional view taken on either side of the gate electrode, e.g., they will appear substantially the same on the source side as on the drain side. In embodiments, as noted above, the source or drain structures 1054 have portions below and above the upper surface of the insulating structure 1006. In embodiments, as shown, the source or drain structures 1054 have a weaker facet relative to the source or drain structures 1004. In embodiments, a conductive contact 1058 is formed over the source or drain structures 1054. In one such embodiment, the weaker facet and resulting narrower growth of the source or drain structures 1054 (as compared to the source or drain structures 1004) enhances the good coverage of the conductive contact 1058.

[0193] The shape of the source or drain structures of the PMOS device can be changed to improve the contact area with the overlying contact. For example, FIG. 11 A cross-sectional view of another integrated circuit structure taken at a source or drain location is shown in accordance with an embodiment of the disclosure.

[0194] Referring to FIG. 11 , the integrated circuit structure 1100 includes a P-type semiconductor (e.g., PMOS) device. The PMOS device includes a first fin 1102, e.g., a silicon fin. A first epitaxial source or drain structure 1104 is embedded in the first fin 1102. In one embodiment, although not shown, the first epitaxial source or drain structure 1104 is on a first side of a first gate electrode (which can be formed over an upper fin portion of a channel portion such as the fin 1102), and a second epitaxial source or drain structure is embedded in the first fin 1102 at a second side of such first gate electrode opposite the first side. In embodiments, the first and second epitaxial source or drain structures include silicon and germanium, and have a profile 1105. In one embodiment, the profile is a matchstick profile, as shown in FIG. 11. A first conductive electrode 1108 is over the first epitaxial source or drain structure 1104.

[0195] Referring again to FIG. 11In an embodiment, integrated circuit structure 1100 also includes an N-type semiconductor (e.g., NMOS) device. The NMOS device includes a second fin 1152, such as a silicon fin. A third epitaxial source or drain structure 1154 is embedded in the second fin 1152. In one embodiment, although not shown, the third epitaxial source or drain structure 1154 is at a first side of a second gate electrode (which can be formed over an upper fin portion, such as a channel portion, of the fin 1152), and a fourth epitaxial source or drain structure is embedded in the second fin 1152 at a second side of such second gate electrode opposite the first side. In an embodiment, the third and fourth epitaxial source or drain structures include silicon, and have a profile substantially the same as the profile 1105 of the first and second epitaxial source or drain structures 1004. A second conductive electrode 1158 is over the third epitaxial source or drain structure 1154.

[0196] In an embodiment, the first epitaxial source or drain structure 1104 has a weaker facet. In an embodiment, the first epitaxial source or drain structure 1104 has a height of approximately 50 nanometers, and has a width in the range of 30-35 nanometers. In one such embodiment, the third epitaxial source or drain structure 1154 has a height of approximately 50 nanometers, and has a width in the range of 30-35 nanometers.

[0197] In an embodiment, the first epitaxial source or drain structure 1104 varies in a gradient of germanium concentration from approximately 20% at a bottom 1104A of the first epitaxial source or drain structure 1104 to approximately 45% at a top 1104B of the first epitaxial source or drain structure 1104. In an embodiment, the first epitaxial source or drain structure 1104 is doped with boron atoms. In one such embodiment, the third epitaxial source or drain structure 1154 is doped with phosphorus atoms or arsenic atoms.

[0198] FIG. 12A - FIG. 12D Cross-sectional views are shown that are taken at source or drain locations and represent various operations in fabricating an integrated circuit structure, in accordance with embodiments of the present disclosure.

[0199] Reference is made to FIG. 12A A method of fabricating an integrated circuit structure includes forming a fin, such as a silicon fin from a silicon substrate 1201. The fin 1202 has a lower fin portion 1202A and an upper fin portion 1202B. In an embodiment, although not shown, at a location entering the page, a gate electrode is formed over a portion of the upper fin portion 1202B of the fin 1202. Such gate electrode has a first side opposite a second side, and bounds a source or drain location on the first and second sides. For example, for purposes of illustration, FIG. 12A - FIG. 12DThe cross-sectional position of the view is taken at one of the source or drain locations at one of the sides of the gate electrode.

[0200] Referring to FIG. 12B The source or drain locations of the fin 1202 are recessed to form recessed fin portions 1206. The recessed source or drain locations of the fin 1202 can be at one side of the gate electrode and at a second side of the gate electrode. Referring to FIG. 12A and FIG. 12B Both, in an embodiment, the dielectric spacer 1204 is formed along the sidewalls of a portion of the fin 1202, e.g., at one side of the gate structure. In one such embodiment, recessing the fin 1202 involves recessing the fin 1202 below a top surface 1204A of the dielectric spacer 1204.

[0201] Referring to FIG. 12C An epitaxial source or drain structure 1208 is formed on the recessed fin 1206, e.g., so that it can be formed at one side of the gate electrode. In one such embodiment, a second epitaxial source or drain structure is formed on a second portion of the recessed fin 1206 at a second side of such gate electrode. In an embodiment, the epitaxial source or drain structure 1208 includes silicon and germanium and has a matchstick profile, as shown in FIG. 12C In an embodiment, the dielectric spacer 1204 is included and along a lower portion 1208A of the sidewalls of the epitaxial source or drain structure 1208, as shown.

[0202] Referring to FIG. 12D A conductive electrode 1210 is formed on the epitaxial source or drain structure 1208. In an embodiment, the conductive electrode 1210 includes a conductive barrier layer 1210A and a conductive fill material 1201B. In one embodiment, the conductive electrode 1210 follows the profile of the epitaxial source or drain structure 1208, as shown. In other embodiments, an upper portion of the epitaxial source or drain structure 1208 is etched during fabrication of the conductive electrode 1210.

[0203] In another aspect, fin trimming isolation (FTI) and single gate isolation for isolated fins are described. Non-planar transistors utilizing fins of semiconductor material protruding from a substrate surface employ a gate electrode that wraps two, three, or even all sides of the fin (i.e., dual gate, tri-gate, nanowire transistor). Typically, source and drain regions are then formed in the fin on either side of the gate electrode, or as a regrown portion of the fin. To isolate a source or drain region of a first non-planar transistor from a source or drain region of an adjacent second non-planar transistor, a gap or space can be formed between two adjacent fins. Such isolation gaps typically require some sort of masked etch. Once isolated, the gate stack is then typically patterned over the individual fins again utilizing some sort of masked etch (e.g., line etch or opening etch, depending on the particular implementation).

[0204] One potential issue with the fin isolation techniques described above is that the gate is not self-aligned to the ends of the fin, and the alignment of the gate stack pattern to the semiconductor fin pattern relies on the overlap of the two patterns. As such, lithography overlay tolerance is added to the dimensioning of the semiconductor fin and the isolation gap, where the fin needs to be larger in length, and the isolation gap is larger than the isolation gap for a given level of transistor functionality. Thus, device architectures and fabrication techniques that reduce this excess dimensioning provide a highly advantageous improvement in transistor density.

[0205] Another potential issue with the fin isolation techniques described above is that the stress in the semiconductor fin needed to improve carrier mobility can be lost from the channel region of the transistor, where, during fabrication, too much unconstrained fin surface is left, allowing the fin strain to relax. Thus, device architectures and fabrication techniques that maintain a higher level of the desired fin stress provide an advantageous improvement in non-planar transistor performance.

[0206] In accordance with embodiments of the present disclosure, fin-through-gate isolation architectures and techniques are described herein. In the illustrated exemplary embodiments, non-planar transistors in a microelectronic device such as an integrated circuit (IC) are isolated from one another in a manner that is self-aligned to the gate electrodes of the transistors. Although embodiments of the present disclosure are applicable to nearly any IC that employs non-planar transistors, exemplary ICs include, but are not limited to: microprocessor cores including logic and memory (SRAM) portions, RFICs (e.g., wireless ICs including digital baseband and analog front-end modules), and power ICs.

[0207] In embodiments, two end portions of adjacent semiconductor fins are electrically isolated from one another with isolation regions, with only one patterning mask level being utilized to position the isolation regions relative to gate electrodes. In embodiments, a single mask is employed to form a plurality of fixed-pitch strips of sacrificial placeholders, a first subset of the strips of placeholders defining locations or dimensions of the isolation regions, while a second subset of the strips of placeholders defining locations or dimensions of the gate electrodes. In certain embodiments, the first subset of strips of placeholders is removed, and isolation cuts are made into the semiconductor fins in openings resulting from the removal of the first subset, while the second subset of strips of placeholders is ultimately replaced with non-sacrificial gate electrode stacks. As a subset of the placeholders used for gate electrode replacement is used to form the isolation regions, this approach and resulting architecture is referred to herein as "through- gate" isolation. For example, one or more through-gate isolation embodiments described herein can enable higher transistor density and higher levels of beneficial transistor channel stress.

[0208] With isolation defined after placement or definition of gate electrodes, greater transistor density can be achieved, as gate electrodes can be utilized on the field to perfectly perform fin isolation dimensioning and placement, such that gate electrodes and isolation regions are integer multiples of the minimum feature pitch of a single masking level. In other embodiments where semiconductor fins have a lattice mismatch with a substrate on which the fins are disposed, greater degrees of strain are maintained by defining isolation after placement or definition of gate electrodes. For such embodiments, other features of transistors formed prior to definition of end portions of fins (e.g., gate electrodes and added source or drain material) help to mechanically maintain fin strain after isolation cuts are made into the fins.

[0209] To provide further context, transistor scaling can benefit from more densely packed cells within a chip. Currently, most cells are separated from their adjacent cells by two or more dummy gates, with the dummy gates having buried fins. The dummy gates connect one cell to another by etching the fins underneath the two or more dummy gates to isolate the cells. If the number of dummy gates separating adjacent cells can be reduced from two or more to one, scaling can be significantly beneficial. As noted above, one approach requires two or more dummy gates. The fins underneath the two or more dummy gates are etched during fin patterning. A potential problem with this approach is that the dummy gates consume space on the chip that could be used for cells. In embodiments, approaches described herein enable adjacent cells to be separated using only a single dummy gate.

[0210] In embodiments, the fin trim isolation approach is implemented as a self- aligned patterning scheme. Here, the fins underneath individual gates are etched away. Thus, adjacent cells can be separated by a single dummy gate. Advantages of this approach can include saving space on the chip and allowing more compute power per area. This approach can also allow fin trimming to be performed at sub-fin pitch distances.

[0211] FIG. 13A and FIG. 13B Plan views representing various operations in a method of patterning fins with single gate spacing for forming local isolation structures are shown in accordance with embodiments of the present disclosure.

[0212] Referring to FIG. 13A , a plurality of fins 1302 are shown having a length along a first direction 1304. A grid 1306 is shown along a second direction 1308 orthogonal to the first direction 1304, with spacing 1307 between the grid defining locations for eventual formation of a plurality of gate lines.

[0213] Referring to FIG. 13B , a portion of the plurality of fins 1302 is cut (e.g., removed by an etching process) to leave fins 1310 with cutouts 1312 therein. Thus, the isolation structures eventually formed in the cutouts 1312 have a size that exceeds that of a single gate line, e.g., that of three gate lines 1306. Thus, gate structures eventually formed along the locations of the gate lines 1306 are formed over the isolation structures formed at least partially in the cutouts 1312. Thus, the cutouts 1312 are relatively wide fin cutouts.

[0214] FIG. 14A - FIG. 14D Plan views representing various operations in a method of patterning fins with single gate spacing for forming local isolation structures are shown in accordance with another embodiment of the present disclosure.

[0215] Referring to FIG. 14A , a method of fabricating an integrated circuit structure includes forming a plurality of fins 1402, individual fins of the plurality of fins 1402 having a longest dimension along a first direction 1404. A plurality of gate structures 1406 is over the plurality of fins 1402, individual gate structures of the gate structures 1406 having a longest dimension along a second direction 1408 orthogonal to the first direction 1404. In embodiments, the gate structures 1406 are sacrificial or dummy gate lines, e.g., fabricated from polysilicon. In one embodiment, the plurality of fins 1402 are silicon fins and are continuous with a portion of a silicon substrate below.

[0216] Referring to FIG. 14BA dielectric material structure 1410 is formed between adjacent ones of the plurality of gate structures 1406.

[0217] Referring to FIG. 14C A portion 1412 of one of the plurality of gate structures 1406 is removed to expose a portion 1414 of each of the plurality of fins 1402. In embodiments, removing the portion 1412 of one of the plurality of gate structures 1406 involves using a lithography window 1416 that is wider than a width 1418 of the portion 1412 of one of the plurality of gate structures 1406.

[0218] Referring to FIG. 14D The exposed portion 1414 of each of the plurality of fins 1402 is removed to form a cutout region 1420. In embodiments, the exposed portion 1414 of each of the plurality of fins 1402 is removed using a dry or plasma etch process. In embodiments, removing the exposed portion 1414 of each of the plurality of fins 1402 involves etching to a depth that is less than a height of the plurality of fins 1402. In one such embodiment, the depth is greater than a depth of a source or drain region in the plurality of fins 1402. In embodiments, the depth is deeper than a depth of an active portion of the plurality of fins 1402 to provide an isolation margin. In embodiments, the exposed portion 1414 of each of the plurality of fins 1402 is removed without etching or substantially without etching a source or drain region (e.g., an epitaxial source or drain region) of the plurality of fins 1402. In one such embodiment, the exposed portion 1414 of each of the plurality of fins 1402 is removed without laterally etching or substantially without laterally etching a source or drain region (e.g., an epitaxial source or drain region) of the plurality of fins 1402.

[0219] In embodiments, the cutout region 1420 is ultimately filled with an insulating layer, for example, in place of the removed portion 1414 of each of the plurality of fins 1402. Exemplary insulating layer or "multi-cut" or "plug" structures are described below. However, in other embodiments, the cutout region 1420 is only partially filled with an insulating layer, and then a conductive structure is formed therein. The conductive structure can be used as a local interconnect. In embodiments, prior to filling the cutout region 1420 with an insulating layer or with an insulating layer that accommodates a local interconnect structure, dopants can be implanted or transported into the local cutout portion of one or more fins by the cutout region 1420 from a solid source of dopants.

[0220] FIG. 15 A cross-sectional view of an integrated circuit structure having fins with multi-gate isolation for local isolation is shown, in accordance with an embodiment of the present disclosure.

[0221] Referring to FIG. 15The silicon fin 1502 has a first fin portion 1504 laterally adjacent to a second fin portion 1506. The first fin portion 1504 is separated from the second fin portion 1506 by a wider cut 1508, e.g., as described in connection with FIG. 13A and FIG. 13B The wider cut 1508 has a width X. A dielectric fill material 1510 is formed in the wider cut 1508 and electrically isolates the first fin portion 1504 from the second fin portion 1506. A plurality of gate lines 1512 are over the silicon fin 1502, where each of the gate lines can include a gate dielectric and gate electrode stack 1514, a dielectric cap 1516, and a sidewall spacer 1518. Two of the gate lines (the left two gate lines 1512) occupy the wider cut 1508, effectively separating the first fin portion 1504 from the second fin portion 1506 by two dummy gates or passive gates.

[0222] In contrast, the fin portions can be separated by a single gate distance. As an example, FIG. 16A A cross-sectional view of an integrated circuit structure having fins with single gate separation for local isolation is shown, according to another embodiment of the disclosure.

[0223] Referring to FIG. 16A The silicon fin 1602 has a first fin portion 1604 laterally adjacent to a second fin portion 1606. The first fin portion 1604 is separated from the second fin portion 1606 by a narrower cut 1608, e.g., as described in connection with FIG. 14A - FIG. 14D The narrower cut 1608 has a width Y, where Y is less than FIG. 15 A dielectric fill material 1610 is formed in the narrower cut 1608 and electrically isolates the first fin portion 1604 from the second fin portion 1606. A plurality of gate lines 1612 are over the silicon fin 1602, where each of the gate lines can include a gate dielectric and gate electrode stack 1614, a dielectric cap 1616, and a sidewall spacer 1618. The dielectric fill material 1610 occupies the location of a single gate line that was previously present, effectively separating the first fin portion 1604 from the second fin portion 1606 by a single "punch through" gate line. In one embodiment, residual spacer material 1620 remains on the sidewalls in the location of the removed gate line portion, as shown. It should be appreciated that other regions of the fin 1602 can be isolated from one another by two or more passive gate lines (a region 1622 with three passive gate lines) fabricated by an earlier, wider fin cut process, as described below.

[0224] Referring again to FIG. 16AThe integrated circuit structure 1600 includes a fin 1602, such as a silicon fin. The fin 1602 has a longest dimension along a first direction 1650. An isolation structure 1610 separates a first upper portion 1604 of the fin 1602 from a second upper portion 1606 of the fin 1602 along the first direction 1650. The isolation structure 1610 has a center 1611 along the first direction 1650.

[0225] A first gate structure 1612A is over the first upper portion 1604 of the fin 1602, the first gate structure 1612A having a longest dimension along a second direction 1652 (e.g., into the page) that is orthogonal to the first direction 1650. A center 1613A of the first gate structure 1612A is spaced apart from the center 1611 of the isolation structure 1610 by a pitch along the first direction 1650. A second gate structure 1612B is over the first upper portion 1604 of the fin, the second gate structure 1612B having a longest dimension along the second direction 1652. A center 1613B of the second gate structure 1612B is spaced apart from the center 1613A of the first gate structure 1612A by a pitch along the first direction 1650. A third gate structure 1612C is over the second upper portion 1606 of the fin 1602, the third gate structure 1612C having a longest dimension along the second direction 1652. A center 1613C of the third gate structure 1612C is spaced apart from the center 1611 of the isolation structure 1610 by a pitch along the first direction 1650. In embodiments, the isolation structure 1610 has a top that is generally coplanar with a top of the first gate structure 1612A, a top of the second gate structure 1612B, and a top of the third gate structure 1612C, as shown.

[0226] In embodiments, each of the first gate structure 1612A, the second gate structure 1612B, and the third gate structure 1612C includes a gate electrode 1660 over and between sidewalls of a high-k gate dielectric layer 1662, as shown for the exemplary third gate structure 1612C. In one such embodiment, each of the first gate structure 1612A, the second gate structure 1612B, and the third gate structure 1612C further includes an insulating cap 1616 over the gate electrode 1660 and over the sidewalls of the high-k gate dielectric layer 1662.

[0227] In an embodiment, the integrated circuit structure 1600 further includes a first epitaxial semiconductor region 1664A on the first upper portion 1604 of the fin 1602 between the first gate structure 1612A and the isolation structure 1610. A second epitaxial semiconductor region 1664B is on the first upper portion 1604 of the fin 1602 between the first gate structure 1612A and the second gate structure 1612B. A third epitaxial semiconductor region 1664C is on the second upper portion 1606 of the fin 1602 between the third gate structure 1612C and the isolation structure 1610. In one embodiment, the first 1664A, second 1664B, and third 1664C epitaxial semiconductor regions include silicon and germanium. In another embodiment, the first 1664A, second 1664B, and third 1664C epitaxial semiconductor regions include silicon.

[0228] In an embodiment, the isolation structure 1610 induces stress on the first upper portion 1604 of the fin 1602 and on the second upper portion 1606 of the fin 1602. In one embodiment, the stress is compressive stress. In one embodiment, the stress is tensile stress. In other embodiments, the isolation structure 1610 is a partially filled insulating layer, and then a conductive structure is formed therein. The conductive structure can be used as a local interconnect. In an embodiment, prior to forming the isolation structure 1610 with an insulating layer or with an insulating layer that accommodates a local interconnect structure, dopants are implanted or transported into the local cut portions of one or more fins from a solid source of dopant layer.

[0229] In another aspect, it is recognized that, instead of an active gate electrode at a local location of a fin cut or a wider location of a fin cut, an isolation structure, such as the isolation structure 1610 described above, can be formed. Further, the depth of such local or wider locations of a fin cut can be formed to vary within the fin relative to one another. In a first example, FIG. 16B A cross-sectional view showing that a fin isolation structure can be formed to replace locations of gate electrodes is shown in accordance with an embodiment of the present disclosure.

[0230] Reference is made to FIG. 16BFins 1680, such as silicon fins, are formed over and can be continuous with a substrate 1682. Fins 1680 have a fin end or wide fin cutout 1684, which can be formed when the fins are patterned, for example, in the fin trim last approach described above. Fins 1680 also have a partial cutout 1686, where portions of fins 1680 are removed, for example, using the fin trim isolation approach described above, where dummy gates are replaced with dielectric plugs. An active gate electrode 1688 is formed over the fins, and is shown slightly in front of fins 1680 for illustrative purposes, and fins 1680 are in the background, where the dashed lines represent the area covered in the front view. A dielectric plug 1690 can be formed at the fin end or wide fin cutout 1684 to replace the active gate at such locations. Additionally, or as an alternative, a dielectric plug 1692 can be formed at the partial cutout 1686 to replace the active gate at such locations. It will be appreciated that epitaxial source or drain regions 1694 are also shown at the location of fins 1680 between active gate electrode 1688 and plug 1690 or 1692. Additionally, in implementations, the surface roughness of the end of the fin at the partial cutout 1686 is rougher than the end of the fin at the wide cutout location, as shown. FIG. 16B

[0231] FIG. 17A - FIG. 17C Various depth possibilities for fin cutouts fabricated using the fin trim isolation approach according to embodiments of the disclosure are shown.

[0232] Referring to FIG. 17A Semiconductor fins 1700, such as silicon fins, are formed over and can be continuous with an underlying substrate 1702. Fins 1700 have a lower fin portion 1700A and an upper fin portion 1700B, as defined by the height of insulating structure 1704 relative to fins 1700. A partial fin isolation cutout 1706A separates fins 1700 into a first fin portion 1710 and a second fin portion 1712. In the example shown along the a-a' axis, the depth of partial fin isolation cutout 1706A is the entire depth of fins 1700 to substrate 1702. FIG. 17A

[0233] Referring to FIG. 17B In a second example, the depth of partial fin isolation cutout 1706B is deeper than the entire depth of fins 1700 to substrate 1702, as shown along the a-a' axis. That is, cutout 1706B extends into underlying substrate 1702.

[0234] Referring to FIG. 17C ​​In a third example, as shown along the a-a' axis, the partial fin isolation cut 1706C has a depth that is less than the full depth of the fin 1700, but deeper than the upper surface of the isolation structure 1704. Again, reference is made to FIG. 17C In a fourth example, as shown along the a-a' axis, the partial fin isolation cut 1706D has a depth that is less than the full depth of the fin 1700, and at a level that is approximately coplanar with the upper surface of the isolation structure 1704.

[0235] FIG. 18 Plan views and corresponding cross-sectional views taken along the a-a' axis showing possible options for the depth of a partial location of a fin cut within a fin as compared to the depth of a wider location, in accordance with embodiments of the present disclosure.

[0236] Reference is made to FIG. 18 , first and second semiconductor fins 1800 and 1802, such as silicon fins, have upper fin portions 1800B and 1802B that extend above an insulating structure 1804. Both fins 1800 and 1802 have a fin end or wide fin cut 1806, e.g., such as can be formed when the fins are patterned in the last way of fin trimming described above. Both fins 1800 and 1802 also have a partial cut 1808, where a portion of the fin 1800 or 1802 is removed, e.g., using the last way of fin trimming isolation described above where a dummy gate is replaced with a dielectric plug. In embodiments, the surface roughness of the end of the fin 1800 and 1802 at the partial cut 1808 is rougher than the end of the fin at the location of 1806, as shown. FIG. 18

[0237] Reference is made to FIG. 18 , a cross-sectional view, lower fin portions 1800A and 1802A can be seen below the height of the insulating structure 1804. Also seen in the cross-sectional view is a residual portion 1810 of the fin that was removed at the last way of fin trimming prior to forming the insulating structure 1804, as described above. Although shown as protruding above the substrate, the residual portion 1810 can also be at the level of the substrate or into the substrate, as shown by the additional example wide cut depth 1820. It should be appreciated that the wide cut 1806 of the fins 1800 and 1802 can also be at the levels described for the cut depth 1820, examples of which are shown. The partial cut 1808 can have an example depth that corresponds to the depths described for FIGS. 17A-17C

[0238] Reference is made to FIG. 16A , FIG. 16B , FIGS. 17A-17C and FIG. 18 ​​According to embodiments of the present disclosure, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a first direction. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin along the first direction. The first isolation structure has a width along the first direction. The first end of the first portion of the fin has a surface roughness. A gate structure includes a gate electrode over the top of a region of the first portion of the fin and laterally adjacent to the sidewalls of the region. The gate structure has a width along the first direction, and a center of the gate structure is spaced apart from a center of the first isolation structure by a pitch along the first direction. A second isolation structure is over a second end of the first portion of the fin, the second end opposite the first end. The second isolation structure has a width along the first direction, and the second end of the first portion of the fin has a surface roughness that is less than the surface roughness of the first end of the first portion of the fin. The center of the second isolation structure is spaced apart from the center of the gate structure by a pitch along the first direction.

[0239] In one embodiment, the first end of the first portion of the fin has a scalloped topography, as shown in FIG. 16B. In one embodiment, a first epitaxial semiconductor region is on the first portion of the fin between the gate structure and the first isolation structure. A second epitaxial semiconductor region is on the first portion of the fin between the gate structure and the second isolation structure. In one embodiment, the first and second epitaxial semiconductor regions have a width along a second direction orthogonal to the first direction, the width along the second direction being wider than a width of the first portion of the fin under the gate structure along the second direction, e.g., as shown in the epitaxial features shown in FIG. 11 and FIG. 12D perspective views shown in FIG. 11 and FIG. 12D In one embodiment, the gate structure further includes a high-k dielectric layer between the gate electrode and the first portion of the fin and along sidewalls of the gate electrode.

[0240] Reference is made to FIG. 16A , FIG. 16B , FIGS. 17A-17C and FIG. 18According to another embodiment of the disclosure, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls, where the top has a longest dimension along a direction. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin along the direction. The first end of the first portion of the fin has a depth. A gate structure includes a gate electrode over the top of a region of the first portion of the fin and laterally adjacent to the sidewalls of the region. A second isolation structure is over a second end of the first portion of the fin, the second end opposite the first end. The second end of the first portion of the fin has a depth different from the depth of the first end of the first portion of the fin.

[0241] In one embodiment, the depth of the second end of the first portion of the fin is less than the depth of the first end of the first portion of the fin. In one embodiment, the depth of the second end of the first portion of the fin is greater than the depth of the first end of the first portion of the fin. In one embodiment, the first isolation structure has a width along the direction, and the gate structure has a width along the direction. The second isolation structure has a width along the direction. In one embodiment, a center of the gate structure is spaced apart from a center of the first isolation structure by a pitch along the direction, and a center of the second isolation structure is spaced apart from the center of the gate structure by the pitch along the direction.

[0242] Referring to FIG. 16A , FIG. 16B , FIGS. 17A-17C and FIG. 18 According to another embodiment of the disclosure, an integrated circuit structure includes a first fin including silicon, the first fin having a top and sidewalls, where the top has a longest dimension along a direction, and a discontinuity separates a first end of a first portion of the first fin from a first end of a second portion of the fin along the direction. The first portion of the first fin has a second end opposite the first end, and the first end of the first portion of the fin has a depth. The integrated circuit structure further includes a second fin including silicon, the second fin having a top and sidewalls, where the top has a longest dimension along the direction. The integrated circuit structure further includes a remaining or residual fin portion between the first fin and the second fin. The residual fin portion has a top and sidewalls, where the top has a longest dimension along the direction, and the top is not co-planar with the depth of the first end of the first portion of the fin.

[0243] In one embodiment, the first end of the first portion of the fin has a depth that is lower than a top of the remaining or residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth that is co-planar with the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth that is lower than the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth that is higher than the depth of the first end of the first portion of the fin. In one embodiment, the first end of the first portion of the fin has a depth that is higher than a top of the remaining or residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth that is co-planar with the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth that is lower than the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth that is higher than the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth that is co-planar with a top of the residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth that is lower than the top of the residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth that is higher than the top of the residual fin portion.

[0244] In another aspect, a dielectric plug formed in the location of a local fin cut or a wide fin cut can be adjusted to provide a specific stress to the fin or fin portion. In such an embodiment, the dielectric plug can be referred to as a fin end stressor.

[0245] One or more embodiments relate to the fabrication of fin-based semiconductor devices. Performance improvements to such devices can be made through channel stress induced from a multi-plug fill process. Embodiments can include inducing mechanical stress in a metal oxide semiconductor field effect transistor (MOSFET) channel with material properties in a multi-plug fill process. As a result, the induced stress can boost the mobility and drive current of the transistor. Furthermore, the plug fill methods described herein can allow for the elimination of any seam or void formation during deposition.

[0246] To provide context, the unique material properties of the plug fill that manipulates the adjoining fin can induce stress within the channel. According to one or more embodiments, by adjusting the composition, deposition, and post-treatment conditions of the plug fill material, the stress in the channel is modulated to benefit both NMOS and PMOS transistors. Furthermore, such plugs can be present deeper in the fin substrate compared to other common stressor techniques such as epitaxial source or drain. The properties of the plug fill that enable this effect also eliminate seams or porosity during deposition and mitigate certain defect modes during processing.

[0247] To provide more context, currently there is no artificial stress engineering for gate (poly) plugs. Stress enhancement from traditional stressors such as epitaxial source or drain, dummy poly gate removal, stress liners, etc. unfortunately tends to decrease as device pitch shrinks. To address one or more of the above issues, according to one or more embodiments of the present disclosure, additional stressors are incorporated into the transistor structure. Another possible benefit of this process can be the elimination of seams or porosity within the plug, which is common for other chemical vapor deposition methods.

[0248] FIG. 19A and FIG. 19B Cross-sectional views showing various operations in a method of selecting fin end stressor locations at the ends of fins having wide cuts as part of, for example, the fin trim last process described above, according to embodiments of the present disclosure, are shown.

[0249] Referring to FIG. 19A A fin 1900, such as a silicon fin, is formed over and can be continuous with a substrate 1902. The fin 1900 has a fin end or wide fin cut 1904, which can be formed when the fin is patterned, for example, in the fin trim last approach described above. Active gate electrode locations 1908 and dummy gate electrode locations 1908 are formed over the fin 1900, and are shown slightly in front of the fin 1900 for illustrative purposes, and the fin 1900 is in the background, with the dashed lines representing the area covered in the front view. It is to be appreciated that epitaxial source or drain regions 1910 are also shown at locations of the fin 1900 between the gate locations 1906 and 1908. Furthermore, interlayer dielectric material 1912 is included at locations of the fin 1900 between the gate locations 1906 and 1908.

[0250] Referring to FIG. 19BThe gate occupant structure or dummy gate location 1908 is removed to expose the fin tip and wide fin cutout 1904. This removal creates an opening 1920, in which a dielectric plug, such as a fin tip stress source dielectric plug, can eventually be formed.

[0251] FIG. 20A and FIG. 20B Cross-sectional views are shown of various operations in a method according to embodiments of the present disclosure for selecting the fin end stress location at the fin end with a partial cut as part of, for example, the fin trimming isolation process described above.

[0252] refer to FIG. 20A A fin 2000, such as a silicon fin, is formed above and may be continuous with the substrate 2002. The fin 2000 has a partial notch 2004, wherein a portion of the fin 2000 is removed, for example, using a fin trimming isolation method in which a dummy gate is removed and the fin is etched in a localized location, as described above. Active gate electrode locations 2006 and dummy gate electrode locations 2008 are formed above the fin 2000 and, for illustrative purposes, are shown slightly in front of the fin 2000, with the fin 2000 in the background, where the dashed lines represent the covered area in the front view. It should be appreciated that an epitaxial source or drain region 2010 is also shown at the location of the fin 2000 between gate locations 2006 and 2008. Furthermore, an interlayer dielectric material 2012 is included at the location of the fin 2000 between gate locations 2006 and 2008.

[0253] refer to FIG. 20B The gate occupant structure or dummy gate electrode location 2008 is removed to expose the fin tip with a partial cutout 2004. This removal creates an opening 2020, in which a dielectric plug, such as a stress-source dielectric plug for the fin tip, can eventually be formed.

[0254] FIGS. 21A-21M Cross-sectional views are shown of various operations in a method of manufacturing an integrated circuit structure with differentiated fin-end dielectric plugs according to embodiments of the present disclosure.

[0255] refer to FIG. 21AThe starting structure 2100 includes NMOS and PMOS regions. The NMOS region of the starting structure 2100 includes a first fin 2102, e.g., a first silicon fin, formed over and can be continuous with a substrate 2104. The first fin 2102 has a fin end 2106, which can be formed from a local or wide fin cut. A first active gate electrode location 2108 and a first dummy gate electrode location 2110 are formed over the first fin 2102, and are shown for purposes of illustration slightly in front of the first fin 2102, and the first fin 2102 in the background, with the dashed lines representing the area covered in the front view. Also shown at the location of the first fin 2102 between the gate locations 2108 and 2110 is an epitaxial N-type source or drain region 2112, e.g., an epitaxial silicon source or drain structure. Further, an interlayer dielectric material 2114 is included at the location of the first fin 2102 between the gate locations 2108 and 2110.

[0256] The PMOS region of the starting structure 2100 includes a second fin 2122, e.g., a second silicon fin, formed over and can be continuous with the substrate 2104. The second fin 2122 has a fin end 2126, which can be formed from a local or wide fin cut. A second active gate electrode location 2128 and a second dummy gate electrode location 2130 are formed over the second fin 2122, and are shown for purposes of illustration slightly in front of the second fin 2122, and the second fin 2122 in the background, with the dashed lines representing the area covered in the front view. Also shown at the location of the second fin 2122 between the gate locations 2128 and 2130 is an epitaxial P-type source or drain region 2132, e.g., an epitaxial silicon germanium source or drain structure. Further, an interlayer dielectric material 2134 is included at the location of the second fin 2122 between the gate locations 2128 and 2130.

[0257] Referring to FIG. 21B , the first and second dummy gate electrodes at locations 2110 and 2130, respectively, are removed. In removing, the fin end 2106 of the first fin 2102 and the fin end 2126 of the second fin 2122 are exposed. The removal also creates openings 2116 and 2136, respectively, in which a dielectric plug, e.g., a fin end stressor dielectric plug, can be formed.

[0258] Referring to FIG. 21C , a material liner 2140 is formed conformally to the structure of FIG. 21B In an embodiment, the material liner includes silicon and nitrogen, e.g., a silicon nitride material liner.

[0259] Referring toFIG. 21D A protective cap layer 2142, such as a metal nitride layer, is formed over the structure of FIG. 21C .

[0260] Referring to FIG. 21E A hardmask material 2144, such as a carbon-based hardmask material, is formed over the structure of FIG. 21D . A lithographic mask or mask stack 2146 is formed over the hardmask material 2144.

[0261] Referring to FIG. 21F Portions of the hardmask material 2144 and the protective cap layer 2142 in the PMOS region are removed from the structure of FIG. 21E . The lithographic mask or mask stack 2146 is also removed.

[0262] Referring to FIG. 21G A second material liner 2148 is formed conformally with the structure of FIG. 21F . In embodiments, the second material liner includes silicon and nitrogen, such as a second silicon nitride material liner. In embodiments, the second material liner 2148 has a different stress state to adjust stress in the exposed plug.

[0263] Referring to FIG. 21H A second hardmask material 2150, such as a second carbon-based hardmask material, is formed over the structure of FIG. 21G and then recessed into the openings 2136 of the PMOS region of the structure.

[0264] Referring to FIG. 21I The second material liner 2148 is etched away from the structure of FIG. 21H to remove the second material liner 2148 from the NMOS region and recess the second material liner 2148 in the PMOS region of the structure.

[0265] Referring to FIG. 21J The hardmask material 2144, the protective cap layer 2142, and the second hardmask material 2150 are removed from the structure of FIG. 21I . This removal leaves two different fill structures for the openings 2116, respectively, compared to the openings 2136.

[0266] Referring to FIG. 21K An insulative fill material 2152 is formed in the openings 2116 and 2136 of the structure of FIG. 21J and planarized. In embodiments, the insulative fill material 2152 is a flowable oxide material, such as a flowable silicon oxide or silicon dioxide material.

[0267] Referring to FIG. 21L The insulative fill material 2152 is recessed into FIG. 21KThe recessed insulative fill material 2154 is formed within the openings 2116 and 2136 of the structure 2100 to form a recessed insulative fill material 2154. In embodiments, a vapor oxidation process is performed as part of the recessing process, or after the recessing process to cure the recessed insulative fill material 2154. In one such embodiment, the recessed insulative fill material 2154 shrinks, inducing tensile stress on the fins 2102 and 2122. However, there is less tensile stress inducing material in the PMOS region than in the NMOS region.

[0268] Referring to FIG. 21M , a third material liner 2156 is over the structure 2100. In embodiments, the third material liner 2156 includes silicon and nitrogen, such as a third silicon nitride material liner. In embodiments, the third material liner 2156 prevents the recessed insulative fill material 2154 from being etched away during subsequent source or drain contact etches. FIG. 21L

[0269] FIGS. 22A-22D A cross-sectional view of an exemplary structure of a PMOS fin end stressor dielectric plug is shown, in accordance with an embodiment of the present disclosure.

[0270] Referring to FIG. 22A , the opening 2136 on the PMOS region of the structure 2100 includes a material liner 2140 along sidewalls of the opening 2136. A second material liner 2148 is coformal with a lower portion of the material liner 2140, but recessed relative to an upper portion of the material liner 2140. A recessed insulative fill material 2154 is within the second material liner 2148, and has an upper surface that is co-planar with an upper surface of the second material liner 2148. A third material liner 2156 is within the upper portion of the material liner 2140, and on an upper surface of the insulative fill material 2154 and on an upper surface of the second material liner 2148. The third material liner 2156 has a seam 2157, for example, as an artifact of a deposition process used to form the third material liner 2156.

[0271] Referring to FIG. 22B , the opening 2136 on the PMOS region of the structure 2100 includes a material liner 2140 along sidewalls of the opening 2136. A second material liner 2148 is coformal with a lower portion of the material liner 2140, but recessed relative to an upper portion of the material liner 2140. A recessed insulative fill material 2154 is within the second material liner 2148, and has an upper surface that is co-planar with an upper surface of the second material liner 2148. A third material liner 2156 is within the upper portion of the material liner 2140, and on an upper surface of the insulative fill material 2154 and on an upper surface of the second material liner 2148. The third material liner 2156 has no seam. ​

[0272] Referring to FIG. 22C The opening 2136 over the PMOS region of the structure 2100 includes a material lining 2140 along sidewalls of the opening 2136. A second material lining 2148 is coformal with a lower portion of the material lining 2140, but recessed relative to an upper portion of the material lining 2140. A recessed insulative fill material 2154 is within and above the second material lining 2148, and has an upper surface that is above an upper surface of the second material lining 2148. A third material lining 2156 is within the upper portion of the material lining 2140, and on an upper surface of the insulative fill material 2154. The third material lining 2156 is shown as being seamless, but in other embodiments the third material lining 2156 has a seam.

[0273] Referring to FIG. 22D The opening 2136 over the PMOS region of the structure 2100 includes a material lining 2140 along sidewalls of the opening 2136. A second material lining 2148 is coformal with a lower portion of the material lining 2140, but recessed relative to an upper portion of the material lining 2140. A recessed insulative fill material 2154 is within and above the second material lining 2148, and has an upper surface that is below an upper surface of the second material lining 2148. A third material lining 2156 is within the upper portion of the material lining 2140, and on an upper surface of the insulative fill material 2154 and on an upper surface of the second material lining 2148. The third material lining 2156 is shown as being seamless, but in other embodiments the third material lining 2156 has a seam.

[0274] Referring to FIG. 19A , FIG. 19B , FIG. 20A , FIG. 20B , FIGS. 21A-21M and FIG. 22A - FIG. 22DAccording to embodiments of the present disclosure, an integrated circuit structure includes a fin, e.g., of silicon, having a top and sidewalls. The top has a longest dimension along a direction. A first isolation structure is over a first end of the fin. A gate structure includes a gate electrode over the top of a region of the fin and laterally adjacent the sidewalls of the region. The gate structure is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure along the direction. The first and second isolation structures both include a first dielectric material (e.g., material liner 2140) laterally surrounding a second dielectric material (e.g., second material liner 2148) of a recess different from the first dielectric material. The second dielectric material of the recess laterally surrounds at least a portion of a third dielectric material (e.g., recessed insulative fill material 2154) different from the first and second dielectric materials.

[0275] In one embodiment, the first and second isolation structures both further include a fourth dielectric material (e.g., third material liner 2156) laterally surrounded by an upper portion of the first dielectric material, the fourth dielectric material being on an upper surface of the third dielectric material. In one such embodiment, the fourth dielectric material is further on an upper surface of the second dielectric material. In another such embodiment, the fourth dielectric material has a generally vertical central seam. In another such embodiment, the fourth dielectric material is free of seams.

[0276] In one embodiment, the third dielectric material has an upper surface that is co-planar with an upper surface of the second dielectric material. In one embodiment, the third dielectric material has an upper surface that is below an upper surface of the second dielectric material. In one embodiment, the third dielectric material has an upper surface that is above an upper surface of the second dielectric material, and the third dielectric material is further on top of the upper surface of the second dielectric material. In one embodiment, the first and second isolation structures induce compressive stress on the fin. In one such embodiment, the gate electrode is a P-type gate electrode.

[0277] In one embodiment, the first isolation structure has a width along the direction, the gate structure has a width along the direction, and the second isolation structure has a width along the direction. In one such embodiment, a center of the gate structure is spaced apart from a center of the first isolation structure by a pitch along the direction, and a center of the second isolation structure is spaced apart from the center of the gate structure by the pitch along the direction. In one embodiment, the first and second isolation structures are both in corresponding trenches in an interlayer dielectric layer.

[0278] In one such embodiment, the first source or drain region is between the gate structure and the first isolation structure. The second source or drain region is between the gate structure and the second isolation structure. In one such embodiment, the first and second source or drain regions are embedded source or drain regions comprising silicon and germanium. In one such embodiment, the gate structure further comprises a high-k dielectric layer between the gate electrode and the fin and along the sidewalls of the gate electrode.

[0279] In another aspect, the depth of individual dielectric plugs can vary within a semiconductor structure or within a architecture formed on a common substrate. As an example, FIG. 23A A cross-sectional view of another semiconductor structure with fin end stress inducing features is shown in accordance with another embodiment of the disclosure. Referring to FIG. 23A , including a shallow dielectric plug 2308A and a pair of deep dielectric plugs 2308B and 2308C. In one such embodiment, as shown, the shallow dielectric plug 2308C is at a depth approximately equal to the depth of the semiconductor fins 2302 within the substrate 2304, while the pair of deep dielectric plugs 2308B and 2308C are at a depth less than the depth of the semiconductor fins 2302 within the substrate 2304.

[0280] Referring again to FIG. 23A , such an arrangement can enable stress amplification on fin-trimmed isolation (FTI) devices in trenches etched deeper into the substrate 2304 in order to provide isolation between adjacent fins 2302. Such an approach can be implemented to increase the density of transistors on a chip. In embodiments, the stress effects induced from plug filling on transistors are amplified in FTI transistors because stress transfer occurs both in the fin and in the substrate or just underneath the transistor.

[0281] In another aspect, the width or amount of tensile stress inducing oxide layer included in a dielectric plug can vary within a semiconductor structure or within an architecture formed on a common substrate, for example, depending on whether the device is a PMOS device or an NMOS device. As an example, FIG. 23B A cross-sectional view of another semiconductor structure with fin end stress inducing features is shown in accordance with another embodiment of the disclosure. Referring to FIG. 23B , in particular embodiments, NMOS devices include relatively more tensile stress inducing oxide layer 2350 than corresponding PMOS devices.

[0282] Referring again to FIG. 23BIn embodiments, differential plug filling is implemented to induce appropriate stresses in NMOS and PMOS. For example, NMOS plugs 2308D and 2308E have a greater volume and greater width of tensile stress inducing oxide layer 2350 than PMOS plugs 2308F and 2308G. Plug filling can be patterned to induce different stresses in NMOS and PMOS devices. For example, photolithography can be used to pattern open PMOS devices (e.g., widen the dielectric plug trench for PMOS devices), at which point different fill options can be performed to differentiate plug filling in NMOS devices from plug filling in PMOS devices. In exemplary embodiments, reducing the volume of flowable oxide in plugs on PMOS devices can reduce induced tensile stress. In one such embodiment, compressive stress can be primarily from, for example, compressive stress source and drain regions. In other embodiments, using different plug liners or different fill materials provides adjustable stress control.

[0283] As noted above, it is recognized that multi-plug stress effects can benefit both NMOS transistors (e.g., tensile channel stress) and PMOS transistors (e.g., compressive channel stress). According to embodiments of the present disclosure, the semiconductor fin is a uniaxial stress semiconductor fin. The uniaxial stress semiconductor fin can be stressed in a uniaxial direction with tensile stress or with compressive stress. For example, according to one or more embodiments of the present disclosure, FIG. 24A A tilted view of a fin with tensile uniaxial stress is shown, FIG. 24B A tilted view of a fin with compressive uniaxial stress is shown.

[0284] Referring to FIG. 24A Semiconductor fin 2400 has a discrete channel region (C) disposed therein. Source region (S) and drain region (D) are disposed in semiconductor fin 2400 on either side of channel region (C). The discrete channel region of semiconductor fin 2400 has a current flow direction from source region (S) to drain region (D) in the direction of uniaxial tensile stress (arrows pointing away from each other and toward end portions 2402 and 2404).

[0285] Referring to FIG. 24Bsemiconductor fin 2450 has a discrete channel region (C) disposed therein. A source region (S) and a drain region (D) are disposed in the semiconductor fin 2450 on either side of the channel region (C). The discrete channel region of the semiconductor fin 2450 has a current flow direction from the source region (S) to the drain region (D) along the direction of uniaxial compressive stress (the arrows pointing toward each other and from the ends 2452 and 2454). Thus, embodiments described herein can be implemented to improve transistor mobility and drive current, allowing circuits and chips to be executed faster.

[0286] In another aspect, there can be a relationship between where gate line cuts (multi-cuts) are made and where fin trim isolation (FTI) local fin cuts are made. In embodiments, FTI local cuts are made only in locations where multi-cuts are made. However, in one such embodiment, FTI cuts are not necessarily made at every location where multi-cuts are made.

[0287] FIG. 25A and FIG. 25B A plan view showing various operations in a method of patterning a fin with single gate spacing for forming local isolation structures in selected gate line cut locations is shown, in accordance with an embodiment of the present disclosure.

[0288] Referring to FIG. 25A A method of fabricating an integrated circuit structure includes forming a plurality of fins 2502, individual fins of the plurality of fins 2502 having a longest dimension along a first direction 2504. A plurality of gate structures 2506 is over the plurality of fins 2502, individual fins of the gate structures 2506 having a longest dimension along a second direction 2508 that is orthogonal to the first direction 2504. In embodiments, the gate structures 2506 are sacrificial or dummy gate lines, fabricated, for example, from polysilicon. In one embodiment, the plurality of fins 2502 are silicon fins, and are continuous with a portion of an underlying silicon substrate.

[0289] Referring again to FIG. 25A, a dielectric material structure 2510 is formed between adjacent gate structures of the plurality of gate structures 2506. Portions 2512 and 2513 of two of the plurality of gate structures 2506 are removed to expose portions of each of the plurality of fins 2502. In an embodiment, removing portions 2512 and 2513 of two of the gate structures 2506 involves using a lithography window that is wider than a width of each of the portions 2512 and 2513 of the gate structures 2506. The exposed portions of each of the plurality of fins 2502 at location 2512 are removed to form a cutout region 2520. In an embodiment, the exposed portions of each of the plurality of fins 2502 are removed using a dry or plasma etching process. However, the exposed portions of each of the plurality of fins 2502 at location 2513 are masked from being removed. In an embodiment, region 2512 / 2520 represents both a multi-cut and an FTI partial fin cut. However, location 2513 represents only a multi-cut.

[0290] Referring to FIG. 25B , locations 2512 / 2520 of the multi-cut and FTI partial fin cut and location 2513 of the multi-cut are filled with an insulating structure 2530, such as a dielectric plug. An exemplary insulating structure or “multi-cut” or “plug” structure is described below.

[0291] FIGS. 26A-26C Cross-sectional views of various possibilities for dielectric plugs for multi-cut and FTI partial fin cut locations and only multi-cut locations for various regions of the structure of FIG. 25B are shown in accordance with embodiments of the present disclosure.

[0292] Referring to FIG. 26A , a cross-sectional view of a portion 2600A of the dielectric plug 2530 at location 2513 is shown along the a-a’ axis of the structure of FIG. 25B . The portion 2600A of the dielectric plug 2530 is shown on uncut fins 2502 and between dielectric material structures 2510.

[0293] Referring to FIG. 26B , a cross-sectional view of a portion 2600B of the dielectric plug 2530 at location 2512 is shown along the b-b’ axis of the structure of FIG. 25B . The portion 2600B of the dielectric plug 2530 is shown on cut fin locations 2520 and between dielectric material structures 2510.

[0294] Referring to FIG. 26C , a cross-sectional view of a portion 2600C of the dielectric plug 2530 at location 2513 is shown along the c-c’ axis of the structure of FIG. 25BA cross-sectional view of a portion 2600C of the dielectric plug 2530 at location 2512 along the c-c' axis of the structure is shown. The portion 2600C of the dielectric plug 2530 is shown on the trench isolation structure 2602 between the fins 2502 and between the dielectric material structure 2510. In the embodiment whose example is described above, the trench isolation structure 2602 includes a first insulating layer 2602A, a second insulating layer 2602B, and an insulating fill material 2602C on the second insulating layer 2602B.

[0295] Referring to FIG. 25A , FIG. 25B and FIGS. 26A-26C , in accordance with embodiments of the present disclosure, a method of fabricating an integrated circuit structure includes forming a plurality of fins, individual fins of the plurality of fins along a first direction. A plurality of gate structures is formed over the plurality of fins, individual gate structures of the plurality of gate structures along a second direction orthogonal to the first direction. A dielectric material structure is formed between adjacent gate structures of the plurality of gate structures. Portions of a first gate structure of the plurality of gate structures are removed to expose a first portion of each of the plurality of fins. Portions of a second gate structure of the plurality of gate structures are removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed. A first insulating structure is formed in a location of the removed first portion of the plurality of fins. A second insulating structure is formed in a location of the removed portion of the second of the plurality of gate structures.

[0296] In one embodiment, removing the portions of the first and second gate structures of the plurality of gate structures involves using a lithography window that is wider than a width of each of the portions of the first and second gate structures of the plurality of gate structures. In one embodiment, removing the exposed first portion of each of the plurality of fins involves etching to a depth that is less than a height of the plurality of fins. In one such embodiment, the depth is greater than a depth of a source or drain region in the plurality of fins. In one embodiment, the plurality of fins includes silicon fins and is continuous with a portion of a silicon substrate below.

[0297] Referring to FIG. 16A , FIG. 25A , FIG. 25B and FIGS. 26A-26CAccording to another embodiment of the disclosure, an integrated circuit structure includes a fin including silicon, the fin having a longest dimension along a first direction. An isolation structure is over an upper portion of the fin, the isolation structure having a center along the first direction. A first gate structure is over the upper portion of the fin, the first gate structure having a longest dimension along a second direction orthogonal to the first direction. A center of the first gate structure is spaced apart from the center of the isolation structure by a pitch along the first direction. A second gate structure is over the upper portion of the fin, the second gate structure having a longest dimension along the second direction. A center of the second gate structure is spaced apart from the center of the first gate structure by the pitch along the first direction. A third gate structure is over the upper portion of the fin on a side of the isolation structure opposite the first and second gate structures, the third gate structure having a longest dimension along the second direction. A center of the third gate structure is spaced apart from the center of the isolation structure by the pitch along the first direction.

[0298] In one embodiment, each of the first, second, and third gate structures includes a gate electrode on and between sidewalls of a high-k gate dielectric layer. In one such embodiment, each of the first, second, and third gate structures further includes an insulating cap on the gate electrode and on the sidewalls of the high-k gate dielectric layer.

[0299] In one embodiment, a first epitaxial semiconductor region is on the upper portion of the fin between the first gate structure and the isolation structure. A second epitaxial semiconductor region is on the upper portion of the fin between the first gate structure and the second gate structure. A third epitaxial semiconductor region is on the upper portion of the fin between the third gate structure and the isolation structure. In one such embodiment, the first, second, and third epitaxial semiconductor regions include silicon and germanium. In another such embodiment, the first, second, and third epitaxial semiconductor regions include silicon.

[0300] For reference FIG. 16A , FIG. 25A , FIG. 25B and FIGS. 26A-26CAccording to another embodiment of the disclosure, an integrated circuit structure includes a shallow trench isolation (STI) structure between a pair of semiconductor fins, the STI structure having a longest dimension along a first direction. An isolation structure is on the STI structure, the isolation structure having a center along the first direction. A first gate structure is on the STI structure, the first gate structure having a longest dimension along a second direction orthogonal to the first direction. A center of the first gate structure is spaced apart from the center of the isolation structure by a pitch along the first direction. A second gate structure is on the STI structure, the second gate structure having a longest dimension along the second direction. A center of the second gate structure is spaced apart from the center of the first gate structure by the pitch along the first direction. A third gate structure is on the STI structure on a side of the isolation structure opposite the first and second gate structures, the third gate structure having a longest dimension along the second direction. A center of the third gate structure is spaced apart from the center of the isolation structure by the pitch along the first direction.

[0301] In one embodiment, each of the first, second, and third gate structures includes a gate electrode on and between sidewalls of a high-k gate dielectric layer. In one such embodiment, each of the first, second, and third gate structures further includes an insulating cap on the gate electrode and on the sidewalls of the high-k gate dielectric layer. In one embodiment, the pair of semiconductor fins are a pair of silicon fins.

[0302] In another aspect, whether with multi-cut and FTI local fin cut together or just multi-cut, the insulating structure or dielectric plug used to fill the cut location can extend laterally into the dielectric spacer of the corresponding cut gate line, even beyond the dielectric spacer of the corresponding cut gate line.

[0303] In a first example where the trench contact shape is not affected by the multi-cut dielectric plug, FIG. 27A Plan views and corresponding cross-sectional views of an integrated circuit structure having gate line cuts with dielectric plugs extending into the dielectric spacer of the gate line are shown according to embodiments of the disclosure.

[0304] Reference is made to FIG. 27AThe integrated circuit structure 2700A includes a first silicon fin 2702 having a longest dimension along a first direction 2703. A second silicon fin 2704 has a longest dimension along the first direction 2703. An insulator material 2706 is between the first silicon fin 2702 and the second silicon fin 2704. A gate line 2708 is over the first silicon fin 2702 and over the second silicon fin 2704 along a second direction 2709, the second direction 2709 being orthogonal to the first direction 2703. The gate line 2708 has a first side 2708A and a second side 2708B, and has a first end 2708C and a second end 2708D. The gate line 2708 has a discontinuity 2710 over the insulator material 2706 between the first end 2708C and the second end 2708D of the gate line 2708. The discontinuity 2710 is filled by a dielectric plug 2712.

[0305] A trench contact 2714 is over the first silicon fin 2702 and over the second silicon fin 2704 along the second direction 2709 at a first side 2708A of the gate line 2708. The trench contact 2714 is continuous over the insulator material 2706 at a location 2715 laterally adjacent to the dielectric plug 2712. A dielectric spacer 2716 is laterally between the trench contact 2714 and the first side 2708A of the gate line 2708. The dielectric spacer 2716 is continuous along the first side 2708A of the gate line 2708 and the dielectric plug 2712. The dielectric spacer 2716 has a width (W2) laterally adjacent to the dielectric plug 2712 that is thinner than a width (Wl) laterally adjacent to the first side 2708A of the gate line 2708.

[0306] In one embodiment, a second trench contact 2718 is over the first silicon fin 2702 and over the second silicon fin 2704 along the second direction 2709 at a second side 2708B of the gate line 2708. The second trench contact 2718 is continuous over the insulator material 2706 at a location 2719 laterally adjacent to the dielectric plug 2712. In one such embodiment, a second dielectric spacer 2720 is laterally between the second trench contact 2718 and the second side 2708B of the gate line 2708. The second dielectric spacer 2720 is continuous along the second side 2708B of the gate line 2708 and the dielectric plug 2712. The second dielectric spacer has a width laterally adjacent to the dielectric plug 2712 that is thinner than a width laterally adjacent to the second side 2708B of the gate line 2708.

[0307] In one embodiment, the gate line 2708 includes a high-k gate dielectric layer 2722, a gate electrode 2724, and a dielectric cap layer 2726. In one embodiment, the dielectric plug 2712 includes the same material as the dielectric spacer 2714, but is separate from the dielectric spacer 2714. In one embodiment, the dielectric plug 2712 includes a different material than the dielectric spacer 2714.

[0308] In a second example where the trench contact shape is influenced by a multi- cut dielectric plug, FIG. 27B A plan view and corresponding cross-sectional view of an integrated circuit structure having a gate line cut with a dielectric plug extending outside of a dielectric spacer of a gate line, according to another embodiment of the present disclosure, is shown.

[0309] Reference is made to FIG. 27B The integrated circuit structure 2700B includes a first silicon fin 2752 having a longest dimension along a first direction 2753. A second silicon fin 2754 has a longest dimension along the first direction 2753. An insulator material 2756 is between the first silicon fin 2752 and the second silicon fin 2754. A gate line 2758 is over the first silicon fin 2752 and over the second silicon fin 2754 along a second direction 2759, the second direction 2759 being orthogonal to the first direction 2753. The gate line 2758 has a first side 2758A and a second side 2758B, and has a first end 2758C and a second end 2758D. The gate line 2758 has a discontinuity 2760 over the insulator material 2756 between the first end 2758C and the second end 2758D of the gate line 2758. The discontinuity 2760 is filled by a dielectric plug 2762.

[0310] A trench contact 2764 is over the first silicon fin 2752 and over the second silicon fin 2754 along the second direction 2759 at the first side 2758A of the gate line 2758. The trench contact 2764 is continuous over the insulator material 2756 at a location 2765 laterally adjacent to the dielectric plug 2762. A dielectric spacer 2766 is laterally between the trench contact 2764 and the first side 2758A of the gate line 2758. The dielectric spacer 2766 is along the first side 2758A of the gate line 2758 but not along the dielectric plug 2762, resulting in a discontinuous dielectric spacer 2766. The trench contact 2764 has a width (Wl) laterally adjacent to the dielectric plug 2762 that is thinner than a width (W2) laterally adjacent to the dielectric spacer 2766.

[0311] In one embodiment, the second trench contact 2768 is over the first silicon fin 2752 and over the second silicon fin 2754 along the second direction 2759 at the second side 2758B of the gate line 2758. The second trench contact 2768 is continuous over the insulator material 2756 at a location 2769 laterally adjacent to the dielectric plug 2762. In one such embodiment, a second dielectric spacer 2770 is laterally between the second trench contact 2768 and the second side 2758B of the gate line 2758. The second dielectric spacer 2770 is discontinuous along the second side 2758B of the gate line 2758 but not along the dielectric plug 2762. The second trench contact 2768 has a width laterally adjacent to the dielectric plug 2762 that is thinner than a width laterally adjacent to the second dielectric spacer 2770.

[0312] In one embodiment, the gate line 2758 includes a high-k dielectric layer 2772, a gate electrode 2774, and a dielectric cap layer 2776. In one embodiment, the dielectric plug 2762 includes the same material as the dielectric spacer 2764 but is separate from the dielectric spacer 2764. In one embodiment, the dielectric plug 2762 includes a different material than the dielectric spacer 2764.

[0313] In a third example of a dielectric plug for a multi-cut location tapering from a top of the plug to a bottom of the plug, FIGS. 28A-28F Cross-sectional views showing various operations in a method of fabricating an integrated circuit structure having a gate line cut with a dielectric plug having an upper portion extending beyond a dielectric spacer of a gate line and a lower portion extending into the gate line dielectric spacer, in accordance with another embodiment of the present disclosure, are shown.

[0314] Referring to FIG. 28A A plurality of gate lines 2802 are formed over the structure 2804, e.g., over a trench isolation structure between semiconductor fins. In one embodiment, each of the gate lines 2802 is a sacrificial or dummy gate line, e.g., having a dummy gate electrode 2806 and a dielectric cap 2808. Portions of such sacrificial or dummy gate lines can be later replaced, e.g., after dielectric plug formation described below, in a replacement gate process. A dielectric spacer 2810 is along sidewalls of the gate lines 2802. A dielectric material 2812, such as a dielectric interlayer, is between the gate lines 2802. A mask 2814 is formed and lithographically patterned to expose a portion of one of the gate lines 2802.

[0315] Referring to FIG. 28BWith the mask 2814 in place, an etch process is used to remove the center gate line 2802. The mask 2814 is then removed. In an embodiment, the etch process etches away portions of the dielectric spacer 2810 of the removed gate line 2802, thereby forming a reduced dielectric spacer 2816. In addition, the upper portion of the dielectric material 2812 exposed by the mask 2814 is etched away in the etch process, thereby forming an etched dielectric material portion 2818. In a particular embodiment, a residual dummy gate material 2820, such as residual polysilicon, remains in the structure as an artifact of the incomplete etch process.

[0316] Referring to FIG. 28C , a hard mask 2822 is formed over the structure of FIG. 28B . The hard mask 2822 can be conformal to the upper portion of the structure of FIG. 28B , and in particular to the etched dielectric material portion 2818.

[0317] Referring to FIG. 28D , the residual dummy gate material 2820 is removed, for example, using an etch process that can be chemically similar to the etch process used to remove the center gate line of the gate lines 2802. In an embodiment, the hard mask 2822 protects the etched dielectric material portion 2818 from further etching during the removal of the residual dummy gate material 2820.

[0318] Referring to FIG. 28E , the hard mask 2822 is removed. In one embodiment, the hard mask 2822 is removed without or substantially without further etching the etched dielectric material portion 2818.

[0319] Referring to FIG. 28F , a dielectric plug 2830 is formed in the opening of the structure of FIG. 28E . An upper portion of the dielectric plug 2830 is over the etched dielectric material portion 2818, for example, effectively beyond the initial spacer 2810. A lower portion of the dielectric plug 2830 is adjacent to the reduced dielectric spacer 2816, for example, effectively into but not beyond the initial spacer 2810. As a result, the dielectric plug 2830 has a tapered profile, as shown in FIG. 28F . It should be appreciated that the dielectric plug 2830 can be fabricated from the materials and processes described above for other multi-cut or FTI plug or fin end stressor.

[0320] In another aspect, portions of the placeholder gate structure or dummy gate structure can remain over the trench isolation region below the permanent gate structure during the replacement gate process as a protective structure to prevent etching of the trench isolation region. For example, FIGS. 29A-29CPlan views and corresponding cross-sectional views of an integrated circuit structure having a residual dummy gate material at a portion of a bottom of a permanent gate stack, in accordance with an embodiment of the present disclosure, are shown.

[0321] Reference is made to FIGS. 29A-29C The integrated circuit structure includes a fin 2902, such as a silicon fin, protruding from a semiconductor substrate 2904. The fin 2902 has a lower fin portion 2902B and an upper fin portion 2902A. The upper fin portion 2902A has a top 2902C and a sidewall 2902D. An isolation structure 2906 surrounds the lower fin portion 2902B. The isolation structure 2906 includes an insulating material 2906C having a top surface 2907. A semiconductor material 2908 is on a portion of the top surface 2907 of the insulating material 2906C. The semiconductor material 2908 is separate from the fin 2902.

[0322] A gate dielectric layer 2910 is over the top 2902C of the upper fin portion 2902A and laterally adjacent to the sidewall 2902D of the upper fin portion 2902A. The gate dielectric layer 2910 is further over the semiconductor material 2908 on the portion of the top surface 2907 of the insulating material 2906C. An intervening additional gate dielectric layer 2911, such as an oxidized portion of the fin 2902, can be between the gate dielectric layer 2910 over the top 2902C of the upper fin portion 2902A and the sidewall 2902D of the upper fin portion 2902A and laterally adjacent to the sidewall 2902D. A gate electrode 2912 is over the gate dielectric layer 2910 over the top 2902C of the upper fin portion 2902A and laterally adjacent to the sidewall 2902D of the upper fin portion 2902A. The gate electrode 2912 is further over the gate dielectric layer 2910 on the semiconductor material 2908 on the portion of the top surface 2907 of the insulating material 2906C. A first source or drain region 2916 is adjacent to a first side of the gate electrode 2912 and a second source or drain region 2918 is adjacent to a second side of the gate electrode 2912, the second side being opposite the first side. In the above-described embodiment whose examples are described, the isolation structure 2906 includes a first insulating layer 2906A, a second insulating layer 2906B, and the insulating material 2606C.

[0323] In one embodiment, the semiconductor material 2908 on portions of the top surface 2907 of the insulating material 2906C is or includes polysilicon. In one embodiment, the top surface 2907 of the insulating material 2906C has a concave depression, and as shown, the semiconductor material 2908 is in the concave depression. In one embodiment, the isolation structure 2906 includes a second insulating material (2906A or 2906B or both 2906A / 2906B) along the bottom and sidewalls of the insulating material 2906C. In one such embodiment, portions of the second insulating material (2906A or 2906B or both 2906A / 2906B) along the sidewalls of the insulating material 2906C have a top surface that is above the uppermost surface of the insulating material 2906, as shown. In one embodiment, the top surface of the second insulating material (2906A or 2906B or both 2906A / 2906B) is higher than or coplanar with the uppermost surface of the semiconductor material 2908.

[0324] In one embodiment, the semiconductor material 2908 on portions of the top surface 2907 of the insulating material 2906C does not extend beyond the gate dielectric layer 2910. That is, from a plan view perspective, the location of the semiconductor material 2908 is limited to the area covered by the gate stack 2912 / 2910. In one embodiment, a first dielectric spacer 2920 is along a first side of the gate electrode 2912. A second dielectric spacer 2922 is along a second side of the gate electrode 2912. In one such embodiment, the gate dielectric layer 2910 also extends along the sidewalls of the first and second dielectric spacers 2920, 2922, as shown. FIG. 29B

[0325] In one embodiment, the gate electrode 2912 includes a conformal conductive layer 2912A (e.g., a work function layer). In one such embodiment, the work function layer 2912A includes titanium and nitrogen. In another embodiment, the work function layer 2912A includes titanium, aluminum, carbon, and nitrogen. In one embodiment, the gate electrode 2912 also includes a conductive fill metal layer 2912B over the work function layer 2912A. In one such embodiment, the conductive fill metal layer 2912B includes tungsten. In a particular embodiment, the conductive fill metal layer 2912B includes 95 atomic percent or more tungsten and 0.1 to 2 atomic percent fluorine. In one embodiment, an insulating cap 2924 is on the gate electrode 2912 and can extend over the gate dielectric layer 2910, as shown. FIG. 29B

[0326] FIGS. 30A-30D ​​Cross-sectional views illustrating various operations in a method of fabricating an integrated circuit structure having a residual dummy gate material at a portion of a bottom of a permanent gate stack, according to another embodiment of the present disclosure, are shown. The perspective view is along FIG. 29C a portion of the a-a' axis of the structure.

[0327] Referring to FIG. 30A , a method of fabricating an integrated circuit structure includes forming a fin 3000 from a semiconductor substrate 3002. The fin 3000 has a lower fin portion 3000A and an upper fin portion 3000B. The upper fin portion 3000B has a top 3000C and a sidewall 3000D. An isolation structure 3004 surrounds the lower fin portion 3000A. The isolation structure 3004 includes an insulating material 3004C having a top surface 3005. A placeholder gate electrode 3006 is over the top 3000C of the upper fin portion 3000B and laterally adjacent to the sidewall 3000D of the upper fin portion 3000B. The placeholder gate electrode 3006 includes a semiconductor material.

[0328] Although not shown from the perspective of FIG. 30A (but shown in FIG. 29C for which locations are shown), a first source or drain region can be formed adjacent to a first side of the placeholder gate electrode 3006, and a second source or drain region can be formed adjacent to a second side of the placeholder gate electrode 3006, the second side opposite the first side. Further, a gate dielectric spacer can be formed along the sidewall of the placeholder gate electrode 3006, and an interlayer dielectric (ILD) layer can be formed laterally adjacent to the placeholder gate electrode 3006.

[0329] In one embodiment, the placeholder gate electrode 3006 is or includes polysilicon. In one embodiment, the top surface 3005 of the insulating material 3004C of the isolation structure 3004 has a concave depression, as shown. A portion of the placeholder gate electrode 3006 is in the concave depression. In one embodiment, the isolation structure 3004 includes a second insulating material (3004A or 3004B or both 3004A / 3004B) along a bottom and sidewall of the insulating material 3004C, as shown. In one such embodiment, the second insulating material (3004A or 3004B or both 3004A / 3004B) has a top surface along a portion of the sidewall of the insulating material 3004C that is above at least a portion of the top surface 3005 of the insulating material 3004C. In one embodiment, the top surface of the second insulating material (3004A or 3004B or both 3004A / 3004B) is above a lowest surface of a portion of the placeholder gate electrode 3006.

[0330] Referring to FIG. 30BFor example, along FIG. 30A The placeholder gate electrode 3006 is etched from the top 3000C and sidewall 3000D of the upper fin portion 3000B in direction 3008. This etching process can be referred to as a gate replacement process. In an embodiment, the etching or gate replacement process is not completed, and a portion 3012 of the placeholder gate electrode 3006 is left on at least a portion of the top surface 3005 of the insulating material 3004C of the isolation structure 3004.

[0331] refer to FIG. 30A and FIG. 30B In one embodiment, the oxide portion 3010 of the upper fin portion 3000B formed before the formation of the placeholder gate electrode 3006 is retained during the etching process, as shown. However, in another embodiment, a placeholder gate dielectric layer is formed before the formation of the placeholder gate electrode 3006 and is removed after etching the placeholder gate electrode.

[0332] refer to FIG. 30C A gate dielectric layer 3014 is formed on the top 3000C of the upper fin portion 3000B and laterally adjacent to the sidewall 3000D of the upper fin portion 3000B. In one embodiment, the gate dielectric layer 3014 is formed on the oxide portion 3010 of the upper fin portion 3000B above the top 3000C of the upper fin portion 3000B and laterally adjacent to the sidewall 3000D of the upper fin portion 3000B, as shown. In another embodiment, where the oxide portion 3010 of the upper fin portion 3000B is removed after etching the placeholder gate electrode, the gate dielectric layer 3014 is formed directly on the upper fin portion 3000B, on the top 3000C of the upper fin portion 3000B, and laterally adjacent to the sidewall 3000D of the upper fin portion 3000B. In any case, in the embodiments, the gate dielectric layer 3014 is further formed on a portion 3012 of the occupier gate electrode 3006 on a portion of the top surface 3005 of the insulating material 3004C of the isolation structure 3004.

[0333] refer to FIG. 30D A permanent gate electrode 3016 is formed on the gate dielectric layer 3014 above the top 3000C of the upper fin portion 3000B and is laterally adjacent to the sidewall 3000D of the upper fin portion 3000B. The permanent gate electrode 3016 is further formed on the gate dielectric layer 3014 on the portion 3012 of the occupier gate electrode 3006 on the top surface 3005 of the insulating material 3004C.

[0334] In one embodiment, forming the permanent gate electrode 3016 includes forming a work function layer 3016A. In one such embodiment, the work function layer 3016A includes titanium and nitrogen. In another such embodiment, the work function layer 3016A includes titanium, aluminum, carbon, and nitrogen. In one embodiment, forming the permanent gate electrode 3016 further includes forming a conductive fill metal layer 3016B formed over the work function layer 3016A. In one such embodiment, forming the conductive fill metal layer 3016B includes forming a tungsten-containing film using atomic layer deposition (ALD) with a tungsten hexafluoride (WF6) precursor. In an embodiment, an insulating gate cap layer 3018 is formed over the permanent gate electrode 3016.

[0335] In another aspect, some embodiments of the present disclosure include an amorphous high-k layer for a gate electrode in a gate dielectric structure. In other embodiments, a partially or fully crystalline high-k layer for a gate electrode is included in a gate dielectric structure. In one embodiment including a partially or fully crystalline high-k layer, the gate dielectric structure is a ferroelectric (FE) gate dielectric structure. In another embodiment including a partially or fully crystalline high-k layer, the gate dielectric structure is an anti-ferroelectric (AFE) gate dielectric structure.

[0336] In embodiments, ways to increase charge in a device channel and improve subthreshold behavior by employing ferroelectric or anti-ferroelectric gate oxides are described herein. Ferroelectric and anti-ferroelectric gate oxides are capable of increasing channel charge to achieve higher current, and are also capable of making a sharper turn-on behavior.

[0337] To provide context, hafnium or zirconium (Hf or Zr)-based ferroelectric and anti-ferroelectric (FE or AFE) materials are typically much thinner than ferroelectric materials such as lead zirconium titanate (PZT), such that they can be compatible with highly scaled logic technologies. FE or AFE materials have two features that can improve the performance of logic transistors: (1) higher charge in the channel enabled by FE or AFE polarization, and (2) sharper turn-on behavior due to the sharp FE or AFE transition. Such properties can improve transistor performance by increasing current and reducing subthreshold swing (SS).

[0338] FIG. 31A A cross-sectional view of a semiconductor device having a ferroelectric or anti-ferroelectric gate dielectric structure in accordance with embodiments of the present disclosure is shown.

[0339] Reference FIG. 31AIn one embodiment, integrated circuit structure 3100 includes a gate structure 3102 over a substrate 3104. In one embodiment, gate structure 3102 is over or on a semiconductor channel structure 3106 that includes a single crystalline material such as single crystalline silicon. Gate structure 3102 includes a gate dielectric over semiconductor channel structure 3106 and a gate electrode over the gate dielectric. The gate dielectric includes a ferroelectric or anti-ferroelectric polycrystalline material layer 3102A. The gate electrode has a conductive layer 3102B over the ferroelectric or anti-ferroelectric polycrystalline material layer 3102A. The conductive layer 3102B includes a metal and can be a barrier layer, a work function layer, or a template layer that enhances crystallinity of the FE or AFE layer. One or more gate fill layers 3102C are on or over the conductive layer 3102B. Source region 3108 and drain region 3110 are on opposite sides of gate structure 3102. Source or drain contact 3112 is electrically connected to source region 3108 and drain region 3110 at location 3149 and is spaced apart from gate structure 3102 by an interlayer dielectric layer 3114 or a gate dielectric spacer 3116. In one embodiment, source region 3108 and drain region 3110 are regions of substrate 3104. In embodiments, source or drain contact 3112 includes a barrier layer 3112A and a conductive trench fill material 3112B. In one embodiment, ferroelectric or anti-ferroelectric polycrystalline material layer 3102A extends along dielectric spacer 3116 as shown in FIG. 31B. FIG. 31A In one embodiment, and throughout this disclosure, ferroelectric or anti-ferroelectric polycrystalline material layer 3102A is a ferroelectric polycrystalline material layer. In one embodiment, the ferroelectric polycrystalline material layer is an oxide including Zr and Hf with a 50:50 Zr:Hr ratio or more Zr. The ferroelectric effect can increase with increasing orthorhombic crystallinity. In one embodiment, the ferroelectric polycrystalline material layer has at least 80% orthorhombic crystallinity. FIG. 31A

[0340] In one embodiment, and throughout this disclosure, ferroelectric or anti-ferroelectric polycrystalline material layer 3102A is a ferroelectric polycrystalline material layer. In one embodiment, the ferroelectric polycrystalline material layer is an oxide including Zr and Hf with a 50:50 Zr:Hr ratio or more Zr. The ferroelectric effect can increase with increasing orthorhombic crystallinity. In one embodiment, the ferroelectric polycrystalline material layer has at least 80% orthorhombic crystallinity.

[0341] In one embodiment, and throughout this disclosure, ferroelectric or anti-ferroelectric polycrystalline material layer 3102A is a ferroelectric polycrystalline material layer. In one embodiment, the ferroelectric polycrystalline material layer is an oxide including Zr and Hf with a 50:50 Zr:Hr ratio or more Zr. The ferroelectric effect can increase with increasing orthorhombic crystallinity. In one embodiment, the ferroelectric polycrystalline material layer has at least 80% orthorhombic crystallinity.

[0342] ​In embodiments, and applicable throughout the disclosure, the gate dielectric of the gate stack 3102 further includes an amorphous dielectric layer 3103, such as a native silicon oxide layer, a high-K dielectric (HfOx, AI2O3, etc.), or a combination of oxide and high-K, between the ferroelectric or anti-ferroelectric poly material layer 3102A and the semiconductor channel structure 3106. In embodiments, and applicable throughout the disclosure, the ferroelectric or anti-ferroelectric poly material layer 3102A has a thickness in the range of 1 nanometer to 8 nanometers. In embodiments, and applicable throughout the disclosure, the ferroelectric or anti-ferroelectric poly material layer 3102A has a grain size approximately in the range of 20 nanometers or greater.

[0343] In embodiments, after depositing the ferroelectric or anti-ferroelectric poly material layer 3102A, such as by atomic layer deposition (ALD), a layer comprising metal is formed on the ferroelectric or anti-ferroelectric poly material layer 3102A (e.g., layer 3102B, such as 5-10 nanometers of titanium nitride or tantalum nitride or tungsten). Annealing is then performed. In one embodiment, the annealing is performed for a time period in the range of 1 millisecond to 30 minutes. In one embodiment, the annealing is performed at a temperature in the range of 500-1100 degrees Celsius.

[0344] FIG. 31B A cross-sectional view of another semiconductor device having a ferroelectric or anti-ferroelectric gate dielectric structure is shown, in accordance with another embodiment of the disclosure.

[0345] Reference FIG. 31BThe integrated circuit structure 3150 includes a gate structure 3152 over a substrate 3154. In one embodiment, the gate structure 3152 is over or on a semiconductor channel structure 3156 that includes a single crystalline material such as single crystalline silicon. The gate structure 3152 includes a gate dielectric over the semiconductor channel structure 3156 and a gate electrode over the gate dielectric structure. The gate dielectric includes a ferroelectric or anti-ferroelectric polycrystalline material layer 3152A and can also include an amorphous oxide layer 3153. The gate electrode has a conductive layer 3152B that is on the ferroelectric or anti-ferroelectric polycrystalline material layer 3152A. The conductive layer 3152B includes a metal and can be a barrier layer or a work function layer. One or more gate fill layers 3152C are on or over the conductive layer 3152B. Raised source regions 3158 and raised drain regions 3160 (e.g., regions of a semiconductor material that are different from the semiconductor channel structure 3156) are on opposite sides of the gate structure 3152. Source or drain contacts 3162 are electrically connected to the source regions 3158 and the drain regions 3160 at locations 3199 and are spaced apart from the gate structure 3152 by one or both of an interlayer dielectric layer 3164 or a gate dielectric spacer 3166. In embodiments, the source or drain contacts 3162 include a barrier layer 3162A and a conductive trench fill material 3162B. In one embodiment, the ferroelectric or anti-ferroelectric polycrystalline material layer 3152A extends along the dielectric spacer 3166 as shown. FIG. 31B

[0346] FIG. 32A A plan view of a plurality of gate lines over a semiconductor fin pair is shown in accordance with another embodiment of the disclosure.

[0347] Referring to FIG. 32A , a plurality of active gate lines 3204 are formed over a plurality of semiconductor fins 3200. Dummy gate lines 3206 are at ends of the plurality of semiconductor fins 3200. Spacing 3208 between the gate lines 3204 / 3206 is a location where a trench contact can be positioned to provide a conductive contact to a source or drain region (e.g., source or drain regions 3251, 3252, 3253, and 3254). In embodiments, the pattern of the plurality of gate lines 3204 / 3206 or the pattern of the plurality of semiconductor fins 3200 is described as a grid structure. In one embodiment, the grid-like pattern includes a plurality of gate lines 3204 / 3206, or a pattern of the plurality of semiconductor fins 3200, or both, that are spaced apart at a constant pitch and have a constant width.

[0348] FIG. 32B A cross-sectional view taken along the a-a' axis of FIG. 32A is shown in accordance with an embodiment of the disclosure.

[0349] Referring to​FIG. 32B A plurality of active gate lines 3264 are formed over a semiconductor fin 3262 formed over a substrate 3260. Dummy gate lines 3266 are at ends of the semiconductor fin 3262. A dielectric layer 3270 is outside of the dummy gate lines 3266. Trench contact material 3297 is between the active gate lines 3264 and between the dummy gate lines 3266 and the active gate lines 3264. An embedded source or drain structure 3268 is in the semiconductor fin 3262 between the active gate lines 3264 and between the dummy gate lines 3266 and the active gate lines 3264.

[0350] The active gate lines 3264 include a gate dielectric structure 3272, a work function gate electrode portion 3274, and a fill gate electrode portion 3276, and a dielectric cap layer 3278. A dielectric spacer 3280 lines sidewalls of the active gate lines 3264 and the dummy gate lines 3266. In an embodiment, the gate dielectric structure 3272 includes a ferroelectric or anti-ferroelectric polycrystalline material layer 3298. In one embodiment, the gate dielectric structure 3272 also includes an amorphous oxide layer 3299.

[0351] In another aspect, devices of the same conductivity type (e.g., N-type or P-type) can have differentiated gate electrode stacks for the same conductivity type. However, for purposes of comparison, devices of the same conductivity type can have differentiated voltage thresholds (VT) based on modulated doping.

[0352] FIG. 33A Cross-sectional views of pairs of NMOS devices and pairs of PMOS devices are shown, with the pairs of NMOS devices having differentiated voltage thresholds based on modulated doping, and the pairs of PMOS devices having differentiated voltage thresholds based on modulated doping, in accordance with embodiments of the present disclosure.

[0353] Reference FIG. 33AThe first NMOS device 3302 is adjacent to the second NMOS device 3304 over the semiconductor active region 3300 (e.g., over a silicon fin or substrate). Both the first NMOS device 3302 and the second NMOS device 3304 include a gate dielectric layer 3306, a first gate electrode conductive layer 3308 (e.g., a work function layer), and a gate electrode conductive fill 3310. In embodiments, the first gate electrode conductive layer 3308 of the first NMOS device 3302 and the second NMOS device 3304 have the same material and the same thickness, thereby having the same work function. However, the first NMOS device 3302 has a lower VT than the second NMOS device 3304. In one such embodiment, the first NMOS device 3302 is referred to as a “standard VT” device, and the second NMOS device 3304 is referred to as a “high VT” device. In embodiments, the differential VT is achieved by using modulated doping or differential implant doping at regions 3312 of the first NMOS device 3302 and the second NMOS device 3304.

[0354] Referring again to FIG. 33A The first PMOS device 3322 is adjacent to the second PMOS device 3324 over the semiconductor active region 3320 (e.g., over a silicon fin or substrate). Both the first PMOS device 3322 and the second PMOS device 3324 include a gate dielectric layer 3326, a first gate electrode conductive layer 3328 (e.g., a work function layer), and a gate electrode conductive fill 3330. In embodiments, the first gate electrode conductive layer 3328 of the first PMOS device 3322 and the second PMOS device 3324 have the same material and the same thickness, thereby having the same work function. However, the first PMOS device 3322 has a higher VT than the second PMOS device 3324. In one such embodiment, the first PMOS device 3322 is referred to as a “standard VT” device, and the second PMOS device 3324 is referred to as a “low VT” device. In embodiments, the differential VT is achieved by using modulated doping or differential implant doping at regions 3332 of the first PMOS device 3322 and the second PMOS device 3324.

[0355] In contrast to FIG. 33A FIG. 33B A cross-sectional view of a pair of NMOS devices having differential voltage thresholds based on differential gate electrode structures and a pair of PMOS devices having differential voltage thresholds based on differential gate electrode structures is shown, in accordance with another embodiment of the disclosure.

[0356] Referring to FIG. 33B ​The first NMOS device 3352 is adjacent to the second NMOS device 3354 above the semiconductor active region 3350 (e.g., above a silicon fin or substrate). Both the first NMOS device 3352 and the second NMOS device 3354 include a gate dielectric layer 3356. However, the first NMOS device 3352 and the second NMOS device 3354 have structurally different gate electrode stacks. Specifically, the first NMOS device 3322 includes a first gate electrode conductive layer 3358 such as a first work function layer, and a gate electrode conductive fill 3360. The second NMOS device 3354 includes a second gate electrode conductive layer 3359 such as a second work function layer, the first gate electrode conductive layer 3358, and the gate electrode conductive fill 3360. The first NMOS device 3352 has a lower VT than the second NMOS device 3354. In one such embodiment, the first NMOS device 3352 is referred to as a "standard VT" device, and the second NMOS device 3354 is referred to as a "high VT" device. In embodiments, differential VT is achieved by using differential gate stacks for the same conductivity type devices.

[0357] Referring again to FIG. 33B The first PMOS device 3372 is adjacent to the second PMOS device 3374 above the semiconductor active region 3370 (e.g., above a silicon fin or substrate). Both the first PMOS device 3372 and the second PMOS device 3374 include a gate dielectric layer 3376. However, the first PMOS device 3372 and the second PMOS device 3374 have structurally different gate electrode stacks. Specifically, the first PMOS device 3372 includes a gate electrode conductive layer 3378A (e.g., a work function layer) having a first thickness, and a gate electrode conductive fill 3380. The second PMOS device 3374 includes a gate electrode conductive layer 3378B having a second thickness, and the gate electrode conductive fill 3380. In one embodiment, the gate electrode conductive layer 3378A and the gate electrode conductive layer 3378B have the same composition, but the gate electrode conductive layer 3378B has a thickness (second thickness) that is greater than the thickness (first thickness) of the gate electrode conductive layer 3378A. The first PMOS device 3372 has a higher VT than the second PMOS device 3374. In one such embodiment, the first PMOS device 3372 is referred to as a "standard VT" device, and the second PMOS device 3374 is referred to as a "low VT" device. In embodiments, differential VT is achieved by using differential gate stacks for the same conductivity type devices.

[0358] Referring again to FIG. 33BAccording to embodiments of the present disclosure, an integrated circuit structure includes a fin (e.g., a silicon fin, such as 3350). It will be appreciated that the fin has a top (as shown) and sidewalls (into and out of the page). A gate dielectric layer 3356 is over the top of the fin and laterally adjacent to the sidewalls of the fin. An N-type gate electrode of a device 3354 is over the gate dielectric layer 3356 over the top of the fin and laterally adjacent to the sidewalls of the fin. The N-type gate electrode includes a P-type metal layer 3359 over the gate dielectric layer 3356 and an N-type metal layer 3358 over the P-type metal layer 3359. It will be appreciated that a first N-type source or drain region can be adjacent to a first side of the gate electrode (e.g., into the page) and a second N-type source or drain region can be adjacent to a second side of the gate electrode (e.g., out of the page), the second side opposite the first side.

[0359] In one embodiment, the P-type metal layer 3359 includes titanium and nitrogen, and the N-type metal layer 3358 includes titanium, aluminum, carbon, and nitrogen. In one embodiment, the P-type metal layer 3359 has a thickness within a range of 2-12 Angstroms, and in a particular embodiment, the P-type metal layer 3359 has a thickness within a range of 2-4 Angstroms. In one embodiment, the N-type gate electrode further includes a conductive fill metal layer 3360 over the N-type metal layer 3358. In one such embodiment, the conductive fill metal layer 3360 includes tungsten. In a particular embodiment, the conductive fill metal layer 3360 includes 95 or greater atomic percent tungsten and 0.1 to 2 atomic percent fluorine.

[0360] Referring again to FIG. 33B According to another embodiment of the present disclosure, an integrated circuit structure includes a first N-type device 3352 having a voltage threshold (VT), the first N-type device 3352 having a first gate dielectric layer 3356, and a first N-type metal layer 3358 over the first gate dielectric layer 3356. Also included is a second N-type device 3354 having a voltage threshold (VT), the second N-type device 3354 having a second gate dielectric layer 3356, a P-type metal layer 3359 over the second gate dielectric layer 3356, and a second N-type metal layer 3358 over the P-type metal layer 3359.

[0361] In one embodiment, the VT of the second N-type device 3354 is higher than the VT of the first N-type device 3352. In one embodiment, the first N-type metal layer 3358 and the second N-type metal layer 3358 have the same composition. In one embodiment, the first N-type metal layer 3358 and the second N-type metal layer 3358 have the same thickness. In one embodiment, the N-type metal layer 3358 includes titanium, aluminum, carbon, and nitrogen, and the P-type metal layer 3359 includes titanium and nitrogen.

[0362] Referring again to FIG. 33B , according to another embodiment of the disclosure, an integrated circuit structure includes a first P-type device 3372 having a voltage threshold (VT), the first P-type device 3372 having a first gate dielectric layer 3376, and a first P-type metal layer 3378A on the first gate dielectric layer 3376. The first P-type metal layer 3378A has a thickness. A second P-type device 3378 is also included and has a voltage threshold (VT). The second P-type device 3374 has a second gate dielectric layer 3376 and a second P-type metal layer 3378B on the second gate dielectric layer 3376. The second P-type metal layer 3378B has a thickness that is greater than the thickness of the first P-type metal layer 3378A.

[0363] In one embodiment, the VT of the second P-type device 3374 is lower than the VT of the first P-type device 3372. In one embodiment, the first P-type metal layer 3378A and the second P-type metal layer 3378B have the same composition. In one embodiment, the first P-type metal layer 3378A and the second P-type metal layer 3378B both include titanium and nitrogen. In one embodiment, the thickness of the first P-type metal layer 3378A is less than a work function saturation thickness of the material of the first P-type metal layer 3378A. In one embodiment, although not shown, the second P-type metal layer 3378B includes a first metal film (e.g., from a second deposition) on a second metal film (e.g., from a first deposition), and a seam between the first metal film and the second metal film.

[0364] Referring again to FIG. 33B , according to another embodiment of the disclosure, an integrated circuit structure includes a first N-type device 3352 having a first gate dielectric layer 3356, and a first N-type metal layer 3358 on the first gate dielectric layer 3356. A second N-type device 3354 has a second gate dielectric layer 3356, a first P-type metal layer 3359 on the second gate dielectric layer 3356, and a second N-type metal layer 3358 on the first P-type metal layer 3359. A first P-type device 3372 has a third gate dielectric layer 3376 and a second P-type metal layer 3378A on the third gate dielectric layer 3376. The second P-type metal layer 3378A has a thickness. A second P-type device 3374 has a fourth gate dielectric layer 3376 and a third P-type metal layer 3378B on the fourth gate dielectric layer 3376. The third P-type metal layer 3378B has a thickness that is greater than the thickness of the second P-type metal layer 3378A.

[0365] In one embodiment, the first N-type device 3352 has a voltage threshold (VT), the second N-type device 3354 has a voltage threshold (VT), and the VT of the second N-type device 3354 is lower than the VT of the first N-type device 3352. In one embodiment, the first P-type device 3372 has a voltage threshold (VT), the second P-type device 3374 has a voltage threshold (VT), and the VT of the second P-type device 3374 is lower than the VT of the first P-type device 3372. In one embodiment, the third P-type metal layer 3378B includes a first metal film on a second metal film, and a seam between the first metal film and the second metal film.

[0366] It should be recognized that more than two types of VT devices for the same conductivity type can be included in the same structure (e.g., on the same die). In a first example, FIG. 34A A cross-sectional view of three NMOS devices and three PMOS devices is shown, the three NMOS devices having differentialized voltage thresholds based on differentialized gate electrode structures and modulated doping, the three PMOS devices having differentialized voltage thresholds based on differentialized gate electrode structures and modulated doping, in accordance with an embodiment of the present disclosure.

[0367] Reference is made to FIG. 34AThe first NMOS device 3402 is adjacent to a second NMOS device 3404 and a third NMOS device 3403 over a semiconductor active region 3400 (e.g., over a silicon fin or substrate). The first NMOS device 3402, the second NMOS device 3404, and the third NMOS device 3403 include a gate dielectric layer 3406. The first NMOS device 3402 and the third NMOS device 3403 have a gate electrode stack that is the same or similar in structure. However, the second NMOS device 3404 has a gate electrode stack that is different in structure from the first NMOS device 3402 and the third NMOS device 3403. Specifically, the first NMOS device 3402 and the third NMOS device 3403 include a first gate electrode conductive layer 3408 (e.g., a first work function layer) and a gate electrode conductive fill 3410. The second NMOS device 3404 includes a second gate electrode conductive layer 3409 (e.g., a second work function layer), the first gate electrode conductive layer 3408, and the gate electrode conductive fill 3410. The first NMOS device 3402 has a lower VT than the second NMOS device 3404. In one such embodiment, the first NMOS device 3402 is referred to as a "standard VT" device and the second NMOS device 3404 is referred to as a "high VT" device. In embodiments, differential VT is achieved by using differential gate stacks for the same conductivity type devices. In embodiments, the third NMOS device 3403 has a different VT than the VT of the first NMOS device 3402 and the second NMOS device 3404, even though the gate electrode structure of the third NMOS device 3403 is the same as the gate electrode structure of the first NMOS device 3402. In one embodiment, the VT of the third NMOS device is between the VT of the first NMOS device 3402 and the VT of the second NMOS device 3404. In embodiments, the differential VT between the third NMOS device 3403 and the first NMOS device 3402 is achieved by using a modulated doping or differential implant doping at a region 3412 of the third NMOS device 3403. In one such embodiment, the third N-type device 3403 has a channel region with a different dopant concentration than the dopant concentration of the channel region of the first N-type device 3402.

[0368] Referring again to FIG. 34AThe first PMOS device 3422 is adjacent to a second PMOS device 3424 and a third PMOS device 3423 over a semiconductor active region 3420 (e.g., over a silicon fin or substrate). The first PMOS device 3422, the second PMOS device 3424, and the third PMOS device 3423 include a gate dielectric layer 3426. The first PMOS device 3422 and the third PMOS device 3423 have a structurally identical or similar gate electrode stack. However, the second PMOS device 3424 has a gate electrode stack that is structurally different from the first PMOS device 3422 and the third PMOS device 3423. Specifically, the first PMOS device 3422 and the third PMOS device 3423 include a gate electrode conductive layer 3408A (e.g., a work function layer) having a first thickness, and a gate electrode conductive fill 3430. The second PMOS device 3424 includes a gate electrode conductive layer 3428B having a second thickness, and the gate electrode conductive fill 3430. In one embodiment, the gate electrode conductive layer 3428A and the gate electrode conductive layer 3428B have the same composition, but the gate electrode conductive layer 3428B has a thickness (second thickness) that is greater than the thickness (first thickness) of the gate electrode conductive layer 3428A. In an embodiment, the first PMOS device 3422 has a higher VT than the second PMOS device 3424. In one such embodiment, the first PMOS device 3422 is referred to as a "standard VT" device, and the second PMOS device 3424 is referred to as a "low VT" device. In an embodiment, differential VT is achieved by using differential gate stacks for devices of the same conductivity type. In an embodiment, the third PMOS device 3423 has a different VT than the VT of the first PMOS device 3422 and the VT of the second PMOS device 3424, even though the gate electrode structure of the third PMOS device 3423 is the same as the gate electrode structure of the first PMOS device 3422. In one embodiment, the VT of the third PMOS device 3423 is between the VT of the first PMOS device 3422 and the VT of the second PMOS device 3424. In an embodiment, the differential VT between the third PMOS device 3423 and the first PMOS device 3422 is achieved by using a modulated doping or differential implant doping at a region 3432 of the third PMOS device 3423. In one such embodiment, the channel region of the third P-type device 3423 has a different dopant concentration than the dopant concentration of the channel region of the first P-type device 3422.

[0369] In a second example, FIG. 34BA cross-sectional view of three NMOS devices having differentiated voltage thresholds based on differentiated gate electrode structures and modulated doping and three PMOS devices having differentiated voltage thresholds based on differentiated gate electrode structures and modulated doping is shown in accordance with another embodiment of the present disclosure.

[0370] Referring to FIG. 34B A first NMOS device 3452 is adjacent to a second NMOS device 3454 and a third NMOS device 3453 over a semiconductor active region 3450 (e.g., a silicon fin or a substrate). The first NMOS device 3452, the second NMOS device 3454, and the third NMOS device 3453 include a gate dielectric layer 3456. The second NMOS device 3454 and the third NMOS device 3453 have a structurally identical or similar gate electrode stack. However, the first NMOS device 3452 has a gate electrode stack that is structurally different from the second NMOS device 3454 and the third NMOS device 3453. Specifically, the first NMOS device 3452 includes a first gate electrode conductive layer 3458 (e.g., a first work function layer) and a gate electrode conductive fill 3460. The second NMOS device 3454 and the third NMOS device 3453 include a second gate electrode conductive layer 3459 (e.g., a second work function layer), the first gate electrode conductive layer 3458, and the gate electrode conductive fill 3460. The first NMOS device 3452 has a lower VT than the second NMOS device 3454. In one such embodiment, the first NMOS device 3452 is referred to as a "standard VT" device and the second NMOS device 3454 is referred to as a "high VT" device. In an embodiment, differentiated VT is achieved by using differentiated gate stacks for the same conductivity type devices. In an embodiment, the third NMOS device 3453 has a different VT than the VT of the first NMOS device 3452 and the VT of the second NMOS device 3454, even though the gate electrode structure of the third NMOS device 3453 is the same as the gate electrode structure of the second NMOS device 3454. In one embodiment, the VT of the third NMOS device 3453 is between the VT of the first NMOS device 3452 and the VT of the second NMOS device 3454. In an embodiment, the differentiated VT between the third NMOS device 3453 and the second NMOS device 3454 is achieved by using modulated doping or differentiated implant doping at a region 3462 of the third NMOS device 3453. In one such embodiment, the third N-type device 3453 has a channel region with a different dopant concentration than the dopant concentration of the channel region of the second N-type device 3454.

[0371] Referring again toFIG. 34B A first PMOS device 3472 is adjacent to a second PMOS device 3474 and a third PMOS device 3473 over a semiconductor active region 3470 (e.g., over a silicon fin or substrate). The first PMOS device 3472, the second PMOS device 3474, and the third PMOS device 3473 include a gate dielectric layer 3476. The second PMOS device 3474 and the third PMOS device 3473 have a structurally identical or similar gate electrode stack. However, the first PMOS device 3472 has a gate electrode stack that is structurally different from the second PMOS device 3474 and the third PMOS device 3473. Specifically, the first PMOS device 3472 includes a gate electrode conductive layer 3478A (e.g., a work function layer) having a first thickness, and a gate electrode conductive fill 3480. The second PMOS device 3474 and the third PMOS device 3473 include a gate electrode conductive layer 3478B having a second thickness, and the gate electrode conductive fill 3480. In one embodiment, the gate electrode conductive layer 3478A and the gate electrode conductive layer 3478B have the same composition, but the gate electrode conductive layer 3478B has a thickness (second thickness) that is greater than the thickness (first thickness) of the gate electrode conductive layer 3478A. In an embodiment, the first PMOS device 3472 has a higher VT than the second PMOS device 3474. In one such embodiment, the first PMOS device 3472 is referred to as a “standard VT” device, and the second PMOS device 3474 is referred to as a “low VT” device. In an embodiment, differentialized VTs are achieved by using differentialized gate stacks for devices of the same conductivity type. In an embodiment, the third PMOS device 3473 has a different VT than the VT of the first PMOS device 3472 and the VT of the second PMOS device 3474, even though the gate electrode structure of the third PMOS device 3473 is the same as the gate electrode structure of the second PMOS device 3474. In one embodiment, the VT of the third PMOS device 3473 is between the VT of the first PMOS device 3472 and the VT of the second PMOS device 3474. In an embodiment, the differentialized VT between the third PMOS device 3473 and the first PMOS device 3472 is achieved by using a modulated doping or a differentialized implant doping at a region 3482 of the third PMOS device 3473. In one such embodiment, the channel region of the third P-type device 3473 has a different dopant concentration than the dopant concentration of the channel region of the second P-type device 3474.

[0372] FIGS. 35A-35D Cross-sectional views illustrating various operations in a method of fabricating an NMOS device having differentialized voltage thresholds based on differentialized gate electrode structures, in accordance with an embodiment of the present disclosure, are shown.

[0373] Referring to FIG. 35A wherein the "standard VT NMOS" region (STD VT NMOS) and the "high VT NMOS" region (HIGH VT NMOS) are shown as diverging on a common substrate, a method of fabricating an integrated circuit structure includes forming a gate dielectric layer 3506 over the first semiconductor fin 3502 and over the second semiconductor fin 3504 (e.g., over the first and second silicon fins). A P-type metal layer 3508 is formed on the gate dielectric layer 3506 over the first semiconductor fin 3502 and over the second semiconductor fin 3504.

[0374] Referring to FIG. 35B A portion of the P-type metal layer 3508 is removed from the gate dielectric layer 3506 over the first semiconductor fin 3502, but a portion 3509 of the P-type metal layer 3508 remains on the gate dielectric layer 3506 over the second semiconductor fin 3504.

[0375] Referring to FIG. 35C An N-type metal layer 3510 is formed on the gate dielectric layer 3506 over the first semiconductor fin 3502 and on the portion 3509 of the P-type metal layer on the gate dielectric layer 3506 over the second semiconductor fin 3504. In embodiments, subsequent processing includes forming a first N-type device having a voltage threshold (VT) over the first semiconductor fin 3502 and a second N-type device having a voltage threshold (VT) over the second semiconductor fin 3504, wherein the VT of the second N-type device is higher than the VT of the first N-type device.

[0376] Referring to FIG. 35D In embodiments, a conductive fill metal layer 3512 is formed on the N-type metal layer 3510. In one such embodiment, forming the conductive fill metal layer 3512 includes forming a tungsten-containing film using atomic layer deposition (ALD) with a tungsten hexafluoride (WF6) precursor.

[0377] FIGS. 36A-36D Cross-sectional views illustrating various operations in a method of fabricating a PMOS device having differentialized voltage thresholds based on differentialized gate electrode structures, in accordance with embodiments of the present disclosure, are shown.

[0378] Referring to FIG. 36Awherein "standard VT PMOS" region (STD VT PMOS) and "low VT PMOS" region (LOW VT PMOS) are shown as bifurcated on a common substrate, a method of fabricating an integrated circuit structure includes forming a gate dielectric layer 3606 over the first semiconductor fin 3602 and over the second semiconductor fin 3604 (e.g., over the first and second silicon fins). A first P-type metal layer 3608 is formed on the gate dielectric layer 3606 over the first semiconductor fin 3602 and over the second semiconductor fin 3604.

[0379] Referring to FIG. 36B A portion of the first P-type metal layer 3608 is removed from the gate dielectric layer 3606 over the first semiconductor fin 3602, but a portion 3609 of the first P-type metal layer 3608 remains on the gate dielectric layer 3606 over the second semiconductor fin 3604.

[0380] Referring to FIG. 36C A second P-type metal layer 3610 is formed on the gate dielectric layer 3606 over the first semiconductor fin 3602, and on the portion 3609 of the first P-type metal layer on the gate dielectric layer 3606 over the second semiconductor fin 3604. In an embodiment, subsequent processing includes forming a first P-type device having a voltage threshold (VT) over the first semiconductor fin 3602, and forming a second P-type device having a voltage threshold (VT) over the second semiconductor fin 3604, wherein the VT of the second P-type device is lower than the VT of the first P-type device.

[0381] In one embodiment, the first P-type metal layer 3608 and the second P-type metal layer 3610 have the same composition. In one embodiment, the first P-type metal layer 3608 and the second P-type metal layer 3610 have the same thickness. In one embodiment, the first P-type metal layer 3608 and the second P-type metal layer 3610 have the same thickness and the same composition. In one embodiment, a seam 3611 is between the first P-type metal layer 3608 and the second P-type metal layer 3610, as shown.

[0382] Referring to FIG. 36D In an embodiment, a conductive fill metal layer 3612 is formed over the P-type metal layer 3610. In one such embodiment, forming the conductive fill metal layer 3612 includes forming a tungsten-containing film using atomic layer deposition (ALD) with a tungsten hexafluoride (WF6) precursor. In one embodiment, prior to forming the conductive fill metal layer 3612, an N-type metal layer 3614 is formed on the P-type metal layer 3610, as shown. In one such embodiment, the N-type metal layer 3614 is an artifact of a dual metal gate replacement processing scheme.

[0383] In another aspect, metal gate structures for complementary metal-oxide-semiconductor (CMOS) semiconductor devices are described. In an example, FIG. 37 A cross-sectional view of an integrated circuit structure with a P / N junction is shown in accordance with an embodiment of the present disclosure.

[0384] Referring to FIG. 37 The integrated circuit structure 3700 includes a semiconductor substrate 3702 having an N-well region 3704 with a first semiconductor fin 3706 protruding therefrom and a P-well region 3708 with a second semiconductor fin 3710 protruding therefrom. The first semiconductor fin 3706 is spaced apart from the second semiconductor fin 3710. The N-well region 3704 and the P-well region 3708 are directly adjacent in the semiconductor substrate 3702. A trench isolation structure 3712 is on the semiconductor substrate 3702 outside of and between the first semiconductor fin 3706 and the second semiconductor fin 3710. The first 3706 and second 3710 semiconductor fins extend above the trench isolation structure 3712.

[0385] A gate dielectric layer 3714 is on the first 3706 and second 3710 semiconductor fins and on the trench isolation structure 3712. The gate dielectric layer 3714 is continuous between the first 3706 and second 3710 semiconductor fins. A conductive layer 3716 is on the gate dielectric layer 3714 over the first semiconductor fin 3706 but not on the gate dielectric layer 3714 over the second semiconductor fin 3710. In one embodiment, the conductive layer 3716 includes titanium, nitrogen, and oxygen. A p-type metal gate layer 3718 is on the conductive layer 3716 over the first semiconductor fin 3706 but not on the conductive layer 3716 over the second semiconductor fin 3710. The p-type metal gate layer 3718 is further on a portion of but not all of the trench isolation structure 3712 between the first semiconductor fin 3706 and the second semiconductor fin 3710. An n-type metal gate layer 3720 is on the second semiconductor fin 3710, on the trench isolation structure 3712 between the first semiconductor fin 3706 and the second semiconductor fin 3710, and on the p-type metal gate layer 3718.

[0386] In one embodiment, an interlayer dielectric (ILD) layer 3722 is over the trench isolation structure 3712 outside the first semiconductor fin 3706 and the second semiconductor fin 3710. The ILD layer 3722 has an opening 3724 that exposes the first 3706 and second 3710 semiconductor fins. In one such embodiment, a conductive layer 3716, a p-type metal gate layer 3718, and an n-type metal gate layer 3720 are further formed along sidewalls 3726 of the opening 3724, as shown. In a particular embodiment, the conductive layer 3716 has a top surface 3717 that is below a top surface 3719 of the p-type metal gate layer 3718 along the sidewalls 3726 of the opening 3724 and below a top surface 3721 of the n-type metal gate layer 3720 along the sidewalls 3726 of the opening 3724, as shown.

[0387] In one embodiment, the p-type metal gate layer 3718 includes titanium and nitrogen. In one embodiment, the n-type metal gate layer 3720 includes titanium and aluminum. In one embodiment, a conductive fill metal layer 3730 is over the n-type metal layer 3720, as shown. In one such embodiment, the conductive fill metal layer 3730 includes tungsten. In a particular embodiment, the conductive fill metal layer 3730 includes 95 or greater atomic percent tungsten and 0.1 to 2 atomic percent fluorine. In one embodiment, the gate dielectric layer 3714 has a layer that includes hafnium and oxygen. In one embodiment, a thermal or chemical oxide layer 3732 is between upper portions of the first 3706 and second 3710 semiconductor fins, as shown. In one embodiment, the semiconductor substrate 3702 is a bulk silicon semiconductor substrate.

[0388] Now referring to only FIG. 37 the right side of FIG. 1, in accordance with embodiments of the present disclosure, an integrated circuit structure includes a semiconductor substrate 3702 that includes an N-well region 3704 having a semiconductor fin 3706 protruding therefrom. A trench isolation structure 3712 is on the semiconductor substrate 3702 around the semiconductor fin 3706. The semiconductor fin 3706 extends over the trench isolation structure 3712. A gate dielectric layer 3714 is over the semiconductor fin 3706. A conductive layer 3716 is over the gate dielectric layer 3714 over the semiconductor fin 3706. In one embodiment, the conductive layer 3716 includes titanium, nitrogen, and oxygen. A p-type metal gate layer 3718 is over the conductive layer 3716 over the semiconductor fin 3706.

[0389] In one embodiment, an interlayer dielectric (ILD) layer 3722 is above the trench isolation structure 3712. The ILD layer has an opening that exposes the semiconductor fin 3706. A conductive layer 3716 and a P-type metal gate layer 3718 are further formed along the sidewalls of the opening. In one such embodiment, the conductive layer 3716 along the sidewalls of the opening has a top surface that is lower than a top surface of the P-type metal gate layer 3718 along the sidewalls of the opening. In one embodiment, the P-type metal gate layer 3718 is above the conductive layer 3716. In one embodiment, the P-type metal gate layer 3718 includes titanium and nitrogen. In one embodiment, a conductive fill metal layer 3730 is above the P-type metal gate layer 3718. In one such embodiment, the conductive fill metal layer 3730 includes tungsten. In a particular such embodiment, the conductive fill metal layer 3730 is composed of 95 or greater atomic percent tungsten and 0.1 to 2 atomic percent fluorine. In one embodiment, the gate dielectric layer 3714 includes a layer having hafnium and oxygen.

[0390] FIGS. 38A-38H Cross-sectional views illustrating various operations in a method of fabricating an integrated circuit structure using a dual metal gate replacement gate process flow, in accordance with an embodiment of the present disclosure, are shown.

[0391] Reference FIG. 38A which shows NMOS (N-type) and PMOS (P-type) regions, a method of fabricating an integrated circuit structure includes forming an interlayer dielectric (ILD) layer 3802 over first 3804 and second 3806 semiconductor fins over a substrate 3800. An opening 3808 is formed in the ILD layer 3802 that exposes the first 3804 and second 3806 semiconductor fins. In one embodiment, the opening 3808 is formed by removing a gate placeholder or dummy gate structure that was initially in place over the first 3804 and second 3806 semiconductor fins.

[0392] A gate dielectric layer 3810 is formed in the opening 3808 and over the first 3804 and second 3806 semiconductor fins and over a portion of a trench isolation structure 3812 between the first 3804 and second 3806 semiconductor fins. In one embodiment, the gate dielectric layer 3810 is formed over a thermal or chemical oxide layer 3811, such as a silicon oxide or silicon dioxide layer, formed on the first 3804 and second 3806 semiconductor fins, as shown. In another embodiment, the gate dielectric layer 3810 is formed directly on the first 3804 and second 3806 semiconductor fins.

[0393] A conductive layer 3814 is formed over the gate dielectric layer 3810 formed over the first 3804 and second 3806 semiconductor fins. In one embodiment, the conductive layer 3814 includes titanium, nitrogen, and oxygen. A p-type metal gate layer 3816 is formed over the conductive layer 3814 formed over the first semiconductor fin 3804 and over the second semiconductor fin 3806.

[0394] Referring to FIG. 38B , a dielectric etch stop layer 3818 is formed over the p-type metal gate layer 3816. In one embodiment, the dielectric etch stop layer 3818 includes a first silicon oxide (e.g., S1O2) layer, an aluminum oxide layer (e.g., AI2O3) over the first silicon oxide layer, and a second silicon oxide (e.g., S1O2) layer over the aluminum oxide layer.

[0395] Referring to FIG. 38C , a mask 3820 is formed over FIG. 38B structure. The mask 3820 covers the PMOS region and exposes the NMOS region.

[0396] Referring to FIG. 38D , the dielectric etch stop layer 3818, the p-type metal gate layer 3816, and the conductive layer 3814 are patterned to provide a patterned dielectric etch stop layer 3819, a patterned p-type metal gate layer 3817 over the patterned conductive layer 3815 over the first semiconductor fin 3804 but not over the second semiconductor fin 3806. In an embodiment, the conductive layer 3814 protects the second semiconductor fin 3806 during the patterning.

[0397] Referring to FIG. 38E , the mask 3820 is removed from FIG. 38D structure. Referring to FIG. 38F , the patterned dielectric etch stop layer 3819 is removed from FIG. 38E structure.

[0398] Referring to FIG. 38Gn-type metal gate layer 3822 is formed over the second semiconductor fin 3806, over portions of the trench isolation structure 3812 between the first semiconductor fin 3804 and the second semiconductor fin 3806, and over the patterned p-type metal gate layer 3817. In an embodiment, the patterned conductive layer 3815, the patterned p-type metal gate layer 3817, and the n-type metal gate layer 3822 are further formed along the sidewalls 3824 of the opening 3808. In one such embodiment, the patterned conductive layer 3815 has a top surface that is below a top surface of the patterned p-type metal gate layer 3817 along the sidewalls 3824 of the opening 3808, and that is below a top surface of the n-type metal gate layer 3822 along the sidewalls 3824 of the opening 3808.

[0399] Referring to FIG. 38H A conductive fill metal layer 3826 is formed over the n-type metal layer 3822. In one embodiment, the conductive fill metal layer 3826 is formed by depositing a tungsten-containing film with a tungsten hexafluoride (WF6) precursor using atomic layer deposition (ALD).

[0400] In another aspect, a dual silicide structure for a complementary metal-oxide-semiconductor (CMOS) semiconductor device is described. As an example process flow, FIGS. 39A-39H Cross-sectional views representing various operations in a method of fabricating a dual silicide-based integrated circuit according to embodiments of the present disclosure are shown.

[0401] Referring to FIG. 39A In which the NMOS and PMOS regions are shown as diverging on a common substrate, a method of fabricating an integrated circuit structure includes forming a first gate structure 3902, which can include a dielectric sidewall spacer 3903 over a first fin 3904, such as a first silicon fin. A second gate structure 3952, which can include a dielectric sidewall spacer 3953, is formed over a second fin 3954, such as a second silicon fin. An insulating material 3906 is formed adjacent to the first gate structure 3902 over the first fin 3904 and adjacent to the second gate structure 3952 over the second fin 3954. In one embodiment, the insulating material 3906 is a sacrificial material and is used as a mask during a dual silicide process.

[0402] Referring to FIG. 39BA first portion of the insulating material 3906 is removed from over the first fin 3904 but not from over the second fin 3954 to expose first 3908 and second 3910 source or drain regions of the first fin 3904 adjacent the first gate structure 3902. In an embodiment, the first 3908 and second 3910 source or drain regions are epitaxial regions formed within recessed portions of the first fin 3904, as shown. In one such embodiment, the first 3908 and second 3910 source or drain regions include silicon and germanium.

[0403] Referring to FIG. 39C , a first metal silicide layer 3912 is formed on the first 3908 and second 3910 source or drain regions of the first fin 3904. In one embodiment, the first metal silicide layer 3912 is formed by depositing a layer including nickel and platinum on the structure of FIG. 39B , annealing the layer including nickel and platinum, and removing unreacted portions of the layer including nickel and platinum.

[0404] Referring to FIG. 39D , after the first metal silicide layer 3912 is formed, a second portion of the insulating material 3906 is removed from over the second fin 3954 to expose third 3958 and fourth 3960 source or drain regions of the second fin 3954 adjacent the second gate structure 3952. In an embodiment, the second 3958 and third 3960 source or drain regions are formed within the second fin 3954, e.g., within the second silicon fin, as shown. However, in another embodiment, the third 3958 and fourth 3960 source or drain regions are epitaxial regions formed within recessed portions of the second fin 3954. In one such embodiment, the third 3958 and fourth 3960 source or drain regions include silicon.

[0405] Referring to FIG. 39E , a first metal layer 3914 is formed on the structure of FIG. 39D , i.e., on the first 3908, second 3910, third 3958, and fourth 3960 source or drain regions. A second metal silicide layer 3962 is then formed on the third 3958 and fourth 3960 source or drain regions of the second fin 3954. For example, the second metal silicide layer 3962 is formed from the first metal layer 3914 using an annealing process. In an embodiment, the composition of the second metal silicide layer 3962 is different from the composition of the first metal silicide layer 3912. In one embodiment, the first metal layer 3914 is or includes a titanium layer. In one embodiment, the first metal layer 3914 is formed as a conformal metal layer, e.g., conformal with the open trench of FIG. 39D , as shown.

[0406] Referring to FIG. 39FIn an embodiment, the first metal layer 3914 is recessed to form a U-shaped metal layer 3916 over each of the first 3908, second 3910, third 3958, and fourth 3960 source or drain regions.

[0407] Referring to FIG. 39G In an embodiment, a second metal layer 3918 is formed over the U-shaped metal layer 3916 of the structure of FIG. 39F In an embodiment, the second metal layer 3918 is of a different composition than the U-shaped metal layer 3916.

[0408] Referring to FIG. 39H In an embodiment, a third metal layer 3920 is formed over the second metal layer 3918 of the structure of FIG. 39G In an embodiment, the third metal layer 3920 is of the same composition as the U-shaped metal layer 3916.

[0409] Referring again to FIG. 39H According to embodiments of the present disclosure, the integrated circuit structure 3900 includes a P-type semiconductor device (PMOS) over a substrate. The P-type semiconductor device includes a first fin 3904, e.g., a first silicon fin. It should be appreciated that the first fin has a top (shown as 3904A) and sidewalls (into and out of the page). A first gate electrode 3902 includes a first gate dielectric layer over the top 3904A of the first fin 3904 and laterally adjacent to the sidewalls of the first fin 3904, and includes a first gate electrode over the first gate dielectric layer over the top 3904A of the first fin 3904 and laterally adjacent to the sidewalls of the first fin 3904. The first gate electrode 3902 has a first side 3902A and a second side 3902B opposite the first side 3902A.

[0410] A first 3908 and a second 3910 semiconductor source or drain region are adjacent to the first 3902A and second 3902B sides of the first gate electrode 3902, respectively. A first 3930 and a second 3932 trench contact structure are over the first 3908 and second 3910 semiconductor source or drain regions adjacent to the first 3902A and second 3902B sides of the first gate electrode 3902, respectively. A first metal silicide layer 3912 is directly between the first 3930 and second 3932 trench contact structures and the first 3908 and second 3910 semiconductor source or drain regions, respectively.

[0411] The integrated circuit structure 3900 includes an N-type semiconductor device (NMOS) above a substrate. The N-type semiconductor device includes a second fin 3954, e.g., a second silicon fin. It should be appreciated that the second fin has a top (shown as 3954A) and sidewalls (into and out of the page). A second gate electrode 3952 includes a second gate dielectric layer over the top 3954A of the second fin 3954 and laterally adjacent the sidewalls of the second fin 3954, and includes a second gate electrode over the second gate dielectric layer over the top 3954A of the second fin 3954 and laterally adjacent the sidewalls of the second fin 3954. The second gate electrode 3952 has a first side 3952A and a second side 3952B opposite the first side 3952A.

[0412] A third 3958 and fourth 3960 semiconductor source or drain region is adjacent the first 3952A and second 3952B sides of the second gate electrode 3952, respectively. A third 3970 and fourth 3972 trench contact structure is over the third 3958 and fourth 3960 semiconductor source or drain region adjacent the first 3952A and second 3952B sides of the second gate electrode 3952, respectively. A second metal silicide layer 3962 is between the third 3970 and fourth 3972 trench contact structure and the third 3958 and fourth 3960 semiconductor source or drain region, respectively. In an embodiment, the first metal silicide layer 3912 includes at least one metal species not included in the second metal silicide layer 3962.

[0413] In one embodiment, the second metal silicide layer 3962 includes titanium and silicon. The first metal silicide layer 3912 includes nickel, platinum, and silicon. In one embodiment, the first metal silicide layer 3912 further includes germanium. In one embodiment, the first metal silicide layer 3912 further includes titanium, e.g., incorporated into the first metal silicide layer 3912 during a subsequent formation of the second metal silicide layer 3962 using the first metal layer 3914. In one such embodiment, the silicide layer already formed on the PMOS source or drain region is further modified by the anneal process used to form the silicide region on the NMOS source or drain region. This can result in the silicide layer on the PMOS source or drain region having a small percentage of all of the silicide metals. However, in other embodiments, such a silicide layer already formed on the PMOS source or drain region is not changed or substantially changed by the anneal process used to form the silicide region on the NMOS source or drain region.

[0414] In one embodiment, the first 3908 and second 3910 semiconductor source or drain regions are first and second embedded semiconductor source or drain regions comprising silicon and germanium. In one such embodiment, the third 3958 and fourth 3960 semiconductor source or drain regions are third and fourth embedded semiconductor source or drain regions comprising silicon. In another embodiment, the third 3958 and fourth 3960 semiconductor source or drain regions are formed in the fin 3954 and are not embedded epitaxial regions.

[0415] In embodiments, the first 3930, second 3932, third 3970, and fourth 3972 trench contact structures all comprise a U-shaped metal layer 3916 and a T-shaped metal layer 3918 on and over the U-shaped metal layer 3916. In one embodiment, the U-shaped metal layer 3916 comprises titanium and the T-shaped metal layer 3918 comprises cobalt. In one embodiment, the first 3930, second 3932, third 3970, and fourth 3972 trench contact structures all comprise a third metal layer 3920 on the T-shaped metal layer 3918. In one embodiment, the third metal layer 3920 and the U-shaped metal layer 3916 have the same composition. In particular embodiments, the third metal layer 3920 and the U-shaped metal layer comprise titanium and the T-shaped metal layer 3918 comprises cobalt.

[0416] In another aspect, trench contact structures, for example for source or drain regions, are described. In examples, FIG. 40A A cross-sectional view of an integrated circuit structure having a trench contact for an NMOS device is shown in accordance with an embodiment of the disclosure. FIG. 40B A cross-sectional view of an integrated circuit structure having a trench contact for a PMOS device is shown in accordance with another embodiment of the disclosure.

[0417] Reference is made to FIG. 40AThe integrated circuit structure 4000 includes a fin 4002, such as a silicon fin. A gate dielectric layer 4004 is over the fin 4002. A gate electrode 4006 is over the gate dielectric layer 4004. In an embodiment, the gate electrode 4006 includes a conformal conductive layer 4008 and a conductive fill 4010. In an embodiment, a dielectric cap 4012 is over the gate electrode 4006 and over the gate dielectric layer 4004. The gate electrode has a first side 4006A and a second side 4006B opposite the first side 4006A. Dielectric spacers 4013 are along sidewalls of the gate electrode 4006. In one embodiment, the gate dielectric layer 4004 is further between a first one of the dielectric spacers 4013 and the first side 4006A of the gate electrode 4006, and between a second one of the dielectric spacers 4013 and the second side 4006B of the gate electrode 4006, as shown. In an embodiment, although not shown, a thin oxide layer such as a thermal or chemical oxide silicon or silicon dioxide layer is between the fin 4002 and the gate dielectric layer 4004.

[0418] First 4014 and second 4016 semiconductor source or drain regions are adjacent the first 4006A and second 4006B sides of the gate electrode 4006, respectively. In one embodiment, the first 4014 and second 4016 semiconductor source or drain regions are in the fin 4002, as shown. However, in another embodiment, the first 4014 and second 4016 semiconductor source or drain regions are embedded epitaxial regions formed in recesses of the fin 4002.

[0419] First 4018 and second 4020 trench contact structures are over the first 4014 and second 4016 semiconductor source or drain regions adjacent the first 4006A and second 4006B sides of the gate electrode 4006, respectively. The first 4018 and second 4020 trench contact structures both include a U-shaped metal layer 4022 and a T-shaped metal layer 4024 over and on the U-shaped metal layer 4022. In one embodiment, the U-shaped metal layer 4022 and the T-shaped metal layer 4024 have different compositions. In one such embodiment, the U-shaped metal layer 4022 includes titanium and the T-shaped metal layer 4024 includes cobalt. In one embodiment, the first 4018 and second 4020 trench contact structures both include a third metal layer 4026 on the T-shaped metal layer 4024. In one such embodiment, the third metal layer 4026 and the U-shaped metal layer 4022 have the same composition. In a particular embodiment, the third metal layer 4026 and the U-shaped metal layer 4022 include titanium and the T-shaped metal layer 4024 includes cobalt.

[0420] The first trench contact via 4028 is electrically connected to the first trench contact 4018. In a particular embodiment, the first trench contact via 4028 is on and coupled with the third metal layer 4026 of the first trench contact 4018. The first trench contact via 4028 is further on and in contact with a portion of one of the dielectric spacers 4013, and on and in contact with a portion of the dielectric cap 4012. The second trench contact via 4030 is electrically connected to the second trench contact 4020. In a particular embodiment, the second trench contact via 4030 is on and coupled with the third metal layer 4026 of the second trench contact 4020. The second trench contact via 4030 is further on and in contact with a portion of another of the dielectric spacers 4013, and on and in contact with another portion of the dielectric cap 4012.

[0421] In an embodiment, a metal silicide layer 4032 is between the first 4018 and second 4020 trench contact structures and the first 4014 and second 4016 semiconductor source or drain regions, respectively. In one embodiment, the metal silicide layer 4032 includes titanium and silicon. In a particular such embodiment, the first 4014 and second 4016 semiconductor source or drain regions are first and second N-type semiconductor source or drain regions.

[0422] Referring to FIG. 40B The integrated circuit structure 4050 includes a fin 4052, such as a silicon fin. A gate dielectric layer 4054 is over the fin 4052. A gate electrode 4056 is over the gate dielectric layer 4054. In an embodiment, the gate electrode 4056 includes a conformal conductive layer 4058 and a conductive fill 4060. In an embodiment, a dielectric cap 4062 is over the gate electrode 4056 and over the gate dielectric layer 4054. The gate electrode has a first side 4056A and a second side 4056B opposite the first side 4056A. Dielectric spacers 4063 are along sidewalls of the gate electrode 4056. In one embodiment, the gate dielectric layer 4054 is further between a first one of the dielectric spacers 4063 and the first side 4056A of the gate electrode 4056, and between a second one of the dielectric spacers 4063 and the second side 4056B of the gate electrode 4056, as shown. In an embodiment, although not shown, a thin oxide layer such as a thermal or chemical silicon or silicon dioxide layer is between the fin 4052 and the gate dielectric layer 4054.

[0423] A first 4064 and a second 4066 semiconductor source or drain region are adjacent to a first 4056A and a second 4056B side of the gate electrode 4056, respectively. In one embodiment, the first 4064 and the second 4066 semiconductor source or drain region are embedded epitaxial regions formed in recesses 4065 and 4067 of the fin 4052, as shown. However, in another embodiment, the first 4064 and the second 4066 semiconductor source or drain region are in the fin 4052.

[0424] A first 4068 and a second 4070 trench contact structure are over the first 4064 and the second 4066 semiconductor source or drain region adjacent to a first 4056A and a second 4056B side of the gate electrode 4056, respectively. The first 4068 and the second 4070 trench contact structure both include a U-shaped metal layer 4072 and a T-shaped metal layer 4074 over and on the U-shaped metal layer 4072. In one embodiment, the U-shaped metal layer 4072 and the T-shaped metal layer 4074 have different compositions. In one such embodiment, the U-shaped metal layer 4072 includes titanium and the T-shaped metal layer 4074 includes cobalt. In one embodiment, the first 4068 and the second 4070 trench contact structure both further include a third metal layer 4076 on the T-shaped metal layer 4074. In one such embodiment, the third metal layer 4076 and the U-shaped metal layer 4072 have the same composition. In a particular embodiment, the third metal layer 4076 and the U-shaped metal layer 4072 include titanium and the T-shaped metal layer 4074 includes cobalt.

[0425] A first trench contact via 4078 is electrically connected to the first trench contact 4068. In a particular embodiment, the first trench contact via 4078 is on and coupled with the third metal layer 4076 of the first trench contact 4068. The first trench contact via 4078 is further on and in contact with a portion of one of the dielectric spacers 4063 and on and in contact with a portion of the dielectric cap 4062. A second trench contact via 4080 is electrically connected to the second trench contact 4070. In a particular embodiment, the second trench contact via 4080 is on and coupled with the third metal layer 4076 of the second trench contact 4070. The second trench contact via 4080 is further on and in contact with a portion of another of the dielectric spacers 4063 and on and in contact with another portion of the dielectric cap 4062.

[0426] In an embodiment, metal silicide layers 4082 are directly between first 4068 and second 4070 trench contact structures and first 4064 and second 4066 semiconductor source or drain regions, respectively. In one embodiment, metal silicide layers 4082 include nickel, platinum, and silicon. In a particular such embodiment, first 4064 and second 4066 semiconductor source or drain regions are first and second P-type semiconductor source or drain regions. In one embodiment, metal silicide layers 4082 also include germanium. In one embodiment, metal silicide layers 4082 also include titanium.

[0427] One or more embodiments described herein relate to using chemical vapor deposition for wrap-around semiconductor contacts. Embodiments can apply to or include one or more of chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), conductive contact fabrication, or thin films.

[0428] Particular embodiments can include using low temperature (e.g., below 500 degrees Celsius, or in the range of 400-500 degrees Celsius) chemical vapor deposition of contact metals, such as titanium or similar metals, to provide conformal source or drain contacts. Implementing such conformal source or drain contacts can improve three-dimensional (3D) transistor complementary metal-oxide-semiconductor (CMOS) performance.

[0429] To provide context, sputtering can be used to deposit metals to semiconductor contact layers. Sputtering is a line-of-sight process and can not be well suited for 3D transistor fabrication. Known sputtering schemes have poor or incomplete metal-semiconductor junctions on device contact surfaces, with an angle to the deposited incidence.

[0430] According to one or more embodiments of the present disclosure, low temperature chemical vapor deposition processes are implemented to fabricate contact metals to provide conformality in three-dimensions and maximize metal semiconductor junction contact area. The resulting greater contact area can reduce junction resistance. Embodiments can include deposition on semiconductor surfaces having non-planar topography, where topography of a region refers to the surface shape and features themselves, and non-planar topography includes uneven surface shape and features or portions of surface shape and features, i.e., not completely flat surface shape and features.

[0431] Embodiments described herein can include fabricating wrap-around contact structures. In one such embodiment, the use of pure metal conformally deposited onto a transistor source-drain contact by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or plasma-enhanced atomic layer deposition is described. Such conformal deposition can be used to increase the available area of a metal-semiconductor contact and reduce resistance, thereby improving the performance of a transistor device. In embodiments, the low temperature of the deposition results in minimized junction resistance per unit area.

[0432] It will be appreciated that various integrated circuit structures can be fabricated using integrated schemes involving metal layer deposition processes as described herein. According to embodiments of the present disclosure, a method of fabricating an integrated circuit structure includes providing a substrate having a feature thereon in a chemical vapor deposition (CVD) chamber having an RF source. The method also includes reacting titanium tetrachloride (TiCl4) and hydrogen (H2) to form a titanium (Ti) layer on the feature of the substrate.

[0433] In embodiments, the titanium layer has a total atomic composition including 98% or more titanium, and 0.5-2% chlorine. In alternative embodiments, high purity metal layers of zirconium (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb), or vanadium (V) are fabricated using similar processes. In embodiments, there is relatively little film thickness variation, for example, in embodiments, all coverages are greater than 50%, and the nominal value is 70% or greater (i.e., thickness variation is 30% or less). In embodiments, the thickness measured on silicon (Si) or silicon germanium (SiGe) is thicker than the thickness measured on other surfaces, as the Si or SiGe reacts during deposition and speeds up the uptake of Ti. In embodiments, the film composition includes approximately 0.5% Cl (or less than 1%) as an impurity, with substantially no other observed impurities. In embodiments, the deposition process enables the metal to cover on non-line-of-sight surfaces, for example, surfaces hidden from line-of-sight sputter deposition. Embodiments described herein can be implemented to improve transistor device drive by reducing the external resistance of current driven through the source and drain contacts.

[0434] According to embodiments of the present disclosure, the feature of the substrate is a source or drain contact trench exposing a semiconductor source or drain structure. The titanium layer (or other high purity metal layer) is a conductive contact layer for the semiconductor source or drain structure. Exemplary embodiments of such implementations are described below in connection with FIG. 41A 、 FIG. 41B 、 FIG. 42 、 FIGS. 43A-43C and FIG. 44 Exemplary embodiments of such implementations are described below in connection with

[0435] FIG. 41AA cross-sectional view of a semiconductor device having a conductive contact on a raised source or drain region is shown in accordance with an embodiment of the present disclosure.

[0436] Referring to FIG. 41A , the semiconductor structure 4100 includes a gate structure 4102 over a substrate 4104. The gate structure 4102 includes a gate dielectric layer 4102A, a work function layer 4102B, and a gate fill 4102C. A source region 4108 and a drain region 4110 are on opposite sides of the gate structure 4102. A source or drain contact 4112 is electrically connected to the source region 4108 and the drain region 4110 and is spaced apart from the gate structure 4102 by one or both of an interlayer dielectric 4114 or a gate dielectric spacer 4116. The source region 4108 and the drain region 4110 are regions of the substrate 4104.

[0437] In embodiments, the source or drain contact 4112 includes a high purity metal layer 4112A, e.g., as described above, and a conductive trench fill material 4112B. In one embodiment, the high purity metal layer 4112A has a total atomic composition that includes 98% or greater titanium. In one such embodiment, the total atomic composition of the high purity metal layer 4112A also includes 0.5-2% chlorine. In embodiments, the high purity metal layer 4112A has a thickness variation of 30% or less. In embodiments, the conductive trench fill material 4112B is composed of a conductive material such as, but not limited to, Cu, Al, W, or alloys thereof.

[0438] FIG. 41B A cross-sectional view of another semiconductor device having a conductive contact on a raised source or drain region is shown in accordance with an embodiment of the present disclosure.

[0439] Referring to FIG. 41B , the semiconductor structure 4150 includes a gate structure 4152 over a substrate 4154. The gate structure 4152 includes a gate dielectric layer 4152A, a work function layer 4152B, and a gate fill 4152C. A source region 4158 and a drain region 4160 are on opposite sides of the gate structure 4152. A source or drain contact 4162 is electrically connected to the source region 4158 and the drain region 4160 and is spaced apart from the gate structure 4152 by one or both of an interlayer dielectric layer 4164 or a gate dielectric spacer 4166. The source region 4158 and the drain region 4160 are epitaxial or embedded material regions formed in etched away regions of the substrate 4154. As shown, in embodiments, the source region 4158 and the drain region 4160 are raised source and drain regions. In a specific such embodiment, the raised source and drain regions are raised silicon source and drain regions or raised silicon germanium source and drain regions.

[0440] In embodiments, the source or drain contact 4162 includes a high purity metal layer 4162A, e.g., as described above, and a conductive trench fill material 4162B. In one embodiment, the high purity metal layer 4162A has a total atomic composition that includes 98% or more titanium. In one such embodiment, the total atomic composition of the high purity metal layer 4162A also includes 0.5-2% chlorine. In embodiments, the high purity metal layer 4162A has a thickness variation of 30% or less. In embodiments, the conductive trench fill material 4162B is composed of a conductive material such as, but not limited to, Cu, Al, W, or alloys thereof.

[0441] Accordingly, in embodiments, the unified reference FIG. 41A and FIG. 41B , the integrated circuit structure includes a feature having a surface (a source or drain contact trench that exposes a semiconductor source or drain structure). The high purity metal layer 4112A or 4162A is on the surface of the source or drain contact trench. It should be appreciated that the contact formation process can involve consuming the exposed silicon or germanium or silicon germanium material of the source or drain region. Such consumption can degrade device performance. In contrast, according to embodiments of the disclosure, the surface (4149 or 4199) of the semiconductor source (4108 or 4158) or drain (4110 or 4160) structure is not etched or consumed, or is not substantially etched or consumed, underneath the source or drain contact trench. In one such embodiment, the lack of consumption or etching is due to the low temperature deposition of the high purity metal contact layer.

[0442] FIG. 42 A plan view of a plurality of gate lines over a semiconductor fin is shown, according to embodiments of the disclosure.

[0443] Referring to FIG. 42 , a plurality of active gate lines 4204 are formed over a plurality of semiconductor fins 4200. Dummy gate lines 4206 are at the ends of the plurality of semiconductor fins 4200. The spacing 4208 between the gate lines 4204 / 4206 is where a trench contact can be formed as a conductive contact to a source or drain region, e.g., source or drain regions 4251, 4252, 4253, and 4254.

[0444] FIGS. 43A-43C A cross-sectional view taken along the a-a' axis of various operations in a method of fabricating an integrated circuit structure is shown, according to embodiments of the disclosure. FIG. 42

[0445] Referring to FIG. 43A ​Active gate lines 4304 are formed over semiconductor fins 4302 formed over substrate 4300. Dummy gate lines 4306 are at ends of semiconductor fins 4302. Dielectric layer 4310 is between active gate lines 4304, between dummy gate lines 4306 and active gate lines 4304, and outside of dummy gate lines 4306. Embedded source or drain structures 4308 are in semiconductor fins 4302 between active gate lines 4304 and between dummy gate lines 4306 and active gate lines 4304. Active gate lines 4304 include gate dielectric layer 4312, work function gate electrode portion 4314, and fill gate electrode portion 4316, and dielectric cap layer 4318. Dielectric spacers 4320 are lined along sidewalls of active gate lines 4304 and dummy gate lines 4306.

[0446] Referring to FIG. 43B , portions of dielectric layer 4310 between active gate lines 4304 and between dummy gate lines 4306 and active gate lines 4304 are removed to provide openings 4330 at locations where trench contacts are to be formed. Removing portions of dielectric layer 4310 between active gate lines 4304 and between dummy gate lines 4306 and active gate lines 4304 can result in etching embedded source or drain structures 4308 to provide etched embedded source or drain structures 4332 that can have an upper saddle profile, as shown in FIG. 43B .

[0447] Referring to FIG. 43C , trench contacts 4334 are formed in openings 4330 between active gate lines 4304 and between dummy gate lines 4306 and active gate lines 4304. Each of trench contacts 4334 can include a metal contact layer 4336 and a conductive fill material 4338.

[0448] FIG. 44 A cross-sectional view taken along the b-b' axis of an integrated circuit structure is shown in accordance with an embodiment of the present disclosure. FIG. 42

[0449] Referring to FIG. 44 , fin 4402 is shown over substrate 4404. A lower portion of fin 4402 is surrounded by trench isolation material 4404. An upper portion of fin 4402 has been removed to enable growth of embedded source and drain structures 4406. Trench contacts 4408 are formed in openings of dielectric layer 4410 that expose embedded source and drain structures 4406. Trench contacts include metal contact layer 4412 and conductive fill material 4414. It will be appreciated that, in accordance with an embodiment, metal contact layer 4412 extends to a top of trench contacts 4408, as shown in​FIG. 44 As shown in the diagram. However, in another embodiment, the metal contact layer 4412 does not extend to the top of the trench contact portion 4408, and there are some recesses within the trench contact portion 4408, for example, similar to... FIG. 43C The drawing shows the metal contact layer 4436 in the diagram.

[0450] Therefore, common reference FIG. 42 , FIGS. 43A-43C and FIG. 44 According to embodiments of this disclosure, the integrated circuit structure includes semiconductor fins (4200, 4302, 4402) above a substrate (4300, 4400). The semiconductor fins (4200, 4302, 4402) have a top and sidewalls. Gate electrodes (4204, 4304) are located above the top and adjacent to a portion of the sidewalls of the semiconductor fins (4200, 4302, 4402). The gate electrodes (4204, 4304) define a channel region within the semiconductor fins (4200, 4302, 4402). A first semiconductor source or drain structure (4251, 4332, 4406) is located at a first end of the channel region on a first side of the gate electrodes (4204, 4304), and the first semiconductor source or drain structure (4251, 4332, 4406) has a non-planar topography. The second semiconductor source or drain structure (4252, 4332, 4406) is located at the second end of the channel region on the second side of the gate electrode (4204, 4304), with the second end opposite to the first end and the second side opposite to the first side. The second semiconductor source or drain structure (4252, 4332, 4406) has a non-planar topography. The metal contact materials (4336, 4412) are directly on the first semiconductor source or drain structure (4251, 4332, 4406) and directly on the second semiconductor source or drain structure (4252, 4332, 4406). The metal contact materials (4336, 4412) conform to the non-planar topography of the first semiconductor source or drain structure (4251, 4332, 4406) and conform to the non-planar topography of the second semiconductor source or drain structure (4252, 4332, 4406).

[0451] In embodiments, the metallic contact material (4336, 4412) has a total atomic composition comprising 95% or more of a single metal species. In one such embodiment, the metallic contact material (4336, 4412) has a total atomic composition comprising 98% or more titanium. In a specific such embodiment, the total atomic composition of the metallic contact material (4336, 4412) further comprises 0.5-2% chlorine. In embodiments, the metallic contact material (4336, 4412) has a thickness variation of 30% or less along the non-planar topography of the first semiconductor source or drain structure (4251, 4332, 4406) and along the non-planar topography of the second semiconductor source or drain structure (4252, 4332, 4406).

[0452] In embodiments, the non-planar topography of the first semiconductor source or drain structure (4251, 4332, 4406) and the non-planar topography of the second semiconductor source or drain structure (4252, 4332, 4406) both comprise a raised center portion and a lower side portion, e.g., as shown in FIG. 44 In embodiments, the non-planar topography of the first semiconductor source or drain structure (4251, 4332, 4406) and the non-planar topography of the second semiconductor source or drain structure (4252, 4332, 4406) both comprise a saddle portion, e.g., as shown in FIG. 43C

[0453] In embodiments, the first semiconductor source or drain structure (4251, 4332, 4406) and the second semiconductor source or drain structure (4252, 4332, 4406) both comprise silicon. In embodiments, the first semiconductor source or drain structure (4251, 4332, 4406) and the second semiconductor source or drain structure (4252, 4332, 4406) both further comprise germanium, e.g., in the form of silicon germanium.

[0454] In embodiments, the metallic contact material (4336, 4412) directly on the first semiconductor source or drain structure (4251, 4332, 4406) further follows a sidewall of a trench in a dielectric layer (4320, 4410) over the first semiconductor source or drain structure (4251, 4332, 4406), the trench exposing a portion of the first semiconductor source or drain structure (4251, 4332, 4406). In one such embodiment, the thickness of the metallic contact material (4336) along the sidewall of the trench thins from the first semiconductor source or drain structure (4332 at 4336A) to a location (4336B) over the first semiconductor source or drain structure (4332), FIG. 43C ​An example is shown. In an embodiment, conductive filler material (4338, 4414) is applied to the metal contact material (4336, 4412) within the trench, as... FIG. 43C and FIG. 44 As shown.

[0455] In an embodiment, the integrated circuit structure further includes a second semiconductor fin having a top and sidewalls (e.g., FIG. 42 The upper fins are 4200, 4302, and 4402. Gate electrodes (4204, 4304) are also located on top of a portion of the second semiconductor fin and adjacent to the sidewall of that portion, defining a channel region in the second semiconductor fin. A third semiconductor source or drain structure (4253, 4332, 4406) is located at a first end of the channel region of the second semiconductor fin on the first side of the gate electrodes (4204, 4304), and this third semiconductor source or drain structure has a non-planar topography. A fourth semiconductor source or drain structure (4254, 4332, 4406) is located at a second end of the channel region of the second semiconductor fin on the second side of the gate electrodes (4204, 4304), the second end opposite to the first end, and the fourth semiconductor source or drain structure (4254, 4332, 4406) also has a non-planar topography. The metal contact materials (4336, 4412) are directly on the third semiconductor source or drain structure (4253, 4332, 4406) and directly on the fourth semiconductor source or drain structure (4254, 4332, 4406). The metal contact materials (4336, 4412) conform to the non-planar topography of the third semiconductor source or drain structure (4253, 4332, 4406) and conform to the non-planar topography of the fourth semiconductor source or drain structure (4254, 4332, 4406). In the embodiment, the metal contact materials (4336, 4412) are continuous between the first semiconductor source or drain structure (4251, 4332, left side 4406) and the third semiconductor source or drain structure (4253, 4332, right side 4406), and are continuous between the second semiconductor source or drain structure (4252) and the fourth semiconductor source or drain structure (4254).

[0456] On the other hand, a hard mask material can be used to preserve (prevent corrosion) and can be retained at locations where the conductive trench contact is interrupted above the dielectric material in the trench line position, such as at the contact plug position. For example, FIG. 45A and FIG. 45B Plan view and corresponding cross-sectional view of an integrated circuit structure including a trench contact plug having a hard mask material thereon, according to embodiments of the present disclosure, are shown respectively.

[0457] refer toFIG. 45A and FIG. 45B In an embodiment, integrated circuit structure 4500 includes fin 4502A, e.g., a silicon fin. A plurality of gate structures 4506 are over fin 4502A. Individual gate structures of gate structures 4506 are along a direction 4508 orthogonal to fin 4502A and have a pair of dielectric sidewall spacers 4510. Trench contact structure 4512 is over fin 4502A and directly between dielectric sidewall spacers 4510 of a first pair 4506A / 4506B of gate structures 4506. Contact plug 4514B is over fin 4502A and directly between dielectric sidewall spacers 4510 of a second pair 4506B / 4506C of gate structures 4506. Contact plug 4514B includes a lower dielectric material 4516 and an upper hardmask material 4518.

[0458] In an embodiment, lower dielectric material 4516 of contact plug 4516B includes silicon and oxygen, e.g., a silicon oxide or silicon dioxide material. Upper hardmask material 4518 of contact plug 4516B includes silicon and nitrogen, e.g., a silicon nitride, silicon-rich nitride, or silicon-poor nitride material.

[0459] In an embodiment, trench contact structure 4512 includes a lower conductive structure 4520 and a dielectric cap 4522 over lower conductive structure 4520. In one embodiment, dielectric cap 4522 of trench contact structure 4512 has an upper surface coplanar with an upper surface of upper hardmask material 4518 of contact plug 4514B, as shown.

[0460] In an embodiment, individual gate structures of the plurality of gate structures 4506 include a gate electrode 4524 over a gate dielectric layer 4526. A dielectric cap 4528 is over gate electrode 4524. In one embodiment, dielectric cap 4528 of individual gate structures of the plurality of gate structures 4506 has an upper surface coplanar with an upper surface of upper hardmask material 4518 of contact plug 4514B, as shown. In an embodiment, although not shown, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, is between fin 4502A and gate dielectric layer 4526.

[0461] Referring again to FIG. 45A and FIG. 45BIn an embodiment, integrated circuit structure 4500 includes a plurality of fins 4502, e.g., a plurality of silicon fins. Individual fins of the plurality of fins 4502 are along a first direction 4504. A plurality of gate structures 4506 is over the plurality of fins 4502. Individual gate structures of the plurality of gate structures 4506 are along a second direction 4508 that is orthogonal to the first direction 4504. Individual gate structures of the plurality of gate structures 4506 have a pair of dielectric sidewall spacers 4510. A trench contact structure 4512 is over a first fin 4502A of the plurality of fins 4502 and directly between the pair of dielectric sidewall spacers 4510 of a pair of gate structures 4506. A contact plug 4514A is over a second fin 4502B of the plurality of fins 4502 and directly between the pair of dielectric sidewall spacers 4510 of a pair of gate structures 4506. Similar to the cross-sectional view of contact plug 4514B, contact plug 4514A includes a lower dielectric material 4516 and an upper hardmask material 4518.

[0462] In an embodiment, the lower dielectric material 4516 of contact plug 4516A includes silicon and oxygen, e.g., a silicon oxide or silicon dioxide material. The upper hardmask material 4518 of contact plug 4516A includes silicon and nitrogen, e.g., a silicon nitride, silicon-rich nitride, or silicon-poor nitride material.

[0463] In an embodiment, the trench contact structure 4512 includes a lower conductive structure 4520 and a dielectric cap 4522 over the lower conductive structure 4520. In one embodiment, the dielectric cap 4522 of the trench contact structure 4512 has an upper surface that is coplanar with an upper surface of the upper hardmask material 4518 of contact plug 4514A or 4514B, as shown.

[0464] In an embodiment, individual gate structures of the plurality of gate structures 4506 include a gate electrode 4524 over a gate dielectric layer 4526. A dielectric cap 4528 is over the gate electrode 4524. In one embodiment, the dielectric cap 4528 of individual gate structures of the plurality of gate structures 4506 has an upper surface that is coplanar with an upper surface of the upper hardmask material 4518 of contact plug 4514A or 4514B, as shown. In an embodiment, although not shown, a thin oxide layer, such as a thermal or chemical silicon or silicon dioxide layer, is between fin 4502A and gate dielectric layer 4526.

[0465] One or more embodiments of the present disclosure relate to a gate-aligned contact process. Such a process can be implemented to form a contact structure for semiconductor structure fabrication (e.g., for integrated circuit fabrication). In embodiments, a contact pattern is formed in alignment with an existing gate pattern. In contrast, other approaches typically involve selective contact etching in combination with an additional lithography process that utilizes a lithographic contact pattern in strict registration with an existing gate pattern. For example, another process can include patterning of a multi-(gate) grid, where the contacts and contact plugs are separately patterned.

[0466] According to one or more embodiments described herein, a contact formation method involves forming a contact pattern that is substantially perfectly aligned to an existing gate pattern while eliminating the use of a lithography operation with an ultra-strict registration budget. In one such embodiment, this approach enables the use of a wet etch (e.g., relative to a dry or plasma etch) that is inherently highly selective to produce the contact openings. In embodiments, the contact pattern is formed by utilizing the existing gate pattern in combination with a contact plug lithography operation. In one such embodiment, this approach enables the elimination of the need for a lithography operation that would otherwise be critical to produce the contact pattern (as used in other approaches). In embodiments, the trench contact grid is not separately patterned, but is formed between the multi-(gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid patterning but before the gate grid cut.

[0467] FIGS. 46A-46D Cross-sectional views illustrating various operations in a method of manufacturing an integrated circuit structure including a trench contact plug having a hard mask material thereon are shown in accordance with embodiments of the present disclosure.

[0468] Reference FIG. 46A A method of manufacturing an integrated circuit structure includes forming a plurality of fins, individual fins 4602 of the plurality of fins being along a first direction 4604. Individual fins 4602 of the plurality of fins can include a diffusion region 4606. A plurality of gate structures 4608 is formed over the plurality of fins. Individual gate structures of the plurality of gate structures 4508 are along a second direction 4610 (e.g., direction 4610 in and out of the page) that is orthogonal to the first direction 4604. A sacrificial material structure 4612 is formed between a first pair of the gate structures 4608. A contact plug 4614 is between a second pair of the gate structures 4608. The contact plug includes a lower dielectric material 4616. A hard mask material 4618 is on the lower dielectric material 4616.

[0469] In embodiments, the gate structure 4608 includes a sacrificial or dummy gate stack and a dielectric spacer 4609. The sacrificial or dummy gate stack can be composed of polysilicon or silicon nitride pillars or some other sacrificial material that can be referred to as dummy gate material.

[0470] Referring FIG. 46B , the sacrificial material structure 4612 is removed from the structure of FIG. 46A to form an opening 4620 between the first pair in the gate structure 4608.

[0471] Referring FIG. 46C , a trench contact structure 4622 is formed in the opening 4620 between the first pair in the gate structure 4608. Further, in embodiments, as part of forming the trench contact structure 4622, the hard mask 4618 of FIG. 46A and FIG. 46B is planarized. The final completed contact plug 4614’ includes an upper hard mask material 4616 formed from the hard mask material 4618 and an upper hard mask material 4624.

[0472] In embodiments, the lower dielectric material 4616 of each of the contact plugs 4614’ includes silicon and oxygen and the upper hard mask material 4624 of each of the contact plugs 4614’ includes silicon and nitrogen. In embodiments, each of the trench contact structures 4622 includes a lower conductive structure 4626 and a dielectric cap 4628 on the lower conductive structure 4626. In one embodiment, the dielectric cap 4628 of the trench contact structure 4622 has an upper surface that is coplanar with an upper surface of the upper hard mask material 4624 of the contact plug 4614’.

[0473] Referring FIG. 46D , the sacrificial or dummy gate stack of the gate structure 4608 is replaced in an alternative gate process scheme. In such a scheme, the dummy gate material, e.g., polysilicon or silicon nitride pillar material, is removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, as opposed to being performed from an earlier process.

[0474] Thus, the permanent gate structure 4630 includes a permanent gate dielectric layer 4632 and a permanent gate electrode layer or stack 4634. Further, in embodiments, a top portion of the permanent gate structure 4630 is removed, e.g., by an etching process, and replaced with a dielectric cap 4636. In embodiments, the dielectric cap 4636 of individual permanent gate structures in the permanent gate structure 4630 has an upper surface that is coplanar with an upper surface of the upper hard mask material 4624 of the contact plug 4614’.

[0475] Referring againFIGS. 46A-46D In an embodiment, a replacement gate process is performed after forming the trench contact structure 4622, as shown. However, according to other embodiments, the replacement gate process is performed before forming the trench contact structure 4622.

[0476] In another aspect, contact over active gate (COAG) structures and processes are described. One or more embodiments of the present disclosure relate to a semiconductor structure or device having one or more gate contact structures (e.g., as gate contact vias) disposed over an active portion of a gate electrode of the semiconductor structure or device. One or more embodiments of the present disclosure relate to methods of fabricating a semiconductor structure or device having one or more gate contact structures formed over an active portion of a gate electrode of the semiconductor structure or device. The approaches described herein can be used to reduce standard cell area by enabling formation of gate contacts over active gate regions. In one or more embodiments, the gate contact structures fabricated to contact the gate electrode are self-aligned via structures.

[0477] In techniques that are somewhat relaxed in spatial and layout constraints compared to those of the current generation, contact to the gate structure can be made by forming contact to a portion of the gate electrode disposed over an isolation region. As an example, FIG. 47A A plan view of a semiconductor device having a gate contact disposed over a non-active portion of a gate electrode is shown.

[0478] Reference FIG. 47A The semiconductor structure or device 4700A includes a diffusion or active region 4704 disposed in a substrate 4702 and within an isolation region 4706. One or more gate lines (also referred to as multi-lines), such as gate lines 4708A, 4708B, and 4708C, are disposed over the diffusion or active region 4704 and over a portion of the isolation region 4706. Source or drain contacts (also referred to as trench contacts), such as contacts 4710A and 4710B, are disposed over source and drain regions of the semiconductor structure or device 4700A. Trench contact vias 4712A and 4712B provide contact to the trench contacts 4710A and 4710B, respectively. A separate gate contact 4714, and overlying gate contact via 4716, provide contact to the gate line 4708B. The gate contact 4714 is disposed over the isolation region 4706, but not over the diffusion or active region 4704, from a plan view perspective, as compared to the source or drain trench contacts 4710A or 4710B. Moreover, neither the gate contact 4714 nor the gate contact via 4716 are disposed between the source or drain trench contacts 4710A and 4710B.

[0479] FIG. 47B A cross-sectional view of a non-planar semiconductor device having a gate contact disposed over a non-active portion of a gate electrode is shown. Referring to FIG. 47B , a non-planar version of the device 4700A, the semiconductor structure or device 4700B (e.g. FIG. 47A ) includes a non-planar diffusion or active region 4704C (e.g., a fin structure) formed from a substrate 4702 and within an isolation region 4706. A gate line 4708B is disposed over the non-planar diffusion or active region 4704B as well as over a portion of the isolation region 4706. As shown, the gate line 4708B includes a gate electrode 4750 and a gate dielectric layer 4752, along with a dielectric cap layer 4754. Also visible from this perspective are a gate contact 4714 and an overlying gate contact via 4716, along with an overlying metal interconnect 4760, all of which are disposed in an interlevel dielectric stack or layer 4770. From FIG. 47B this perspective, it is also seen that the gate contact 4714 is disposed over the isolation region 4706, but not over the non-planar diffusion or active region 4704B.

[0480] Referring again to FIG. 47A and FIG. 47B , the arrangements of the semiconductor structures or devices 4700A and 4700B place the gate contact over the isolation region, respectively. Such arrangements waste layout space. However, placing the gate contact over the active region would require an extremely tight registration budget, or the gate size would have to be increased to provide a large enough space for the gate contact to land. Further, historically, gate contacts over diffusion regions have been avoided because of the risk of drilling through other gate materials (e.g., poly) and contacting the underlying active region. One or more embodiments described herein address the above problems by providing viable ways to fabricate a contact structure that makes contact with a portion of a gate electrode formed over a diffusion or active region, as well as the resulting structure.

[0481] As an example, FIG. 48A a plan view of a semiconductor device having a gate contact via disposed over an active portion of a gate electrode is shown, in accordance with an embodiment of the disclosure. Referring to FIG. 48AThe semiconductor structure or device 4800A includes a diffused or active region 4804 disposed in a substrate 4802 and within an isolation region 4806. One or more gate lines, such as gate lines 4808A, 4808B, and 4808C, are disposed over the diffused or active region 4804 and a portion of the isolation region 4806. Source or drain contacts, such as contacts 4810A and 4810B, are disposed over the source and drain regions of the semiconductor structure or device 4800A. Trench contact vias 4812A and 4812B provide contacts with trench contact vias 4810A and 4810B, respectively. A gate contact via 4816 without an intervening separate gate contact layer provides contact with gate line 4808B. FIG. 47A In contrast, from the perspective of the plan view, the gate contact 4816 is disposed above the diffusion region or active region 4804 and between the source or drain contacts 4810A and 4810B.

[0482] FIG. 48B A cross-sectional view of a non-planar semiconductor device having a gate contact via disposed on the active portion of the gate electrode, according to an embodiment of the present disclosure, is shown. (Refer to...) FIG. 48B Semiconductor structures or devices 4800B (e.g.) FIG. 48A The non-planar version of device 4800A includes a non-planar diffused or active region 4804B (e.g., a fin structure) formed from substrate 4802 and within isolation region 4806. Gate line 4808B is disposed over the non-planar diffused or active region 4804B and a portion of isolation region 4806. As shown, gate line 4808B includes a gate electrode 4850 and a gate dielectric layer 4852, together with a dielectric cap layer 4854. A gate contact via 4816, together with an overlay metal interconnect 4860, is also visible in this perspective view; both are disposed within an interlayer dielectric stack or layer 4870. FIG. 48B The perspective view also shows that the gate contact via 4816 is disposed above the non-planar diffusion or active region 4804B.

[0483] Therefore, refer to again FIG. 48A and FIG. 48B In this embodiment, trench contact vias 4812A and 4812B and gate contact via 4816 are formed in the same layer and are substantially coplanar. FIG. 47A Compared to Figure 47B, the contact portion leading to the gate line may, in other cases, include an additional gate contact layer, for example, which may extend perpendicularly to the corresponding gate line. However, in combination FIG. 48A and FIG. 48BThe structures described, fabrication of structures 4800A and 4800B respectively enable the contact to land directly from the metal interconnect layer on the active gate portion without shorting to the adjacent source drain regions. In embodiments, such an arrangement provides a large area reduction in circuit layout by eliminating the need to extend the transistor gate over the isolation region to form a reliable contact portion. As used throughout this document, in embodiments, reference to the active portion of the gate refers to that portion of the gate line or structure disposed over (from a plan view perspective) the active or diffusion region of the underlying substrate. In embodiments, reference to the inactive portion of the gate refers to that portion of the gate line or structure disposed over (from a plan view perspective) the isolation region of the underlying substrate.

[0484] In embodiments, semiconductor structure or device 4800 is a non-planar device, such as but not limited to a finFET or tri-gate device. In such embodiments, the corresponding semiconductor channel region is comprised of or formed in a three- dimensional body. In one such embodiment, the gate electrode stacks of gate lines 4808A-4808C surround at least the top surface and a pair of sidewalls of the three-dimensional body. In another embodiment, such as in a gate-all-around device, at least the channel region is fabricated as a discrete three-dimensional body. In one such embodiment, the gate electrode stacks of gate lines 4808A-4808C each completely surround the channel region.

[0485] More generally, one or more embodiments are directed to ways for directly landing a gate contact via on an active transistor gate and structures formed thereby. Such ways can eliminate the need to extend the gate line over the isolation region for contact purposes. Such ways can also eliminate the need for a separate gate contact (GCN) layer to conduct signals from the gate line or structure. In embodiments, the elimination of the above features is achieved by recessing the contact metal in the trench contact (TCN) and introducing additional dielectric material (e.g., TILA) in the process flow. The additional dielectric material is included as a trench contact dielectric cap layer having different etch characteristics than the gate dielectric material cap layer already used for trench contact alignment in the gate aligned contact process (GAP) handling scheme (e.g., GILA).

[0486] As an example manufacturing scheme, FIGS. 49A-49D Cross-sectional views illustrating various operations in a method of fabricating a semiconductor structure having a gate contact structure disposed over an active portion of a gate in accordance with embodiments of the present disclosure are shown.

[0487] Reference is made to FIG. 49AA semiconductor structure 4900 is provided after trench contact (TCN) formation. It should be appreciated that the particular arrangement of structure 4900 is merely for purposes of illustration and that various possible layouts can benefit from embodiments of the disclosure described herein. Semiconductor structure 4900 includes one or more gate stack structures, such as gate stack structures 4908A-4908E disposed above a substrate 4902. The gate stack structures can include a gate dielectric layer and a gate electrode. Trench contacts to diffusion regions of substrate 4902, such as trench contacts 4910A-4910C, are also included in structure 4900 and are spaced apart from gate stack structures 4908A-4908E by dielectric spacers 4920. Insulative cap layers 4922 can be disposed on gate stack structures 4908A-4908E (e.g., GILA), as also shown. FIG. 49A As also shown, contact barrier regions or "contact plugs" (e.g., regions 4923 fabricated from interlayer dielectric material) can be included in areas where contact formation is to be blocked. FIG. 49A

[0488] In embodiments, providing structure 4900 involves forming a contact pattern that is substantially perfectly aligned to an existing gate pattern while eliminating the use of photolithography operations with super-strict registration budgets. In one such embodiment, this approach enables the use of wet etching (e.g., as compared to dry or plasma etching) that is inherently highly selective to produce contact openings. In embodiments, the contact pattern is formed by leveraging the existing gate pattern in conjunction with a contact plug photolithography operation. In one such embodiment, this approach enables the elimination of the need for photolithography operations that would otherwise be critical to produce the contact pattern as used in other approaches. In embodiments, the trench contact grid is not separately patterned, but is formed between multiple (gate) lines. For example, in one such embodiment, the trench contact grid is formed after gate grid patterning but before gate grid cutting.

[0489] ​Further, the gate stack structures 4908A-4908E can be fabricated by a replacement gate process. In such an approach, dummy gate materials such as polysilicon or silicon nitride pillar material can be removed and replaced with permanent gate electrode material. In one such embodiment, the permanent gate dielectric layer is also formed in this process, as opposed to being performed from an earlier process. In embodiments, the dummy gate is removed by a dry etch or wet etch process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed using a dry etch process including SF6. In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed using a wet etch process including water-based NH4OH or tetraethylammonium hydroxide. In one embodiment, the dummy gate is composed of silicon nitride and is removed using a wet etch including water-based phosphoric acid.

[0490] In embodiments, one or more of the methods described herein contemplate the dummy gate and replacement gate process in combination with dummy and replacement contact processes to achieve structure 4900. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow for high temperature annealing of at least a portion of the permanent gate stack. For example, in a particular such embodiment, annealing of at least a portion of the permanent gate structure is performed at a temperature higher than approximately 600 degrees Celsius, e.g., after formation of the gate dielectric layer. The annealing is performed prior to formation of the permanent contact.

[0491] Reference is made to FIG. 49B , the trench contacts 4910A-4910C of structure 4900 are recessed into the spacer 4920 to provide recessed trench contacts 4911A-4911C having a height lower than the top surface of the spacer 4920 and the insulating cap layer 4922. The insulating cap layer 4924 is then formed on the recessed trench contacts 4911A-4911C (e.g., TILA). According to embodiments of the present disclosure, the insulating cap layer 4924 on the recessed trench contacts 4911A-4911C is composed of a material having different etch characteristics than the insulating cap layer 4922 on the gate stack structures 4908A-4908E. As will be seen in subsequent processing operations, such a difference can be utilized to selectively etch one of 4922 / 4924 relative to the other.

[0492] The trench contacts 4910A-4910C can be recessed by a process selective to the materials of the spacers 4920 and the insulative cap layer 4922. For example, in one embodiment, the trench contacts 4910A-4910C are recessed by an etching process such as a wet etching process or a dry etching process. The insulative cap layer 4924 can be formed by a process suitable to provide a conformal and sealing layer over the exposed portions of the trench contacts 4910A-4910C. For example, in one embodiment, the insulative cap layer 4924 is formed as a conformal layer over the entire structure by a chemical vapor deposition (CVD) process. The conformal layer is then planarized, for example by chemical mechanical polishing (CMP), to provide the insulative cap layer 4924 material only over the trench contacts 4910A-4910C and to re-expose the spacers 4920 and the insulative cap layer 4922.

[0493] As to suitable material combinations for the insulative cap layers 4922 / 4924, in one embodiment, one of the pair 4922 / 4924 is composed of silicon oxide and the other is composed of silicon nitride. In another embodiment, one of the pair 4922 / 4924 is composed of silicon oxide and the other is composed of carbon-doped silicon nitride. In another embodiment, one of the pair 4922 / 4924 is composed of silicon oxide and the other is composed of silicon carbide. In another embodiment, one of the pair 4922 / 4924 is composed of silicon nitride and the other is composed of carbon-doped silicon nitride. In another embodiment, one of the pair 4922 / 4924 is composed of silicon nitride and the other is composed of silicon carbide. In another embodiment, one of the pair 4922 / 4924 is composed of carbon-doped silicon nitride and the other is composed of silicon carbide.

[0494] Referring to FIG. 49C , an interlayer dielectric (ILD) 4930 and a hardmask 4932 stack is formed and patterned to provide, for example, metal (0) trenches 4934 patterned over the structure of FIG. 49B .

[0495] The interlayer dielectric (ILD) 4930 can be composed of a material suitable to electrically isolate metal features eventually formed therein while maintaining a robust structure between front-end and back-end processing. Further, in embodiments, the composition of the ILD 4930 is selected to be in line with a via etch selectivity to the trench contact dielectric cap layer patterning, as described below in connection with FIG. 49DIn more detail, in one embodiment, ILD 4930 is composed of a single or several layers of silicon oxide or a single or several layers of carbon-doped oxide (CDO) material. However, in other embodiments, ILD 4930 has a dual-layer composition, the top portion of which is composed of a different material than the bottom portion of the lower layer of ILD 4930. Hardmask layer 4932 can be composed of a material suitable to act as a subsequent sacrificial layer. For example, in one embodiment, hardmask layer 4932 is composed substantially of carbon, e.g., as a cross-linked organic polymer layer. In other embodiments, a layer of silicon nitride or carbon-doped silicon nitride is used as hardmask 4932. The interlayer dielectric (ILD) 4930 and hardmask 4932 stack can be patterned by photolithography and etching processes.

[0496] With reference to FIG. 49D , via openings 4936 (e.g., VCTs) are formed in interlayer dielectric (ILD) 4930, extending from metal (0) trench 4934 into one or more of recessed trench contacts 4911A-4911C. For example, in FIG. 49D , via openings are formed to expose recessed trench contacts 4911A and 4911C. Forming via openings 4936 includes etching both interlayer dielectric (ILD) 4930 and a corresponding portion of insulative cap layer 4924. In one such embodiment, a portion of insulative cap layer 4922 is exposed during patterning of interlayer dielectric (ILD) 493 (e.g., portions of insulative cap layer 4922 that are over gate stack structures 4908B and 4908E are exposed). In this embodiment, insulative cap layer 4924 is etched to form via openings 4936 with selectivity with respect to insulative cap layer 4922 (i.e., without significantly etching or affecting insulative cap layer 4922).

[0497] In one embodiment, the via opening pattern is ultimately transferred through an etching process to the insulating cap layer 4924 (i.e., the trench contact insulating cap layer) without etching the insulating cap layer 4922 (i.e., the gate insulating cap layer). The insulating cap layer 4924 (TILA) can be composed of any of the following materials or combinations thereof: silicon oxide, silicon nitride, silicon carbide, carbon-doped silicon nitride, carbon-doped silicon oxide, amorphous silicon, various metal oxides and silicides, including zirconium oxide, hafnium oxide, lanthanum oxide, or combinations thereof. The layer can be deposited using any of the following techniques: CVD, ALD, PECVD, PVD, HDP-assisted CVD, low-temperature CVD. The corresponding plasma dry etch is developed as a combination of chemical and physical sputtering mechanisms. Uniform polymer deposition can be used to control material removal rates, etch profiles, and film selectivity. The dry etch typically utilizes a mixture of gases including: NF3, CHF3, C4F8, HBr, and O2, with typical pressures in the range of 30-100 mTorr and plasma bias of 50-1000 Watts. The dry etch can be designed to achieve significant etch selectivity between the cap layers 4924 (TILA) and 4922 (GILA) to minimize the loss of 4922 (GILA) during the dry etch of 4929 (TILA) to form a contact to the source / drain region of the transistor.

[0498] Referring again to FIG. 49D it is to be appreciated that a similar approach can be implemented to fabricate a via opening pattern that is ultimately transferred through an etching process to the insulating cap layer 4922 (i.e., the trench contact insulating cap layer) without etching the insulating cap layer 4924 (i.e., the gate insulating cap layer).

[0499] To further illustrate the concept of a contact over active gate (COAG) technology, FIG. 50 plan views and corresponding cross-sectional views of an integrated circuit structure having a trench contact including an overlying insulating cap layer are shown in accordance with embodiments of the present disclosure.

[0500] Referring to FIG. 50 , the integrated circuit structure 5000 includes a gate line 5004 over a semiconductor substrate or fin 5002, such as a silicon fin. The gate line 5004 includes a gate stack 5005 (e.g., including a gate dielectric layer or stack and a gate electrode over the gate dielectric layer or stack) and a gate insulating cap layer 5006 over the gate stack 5005. Dielectric spacers 5008 are along sidewalls of the gate stack 5005, and in embodiments, along sidewalls of the gate insulating cap layer 5006, as shown.

[0501] Trench contact portions 5010 are adjacent to sidewalls of gate lines 5004 with a dielectric spacer 5008 between gate lines 5004 and trench contact portions 5010. Individual ones of trench contact portions 5010 include a conductive contact structure 5011 and a trench contact portion insulative cap layer 5012 over conductive contact structure 5011.

[0502] Referring again to FIG. 50 , gate contact vias 5014 are formed in openings of gate insulative cap layer 5006 and electrically contact gate stacks 5005. In embodiments, gate contact vias 5014 electrically contact gate stacks 5005 at locations over semiconductor substrate or fin 5002 and laterally between trench contact portions 5010, as shown. In one such embodiment, trench contact portion insulative cap layer 5012 over conductive contact structure 5011 prevents gate contact vias 5014 from shorting gate to source or from shorting gate to drain.

[0503] Referring again to FIG. 50 , trench contact vias 5016 are formed in openings of trench contact portion insulative cap layer 5012 and electrically contact respective conductive contact structures 5011. In embodiments, trench contact vias 5016 electrically contact respective conductive contact structures 5011 at locations over semiconductor substrate or fin 5002 and laterally adjacent to gate stacks 5005 of gate lines 5004, as shown. In one such embodiment, gate insulative cap layer 5006 over gate stacks 5005 prevents trench contact vias 5016 from shorting source to gate or from shorting drain to gate.

[0504] It should be appreciated that different structural relationships between insulative gate cap layers and insulative trench contact cap layers can be fabricated. As an example, FIGS. 51A-51F Cross-sectional views of various integrated circuit structures having trench contact portions including overlying insulative cap layers and having gate stacks including overlying insulative cap layers are shown, in accordance with embodiments of the present disclosure.

[0505] Referring to FIG. 51A , FIG. 51B and FIG. 51C, integrated circuit structures 5100A, 5100B, and 5100C include a fin 5102, such as a silicon fin. Although shown as a cross-sectional view, it is to be appreciated that the fin 5102 has a top 5102A and sidewalls (into and out of the page of the illustrated perspective view). First 5104 and second 5106 gate dielectric layers are over the top 5102A of the fin 5102 and laterally adjacent to the sidewalls of the fin 5102. First 5108 and second 5110 gate electrodes are over the first 5104 and second 5106 gate dielectric layers, over the top 5102A of the fin 5102 and laterally adjacent to the sidewalls of the fin 5102. The first 5108 and second 5110 gate electrodes each include a conformal conductive layer 5109A (such as a work function setting layer) and a conductive fill material 5109B over the conformal conductive layer 5109A. The first 5108 and second 5110 gate electrodes each have a first side 5112 and a second side 5114 opposite the first side 5112. The first 5108 and second 5110 gate electrodes each also have an insulative cap 5116 having a top surface 5118.

[0506] A first dielectric spacer 5120 is adjacent to the first side 5112 of the first gate electrode 5108. A second dielectric spacer 5122 is adjacent to the second side 5114 of the second gate electrode 5110. A semiconductor source or drain region 5124 is adjacent to the first 5120 and second 5122 dielectric spacers. A trench contact structure 5126 is over the semiconductor source or drain region 5124 adjacent to the first 5120 and second 5122 dielectric spacers.

[0507] The trench contact structure 5126 includes an insulative cap 5128 over a conductive structure 5130. The insulative cap 5128 of the trench contact structure 5126 has a top surface 5129 that is substantially coplanar with the top surface 5118 of the insulative cap 5116 of the first 5108 and second 5110 gate electrodes. In embodiments, the insulative cap 5128 of the trench contact structure 5126 laterally extends into recesses 5132 in the first 5120 and second 5122 dielectric spacers. In such embodiments, the insulative cap 5128 of the trench contact structure 5126 is overhanging the conductive structure 5130 of the trench contact structure 5126. However, in other embodiments, the insulative cap 5128 of the trench contact structure 5126 does not laterally extend into the recesses 5132 in the first 5120 and second 5122 dielectric spacers, and thus is not overhanging the conductive structure 5130 of the trench contact structure 5126.

[0508] It is to be appreciated that the conductive structure 5130 of the trench contact structure 5126 can not be rectangular, such as FIGS. 51A-51CThe conductive structures 5130 of the trench contact structures 5126 can have similar or identical cross-sectional geometry to that shown for the conductive structures 5130A shown in the projection of FIG. 12B. FIG. 51A

[0509] In an embodiment, the insulative caps 5128 of the trench contact structures 5126 have a different composition than the composition of the insulative caps 5116 of the first 5108 and second 5110 gate electrodes. In one such embodiment, the insulative caps 5128 of the trench contact structures 5126 include a carbide material, such as a silicon carbide material. The insulative caps 5116 of the first 5108 and second 5110 gate electrodes include a nitride material, such as a silicon nitride material.

[0510] In an embodiment, the insulative caps 5116 of the first 5108 and second 5110 gate electrodes each have a bottom surface 5117A that is lower than a bottom surface 5128A of the insulative cap 5128 of the trench contact structure 5126, as shown in FIG. 12B. In another embodiment, the insulative caps 5116 of the first 5108 and second 5110 gate electrodes each have a bottom surface 5117A that is substantially co-planar with a bottom surface 5128B of the insulative cap 5128 of the trench contact structure 5126, as shown in FIG. 12C. In another embodiment, the insulative caps 5116 of the first 5108 and second 5110 gate electrodes each have a bottom surface 5117C that is higher than a bottom surface 5128C of the insulative cap 5128 of the trench contact structure 5126, as shown in FIG. 12D. FIG. 51A FIG. 51B FIG. 51C

[0511] In an embodiment, the conductive structures 5130 of the trench contact structures 5128 include a U-shaped metal layer 5134, a T-shaped metal layer 5136 on and over the entirety of the U-shaped metal layer 5134, and a third metal layer 5138 on the T-shaped metal layer 5136. The insulative caps 5128 of the trench contact structures 5126 are on the third metal layer 5138. In one such embodiment, the third metal layer 5138 and the U-shaped metal layer 5134 include titanium, and the T-shaped metal layer 5136 includes cobalt. In a particular such embodiment, the T-shaped metal layer 5136 also includes carbon.

[0512] ​​​​In an embodiment, the metal silicide layer 5140 is directly between the conductive structure 5130 of the trench contact structure 5126 and the semiconductor source or drain region 5124. In one such embodiment, the metal silicide layer 5140 includes titanium and silicon. In a particular such embodiment, the semiconductor source or drain region 5124 is an N-type semiconductor source or drain region. In another embodiment, the metal silicide layer 5140 includes nickel, platinum, and silicon. In a particular such embodiment, the semiconductor source or drain region 5124 is a P-type semiconductor source or drain region. In another particular such embodiment, the metal silicide layer also includes germanium.

[0513] In an embodiment, referring to FIG. 51D , the conductive via 5150 is on and electrically connected to a portion of the first gate electrode 5108 that is above the top 5102A of the fin 5102. The conductive via 5150 is in the opening 5152 in the insulating cap 5116 of the first gate electrode 5108. In one such embodiment, the conductive via 5150 is on a portion of the insulating cap 5128 of the trench contact structure 5126, but is not electrically connected to the conductive structure 5130 of the trench contact structure 5126. In a particular such embodiment, the conductive via 5150 is in the etched portion 5154 of the insulating cap 5128 of the trench contact structure 5126.

[0514] In an embodiment, referring to FIG. 51E , the conductive via 5160 is on and electrically connected to a portion of the trench contact structure 5126. The conductive via is in the opening 5162 in the insulating cap 5128 of the trench contact structure 5126. In one such embodiment, the conductive via 5160 is on a portion of the insulating cap 5116 of the first 5108 and second 5110 gate electrodes, but is not electrically connected to the first 5108 and second 5110 gate electrodes. In a particular such embodiment, the conductive via 5160 is in the etched portion 5164 of the insulating cap 5116 of the first 5108 and second 5110 gate electrodes.

[0515] Referring again to FIG. 51E , in an embodiment, the conductive via 5160 is a second conductive via that is of the same structure as the conductive via 5150 of FIG. 51D . In one such embodiment, such a second conductive via 5160 is isolated from the conductive via 5150. In another such embodiment, such a second conductive via 5160 is fused with the conductive via 5150 to form an electrical short contact 5170, as shown in FIG. 51F .

[0516] The approaches and structures described herein can enable other structures or devices to be formed that are not possible or are difficult to manufacture using other methods. In a first example, FIG. 52A A plan view of another semiconductor device having a gate contact via disposed over an active portion of a gate in accordance with another embodiment of the present disclosure is shown. Reference is made to FIG. 52A The semiconductor structure or device 5200 includes a plurality of gate structures 5208A-5208C that intersect with a plurality of trench contacts 5210A and 5210B (features disposed over an active region of a substrate, not shown). A gate contact via 5280 is formed over an active portion of the gate structure 5208B. The gate contact via 5280 is also disposed over an active portion of the gate structure 5208C, coupling the gate structures 5208B and 5208C. It should be appreciated that an intervening trench contact 5210B can be isolated from the contact 5280 using a trench contact isolation cap layer (e.g., TILA). FIG. 52A The contact configuration of the 5200 can provide an easier way to bundle adjacent gate lines in a layout without routing the bundled lines through a metallized upper layer, thus enabling a smaller cell area or a less complex routing scheme or both.

[0517] In a second example, FIG. 52B A plan view of another semiconductor device having a trench contact via coupling a pair of trench contacts in accordance with another embodiment of the present disclosure is shown. Reference is made to FIG. 52B The semiconductor structure or device 5250 includes a plurality of gate structures 5258A-5258C that intersect with a plurality of trench contacts 5260A and 5260B (features disposed over an active region of a substrate, not shown). A trench contact via 5290 is formed over the trench contact 5260A. The trench contact via 5290 is also disposed over the trench contact 5260B, coupling the trench contacts 5260A and 5260B. It should be appreciated that an intervening gate structure 5258B can be isolated from the trench contact via 5290 using a gate isolation cap layer (e.g., through a GILA process). FIG. 52B The contact configuration of the 5250 can provide an easier way to bundle adjacent trench contacts in a layout without routing the bundled lines through a metallized upper layer, thus enabling a smaller cell area or a less complex routing scheme or both.

[0518] The insulative cap layer for the gate electrode can be fabricated using several deposition operations, and as a result, the insulative cap layer can include artifacts of the multiple deposition fabrication processes. For example, FIGS. 53A-53E Cross-sectional views representing various operations in a method of fabricating an integrated circuit structure including a gate stack having an overlying insulative cap layer in accordance with embodiments of the present disclosure are shown.

[0519] Referring FIG. 53A , the starting structure 5300 includes a gate stack 5304 over a substrate or fin 5302. The gate stack 5304 includes a gate dielectric layer 5306, a conformal conductive layer 5308, and a conductive fill material 5310. In embodiments, the gate dielectric layer 5306 is a high-k gate dielectric layer formed using an atomic layer deposition (ALD) process, and the conformal conductive layer is a work function layer formed using an ALD process. In one such embodiment, a thermal or chemical oxide layer 5312, such as a thermal or chemical silicon dioxide or silicon oxide layer, is between the substrate or fin 5302 and the gate dielectric layer 5306. A dielectric spacer 5314, such as a silicon nitride spacer, is adjacent to the sidewalls of the gate stack 5304. The dielectric gate stack 5304 and the dielectric spacer 5314 are contained in an interlayer dielectric (ILD) layer 5316. In embodiments, the gate stack 5304 is formed using a replacement gate and replacement gate dielectric processing scheme. A mask 5318 is patterned over the gate stack 5304 and the ILD layer 5316 to provide an opening 5320 that exposes the gate stack 5304.

[0520] Referring FIG. 53B , the gate stack 5304, including the gate dielectric layer 5306, the conformal conductive layer 5308, and the conductive fill material 5310, is recessed relative to the dielectric spacer 5314 and the layer 5316 using one or more selective etching processes. The mask 5318 is then removed. The recessing provides a cavity 5322 over the recessed gate stack 5324.

[0521] In another embodiment, not shown, the conformal conductive layer 5308 and the conductive fill material 5310 are recessed relative to the dielectric spacer 5314 and the layer 5316, but the gate dielectric layer 5306 is not recessed or is only minimally recessed. It should be appreciated that in other embodiments, a maskless approach based on high etch selectivity is used for the recessing.

[0522] Referring FIG. 53C , a first deposition process of a plurality of deposition processes for fabricating a gate insulating cap layer is performed. The first deposition process is used to form a first insulating layer 5326 that is conformal to the structure of FIG. 53B . In embodiments, the first insulating layer 5326 includes silicon and nitrogen, for example, the first insulating layer 5326 is a silicon nitride (Si3N4) layer, a silicon-rich silicon nitride layer, a silicon-poor silicon nitride layer, or a carbon-doped silicon nitride layer. In embodiments, the first insulating layer 5326 only partially fills the cavity 5322 over the recessed gate stack 5324, as shown.

[0523] refer to FIG. 53D The first insulating layer 5326 undergoes a deep etching process, such as anisotropic etching, to provide a first portion 5328 of the insulating cap layer. The first portion 5328 of the insulating cap layer only partially fills the cavity 5322 above the recessed gate stack 5324.

[0524] refer to FIG. 53E Additional alternating deposition and deep etching processes are performed until the cavity 5322 is filled using the insulating gate cap structure 5330 above the recessed gate stack 5324. In cross-sectional analysis, the seam 5332 may be clearly visible and can indicate the number of alternating deposition and deep etching processes used for the insulating gate cap structure 5330. FIG. 53E In the example shown, the presence of three sets of seams 5332A, 5332B, and 5332C indicates four alternating deposition and deep etching processes for the insulating gate cap structure 5330. In the embodiment, the materials 5330A, 5330B, 5330C, and 5330D of the insulating gate cap structure 5330 separated by seams 5332 all have exactly or substantially the same composition.

[0525] As described throughout this application, the substrate can be made of a semiconductor material capable of withstanding fabrication processes and in which charge can migrate. In embodiments, the substrate is described herein as being made of crystalline silicon, a silicon / germanium or germanium layer doped with charge carriers, such as, but not limited to, phosphorus, arsenic, boron, or combinations thereof...

Claims

1. An integrated circuit structure, comprising: A plurality of conductive interconnects are located in and spaced apart by an interlayer dielectric (ILD) layer above a substrate, each of the plurality of conductive interconnects having an upper surface lower than the upper surface of the ILD layer, wherein each of the plurality of conductive interconnects includes a barrier layer along the sidewalls and bottom of a conductive filler material, and wherein the uppermost surface of the barrier layer is higher than the uppermost surface of the conductive filler material, and the barrier layer has an uppermost surface coplanar with the upper surface of the ILD layer; An etch stop layer is located on and conforms to the ILD layer and the plurality of conductive interconnects, the etch stop layer having a non-planar upper surface, the uppermost portion of the non-planar upper surface being above the ILD layer, and the lowermost portion of the non-planar upper surface being above the plurality of conductive interconnects; A conductive via electrically coupled to an individual conductive interconnect among the plurality of conductive interconnects, the conductive via being located in an opening in the etch stop layer, the opening being above the individual conductive interconnect among the plurality of conductive interconnects but not above the ILD layer, the conductive via being located in a second ILD layer; and A dielectric plug located on a portion of the second ILD layer, wherein the conductive via is below the bottom of the dielectric plug.

2. The integrated circuit structure according to claim 1, wherein, The center of the conductive via is aligned with the center of an individual conductive interconnect among the plurality of conductive interconnects.

3. The integrated circuit structure according to claim 1, wherein, The center of the conductive via is offset from the center of any individual conductive interconnect among the plurality of conductive interconnects.

4. The integrated circuit structure according to claim 1, wherein, Both the barrier layer and the conductive filler material have an uppermost surface that is lower than the upper surface of the ILD layer.

5. The integrated circuit structure according to claim 1, wherein, The conductive filler material has an uppermost surface that is lower than the upper surface of the ILD layer.

6. The integrated circuit structure according to claim 1, wherein, The second ILD layer is on the etch stop layer and conforms to the etch stop layer.

7. The integrated circuit structure according to claim 1, wherein, The ILD layer comprises silicon, carbon, and oxygen, and the etch stop layer comprises silicon and nitrogen.

8. The integrated circuit structure according to claim 1, wherein, The upper surface of each of the plurality of conductive interconnects is 0.5-1.5 nanometers lower than the upper surface of the ILD layer.

9. An integrated circuit structure, comprising: A plurality of conductive interconnects are located in and spaced apart by an interlayer dielectric (ILD) layer above a substrate, wherein an individual conductive interconnect has an upper surface above the upper surface of the ILD layer, wherein the individual conductive interconnect includes a barrier layer along the sidewalls and bottom of a conductive filler material, and wherein the uppermost surface of the barrier layer is lower than the uppermost surface of the conductive filler material, and the barrier layer has an uppermost surface coplanar with the upper surface of the ILD layer; An etch stop layer conformally thereto, situated on and along the plurality of conductive interconnects, the etch stop layer having a non-planar upper surface, the lowermost portion of the non-planar upper surface being above the ILD layer, and the uppermost portion of the non-planar upper surface being above the plurality of conductive interconnects; and A conductive via electrically coupled to an individual conductive interconnect among the plurality of conductive interconnects, the conductive via being located in an opening in the etch stop layer, the opening being above the individual conductive interconnect among the plurality of conductive interconnects but not above the ILD layer, the conductive via being located in a second ILD layer; and A dielectric plug located on a portion of the second ILD layer, wherein the conductive via is below the bottom of the dielectric plug.

10. The integrated circuit structure according to claim 9, wherein, The center of the conductive via is aligned with the center of an individual conductive interconnect among the plurality of conductive interconnects.

11. The integrated circuit structure according to claim 9, wherein, The center of the conductive via is offset from the center of any individual conductive interconnect among the plurality of conductive interconnects.

12. The integrated circuit structure according to claim 9, wherein, Both the barrier layer and the conductive filler material have an uppermost surface that is higher than the upper surface of the ILD layer.

13. The integrated circuit structure according to claim 9, wherein, The conductive filler material has an uppermost surface that is higher than the upper surface of the ILD layer.

14. The integrated circuit structure according to claim 9, wherein, The second ILD layer is on the etch stop layer and conforms to the etch stop layer.

15. The integrated circuit structure according to claim 9, wherein, The ILD layer comprises silicon, carbon, and oxygen, and the etch stop layer comprises silicon and nitrogen.

16. The integrated circuit structure according to claim 9, wherein, The upper surface of each of the plurality of conductive interconnects is 0.5-1.5 nanometers higher than the upper surface of the ILD layer.

17. A method for manufacturing an integrated circuit structure, the method comprising: A plurality of conductive interconnects are formed in a first interlayer dielectric (ILD) layer above the substrate, spaced apart by the first interlayer dielectric (ILD) layer; The plurality of conductive interconnects are recessed relative to the first ILD layer to provide an individual conductive interconnect among the plurality of conductive interconnects having an upper surface lower than the upper surface of the first ILD layer. After recessing the plurality of conductive interconnects, an etch stop layer is formed conformally on and to the first ILD layer and the plurality of conductive interconnects. The etch stop layer has a non-planar upper surface, the uppermost portion of which is above the first ILD layer and the lowermost portion of which is above the plurality of conductive interconnects. A second ILD layer is formed on the etch stop layer; Etch via trenches in the second ILD layer, wherein the etch stop layer points to the location of the via trenches in the second ILD layer during etching; The etch stop layer is etched through the via trench to form an opening in the etch stop layer, the opening being above an individual conductive interconnect among the plurality of conductive interconnects but not above the first ILD layer; Conductive vias are formed in the via trenches and the openings in the etch stop layer, and the conductive vias are electrically coupled to and on individual conductive interconnects among the plurality of conductive interconnects; and A dielectric plug is formed on a portion of the second ILD layer, and the conductive via is lower than the bottom of the dielectric plug. Each of the plurality of conductive interconnects includes a barrier layer along the sidewalls and bottom of the conductive filler material, wherein the uppermost surface of the barrier layer is higher than the uppermost surface of the conductive filler material, and the barrier layer has an uppermost surface coplanar with the upper surface of the first ILD layer.

18. The method according to claim 17, wherein, Recessing the plurality of conductive interconnects includes recessing both the barrier layer and the conductive filler material.

19. The method of claim 17, wherein, Recessing the plurality of conductive interconnects includes recessing the conductive filler material but not substantially recessing the barrier layer.

20. The method of claim 17, wherein, The etch stop layer is redirected to the photolithographically misaligned via trench pattern.

21. The method according to claim 17, wherein, The recessing of the plurality of conductive interconnects includes an amount in the range of 0.5-1.5 nanometers relative to the first ILD layer.

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