Compensation devices for transistors

Abstract

A compensation device for a transistor is provided, the device comprising a transistor having a parasitic capacitance between at least one control terminal and at least one load terminal of a first type. Furthermore, the device comprises advantageously arranged inductors, the inductors being electromagnetically coupled to each other and configured to at least partially compensate for the effect of the parasitic capacitance in a range around a resonant frequency.

Description

Technical Field

[0001] The present disclosure relates generally to apparatus for high frequency transistors. Background Art

[0002] In the field of high-frequency applications, especially in the development of communication systems, there is an increasing trend towards amplifier circuits with smaller sizes, higher power and at the same time meeting the requirements of achieving a larger bandwidth of the signal to be processed. In order to keep the space requirements of the corresponding amplifier circuits or other high-frequency circuits compact, the degree of integration of the amplifier circuits is gradually increasing. For power amplifier circuits, this means great challenges not only in terms of efficiency, but also in terms of linearity and circuit stability. This is applicable to Doherty-type power amplifier circuits. The power amplifier circuits are used in a variety of application fields and frequency ranges, for example, in the field of mobile radio systems, such as 5G systems and MIMO systems, or in the field of radio broadcasting and in other wireless applications, such as WLAN.

[0003] Many power amplifier circuits are composed of transistors, especially power transistors and / or high frequency transistors. For some transistor types, the capacitance between the control terminal and the load terminal of the transistor may cause undesirable feedback characteristics, which may lead to undesirable effects, such as instability of the power amplifier circuit when the transistor is operated.

[0004] The conventional way to ensure the stability of the transistor is to add a stabilizing resistor for attenuating possible oscillations. In some cases, a transistor with a gate terminal is used as a transistor. In these cases, the resistor can be connected to the gate terminal of the transistor. However, in this case, the resistor will cause additional effects that are unfavorable to the power circuit, such as the amplification factor of the power circuit will be reduced due to the resistance and / or the resistance will cause the amplification to be non-ideal as a function of the circuit frequency, which is particularly problematic for Doherty amplifier circuits. This is particularly applicable to the following situation: Gallium nitride transistors (GAN transistors) that can have strong feedback characteristics are used. As a result of the large change in the amplification factor of such an amplifier circuit with frequency, the input matching network used will be mismatched in some cases, which will lead to further loss of amplification and may lead to further loss of system efficiency, and it is difficult to design circuits for a wide frequency range.

[0005] In order to compensate for the effects described above, a feedback system network can be used in some application cases, which includes at least one resistor, inductor and capacitor (RLC network) between the control terminal and the load terminal of the transistor. The additional capacitance is used in this case for DC isolation, since the load terminal and the control terminal are generally at different potentials. However, this additional capacitance of the feedback network can also cause undesirable, disadvantageous effects. Summary of the invention

[0006] An apparatus according to the invention is provided. The following description defines further embodiments.

[0007] According to one embodiment, a device is provided, the device comprising a transistor having at least one control terminal, at least one load terminal of a first type and at least one load terminal of a second type. In this case, the transistor has a parasitic capacitance between the at least one control terminal and the at least one load terminal of the first type. In addition, the device comprises: a first inductor, the first inductor being conductively connected to the at least one control terminal; and a second inductor, the second inductor being conductively connected to the at least one load terminal of the first type. In this case, the first inductor is electromagnetically coupled to the second inductor, and the first inductor, the second inductor and the electromagnetic coupling are configured to at least partially compensate for the effect of the parasitic capacitance in a range near the resonant frequency.

[0008] According to another embodiment, the device includes at least one transistor. The transistor includes: at least one control terminal surface; at least one load terminal surface; at least one first bonding wire, the first bonding wire having a first bonding wire inductance; and at least one second bonding wire, the second bonding wire having a second bonding wire inductance. In this case, at least one first bonding wire is conductively connected to at least one control terminal surface, and at least one second bonding wire is conductively connected to at least one load terminal surface. In addition, the device includes at least one third bonding wire, the third bonding wire having a starting end and an end, wherein at least one first bonding wire is electromagnetically coupled to a first portion of at least one third bonding wire, and at least one second bonding wire is electromagnetically coupled to a second portion of at least one third bonding wire. In addition, at least one third bonding wire is electrically insulated from at least one first bonding wire and at least one second bonding wire, and the starting end and the end are conductively connected to a reference potential.

[0009] According to one embodiment, the device includes at least one transistor, which is conductively connected to at least one control terminal surface and at least one load terminal surface. In addition, the device includes at least one control contact surface and at least one load contact surface and a plurality of first bonding wires, which are conductively connected to the control terminal surface and the control contact surface, respectively. In addition, the device includes: a plurality of second bonding wires, which are conductively connected to at least one load terminal surface and at least one load contact surface, respectively; and a plurality of third bonding wires, each of which has a starting end and an end. Here, the starting end and the end are conductively connected to a reference potential, respectively, and each of the plurality of third bonding wires is electrically insulated from the plurality of first bonding wires and the plurality of second bonding wires. Additionally, the plurality of third bonding wires and the plurality of first bonding wires have a first mutual inductance, and the plurality of third bonding wires and the plurality of second bonding wires have a second mutual inductance. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above summary is to be understood only as a brief overview of some possible implementations and is not to be construed as limiting. In particular, other embodiments may use features different from those set forth above.

[0011] Figure 1 Circuits according to various embodiments are schematically shown.

[0012] Figure 2 Circuits according to various embodiments are schematically shown.

[0013] Figure 3 Circuits according to various embodiments are schematically shown.

[0014] Figure 4 Circuits according to various embodiments are schematically shown.

[0015] Figure 5 A comparative example is schematically shown.

[0016] Figure 6 Schematically shows the Figure 4 Possible implementations of the circuit.

[0017] Figure 7 Shows Figure 5 Comparative example of simulation of different stability parameters as a function of frequency.

[0018] Figure 8 Shown according to Figure 6 Example of simulation of different stability parameters as a function of frequency. DETAILED DESCRIPTION

[0019] In the following, different embodiments are described in detail with reference to the attached drawings. These embodiments are considered as examples only and are not to be construed as being restrictive. For example, in other embodiments, some of the described features or components may be canceled and / or replaced by alternative features or components. The features or components of different embodiments may be combined to form additional embodiments. Variations and modifications described with respect to one embodiment may also be applied to other embodiments. In addition, features or components different from the described or shown features or components may be provided, such as features or components used in conventional power amplifier circuits or high frequency circuits.

[0020] In the drawings, the same reference numerals represent the same or similar elements. The drawings are schematic representations of different embodiments. The elements shown in the drawings are not necessarily shown to scale. Rather, the different elements shown in the drawings are depicted so that their functions and general purposes can be understood by those skilled in the art.

[0021] The described technology and device can be used in a wide range of application fields. For example, the stabilization of transistors is used in conjunction with mobile radio systems, such as 5G and MIMO systems, as described below, but can also be used in many application fields, for example not only in modern mobile systems and industrial systems, but also in the home field. The described technology can also be applied in the field of power amplifiers, in the field of modern high-power technologies, such as GaN systems. The device can also be used in conjunction with so-called smart transistors. Smart transistors are transistors that are equipped with multiple diagnostic capabilities and protection features in order to identify different interference conditions. As a result, overload and short-circuit events can be prevented, which makes it possible to design smart transistors in a cost-optimized and structural manner and require them to withstand loads up to thermal and electrical limits.

[0022] A direct connection or coupling shown in the drawings or described below, i.e. an electrical connection or coupling without intervening elements (e.g. simple metal conductor tracks), can also be achieved via an indirect connection or coupling, i.e. a connection or coupling comprising one or more additional intervening elements, and vice versa, as long as the general function of the connection or coupling, such as providing a voltage, providing a current or providing a control signal, is essentially maintained.

[0023] A conductive connection refers to a coupling that enables the transmission of a DC voltage and / or an AC voltage. A conductive connection can be realized, for example, by means of a continuous metal wire. A conductive connection can also be realized, for example, by means of a conductive surface.

[0024] Generally speaking, in the context of the present application, a transistor has one or more control terminals and two or more load terminals. The opening and closing of the transistor (the operation of the transistor) can be controlled by applying one or more signals to the one or more control terminals. When the transistor is closed, the transistor provides a low-resistance connection between at least two of its load terminals so that current can flow between these load terminals. When the transistor is disconnected, the transistor exhibits a cut-off behavior between its load terminals, i.e., the transistor is high-resistance so that substantially no current can flow between the load terminals, for example, except for undesirable effects that may occur in actual devices, such as leakage currents, etc.

[0025] Many transistors have a transition region between a closed state and an open state, in which a gradual opening of the transistor can be controlled by means of one or more control terminals. Some transistors can have a linear dependence between a control terminal signal and the ohmicity of the connection between at least two load terminals at least in a part of the transition region. In some amplifier arrangements, the transistor is operated in said linear part of the transition region.

[0026] Some transistors may have parasitic, ie, undesirable, capacitances between various terminals. For example, parasitic capacitances may occur between at least one control terminal and at least one load terminal and / or between a first load terminal and a second load terminal.

[0027] In some embodiments, the transistor may be a transistor (RF power transistor) particularly for high frequency and power applications. In some embodiments, the transistor may be implemented using a field effect transistor (FET), such as a MOS transistor (MOSFET), a bipolar transistor with an insulated gate (IGBT), a junction field effect transistor (JFET), a bipolar transistor (BJT), a gallium nitride transistor (GAN transistor), a silicon carbide transistor (SiC transistor), or a transistor with high electron mobility (HEMT). In this case, the load terminal may include at least one load terminal of the first type and at least one load terminal of the second type.

[0028] In the case of a field effect transistor, at least one load terminal of the first type may correspond to a drain terminal or multiple drain terminals, and at least one load terminal of the second type may correspond to a source terminal or multiple source terminals, and at least one control terminal may correspond to a gate terminal or multiple gate terminals.

[0029] In the case of a bipolar transistor or a bipolar transistor with an insulated gate, at least one load terminal of the first type may correspond to a collector terminal or multiple collector terminals, and at least one load terminal of the second type may correspond to an emitter terminal or multiple emitter terminals. One / multiple emitter terminals and one / multiple collector terminals may also be interchanged between the first type and the second type. In the case of a bipolar transistor, at least one control terminal may correspond to a base terminal or multiple base terminals. In the case of a bipolar transistor with an insulated gate, at least one control terminal may correspond to a gate terminal or multiple gate terminals.

[0030] The device may include a die. A die is used to represent a semiconductor chip, which may also be combined with other semiconductor chips.

[0031] The device may include a chip housing. The chip housing may provide an enclosure for the semiconductor chip including connection locations, such as leads, pins or balls. Numerous variants of such chip housings are known to those skilled in the art, which differ in their shape, the materials used, the number and arrangement of connection locations and other characteristics.

[0032] In some transistors, so-called parasitic capacitances occur, i.e., undesired or designed-in but unnecessary capacitances. Such parasitic capacitances occur in particular between different terminals of the transistor. For example, parasitic capacitances occur between the control terminal and the load terminal. As mentioned above, these parasitic capacitances occur between the gate terminal and the drain terminal in field effect transistors. In these cases, when referring to the gate-drain capacitance, C is often used. gd In other cases, capacitance appears between the gate terminal and the source terminal. In these cases, the gate-source capacitance is often referred to as C gs In other types of transistors, the corresponding capacitance would appear between different terminals.

[0033] In the sense of this application, an inductor is used to denote a component or a region of a component which has properties exhibited by an inductor.

[0034] Examples of inductors in connection with the present application may be coils, printed conductors, printed conductor segments, individual conductors, individual bonding wires, multiple bonding wires and / or segments of individual or multiple bonding wires. Such enumeration is not to be interpreted as limiting, but is merely used for illustration. The inductive properties can be changed by changing the components, in particular the component geometry.

[0035] In conjunction with this specification, electromagnetic coupling or mutual inductance is understood as the mutual magnetic influence between two or more spatially adjacent inductors due to electromagnetic interaction. Quantitatively, the electromagnetic coupling or mutual inductance between two inductors can be described by means of a coupling coefficient.

[0036] The sign and value of the coupling coefficient between two inductors depends on many parameters and can be changed by changing these parameters, for example by changing the distance, arrangement and shape of the inductors and corresponding geometrical properties, such as the size and shape of the conducting elements of the inductors.

[0037] In the context of the present application, a resonance frequency is understood to be the resonance frequency of an oscillating circuit, for example the resonance frequency of an oscillating circuit of a capacitor together with an inductance and / or a resistor.

[0038] exist Figure 1 , Figure 2 , Figure 3 and Figure 4 , a transistor 1 is shown, which is coupled to a reference potential 5, an input matching network 8 and an output matching network 9. The transistor 1 has a control terminal 2, a load terminal 3 of a first type and a load terminal 4 of a second type. Between the control terminal 2 and the load terminal 3 of the first type, the transistor 1 has a first parasitic capacitance 6. Furthermore, the transistor 1 can additionally have a second parasitic capacitance 7 between the control terminal 2 and the reference potential 5. Furthermore, the transistor 1 can have a Figures 1 to 4 Other parasitic capacitances not shown.

[0039] In some embodiments, transistor 1 may be a power transistor. Control terminal 2 may be a gate terminal, first type load terminal 3 may be a drain terminal, and second type load terminal 4 may be a source terminal. In this embodiment, parasitic capacitance 6 is referred to as gate-drain capacitance, C gd .

[0040] Figure 1 Circuits according to various embodiments are schematically shown.

[0041] In the illustrated embodiment, the circuit has, in addition to the transistor 1 described above, a feedback network 10 , which includes a first inductor 11 and a second inductor 12 , wherein the first inductor 11 and the second inductor 12 have an electromagnetic coupling 13 .

[0042] The electromagnetic coupling can be configured to at least partially compensate for the effects of first parasitic capacitance 6 in the range around the resonance frequency during operation of transistor 1. This can be achieved by suitable selection of the coupling, for example by providing conductor tracks and suitable selection of first inductance 11 and second inductance 12.

[0043] At least partial compensation of the first parasitic capacitance 6 in the frequency range then exists if a coupled element is designed near a mid-frequency within a specific bandwidth such that the element forms an oscillating circuit with the first parasitic capacitance 6, wherein the oscillating circuit is suitable for compensating for the influence of the first parasitic capacitance 6 within the bandwidth, so that the circuit behaves as effectively as if the first parasitic capacitance 6 did not exist, and the circuit therefore behaves as if no parasitic connection between the control terminal 2 and the first type of load terminal 3 were present in the frequency range, or the influence of the parasitic capacitance is at least reduced.

[0044] The advantage of some of these and the embodiments described below is that for amplifier circuits, such as Doherty amplifier circuits, approximately ideal characteristics when changing impedance as a function of frequency can be achieved. This can simplify the design of amplifiers for a wide frequency range and efficiency at high frequencies.

[0045] Depending on the desired frequency range and power class of the circuit, the inductance can be provided by means of bonding wires, as will also be explained with reference to the following exemplary embodiments.

[0046] Circuits according to these and hereinafter described embodiments may provide the advantages of inductive feedback that is DC isolated.

[0047] DC isolation means that the feedback acts as an electrical insulator for DC voltages or low-frequency voltages. For example, due to the DC isolation between the control terminal and the load terminal of the first type, it is possible to omit the additional capacitor required for DC isolation in the RLC network.

[0048] The circuit according to the various embodiments described above and below can have the property that, due to the elements for compensating the parasitic capacitance 6 , it can stabilize possibly undesirable oscillatory characteristics without additional resistance, as can occur, for example, due to a series circuit of capacitance and inductance in an RLC compensation network.

[0049] Further effects may be approximately ideal amplification characteristics as a function of the load and reduced losses and thus increased efficiency.

[0050] Figure 2 Circuits according to various embodiments are schematically shown.

[0051] exist Figure 2 , a circuit is shown having a transistor 1 , for which the above explanations apply correspondingly.

[0052] exist Figure 2The circuit shown in FIG. 1 includes a first inductor 211, a second inductor 212, a third inductor 213 with a first terminal 221 and a second terminal 222, and a fourth inductor 214 with a third terminal 223 and a fourth terminal 224. The second terminal 222 is conductively connected to the third terminal 223 by means of a first line 215. The first terminal 221 is conductively connected to the fourth terminal 224 by means of a second line 216. Figure 2 In the illustrated embodiment, the first line 215 is coupled to a reference potential 217. In some embodiments, also alternatively or additionally, the second line 216 can also be coupled to a reference potential 217. The reference potential 217 can correspond to the reference potential 5 of the transistor 1. The electromagnetic coupling of the first inductor and the third inductor and the electromagnetic coupling of the second inductor and the fourth inductor each have a subtractive polarity.

[0053] There is an electromagnetic coupling between the first inductor 211 and the third inductor 213, and there is an electromagnetic coupling between the second inductor 212 and the fourth inductor 214. As a result, the circuit can have a total coupling, which includes the respective mutual couplings of the first inductor 211, the second inductor 212, the third inductor 213 and the fourth inductor 214, which can provide an effective coupling between the first inductor 211 and the second inductor 212 in their joint action, and the effective coupling can be used for Figure 1 An embodiment of the coupling 13 is shown in FIG.

[0054] These embodiments can also provide the advantages described above. In addition, the lines 215, 216 can provide flexibility in the implementation of the circuit, because the connection of the lines to the additional inductance can achieve more freedom for designing the corresponding inductance and its arrangement. The possibility of coupling the lines to the reference potential 217 can provide simplification in the implementation, as explained below in conjunction with other embodiments, wherein the reference potential can also be additionally or alternatively provided at other locations, for example at 216.

[0055] Combination Figure 2 The described embodiments are particularly suitable for forming an inductor by means of bonding wires, but are not limited thereto. The conversion can also be carried out by means of planar inductors, coils and transformers, for example.

[0056] Feedback network 210 can be formed without a conductive connection or with a conductive connection to a reference potential, such as ground. This enables additional design freedom and thus design advantages. For example, one or both of the lines 215, 216 shown can be formed by a conductive connection to a conductive surface.

[0057] Figure 3 Circuits according to various embodiments are schematically shown.

[0058] exist Figure 3 Transistor 1 is shown again, for Figure 1 The embodiments of the transistor 1 in FIG. 1 apply accordingly to this transistor, and this transistor is used in a similar circuit relationship in the embodiment shown.

[0059] exist Figure 3 The embodiment shown in FIG. 3 comprises a feedback network 310. A terminal 315 of a first inductor 311 is conductively connected to a control terminal 320, and a terminal 314 of a second inductor 312 is conductively connected to a power terminal 322 of the first type. It is possible by means of the inductors 311, 312 to isolate the terminals 320 and 322 from an AC voltage signal, such as an RF signal. It is thus possible to couple a DC voltage to the transistor 1 via the terminals 320, 322, which DC voltage can be superimposed on an additionally present AC voltage signal. Thus, for example, an RF signal provided by the input matching network 8 can be superimposed on a DC voltage signal provided at the terminal 320 at the control terminal 2 of the transistor. In some embodiments, amplification can be selected by means of the DC voltage signal when the transistor is operated in a linear state. In some embodiments, the transistor 1 is a field effect transistor. Thus, the control terminal 320 can be a gate control terminal and the power terminal 322 of the first type can be a drain supply terminal.

[0060] exist Figure 3 In the embodiment, the inductive coupling 313 is alternatively realized in the form of a parallel circuit, wherein the inductive coupling is connected according to Figure 1 In the embodiment of the invention, the control terminal 320 and the first type of power terminal 322 are connected in series with an input matching network (IMN; English for "input matching impedance") 8 and an output matching network (OMN; English for "output matching impedance") 9. This provides a further possibility for compensating the parasitic capacitance 6. The circuit can also compensate for the feedback of the parasitic capacitance in the transistor by suitable selection of the values ​​of the corresponding inductance and / or coupling coefficient. The conductive connection in the sense of coupling to the control terminal 320 and the first type of power terminal 322 is to be understood only as an example. In particular, inserted components or other supply voltages are possible.

[0061] Figure 4 Circuits according to various embodiments are schematically shown.

[0062] exist Figure 4 Transistor 1 is shown again, for Figure 2 The embodiments of the transistor 1 in FIG. 1 apply accordingly to this transistor, and this transistor is used in a similar circuit relationship in the exemplary embodiment shown.

[0063] exist Figure 4In the embodiment shown in FIG. 4 , a terminal 415 of the first inductor 411 is conductively connected to a control terminal 420, and a terminal 416 of the second inductor 412 is conductively connected to a first type of power terminal 422. In some embodiments, the control terminal 420 may be a gate control terminal and the first type of power terminal 422 may be a drain terminal.

[0064] In this way, the inductive coupling network 410 can be used as in Figure 4 As shown in FIG. 1 , the inductive coupling network is implemented in the form of a parallel circuit, the inductive coupling network includes a third inductor 413 and a fourth inductor 414. Figure 2 6 and 7. In the embodiment shown, the parasitic capacitance 6 is connected in series with an input matching network (MIN) 8 and an output matching network (OMN) 9. This provides greater design freedom for compensating the parasitic capacitance 6 in some embodiments.

[0065] Inductors that are electromagnetically coupled to each other may have different types of electromagnetic coupling.

[0066] In this way, the electromagnetic coupling between the first inductor 411 and the third inductor 413 and the electromagnetic coupling between the second inductor 412 and the fourth inductor 414 may have positive coupling coefficients, respectively.

[0067] Figure 5 A comparative example of an embodiment is schematically shown, which embodiment is then referred to in conjunction with Figure 6 This is described below.

[0068] exist Figure 5 5 shows a device which can be applied, for example, on a circuit board. The circuit board can include a substantially conductive plane at a reference potential 540, wherein the reference potential can be ground potential. At least one transistor is present on the back side of the insulator 501. Figure 5 , the arrangement of two transistors in a housing is shown on the back side of an insulating body 501. The insulating body 501 additionally comprises at least one control connection surface, in this case a first control connection surface 504 and a second control connection surface 503, and at least one first load connection surface 502.

[0069] Furthermore, two further insulating bodies 507 , 508 are provided. On one of the insulating bodies 507 , at least one control contact surface 505 is present, and on the other insulating body 508 , at least one further load connection contact surface 506 is present.

[0070] The insulators 501 , 507 , 508 described here are merely shown by way of example; alternative embodiments are possible. Thus, the substantially conductive plane can also be formed at the reference potential 540 in such a way that an insulating effect occurs due to the interruption.

[0071] Via the contact areas 505 , 506 and possibly further contact areas, contact can be established with further circuit parts (not shown).

[0072] At least one first bonding wire 511 conductively connects at least one control connection surface 503, 504 to at least one control contact surface 505. At least one second bonding wire 520 conductively connects at least one load connection surface 502 to at least one load contact surface 506. These connections can be realized in particular by a plurality of first bonding wires 512, which can have a geometry similar to that shown here, but can also have a different geometry. Figure 5 This is illustrated by taking a plurality of first bonding wires 512 and a plurality of second bonding wires 521 as an example.

[0073] Figure 6 Schematically shows the Figure 4 Possible implementations of the circuit.

[0074] exist Figure 6 Adopted in Figure 5 , wherein the same reference numerals denote the same elements.

[0075] Figure 6 From the basis Figure 5 The discussed device shows the following embodiments according to different embodiments. Figure 4 According to some embodiments, from Figure 4 The coupling network 410 known in the art can be implemented with the aid of at least one third bonding wire 630 or a plurality of third bonding wires 631. The at least one bonding wire 630 or a plurality of third bonding wires 631 each have a start 633 and an end 634. The start and the end are conductively connected to the reference potential 540. The at least one third bonding wire 630 or a plurality of third bonding wires 631 are electrically connected to the reference potential 540. Figure 4 The plurality of first bonding wires 512 and the plurality of second bonding wires 521 shown in the same figure are electrically insulated from each other. Figure 4 According to some embodiments, the effect of the first inductor 411 described in the above description may be caused by at least one first bonding wire 511 or a plurality of first bonding wires 512, and the effect of the second inductor 412 may be caused by at least one second bonding wire 520 or a plurality of second bonding wires 521. By arranging at least one third bonding wire 630 and connecting it to the reference potential 540, due to the geometric characteristics at different regions of the at least one third bonding wire 630, the corresponding Figure 4 The third inductor 413 and the fourth inductor 414 in FIG. Figure 6In some embodiments shown in FIG. 1 , this effect is provided by a plurality of third bonding wires 631, which respectively have mutual inductance with the plurality of first bonding wires 512 in the region of the plurality of first bonding wires 512 and have mutual inductance with the plurality of second bonding wires 521 in the region of the plurality of second bonding wires 521, and the mutual inductance is suitable for combining Figure 4 Functioning as described, this includes in particular electromagnetic coupling of the at least one first bonding wire 511 with a first portion of the at least one third bonding wire 630 and electromagnetic coupling of the at least one second bonding wire 520 with a second portion of the at least one third bonding wire 630 .

[0076] The electromagnetic coupling between at least one third bonding wire 630 and at least one first bonding wire 511 and between at least one third bonding wire 630 and at least one second bonding wire 520 can be configured in particular to at least partially compensate for the effect of parasitic capacitance between at least one control connection surface 504 and at least one load connection surface 502 in a range near the resonance frequency.

[0077] The bonding wire wiring diagram described here as an example can be applied to multiple transistors in different structural forms. This also includes transistors installed in ceramic housings, but also includes solutions directly applied on circuit boards and similar substrate / material technologies. In this case, the bonding wires can be used for connection between the dies. The bonding wires 521, 512 shown can also be stretched in the chip housing, for example in a ceramic housing.

[0078] exist Figure 6 The apparatus shown in can be implemented as a device and in an integrated circuit (IC), but other implementations are also possible.

[0079] Figure 7 Shows the corresponding Figure 5 Comparative example of simulation of different stability parameters as a function of frequency.

[0080] exist Figure 7 The frequency ranges corresponding to Figure 5 701 and the geometric stability parameters μ' 702 and μ1 703 are shown, which can be used to estimate whether the unstable characteristics of the circuit must be taken into account for a specific impedance value. In this case, the values ​​of these three parameters are below 1 over the entire value range shown, so unstable characteristics may exist.

[0081] Figure 8 A simulation of different stabilization parameters as a function of frequency according to one embodiment is shown.

[0082] exist Figure 8The variation of the stability parameters of the circuit according to different embodiments is plotted for a specific frequency range. The k-factor 801 and the geometric stability parameters μ' 802 and μ1 803 are shown again. The stability characteristics can be significantly improved by the feedback network according to different embodiments. It is also possible to achieve parameter-independent stability near the resonance frequency, which can be the case for stability values ​​above 1. Figure 8 This is the case in the frequency range around 4 GHz.

[0083] exist Figure 7 and Figure 8 The simulation curves shown in FIG. 1 are intended only for illustrative purposes; in particular, the curve shapes and values ​​are not to be interpreted as limiting and are dependent on the choice of parameters.

[0084] Although specific embodiments are illustrated and described in this specification, those with common expertise will recognize that a variety of alternative and / or equivalent embodiments may be selected as alternatives to the specific embodiments shown and described in this specification without departing from the scope of the invention as shown. It is intended that this application covers all adaptations or variations of the specific embodiments discussed herein.

[0085] Reference numerals list

[0086] 1 Transistor

[0087] 2 Control terminals

[0088] 3 Type 1 load terminals

[0089] 4 Second type of load terminals

[0090] 5 Reference potential

[0091] 6 First parasitic capacitance

[0092] 7 Second parasitic capacitance

[0093] 8 Input matching network

[0094] 9 Output matching network

[0095] 10 Feedback Network

[0096] 11. First Inductor

[0097] 12 Second Inductor

[0098] 13 Electromagnetic coupling

[0099] 210 Feedback Network

[0100] 211 First Inductor

[0101] 212 Second Inductor

[0102] 213 Third Inductor

[0103] 214 Fourth Inductor

[0104] 215 First Line

[0105] 216 Second Line

[0106] 217 Reference potential

[0107] 221 first terminal

[0108] 222 Second terminal

[0109] 310 Feedback Network

[0110] 311 First Inductor

[0111] 312 Second Inductor

[0112] 313 Inductive coupling

[0113] 314 Terminal of the second inductor

[0114] 315 Terminals of the first inductor

[0115] 320 control terminal

[0116] 322 first type power terminal

[0117] 410 coupling network

[0118] 411 First Inductor

[0119] 412 Second Inductor

[0120] 413 Third Inductor

[0121] 414 Fourth Inductor

[0122] 415 Terminals of the first inductor

[0123] 416 Terminals of the second inductor

[0124] 420 control terminal

[0125] 422 first type power terminal

[0126] 501 Insulator

[0127] 502 Load terminal surface

[0128] 503 Control terminal surface

[0129] 504 control terminal surface

[0130] 505 control contact surface

[0131] 506 load contact surface

[0132] 507 Insulator

[0133] 508 Insulator

[0134] 511 First Bonding Line

[0135] 512 a plurality of first bonding wires

[0136] 520 at least one second bonding wire

[0137] 521 multiple second bonding wires

[0138] 540 reference potential

[0139] 630 at least one third bonding wire

[0140] 631 Multiple third bonding wires

[0141] 633 Starting end (of at least one third bonding wire)

[0142] 634 End of (at least one third bonding wire)

[0143] A Starting point (of the third bonding wires)

[0144] E (end of the third bonding wires)

[0145] 701 k factor

[0146] 702 Stability parameter μ'

[0147] 702 Stability parameter μ1

[0148] 801 k factor

[0149] 802 Stability parameter μ'

[0150] 802 Stability parameter μ1

Claims

1. A compensation device for a transistor, the compensation device comprising: a transistor having a control terminal, a load terminal of a first type and a load terminal of a second type, - wherein the transistor has a parasitic capacitance between the control terminal and a load terminal of the first type, a first inductor, wherein one terminal of the first inductor is conductively connected to the control terminal, a second inductor, wherein one terminal of the second inductor is conductively connected to a load terminal of the first type, - a third inductor having a first terminal and a second terminal, - a fourth inductor having a third terminal and a fourth terminal, - wherein the first inductor is electromagnetically coupled to the second inductor, - wherein the second terminal is conductively connected to the third terminal, - wherein the first terminal is conductively connected to the fourth terminal, - wherein the first inductance, the second inductance and the electromagnetic coupling are configured to at least partially compensate for the effect of parasitic capacitance in a range around the resonance frequency, and - wherein the electromagnetic coupling comprises a first electromagnetic coupling between the first inductance and the third inductance, and a second electromagnetic coupling between the second inductance and the fourth inductance.

2. The compensation device for a transistor according to claim 1, The compensation device has a gate control terminal and a drain supply terminal, wherein a further terminal of the first inductor is conductively connected to the gate control terminal and a further terminal of the second inductor is conductively connected to the drain supply terminal.

3. A compensation device for a transistor according to claim 1 or 2, In this case, at least one of the inductors is implemented by means of at least one bonding wire.

4. A compensation device for a transistor according to claim 1 or 2, The electromagnetic coupling between the first inductor and the third inductor and the electromagnetic coupling between the second inductor and the fourth inductor have subtractive polarity respectively.

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