Low Dropout Amplifier

Abstract

A low voltage dropout amplifier may include an error amplifier having first and second inputs coupled to a reference signal and a feedback signal, respectively. The error amplifier may be configured to generate first and second error signals at first and second outputs, respectively, wherein the first and second error signals are based on a difference between the reference signal and the feedback signal. A sink stage may be coupled to the first output and configured to generate a sink current based on the first error signal. A pull stage may be coupled to the second output and configured to generate a pull current based on the second error signal. An output node may be coupled to sink current and pull current.

Description

[0001] This application is a divisional application of an invention patent application with an application date of December 29, 2014, application number 201410836042.9, and invention name “Low Voltage Dropout Amplifier”. Technical Field

[0002] The present disclosure relates to the field of amplifiers and, more particularly, to the field of low dropout amplifiers including error amplifiers. Background Art

[0003] Handheld battery-powered electronic devices such as tablet computers and smartphones have become widespread in recent years, with usage continuing to rise and additional functionality being added regularly.

[0004] A common type of voltage regulator used in such electronic devices is called a low dropout (LDO) regulator, which can operate with a small input to output a differential voltage and provide a high level of efficiency and heat dissipation. A typical LDO regulator includes an error amplifier that controls a field effect transistor (FET) to cause the FET to sink or source current from or to an output node. One input of the error amplifier receives a feedback signal, while the other input receives a reference voltage. The error amplifier controls the power FET to maintain a constant output voltage.

[0005] Such voltage regulators can be used to power various components of electronic devices such as systems on chips and analog-to-digital converters. For some of these components, it is expected that the LDO regulator can both sink and pull current from or to the output node to produce a high-precision signal output to the output node. In addition, it is expected that the error amplifier has a DC characteristic of low power requirement and low offset, and an AC characteristic of high gain. Therefore, it is expected that there will be further improvements in this range. Summary of the invention

[0006] This Summary is provided to introduce selected concepts that are further described below in the Detailed Description. This Summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used to help limit the scope of the claimed subject matter.

[0007] One aspect is directed to a low voltage dropout amplifier. The low voltage dropout amplifier may include an error amplifier having first and second inputs coupled to a reference signal and a feedback signal, respectively. The error amplifier may be configured to generate first and second error signals at first and second outputs, respectively, wherein the first and second error signals are based on a difference between the reference signal and the feedback signal. A sink stage may be coupled to the first output and configured to generate a sink current based on the first error signal. A pull stage may be coupled to the second output and configured to generate a pull current based on the second error signal. An output node may be coupled to receive the sink current and the pull current.

[0008] Another aspect is directed to an error amplifier. The error amplifier may include a differential input stage including a first input coupled to receive a first signal, a second input coupled to receive a second signal, and a tail. The differential input stage may be configured to generate a comparison signal based on a difference between the first and second signals. At least one gain stage may be coupled to the differential input stage and may be configured to amplify the comparison signal. The differential output stage may have a first and a second output, and may be configured to generate first and second error signals at the first output and the second output based on the comparison signal. The differential output stage may have a first and a second voltage drop circuit. The differential output stage may also have a first output stage transistor having a first conductive terminal coupled to the tail and the first output, a second conductive terminal coupled to at least one gain stage and the second output, and a control terminal coupled to the first voltage drop circuit. The differential output stage may further include a second output stage transistor having a first conductive terminal coupled to the tail and the first output, a second conductive terminal coupled to at least one gain stage and the second output, and a control terminal coupled to the second voltage drop circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic block diagram of a low voltage dropout amplifier according to the present disclosure.

[0010] Figure 2 yes Figure 1 Schematic block diagram of the error amplifier in FIG.

[0011] Figure 3 yes Figure 1 A schematic block diagram of an improvement of a low voltage dropout amplifier in the invention includes an amplifier stage between sink and source transistors and a sink and source current mirror. DETAILED DESCRIPTION

[0012] One or more embodiments of the present disclosure will be described below. These described embodiments are merely examples of currently disclosed technologies. In addition, in order to provide a concise description, all features of the actual implementation may not be described in the specification. It should be appreciated that in the development of all such actual implementations (as in any engineering or design project), numerous implementation-specific decisions may be made to achieve the specific goals of the developer, such as may vary from implementation to implementation to comply with system-related and business-related constraints. In addition, it should be appreciated that such development work may be complex and time-consuming, but for those of ordinary skill in the art who want to benefit from the present disclosure, it will be a routine task in design, production, and manufacturing.

[0013] When introducing elements of various embodiments of the present disclosure, the articles "a", "an", and "the" are intended to mean that there are one or more elements. When referring to transistors, it should be noted that the terms "first conductive terminal" and "second conductive terminal" do not refer to structure or bias, and are instead merely labels. "First conductive terminal" is used to refer to the conductive terminal of the transistor closest to the top of the page on which the accompanying drawings appear, while "second conductive terminal" is used to refer to the conductive terminal of the transistor closest to the bottom of the page on which the accompanying drawings appear. The terms "first conductive terminal" and "second conductive terminal" may be referred to as source and drain, respectively, and this need not remain consistent between transistors. For example, the "first conductive terminal" of one transistor may be a source, while the "first conductive terminal" of another transistor may be a drain.

[0014] First refer to Figure 1 , a voltage regulator 100 for an electronic device is now described. The electronic device may be a tablet, a smartphone, a smart watch, or any suitable device, and in some applications may be powered by a battery (not shown). The voltage regulator 100 may be configured as a low dropout regulator and has both current sinking and current sourcing capabilities.

[0015] The voltage regulator 100 includes an error amplifier 200 coupled between a first power supply Vcc and a ground GND. The error amplifier 200 has first and second inputs coupled to a reference signal Vref and a feedback signal FBK, respectively. The reference signal Vref is not affected by temperature and can be generated by, for example, a bandgap generator (not shown). The feedback signal FBK is provided from a feedback node 105 to which the first, second and third feedback networks 106, 108 and 110 are coupled.

[0016] The error amplifier 200 generates first and second differential error signals Verr1, Verr2 at first and second outputs, EA_out_p, EA_out_n, respectively, and these error signals are based on the difference between the reference signal Vref and the feedback signal FBK. The first feedback network 106 is coupled between the first output of the error amplifier 200 and the feedback node 105, and includes a capacitor Cz2 and a resistor Rz2 connected in series. Similarly, the second feedback network 108 is coupled between the second output of the error amplifier 200 and the feedback circuit node 105, and includes a capacitor Cz1 and a resistor Rz1 connected in series. The third feedback network 110 is coupled between the output node Vout and the feedback node 105. The feedback signal BNK is coupled to the top node TP of the network 110.

[0017] The load, represented by Rload, is coupled between the output node Vout and the ground GND. The third feedback network 110 (as mentioned above) is coupled between the output node Vout and the feedback node 105, and is connected in parallel with the load Rload. The third feedback network 110 includes first and second resistors R1, R2 connected in series. The load capacitor Cload and the resistor ESR representing its equivalent series resistance are coupled in series with each other, and are coupled in parallel with the load Rload and the third feedback network 110.

[0018] The voltage regulator 100 includes a first transistor M14 and a second transistor M10. The first transistor M14 is controlled by a first error signal Verr1 and generates a first current. The sink stage 104 is coupled to the first transistor M14 to receive the first current and mirror the first current to generate a sink current applied to the output node Vout. The second transistor M10 is controlled by a second error signal Verr2 and generates a second current. The pull stage 102 is coupled to the second transistor M10 to receive the second current and mirror the second current to generate a pull current applied to the output node Vout.

[0019] The pull stage 102 outputs a source current based on a feedback signal FBK indicating that the current through the load Rload is within a threshold value of zero or greater than zero, and if the feedback signal FBK indicates that the current through the load Rload is less than zero, the pull stage 102 is turned off. The sink stage 104 draws a sink current based on a feedback signal FBK indicating that the current through the load Rload is within a threshold value of zero or greater than zero. Similarly, if the feedback signal FBK indicates that the current through the load Rload is greater than zero, the sink stage 104 is turned off.

[0020] The first transistor M14 has a first conduction terminal and a body terminal both coupled to the first power source Vcc, a second conduction terminal coupled to the sink stage 104 , and a control terminal coupled to the first output of the error amplifier 200 to receive the first error signal Verr1 .

[0021] The sink stage 104 includes transistors M17 and M18 configured as a current mirror that transfers a first current to a second conductive terminal of the first transistor M14 and draws the first current from the output node Vout. A current limiting resistor Rlim1 (limiting the first current) is coupled in series between the second conductive terminal of the first transistor M14 and the current mirror formed by the transistors M17 and M18.

[0022] The transistor M17 has a first conductive terminal coupled to the current limiting resistor Rlim1, a second conductive terminal and a body terminal both coupled to the ground GND, and a control terminal coupled to the first conductive terminal. The transistor M18 has a first conductive terminal coupled to the output node Vout, a second conductive terminal and a body terminal both coupled to the ground GND, and a control terminal coupled to the control terminal of the transistor M17.

[0023] In more detail, the second transistor M10 has a first conduction terminal coupled to the pull stage 102 , a second conduction terminal and a body terminal both coupled to the ground GND, and a control terminal coupled to the second output of the error amplifier 200 to receive the second error signal Verr2 .

[0024] The pull-up stage 102 includes transistors M15, M16 configured as a current mirror that receives a second current from a first conductive terminal of the second transistor M10 and mirrors the second current to an output node Vout. A current limiting resistor Rlim2 (limiting the second current) is coupled in series between the first conductive terminal of the second transistor M10 and the current mirror formed by the transistors M15, M16.

[0025] The transistor M15 has a first conductive terminal and a body terminal both coupled to the second power source Vbatt, a second conductive terminal coupled to the current limiting resistor Rlim2 to receive the second current, and a control terminal coupled to the second conductive terminal. The transistor M16 has a first conductive terminal and a body terminal both coupled to the second power source Vbatt, a second conductive terminal coupled to the output node Vout, and a control terminal coupled to the control terminal of the transistor M15.

[0026] Reference Figure 2, details of the error amplifier 200 are now given. The error amplifier 200 includes a differential input stage 202, which includes first and second inputs that receive a reference voltage Vref and a feedback signal FBK, respectively (as mentioned above). The differential input stage 202 generates a comparison signal based on the difference between the reference voltage Vref and the feedback signal FBK. The tail 204 is coupled to the differential input stage 202 and mirrors a constant current from the current source CS1 to the differential input stage 202 and to the differential output stage 210 to be described below. The first gain stage 206 or active load circuit is coupled to the differential input stage 202 and amplifies the comparison signal. The second gain stage 208 is coupled to the first gain stage 206 and further amplifies the comparison signal.

[0027] The differential output stage 210 is coupled to the second gain stage 208 and generates and outputs first and second error signals Verr1, Verr2 on first and second outputs EA_out_p, EA_out_n based on the amplified comparison signal. The compensation stage 212 is coupled between the second gain stage 208 and the differential output stage 210 and compensates the amplified comparison signal as understood by those skilled in the art.

[0028] In more detail, the differential input stage 202 includes transistors M1, M2, whose first conductive terminals and their body terminals are coupled to each other. The body terminals of the transistors M1, M2 are also coupled to the first power source Vcc. The second conductive terminals of the transistors M1, M2 are respectively coupled to the first conductive terminals of the transistors M3, M4 constituting the first gain stage 206 (as will be explained below). The control terminals of the transistors M1, M2 are respectively coupled to the reference voltage Vref and the feedback signal FBK.

[0029] The first gain stage 206 or active load stage includes transistors M3, M4, whose first conduction terminals are coupled to second conduction terminals of transistors M1, M2, respectively. Transistors M3, M4 also have second conduction terminals and body terminals, both coupled to ground GND, and control terminals coupled to each other and to the first conduction terminal of transistor M4.

[0030] The second gain stage 208 includes a transistor M8 having a first conduction terminal coupled to the differential output stage 210, a second conduction terminal and a body terminal both coupled to the ground GND, and a control terminal coupled to the first conduction terminal of the transistor M3.

[0031] Tail 204 includes transistors M5, M6, which have first conductive terminals and body terminals that are both coupled to a first power source Vcc, and control terminals that are coupled to each other. Transistor M5 has a second conductive terminal coupled to a control terminal of transistors M5, M6 and a current source CS1. Transistor M6 has a second conductive terminal coupled to the first conductive terminals of transistors M1, M2. Transistor M7 has a first conductive terminal and a body terminal coupled to the first power source Vcc, a second conductive terminal coupled to the differential output stage 210, and a control terminal coupled to the control terminals of transistors M5, M6.

[0032] The differential output stage 210 includes transistors M12, M16 having a first conductive terminal coupled to the second conductive terminal of transistor M7 to receive a constant current therefrom, and a second conductive terminal coupled to the first conductive terminal of transistor M8. The first and second conductive terminals of transistors M12, M16 are also coupled to a compensation network 212. The body terminal of transistor M12 is coupled to ground GND, while the body terminal of transistor M16 is coupled to a first power source Vcc. The control terminal of transistor M12 is coupled to a voltage drop circuit 216, while the control terminal of transistor M16 is coupled to a first voltage drop circuit 214.

[0033] The first voltage drop circuit 214 includes a diode coupled pair of transistors M13, M15 coupled in series with the second current source CS2 to draw a constant current therethrough. The second voltage drop circuit 216 includes a diode coupled pair of transistors M11, M9 coupled in series with the third current source CS3 to receive a constant current therethrough.

[0034] The differential output stage 210 includes a first output for outputting a first error signal Verr1 and coupled to first conduction terminals of transistors M12 and M16. The differential output stage 210 also includes a second output for outputting a second error signal Verr2 and coupled to second conduction terminals of transistors M12 and M16.

[0035] If now refer to Figure 3 As described, in some applications, the amplifier stage 300 can be coupled between the first and second transistors M14, M10 and the sink and source current mirror formed by the transistors M17, M18 and M15, M16. This amplifier stage 300 can help reduce the breakdown current through the transistors M16, M18. Figure 3 As shown, those skilled in the art will appreciate that the amplifier stage is a class AB amplifier.

[0036] Here, a pair of resistors R3, R4 are coupled in series between the second conductive terminal of the first transistor M14 and the first conductive terminal of the second transistor M10. The amplifier stage 300 includes a pair of resistors R5, R6 coupled in series between the first power source Vcc and the ground GND. The transistor M20 has a first conductive terminal coupled to the fourth current source CS4, a second conductive terminal coupled to the first conductive terminal of the transistor M22, a control terminal coupled to its own first conductive terminal and the control terminal of the transistor M21, and a body terminal coupled to its own second conductive terminal.

[0037] The transistor M22 has a first conductive terminal coupled to the second conductive terminal of the transistor M20, a second conductive terminal coupled to the fifth current source CS5, a control terminal coupled to its own second conductive terminal and the control terminal of the transistor M23, and a body terminal coupled to the first power source Vcc. The transistor M21 has a first conductive terminal coupled to the second conductive terminal of the transistor M19 (to be explained below), a second conductive terminal coupled to the first conductive terminal of the transistor M23, a control terminal coupled to the control terminal of the transistor M20, and a body terminal coupled to its own second conductive terminal. The transistor 23 has a first conductive terminal coupled to the second conductive terminal of the transistor M21, a second conductive terminal coupled to the sink stage 104, a control terminal coupled to the control terminal of the transistor M22, and a body terminal coupled to the first power source Vcc.

[0038] A second conduction terminal of transistor M20 and a first conduction terminal of transistor M22 are coupled to a node between resistors R5, R6. A second conduction terminal of transistor M21 and a first conduction terminal of transistor M23 are coupled to a node between resistors R3, R4.

[0039] Refer to Figure 1 and Figure 2 Now, the calculation of the AC parameters of the electronic device 100 is described. When the pull-up stage 102 is turned on and the sink stage 104 is turned off, the loop gain can be calculated as follows:

[0040] A EA(EA_out_n) ≈g M1 (r M1 ||r M3 ) M8 r M8 (1)

[0041]

[0042] When both the pull-up stage 102 and the sink stage 104 are turned on, the loop gain can be calculated as follows:

[0043]

[0044] A EA(EA_out_n) =g M1 (r M1 ||r M3 ) M8 r EA_out_n (4)

[0045] i M12 =i M16 (5)

[0046] g M16 v EA_out_p =g M12 v EA_out_n (6)

[0047]

[0048]

[0049] When the sink stage 104 is turned on and the pull stage 102 is turned off, the loop gain can be calculated as follows:

[0050] A EA(EA_out_p) ≈g M1 (r M1 ||r M3 ) M8 r M7 (9)

[0051]

[0052] While the present disclosure has been described with reference to a limited number of embodiments, those skilled in the art having benefit of this disclosure will appreciate that other embodiments can be conceived which do not depart from the scope of what is disclosed herein. Accordingly, the scope of the present disclosure should be limited only by the appended claims.

Claims

1. A method of operating a low dropout (LDO) circuit, comprising: generating first and second error signals at first and second outputs of the error amplifier based on a difference between a reference signal and a feedback signal received at first and second inputs of the error amplifier; generating a sink current based on the first error signal indicating that a current through a load of the LDO circuit is negative; applying the sink current to an output of the LDO circuit; generating a source current based on the second error signal indicating that a current through a load of the LDO circuit is positive; applying the source current to an output of the LDO circuit; as well as The error amplifier comprises: an n-channel output stage transistor having a drain coupled to the first output, a source coupled to the second output to allow conduction between the first output and the second output in a first direction, and a gate coupled to a second voltage drop circuit; and A p-channel output stage transistor has a source coupled to the first output, a drain coupled to the second output to allow conduction between the first output and the second output in a second direction opposite to the first direction, and a gate coupled to a first voltage drop circuit.

2. The method according to claim 1, further comprising: Class AB amplification of the sink current is applied.

3. The method according to claim 2, further comprising: Class AB amplification of the source current is applied.

4. The method of claim 1 , wherein generating the first error signal and the second error signal comprises: generating a comparison signal based on a difference between the reference signal and the feedback signal; amplifying the comparison signal; as well as The first error signal and the second error signal are generated according to the amplified comparison signal. The method of claim 1 , further comprising limiting the sink current. The method of claim 5 , further comprising limiting the source current.

7. A low voltage difference amplifier, comprising: an error amplifier having first and second inputs coupled to a reference signal and a feedback signal, respectively, and configured to generate first and second error signals at first and second outputs, respectively, the first and second error signals being based on a difference between the reference signal and the feedback signal; a sink stage coupled to the first output and configured to generate a sink current based on the first error signal; a pull stage coupled to the second output and configured to generate a pull current based on the second error signal; as well as an output node coupled to receive the sink current and the source current; The levels include: a transistor having a control terminal coupled to the first output to receive the first error signal, a first conduction terminal coupled to a first power supply node, and a second conduction terminal, the transistor being configured to generate a current from the second conduction terminal of the transistor based on the first error signal; and a sink current mirror coupled to the second conductive terminal of the transistor and the output node and configured to mirror the current to the output node as the sink current; The pull levels include: a transistor having a control terminal coupled to the second output to receive the second error signal, a first conduction terminal coupled to a second power supply node, and a second conduction terminal, the transistor being configured to generate a current from the second conduction terminal of the transistor based on the second error signal; and a source current mirror coupled to the second conductive terminal of the transistor and the output node and configured to mirror the current to the output node as the source current; and a class AB amplifier stage coupled between the transistor of the sink stage and the sink current mirror, and coupled between the transistor of the pull stage and the source current mirror; The error amplifier comprises: an n-channel output stage transistor having a drain coupled to the first output, a source coupled to the second output to allow conduction between the first output and the second output in a first direction, and a gate coupled to a second voltage drop circuit; and A p-channel output stage transistor has a source coupled to the first output, a drain coupled to the second output to allow conduction between the first output and the second output in a second direction opposite to the first direction, and a gate coupled to a first voltage drop circuit.

8. The low voltage dropout amplifier of claim 7, wherein the class AB amplifier stage comprises: a first resistor and a second resistor coupled in series between a first power source (Vcc) and ground; a first transistor (M20) having a first conduction terminal coupled to a fourth current source, a second conduction terminal coupled to the first conduction terminal of the third transistor, a control terminal coupled to the first conduction terminal of the first transistor and a control terminal of the second transistor, and a body terminal coupled to the second conduction terminal of the first transistor; a second transistor (M21) having a first conductive terminal coupled to the second conductive terminal of the fifth transistor (M19), a second conductive terminal coupled to the first conductive terminal of the fourth transistor (M23), and a control terminal coupled to the control terminal of the first transistor, and a body terminal coupled to the second conductive terminal of the second transistor (M21); the third transistor (M22) having a first conductive terminal coupled to the second conductive terminal of the first transistor, a second conductive terminal coupled to a fifth current source, a control terminal coupled to the second conductive terminal of the third transistor and a control terminal of a fourth transistor (M23), and a body terminal coupled to a first power source (Vcc); as well as A fourth transistor (M23) has a first conductive terminal coupled to the second conductive terminal of the second transistor, a second conductive terminal coupled to the sink stage, a control terminal coupled to the control terminal of the third transistor, and a body terminal coupled to a first power source (Vcc).

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