High Speed ​​Open Loop Switch Mode Boost Converter

Abstract

An open-loop switch-mode boost converter includes a switching signal generator circuit that receives a time-varying input signal and outputs a switching signal. The duty cycle of the switching signal has a first nonlinear relationship with the amplitude of the time-varying input signal. An amplifier receives the switching signal and outputs a time-varying output signal, the amplitude of the time-varying output signal has a second nonlinear relationship with the duty cycle of the switching signal. The time-varying output signal has a linear relationship with the time-varying input signal based on the first nonlinear relationship and the second nonlinear relationship. A filter circuit receives the time-varying output signal and outputs a filtered time-varying output signal, the maximum frequency component of the filtered time-varying output signal being substantially the same as the maximum frequency component of the time-varying input signal. The switching signal generator circuit is isolated from the voltage output node and the filter output node.

Description

[0001] Related Applications

[0002] This application claims the benefit of U.S. Non-Provisional Patent Application No. 15 / 879,284, filed on January 24, 2018, and entitled “High-Speed ​​Open-Loop Switch-Mode Boost Converter”; which application is incorporated herein by reference for all purposes. Background Art

[0003] Some systems that amplify high bandwidth signals use a first power converter circuit (usually a switch mode boost power converter) to boost the DC voltage to a fixed high voltage rail. The fixed high voltage rail is used as the input voltage of the second power converter circuit. The second power converter circuit is suitable for amplifying time-varying signals with high maximum frequency components or signal bandwidth. The second power converter is typically implemented as a linear power converter circuit, and in some cases, as a switch mode buck converter circuit. In such an embodiment, the second power converter circuit receives the time-varying signal and reduces the input voltage of the fixed high voltage rail to generate an amplified form of the time-varying signal.

[0004] In the case where the second power converter circuit is a switch-mode buck converter, the time-varying output signal of the switch-mode buck converter is linearly related to the fixed input voltage of the buck converter as a function of the duty cycle of the switching signal. Due to this linear relationship, the switch-mode buck converter can be implemented without a feedback loop, thereby increasing the signal bandwidth of the second power converter circuit. In contrast, the first power converter circuit, when implemented as a switch-mode boost power converter, has a nonlinear relationship between its output voltages as a function of the duty cycle of the switching signal. Because of this nonlinear relationship, a typical switch-mode boost power converter circuit cannot usually be configured without a feedback loop. Summary of the invention

[0005] In some embodiments, a high-speed open-loop switch-mode boost ("open-loop") converter includes a switch signal generator circuit for generating a switch signal. The switch signal generator circuit includes a signal input node for receiving a time-varying input signal, and a switch signal output node for outputting the switch signal. The duty cycle of the switch signal has a first nonlinear relationship with the amplitude of the time-varying input signal. The open-loop converter includes a switch-mode boost amplifier ("amplifier") circuit, which includes an input voltage node for receiving an input voltage, a switch driver input node connected to the switch signal output node for receiving the switch signal, and a signal output node for outputting a time-varying output signal. The amplitude of the time-varying output signal has a second nonlinear relationship with the duty cycle of the switch signal, and the time-varying output signal has a linear relationship with the time-varying input signal based on the first nonlinear relationship and the second nonlinear relationship. The open-loop converter also includes a filter circuit having a filter input node connected to the signal output node of the amplifier circuit to receive the time-varying output signal and a filter output node for outputting a filtered time-varying output signal. The order of the filter circuit is higher than that of a second-order filter. The switching signal generator circuit is communicatively isolated from the voltage output node and the filter output node. The time-varying input signal has a first maximum frequency component that is significantly greater than DC, and the filtered time-varying output signal has a second maximum frequency component that is substantially the same as the first maximum frequency component.

[0006] In some embodiments, a method for amplifying a time-varying signal includes receiving a time-varying input signal at a signal input node of a switch signal generator circuit. Using the switch signal generator circuit to generate a switch signal, the duty cycle of the switch signal has a first nonlinear relationship with the amplitude of the time-varying input signal. The switch signal is output from a switch signal output node of the switch signal generator circuit and received at a switch driver input node of a switch mode boost amplifier ("amplifier") circuit. An input voltage is received at an input voltage node of the amplifier circuit. The amplifier circuit outputs a time-varying output signal from a signal output node of the amplifier circuit, the amplitude of the time-varying output signal has a second nonlinear relationship with the duty cycle of the switch signal, and the time-varying output signal has a linear relationship with the time-varying input signal based on the first nonlinear relationship and the second nonlinear relationship. The time-varying output signal is received from the signal output node of the amplifier circuit at a filter input node of a filter circuit, the order of the filter circuit being higher than a second order filter. The filtered time-varying output signal is output from a filter output node of the filter circuit. The switch signal generator circuit is isolated from the voltage output node and the filter output node in communication. The time-varying input signal has a first maximum frequency component that is significantly greater than DC. The filtered time-varying output signal has a second maximum frequency component that is substantially the same as the first maximum frequency component. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a simplified circuit diagram of a prior art switch-mode boost converter.

[0008] Figure 1B A simplified signal timing diagram associated with a prior art switch-mode boost converter is shown.

[0009] FIG. 2A to FIG. 2B is a simplified circuit diagram of a high speed open loop switch mode boost converter according to some embodiments.

[0010] FIG. 3A to FIG. 3D is a simplified circuit diagram providing details of a switching signal generator circuit for a high speed open loop switch mode boost converter according to some embodiments.

[0011] Figure 3E A simplified signal timing diagram associated with a high speed open loop switch mode boost converter is shown according to some embodiments.

[0012] Figure 4A is a simplified circuit diagram providing details of a filter circuit for a high speed open loop switch mode boost converter according to some embodiments.

[0013] Figure 4B is a simplified transfer function of a filter circuit of a high speed open loop switch mode boost converter according to some embodiments.

[0014] Figure 5 is a simplified circuit diagram of a multi-phase open-loop switch-mode boost converter according to some embodiments.

[0015] Figure 6 is a simplified circuit diagram of a high speed open loop switch mode boost converter according to some embodiments.

[0016] Figure 7 is a simplified circuit diagram of a radio frequency (RF) amplifier implemented using a high speed open loop switch mode boost converter according to some embodiments.

[0017] Figure 8 is a simplified circuit diagram of an audio amplifier implemented using a high-speed open-loop switch-mode boost converter in accordance with some embodiments. DETAILED DESCRIPTION

[0018] Some embodiments described herein provide a high speed open loop switch mode boost ("open loop") converter for amplifying a time-varying signal. In some embodiments, the open loop boost converter receives a time-varying input signal and generates a filtered time-varying output signal that advantageously: i) has a substantially linear relationship with the time-varying input signal, and ii) has a maximum frequency component significantly above DC that is substantially the same as the maximum frequency component of the time-varying input signal (e.g., the frequency component of the input signal is reproduced in the output signal).

[0019] In some embodiments, the open-loop converter generally includes a switching signal generator circuit. The switching signal generator circuit generates a switching signal based on a time-varying input signal. The duty cycle of the switching signal has a first nonlinear relationship with the time-varying input signal. The switching signal drives the switch of the switch-mode boost converter. Based on the switching signal, the switch-mode boost converter generates a time-varying output signal. When the second nonlinear relationship of the switch-mode boost converter is "cancelled" by the first nonlinear relationship, a linear relationship between the time-varying output signal and the time-varying input signal is caused. A high-order (e.g., greater than or equal to second order) filter circuit connected to the output of the switch-mode boost converter substantially passes the frequency components of the time-varying input signal present in the time-varying output signal. The high-order filter circuit also substantially attenuates the frequency of the maximum frequency component of the time-varying input signal present in the time-varying output signal. As will be discussed, such an embodiment can advantageously simplify and improve the power efficiency of circuits that typically require two or more power converters, such as envelope tracking circuits used in radio frequency (RF) amplifier circuits.

[0020] Some systems that amplify high-bandwidth signals use a first power converter circuit (typically a switch-mode boost power converter) to boost a DC voltage to a fixed high-voltage rail. The fixed high-voltage rail is used as an input voltage Vin for a second power converter capable of amplifying the high-bandwidth signal. Such a second converter includes a linear power converter and, in some cases, a switch-mode buck converter. The second power converter circuit receives the high-bandwidth signal and steps down the input voltage of the high-voltage rail to generate an amplified form of the high-bandwidth signal.

[0021] In the case where the second power converter is a switch-mode buck converter, the output voltage Vout of the converter is linearly related to the input voltage Vin of the converter as a function of the converter switching duty cycle D, the relationship being:

[0022] Vout=D×Vin (Equation 1).

[0023] Because Vout is linearly related to Vin, the switch-mode buck converter can be configured without a feedback loop to increase the signal bandwidth of the second power converter circuit.

[0024] In contrast, when implemented as a switch-mode boost power converter, the output voltage Vout of the boost converter of the first power converter and the input voltage Vin of the boost converter have a nonlinear relationship as a function of the switching duty cycle D, which is:

[0025]

[0026] Due to the non-linear relationship shown in Equation 2, a typical switch-mode boost power converter circuit is not usually configured without a feedback loop.

[0027] For example, Figure 1A A simplified circuit diagram of a prior art switch-mode boost power converter ("converter") 100 is shown. The converter 100 receives a fixed input voltage Vin at an input voltage node 102 and generates a boosted DC voltage Vout at an output voltage node 104 to provide power to a load 119. The converter 100 typically includes a comparator circuit 106, a ramp circuit 108, an error amplifier 110, a pulse generator circuit 114, a switch driver circuit 118, a compensator circuit 121, a switch S1, an inductor L1, an output rectifier (e.g., a diode D1), and a capacitor C1. The converter 100 also typically includes a feedback loop 112, which includes the error amplifier 110 and the compensator circuit 121.

[0028] The comparator circuit 106 receives a ramp signal Vramp from the ramp circuit 108. The comparator circuit 106 performs a comparison between the ramp signal Vramp and the control signal Vc received from the error amplifier 110 on the feedback loop 112. The compensator circuit 121 is connected to the error amplifier 110. The error amplifier 110 compares the reference voltage Vref with the (usual) scaled value of the boost voltage Vout (received from the compensator circuit 121) and amplifies the error between Vref and the scaled value of the boost voltage Vout to generate the control signal Vc. The comparison result from the comparator circuit 106 is passed to the pulse generator circuit 114 (e.g., a Schmitt trigger). The pulse generator circuit 114 generates well-defined pulses (e.g., pulses with a minimum pulse width and well-defined pulse edges) based on the comparison result. These pulses form a pulse width modulation (PWM) signal Vpwm at the signal node 116. The PWM signal Vpwm is received at the switch driver input node of the switch driver circuit 118. The switch driver circuit 118 buffers, level shifts, or otherwise adjusts the PWM signal Vpwm to form a suitable gate drive signal to turn switch S1 on and off. When switch S1 is turned on, switch S1 conducts current from the high side of switch S1 to the low side of switch S1. In some embodiments, switch S1 is a field effect transistor (FET). In some embodiments, switch S1 is a power FET. In some embodiments, switch S1 is an n-FET or a p-FET. The high side of switch S1 is connected to the input voltage node 102 through an inductor L1. The low side of switch S1 is connected to a ground node or another bias voltage (e.g., Vss). The high side of switch S1 is also connected to a load through an output rectifier, which is connected to a load at Figure 1A The boost voltage Vout is implemented as a diode D1. Capacitor C1 connects the output voltage node 104 to ground or other bias voltage node. Capacitor C1 generally filters out non-DC frequency components of the boost voltage Vout (eg, passes DC and substantially blocks non-DC frequencies). The boost voltage Vout is received at a load 119.

[0029] As discussed with reference to Equation 2, Vout is nonlinearly related to Vin as a function of the duty cycle D of the PWM signal Vpwm. However, because the feedback loop 112 continuously adjusts the PWM signal Vpwm to minimize the difference between the scaled value of the boost voltage Vout and the reference voltage Vref, the boost voltage Vout will ideally converge to a desired voltage value that is linearly proportional to the reference voltage Vref. However, the circuit elements of the feedback loop 112 (including the compensator circuit 121 and the error amplifier 110) slow down the response time of the feedback loop 112. This slowed response time limits the maximum frequency at which the amplitude of Vc and / or Vin changes and the converter 100 can still reproduce the corresponding (but scaled) amplitude change in the boost voltage Vout. Therefore, the feedback loop 112 is said to limit the bandwidth of the converter 100.

[0030] Figure 1B The simplified signal timing diagram 120 shows the Figure 1A The comparator circuit 106 receives the ramp signal Vramp 122 and the control signal Vc 124 . Figure 1B The simplified signal timing diagram 140 of FIG. 1 shows a PWM signal Vpwm 142 generated from a ramp signal Vramp 122 and a control signal Vc 124 via the comparator circuit 106 and the pulse generator circuit 114. In the example shown, for simplicity, the control signal Vc 124 is shown as constant over time t. However, it should be understood that the control signal Vc 124 may change over time.

[0031] The ramp signal Vramp 122, and by extension the PWM signal Vpwm 142, are shown to have a period T1. The duration that the ramp signal Vramp 122 is below the control signal Vc 124 is designated as duration T1'. Figure 1A The comparison value output by the comparator circuit 106 is positive when the control signal Vc 124 is greater than the ramp signal Vramp 122, and is negative (or zero) when the control signal Vc 124 is less than the ramp signal Vramp 122. The pulse generator circuit 114 receives the comparison value and generates a pulse (e.g., 144) based on the received comparison value. Therefore, the pulse width of the pulse 144 is also the duration T1'. The ratio of the pulse duration T1' to the period T1 is the duty cycle D of the PWM signal Vpwm 142 of the period. As shown in Equation 2, for a fixed input voltage Vin, as the duty cycle D increases and decreases, the boost output voltage Vout also increases and decreases nonlinearly, respectively. The nonlinear relationship is Figure 1B160. As shown, for a fixed input voltage Vin 164, the boost output voltage Vout 162 is a nonlinear function of the duty cycle D of the PWM signal Vpwm 142. Due to this nonlinearity, a switch-mode boost power converter typically requires the use of a feedback loop when used as a signal or voltage amplifier. However, as previously described, the feedback loop 112 limits the upper signal bandwidth that can be reproduced by the converter 100.

[0032] Figure 2A A simplified circuit diagram of a high speed open loop switch mode boost converter ("open loop converter") 240 with linear signal characteristics according to some embodiments is shown. Like numbered elements of the open loop converter 240 may have the same Figure 1A 1 and 2. The corresponding like numbered elements of the converter 100 are similarly described, but design considerations may cause the actual implementation of these elements to be presented differently in the two circuits. Generally, the open-loop converter 240 includes a switching signal generator circuit 242, a switch-mode boost amplifier ("amplifier") circuit portion 243, and a filter circuit 244 to provide power to a load 246. The amplifier circuit portion 243 generally includes an input voltage node 102, a switch driver circuit 118, a switch S1, an inductor L1, a signal output node 252, and an output rectifier implemented here as a diode D1. Figure 2A Some elements of the open-loop converter 240 are omitted in order to simplify the description of the open-loop converter 240 , but these elements are understood to be present. In some embodiments, the switch driver circuit 118 is part of the switch signal generator circuit 242 .

[0033] The open-loop converter 240 receives the time-varying input signal Vsig(t) at the signal input node 248 and generates the switching signal Vpwm'(t) at the output node 250. The duty cycle of the switching signal Vpwm'(t) has a nonlinear relationship with the amplitude of the time-varying input signal Vsig(t). In some embodiments, the relationship between the amplitude and the duty cycle is described as:

[0034]

[0035] Where D(t) is the duty cycle of the switching signal Vpwm'(t), which varies with time t according to the amplitude of the time-varying input signal Vsig(t), and K is a constant. The time-varying input signal Vsig(t) is a signal with rising and falling amplitudes that vary with time, resulting in a frequency component that is significantly greater than DC. In some embodiments, the signal bandwidth Vsig of the time-varying input signal Vsig(t) is BW Or the maximum frequency component fMAX(Vsig(t)) is 20 Hz to 20 kHz; in some embodiments, the signal bandwidth Vsig BWOr the maximum frequency component fMAX(Vsig(t)) is greater than 1 MHz, greater than 10 MHz, and in some embodiments, approximately 100 MHz. In some embodiments, the time-varying input signal Vsig(t) is a sinusoid. In some embodiments, the time-varying input signal Vsig(t) is a modulated sinusoid. In some embodiments, the time-varying input signal Vsig(t) is a signal having a time-varying amplitude, the time-varying amplitude having a frequency component up to and including fMAX(Vsig(t)). In some embodiments, the time-varying input signal Vsig(t) is an audio signal. In some embodiments, the time-varying input signal Vsig(t) is an envelope signal. In some embodiments, the time-varying input signal Vsig(t) is a communication signal or another signal suitable for amplification.

[0036] The switch driver circuit 118 receives the switch signal Vpwm'(t) at the switch driver input node and generates a suitable gate driver signal (such as reference Figure 1A The switch S1 is turned on and off by the switch 250 (described above), thereby generating a boosted time-varying output signal Vout'(t) at the signal output node 252. The time-varying output signal Vout'(t) has a nonlinear relationship with the duty cycle D(t) of the switching signal Vpwm'(t) (similar to the duty cycle of equation 2), which is expressed as:

[0037]

[0038] Therefore, by substituting the first nonlinear relationship of the duty cycle D(t) shown in Equation 3 into the second nonlinear relationship of the time-varying output signal Vout'(t) of Equation 4, it is shown that a linear relationship between the time-varying input signal Vsig(t), the time-varying output signal Vout'(t) and the filtered time-varying output signal VsigOut(t) is obtained. This linear relationship can be expressed as:

[0039] VsigOut(t)=K′×Vsig(t)+Vin (Formula 5),

[0040] The constant K' includes the constant K and the constant input voltage Vin.

[0041] The filter circuit 244 receives the time-varying output signal Vout′(t) at the signal output node 252 and substantially filters out signals with a bandwidth Vsig greater than the time-varying input signal Vsig(t). BWor a frequency component of the maximum frequency component fMAX(Vsig(t)) (e.g., its switching frequency and harmonics). The filter circuit 244 outputs the filtered time-varying output signal VsigOut(t) at the signal output node 254. The filtered time-varying output signal VsigOut(t) is received at the load 246. The filtered time-varying output signal VsigOut(t) advantageously has a signal bandwidth substantially the same as the signal bandwidth of the input signal Vsig(t), and has a maximum frequency component fMAX(VsigOut(t)) that is the same as the maximum frequency component fMAX(Vsig(t)) of the time-varying input signal Vsig(t). That is, both Vsig(t) and VsigOut(t) include a range of frequency components from a minimum frequency component to a maximum frequency component, and the ranges are substantially the same. This is in contrast to the converter 100, which substantially filters out non-DC frequency components of Vout (e.g., the switching frequency) due to the capacitor C1.

[0042] Because the open-loop converter 240 does not have a feedback loop (eg, Figure 1A The open-loop converter 240 is referred to as being communicatively isolated from the signal output nodes 252, 254 because the open-loop converter 240 is not isolated from the feedback loop 112 of the circuit. The two or more circuit nodes that are communicatively isolated do not receive significant current, voltage, or representation of current and voltage between the two or more circuit nodes (e.g., via galvanic isolation, optical isolation, or digital values). However, it should be understood that some insignificant current or voltage may exist between the two nodes due to undesirable inductive connections, ground loops, or other non-ideal factors. The lack of such a feedback loop advantageously enables the open-loop converter 240 to amplify signals with a higher bandwidth than the bandwidth of signals that the converter 100 can amplify.

[0043] In some embodiments, at least the switch signal generator circuit 242, the switch driver circuit 118, and the switch S1 are integrated into a signal integrated circuit (IC) package. In some embodiments, the IC package includes a semiconductor device that integrates multiple circuit elements of the open-loop converter 240. In some embodiments, the semiconductor device includes a substrate and an active layer formed on a monolithic substrate. The active layer includes all or part of the switch signal generator circuit 242, all or part of the switch driver circuit 118, and includes the switch S1. In some embodiments, the active layer is formed using silicon (Si). In some embodiments, the active layer is formed using silicon carbide (SiC). In other embodiments, the active layer is formed using other materials known in the art.

[0044] Figure 2BA simplified circuit diagram of a high speed open loop switch mode boost converter ("open loop converter") 260 with linear signal characteristics is shown in accordance with some embodiments, wherein a synchronous switch S2 is used as an output rectifier instead of a diode D1. The open loop converter 260 generally includes a Figure 2A Like numbered elements are shown and described. The switch driver circuit 262 is shown having a second signal output connected to the gate node of switch S2 to generally synchronously turn on switch S2 when switch S1 is turned off and turn off switch S2 when switch S1 is turned on. As is known in the art, replacing a diode output rectifier with an output rectifier of a synchronous switch can improve system efficiency.

[0045] Figure 3A 1 shows a simplified circuit diagram of an example implementation of a switch signal generator circuit 342 according to some implementations. In some implementations, Figure 2A and / or Figure 2B The switching signal generator circuit 242 shown in is implemented as a switching signal generator circuit 342. Typically, the switching signal generator circuit 342 generates a time-varying ramp signal Vramp'(t), which is used to generate a switching signal Vpwm'(t). The ramp signal Vramp'(t) is nonlinearly related to Vsig(t). At a high level, the switching signal generator circuit 342 includes a voltage-current conversion circuit portion 301, an integrator circuit portion 302, and a pulse generation circuit portion 303. Considering the time-varying input signal Vsig(t) received from the signal input node 248, these circuit portions 301, 302, 303 generate a switching signal Vpwm'(t) having a duty cycle D(t) according to Equation 3. In other embodiments, the switching signal generator circuit 242 / 342 includes other circuit portions suitable for generating a switching signal Vpwm'(t) having a duty cycle D(t) according to Equation 3.

[0046] Figure 3B A simplified circuit diagram of an example implementation of a switch signal generator circuit 342a according to some implementations is shown. In some implementations, Figure 2A and / or Figure 2B The switching signal generator circuit 242 shown in FIG. 2 is implemented as a switching signal generator circuit 342a. In the example embodiment shown, the switching signal generator circuit 342a includes a voltage-current conversion circuit portion 301a, an integrator circuit portion 302a, and a pulse generation circuit portion 303a. Considering the time-varying input signal Vsig(t) received from the signal input node 248, these circuit portions 301a, 302a, 303a generate a switching signal Vpwm'(t) having a duty cycle D(t) according to equation 3.

[0047] In the illustrated embodiment, the exemplary voltage-to-current conversion circuit portion 301a generally includes a switch S3 connected to a positive voltage node Vdd through a resistor R1. In some embodiments, the switch S3 is a field effect transistor (FET). In some embodiments, the switch S3 is an n-FET, a p-FET, or a bipolar junction transistor (BJT). As known in the art, other voltage-to-current conversion circuit portions suitable for generating a time-varying current based on a received time-varying voltage signal, a time-varying digital signal, or a static digital signal can be used for the voltage-to-current conversion portion described herein.

[0048] The integrator circuit portion 302a generally includes a capacitor C2 connected between the voltage-current conversion portion 301a and a ground node (or another bias voltage Vss), a switch S4 connected in parallel with the capacitor C2, and a switch control circuit 305 connected to a switch control node of the switch S4.

[0049] The pulse generation circuit portion 303a generally includes a comparator circuit 307 (which is similar to the comparator circuit 106), wherein a first input terminal is connected to a capacitor C2, a second input terminal is connected to a trigger level generation circuit 309 and is powered between a high voltage rail VcompH and a low voltage rail VcompL. The output of the comparator circuit 307 is connected to an input terminal of a pulse generator circuit 311 (which is similar to the pulse generator circuit 114). In some embodiments, the high voltage rail VcompH is Vdd, and the low voltage rail VcompL is a ground node (or another bias voltage Vss). In some embodiments, the comparator circuit 307 is suitable for generating well-defined pulses, and the pulse generator circuit 311 is optional. In some embodiments, the bias voltage node Vss is a ground node. In some embodiments, the bias voltage node Vss is another bias voltage.

[0050] When driven by the time-varying input signal Vsig(t), switch S3 provides a proportional time-varying current Isig(t) to the integrator circuit portion 302a. In the illustrated embodiment, the amplitude of the time-varying current Isig(t) is 180 degrees out of phase with the time-varying input signal Vsig(t). In other embodiments (e.g., Figure 3DAs shown in FIG. 3 ), the time-varying current Isig(t) is in phase with the time-varying input signal Vsig(t). The ramp signal Vramp'(t) is generated by the integrator circuit portion 302a. The time-varying current Isig(t) charges the capacitor C2 of the integrator circuit portion 302a; when triggered by the switch control circuit 305, the switch S4 discharges the capacitor C2 to the ground voltage node through the switch S4. The value of the capacitor C2 and the switching rate of the switch S4 are selected for the corresponding voltage-to-current conversion circuit portion 301a so that the frequency of the resulting ramp signal Vramp'(t) is at least twice greater than the maximum frequency of the time-varying input signal Vsig(t). By implementing the voltage-to-current conversion circuit portion 301a, the selected capacitance value of the capacitor C2, the discharge rate / time of the switch S4 as driven by the switch control circuit 305, and the discharge duty cycle of the switch S4 as driven by the switch control circuit 305, the frequency of the ramp signal Vramp'(t) can be selected at the design time. In some embodiments, when the switch S4 is turned on, the discharge period of the switch S4 is set to be equal to or greater than the duration for fully discharging the capacitor C2 to the ground node. Figure 3B In the example shown, the amplitude of the time-varying input signal Vsig(t) is 180 degrees out of phase with the corresponding amplitude of the generated ramp signal Vramp'(t). That is, the integrator circuit portion 302a as shown generates a ramp signal Vramp'(t) having a maximum ramp peak amplitude corresponding to the minimum amplitude of the time-varying input signal Vsig(t), and a minimum ramp peak amplitude corresponding to the maximum amplitude of the time-varying input signal Vsig(t).

[0051] The comparator circuit 307 receives the ramp signal Vramp'(t) at a first input terminal and compares the amplitude of the ramp signal Vramp'(t) with the amplitude of the trigger voltage Vtrig received from the trigger level generating circuit (Vtrigger) 309. The comparison result from the comparator circuit 307 is passed to the pulse generator circuit 311. The pulse generator circuit 311 generates well-defined pulses based on the comparison result. These pulses form the switching signal Vpwm'(t) at the output node 250.

[0052] In some embodiments, the components of circuit portions 301a, 302a are selected to generate a Vramp'(t) signal having a maximum ramp peak amplitude equal to or slightly less than the high voltage rail VcompH of comparator circuit 307, and a minimum ramp peak amplitude equal to or slightly greater than the low voltage rail VcompL of comparator circuit 307. In some embodiments, the amplitude of the trigger voltage Vtrig is set at design time to be greater than zero and less than or equal to the minimum ramp peak amplitude of the ramp signal Vramp'(t). In some embodiments, the trigger voltage Vtrig is set to a fixed percentage of the voltage rail of comparator circuit 307. In other embodiments, such as Figure 3C In the embodiment shown in , the magnitude of the trigger voltage Vtrig is determined during operation of the open-loop converter 240 / 260 .

[0053] Figure 3C A simplified circuit diagram of an example implementation of a switch signal generator circuit 342b according to some implementations is shown. In some implementations, Figure 2A / Figure 2B The switching signal generator circuit 242 shown in FIG. 1 is implemented as a switching signal generator circuit 342 b. The switching signal generator circuit 342 b generally includes a voltage-current conversion circuit portion 301 a, an integrator circuit portion 302 a, and a pulse generation circuit portion 303 b. The circuit elements with the same number correspond to those in reference 1. Figure 3B The same numbered circuit elements shown and discussed above. In the illustrated embodiment, a trigger level generating circuit (Vtrigger) 313 is connected to capacitor C2 to receive a ramp signal Vramp'(t). The trigger level generating circuit 313 detects the minimum ramp peak voltage amplitude and generates a trigger voltage Vtrig having an amplitude greater than zero and equal to or less than the detected minimum ramp peak voltage amplitude. Therefore, the amplitude of the trigger voltage Vtrig advantageously corresponds to a specific amplitude of the ramp signal Vramp'(t), rather than being set to an arbitrary amplitude, or setting the amplitude at design time. In some embodiments, detection occurs when the trigger level generating circuit 313 (e.g., from a self-control circuit or a reset control circuit, not shown) receives an external control signal En.

[0054] Figure 3D A simplified circuit diagram of an example implementation of a switch signal generator circuit 342c according to some implementations is shown. In some implementations, Figure 2A / Figure 2B The switching signal generator circuit 242 shown in FIG. 2 is implemented as a switching signal generator circuit 342c. The switching signal generator circuit 342c generally includes a voltage-current conversion circuit portion 301b, an integrator circuit portion 302a, and a pulse generating circuit portion 303a (or Figure 3CThe same numbered circuit elements correspond to the pulse generating circuit portion 303b shown in FIG. Figure 3B The same numbered circuit elements are shown and discussed. In the illustrated embodiment, the voltage-to-current conversion circuit portion 301 b is implemented using a current mirror topology, and the circuit portion 301 b generally includes resistors R2-4 and switches S5-7 connected as shown. In some embodiments, any of the switches S5-S7 can be an n-FET, a p-FET, an n-type power FET, a BJT, or a p-type power FET.

[0055] In the example shown, the amplitude of the time-varying input signal Vsig(t) is in phase with the corresponding amplitude of the generated ramp signal Vramp'(t). That is, the integrator circuit portion 302a generates a ramp signal Vramp'(t) having a maximum ramp peak amplitude corresponding to the maximum amplitude of the time-varying input signal Vsig(t) and a minimum ramp peak amplitude corresponding to the minimum amplitude of the time-varying input signal Vsig(t).

[0056] exist Figure 3E This correspondence is further illustrated in the simplified signal timing diagram 370 of FIG. Figure 3E shows the comparator circuit 307 ( Figure 3D ) received at the signal input node 248. The ramp signal Vramp'(t) 374 is generated based on the time-varying input signal Vsig(t) 372 received at the signal input node 248. In the example shown, the maximum peak amplitude of the ramp signal Vramp'(t) 374 corresponds to the maximum amplitude of the time-varying input signal Vsig(t) 372. The minimum peak amplitude of the ramp signal Vramp'(t) 374 corresponds to the minimum amplitude of the time-varying input signal Vsig(t) 372. Therefore, Vsig(t) 372 and Vramp'(t) 374 are in phase. As shown, the amplitude of the trigger voltage Vtrig 376 is equal to or less than the minimum peak amplitude of the ramp signal Vramp'(t) 374. In some embodiments, as shown in reference Figure 3B As discussed, the magnitude of the trigger voltage Vtrig 376 is set at design time. In other embodiments, such as reference Figure 3C As discussed, the amplitude of the trigger voltage Vtrig 376 is set based on a determination of the minimum generated peak amplitude of the ramp signal Vramp′(t) 374 .

[0057] Figure 3E The simplified signal timing diagram 380 shows the switching signal Vpwm'(t) 382, ​​which corresponds to the relationship between the ramp signal Vramp'(t) 374 and the trigger voltage Vtrig 376. Figure 1BIn contrast to the control signal Vc 124 described above, the trigger voltage Vtrig 376 does not change with time t. However, in a case similar to Figure 3C In the embodiment of the present invention, if the enable signal En is triggered again, a new trigger voltage Vtrig amplitude can be generated. The ramp signal Vramp'(t) 374 and the extended switch signal Vpwm'(t) 382 are shown to have a period T2. The example duration of the ramp signal Vramp'(t) 374 being greater than the trigger voltage Vtrig 376 is designated as the duration T2'. In some embodiments, when the amplitude of the ramp signal Vramp'(t) 374 is greater than the trigger voltage Vtrig 376, the comparator circuit 307 outputs a positive value. The pulse generator circuit 311 receives the comparison value and generates a pulse (e.g., 384) based on the received comparison value. Therefore, the pulse width of the pulse 384 is also the duration T2'. The ratio of the pulse duration T2' to the period T2 is the duty cycle D(t) of the switch signal Vpwm'(t) of the period. The time-varying duty cycle D(t) of the switch signal Vramp'(t) is according to Equation 3.

[0058] like Figure 3E As shown in the simplified timing diagram 390, by substituting the first nonlinear relationship of the duty cycle D(t) shown in Equation 3 into the second nonlinear relationship of the time-varying output signal Vout'(t) in Equation 4, a linear relationship 392 between the time-varying input signal Vsig(t) and the time-varying output signal VsigOut(t) is obtained.

[0059] In some embodiments, the period T2 of the ramp signal Vramp'(t) is selected so that the frequency of the ramp signal Vramp'(t) is two or more times greater than one or both of the maximum frequency component fMAX(Vsig(t)) of the time-varying input signal Vsig(t) or the signal bandwidth VsigBW. In some embodiments, the period T2 of the ramp signal Vramp'(t) is selected so that the frequency of the ramp signal Vramp'(t) is eight or more times greater than one or both of the maximum frequency component fMAX(Vsig(t)) of the time-varying input signal Vsig(t) or the signal bandwidth VsigBW.

[0060] Figure 4A 2 shows a simplified circuit diagram of an example implementation of a filter circuit 444 of an open-loop converter 240 / 260 according to some embodiments. In some embodiments, Figure 2A / Figure 2BThe filter circuit 244 is implemented as a filter circuit 444. In the embodiment shown, the filter circuit 444 is implemented as an N-pole PI filter. The filter circuit 444 receives the time-varying output signal Vout'(t) at the signal output node 252, and outputs the filtered time-varying output signal VsigOut(t) at the signal output node 254. The order of the filter circuit 444 is higher than that of the second-order filter. In other words, the filter circuit 444 is not implemented as a first-order filter such as an RC or RL filter, or a second-order filter such as an RLC filter. The filter circuit 444 generally includes N cascade filter parts, and each filter part generally includes an inductor Ln, a capacitor Cn, and a capacitor Cn+1 connected as shown in the figure. In some embodiments, the filter circuit 444 is implemented as one of a Chebyshev filter circuit, a Butterworth filter circuit, an elliptic filter circuit, a Bessel filter circuit, an active filter circuit (e.g., using one or more operational amplifiers), a digital filter circuit (e.g., using a digital signal processor), or another filter circuit adapted to substantially pass frequencies equal to or less than a maximum frequency component fMAX(Vsig(t)) of the time-varying input signal Vsig(t) and substantially attenuate frequencies greater than a maximum frequency component fMAX(Vsig(t)) of the time-varying input signal Vsig(t), wherein fMAX(Vsig(t)) is significantly greater than DC. In some embodiments, such as Figure 4B As shown in the simplified timing diagram 420 of FIG. 4, the filter circuit 444 has a 3dB cutoff frequency that is greater than the maximum frequency component fMAX(Vsig(t)) of the time-varying input signal Vsig(t). The simplified diagram 420 shows an example transfer function 422 of the filter circuit 244 / 444, which has a 3db cutoff frequency 424 at a frequency f greater than or equal to the maximum frequency component fMAX(Vsig(t)) of the time-varying input signal Vsig(t). For simplicity, various aspects of the transfer function such as passband / stopband ripple (when present) are omitted. In some embodiments, the roll-off of the filter circuit 244 / 444 may be much steeper than shown.

[0061] Figure 5 A simplified circuit diagram of a multi-phase high-speed open-loop switch-mode boost converter (“open-loop converter”) 540 with linear signal characteristics is shown in accordance with some embodiments. Like numbered elements of the open-loop converter 540 may have the same Figure 1A1-m, and each of the switches S1-m and S1-m are synchronous or passive output rectifiers. Similar to the switching signal generator circuit 242, the switching signal generator circuit 542 outputs m copies of the switching signal Vpwm'(t), each copy being phase-shifted by a corresponding θ1-θ. m The m copies of the switching signal Vpwm'(t) with varying phase offsets are driven by m corresponding switch driver circuits 518. 1-m The m switch-mode boost amplifier sections generate m time-varying output signals Vout' 1-m (t), which are recombined at the signal output node 252 to generate the time-varying output signal Vout′(t).

[0062] Figure 6 A simplified circuit diagram of a high speed open loop switch mode boost converter ("open loop converter") 640 with linear signal characteristics according to some embodiments is shown. Like numbered elements of the open loop converter 640 may have the same Figure 1A The converter 100 and Figure 2A The corresponding like numbered elements of the open-loop converter 240 are similarly described, but design considerations may cause the actual implementation of these elements to be presented differently in different circuits. In addition, the open-loop converter 640 includes similar Figure 3C The switching signal generator circuit 342b of the switching signal generator circuit portion 642b and similar Figure 4A Implementation of filter circuit portion 644 of filter circuit 444. Open-loop converter 640 advantageously generates a filtered time-varying output signal VsigOut(t) that is substantially linearly related to the time-varying input signal Vsig(t).

[0063] Figure 7 A simplified circuit diagram of a radio frequency (RF) amplifier circuit 740 capable of high speed open loop envelope tracking according to some embodiments is shown. The RF amplifier circuit 740 includes a Figure 6Implementation of the open-loop converter 640 shown and described. In addition, the RF amplifier circuit 740 generally includes an envelope detector circuit 772, a signal delay circuit 774, and a power amplifier circuit 776. The RF amplifier circuit 740 receives an RF input signal RFsigIn(t) at an input node 778. The envelope detector circuit 772 is a circuit suitable for generating a time-varying envelope signal Venv(t) corresponding to the envelope of the RF input signal RFsigIn(t). The time-varying envelope signal Venv(t) is received at the signal input node 248 of the open-loop converter 640. In some embodiments, the maximum frequency component fMAX(Venv(t)) of the time-varying envelope signal Venv(t) is greater than 10 MHz. The open-loop converter 640 generates a filtered time-varying output signal VenvOut(t) at the signal output node 254. The filtered time-varying output signal VenvOut(t) is received by the power amplifier circuit 776 and thereby used as a power supply rail. The power amplifier circuit 776 receives the delayed RF input signal RFsigIn(t+Τ) delayed by the signal delay circuit 774 and generates an amplified signal RFsigOut(t) at the RF signal output node 780. The RF amplifier circuit 740 implemented using the open-loop converter 640 advantageously uses a single boost stage (e.g., switch S1) and does not require an additional switch-mode buck power converter or a linear power converter. Therefore, the overall efficiency of the RF amplifier circuit 740 is improved relative to a typical RF amplifier circuit having an additional switch-mode converter and / or a linear power converter.

[0064] Figure 8 A simplified circuit diagram of an audio amplifier circuit 840 with high-speed open-loop envelope tracking according to some embodiments is shown. The audio amplifier circuit 840 includes a Figure 6Implementation of the open-loop converter 640 shown and described. In addition, the audio amplifier circuit 840 generally includes an audio signal source 842 and an audio transducer or downstream audio circuit 844 (e.g., a speaker, additional amplification or additional signal conditioning circuit). The audio amplifier circuit 840 receives the time-varying audio signal Vaud(t) from the audio signal source 842 at the signal input node 248 of the open-loop converter 640. In some embodiments, the maximum frequency component fMAX(Vaud(t)) of the time-varying audio signal Vaud(t) is greater than 20 Hz and less than or equal to 20 kHz. The open-loop converter 640 generates a filtered time-varying output signal VaudOut(t) at the signal output node 254. The filtered time-varying output signal VaudOut(t) is received by the audio transducer or downstream audio circuit 844. The audio amplifier circuit 840 implemented using the open-loop converter 640 advantageously uses a single boost stage (e.g., switch S1) and does not use an additional switch-mode buck power converter or a linear power converter. Thus, the overall efficiency of the audio amplifier circuit 840 is improved relative to an audio amplifier circuit having an additional switch-mode converter and / or a linear power converter.

[0065] In the foregoing description, the same reference numerals are used to identify the same elements. In addition, the accompanying drawings are intended to illustrate the main features of the exemplary embodiments in a diagrammatic manner. The accompanying drawings are neither intended to show each feature of the actual embodiment nor to show the relative size of the elements shown, and are not drawn to scale. Now, reference will be made in detail to the embodiments of the disclosed invention, in which one or more examples of the embodiments are shown. Each example is provided by explaining the technology of the present invention rather than by limiting the technology of the present invention. In fact, although this specification has been described in detail with reference to the specific embodiments of the present invention, it should be understood that those skilled in the art can easily conceive of alternatives, variations and equivalents of these embodiments after understanding the foregoing. For example, the characteristic structure shown or described as a part of one embodiment can be used in another embodiment to derive further embodiments. Therefore, the subject matter of the present invention is intended to cover all such modifications and changes within the scope of the attached claims and their equivalents. Without departing from the scope of the present invention more specifically set forth in the attached claims, those skilled in the art can practice these and other modifications and variations of the present invention. In addition, those skilled in the art should understand that the above description is only by way of example and is not intended to limit the present invention.

Claims

1. An open-loop switch-mode boost converter, comprising: a switch signal generator circuit for generating a switch signal, the switch signal generator circuit comprising a signal input node for receiving a time-varying input signal, and a switch signal output node for outputting the switch signal, the duty cycle of the switch signal having a first non-linear relationship with an amplitude of the time-varying input signal; a switch-mode boost amplifier circuit comprising an input voltage node for receiving an input voltage, a switch driver input node connected to the switch signal output node for receiving the switch signal, and a signal output node for outputting a time-varying output signal, the amplitude of the time-varying output signal having a second non-linear relationship with the duty cycle of the switch signal, and the time-varying output signal having a linear relationship with the time-varying input signal based on the first non-linear relationship and the second non-linear relationship; and a filter circuit having a filter input node connected to the signal output node of the amplifier circuit to receive the time-varying output signal, and a filter output node for outputting a filtered time-varying output signal, the filter circuit having an order higher than a second-order filter; in: The switch signal generator circuit is communicatively isolated from the signal output node and the filter output node; The time-varying input signal has a first maximum frequency component, the first maximum frequency component being significantly greater than DC; and The filtered time-varying output signal has a second maximum frequency component that is substantially the same as the first maximum frequency component.

2. The open loop switch mode boost converter of claim 1 , wherein: The switching frequency of the switching signal is at least 2 times greater than the first maximum frequency component of the time-varying input signal; and The filter circuit substantially passes a first frequency that is equal to or less than the first maximum frequency component from the filter input node to the filter output node and substantially attenuates a second frequency that is greater than the first maximum frequency component.

3. The open loop switch mode boost converter of claim 1 , wherein: The first maximum frequency component of the time-varying input signal is greater than 1 MHz.

4. The open loop switch mode boost converter of claim 1, wherein: The switch signal generator circuit comprises: a capacitor including a first terminal connected to a bias voltage node; a voltage-to-current conversion circuit having a first node connected to a positive voltage node, a second node connected to a second terminal of the capacitor, and a current conduction control node connected to the signal input node for receiving the time-varying input signal and controlling a charging current flowing from the positive voltage node to the capacitor to generate a ramp signal, the charging current being proportional to the amplitude of the time-varying input signal; a discharge switch including a high side connected to the second terminal of the capacitor, a low side connected to the bias voltage node, and a switch control node connected to a switch control circuit to control a discharge current flowing from the capacitor to the bias voltage node; a trigger level generating circuit for generating a trigger voltage, the trigger level generating circuit comprising a trigger voltage output node for outputting the trigger voltage; and A voltage comparison circuit has a first input terminal connected to the second terminal of the capacitor and a second input terminal connected to the trigger level generating circuit for receiving the trigger voltage, the voltage comparison circuit having a voltage comparison upper limit.

5. The open loop switch mode boost converter of claim 4, wherein: The maximum ramp voltage of the ramp signal is approximately equal to the voltage comparison upper limit, and the maximum ramp voltage is based on one or more of the voltage-to-current conversion circuit, the capacitance value of the capacitor, the discharge frequency of the discharge switch, and the discharge duty cycle of the discharge switch.

6. The open loop switch mode boost converter of claim 5, wherein: When the discharge switch is in the on state, a discharge period of the discharge switch is equal to or greater than a duration for fully discharging the capacitor to the bias voltage node; and The discharge frequency of the discharge switch is equal to or greater than twice the first maximum frequency component of the time-varying input signal.

7. The open-loop switch-mode boost converter of claim 4, wherein the trigger level generating circuit further comprises: a voltage input node connected to the second terminal of the capacitor to receive a plurality of ramp voltages of the ramp signal, wherein the trigger level generating circuit: Sampling the plurality of ramp voltages to generate a plurality of ramp voltage samples; determining a minimum ramp peak voltage using the plurality of ramp voltage samples; and The trigger voltage is generated based on the minimum ramp peak voltage.

8. The open loop switch mode boost converter of claim 7, wherein: The trigger voltage is greater than the ground voltage and less than or equal to the minimum ramp peak voltage.

9. The open-loop switch-mode boost converter of claim 4, wherein the trigger level generating circuit further comprises: A fixed bias voltage node is provided for the trigger voltage, wherein the trigger voltage is based on a fixed percentage of a voltage rail of the voltage comparison circuit.

10. The open loop switch mode boost converter of claim 1 , wherein the amplifier circuit comprises: a first switch driver circuit having a first input node connected to the switch signal output node for receiving the switch signal, and a first drive signal output node for outputting a first drive signal; a first switching transistor having a first drive node connected to the first drive signal output node for receiving the first drive signal, a first high side connected to the input voltage node through a first inductor, and a first low side connected to a bias voltage node; and A first output rectifier is connected between the first high side of the first switching transistor and the signal output node of the amplifier circuit.

11. The open loop switch mode boost converter of claim 10, further comprising: A semiconductor device, comprising: a monolithic substrate; and an active layer on the monolithic substrate; in: The active layer includes the switching signal generator circuit, the first switching driver circuit, and the first switching transistor.

12. The open loop switch mode boost converter of claim 10, wherein the amplifier circuit further comprises: a second switch driver circuit having a second input node connected to another switch signal output node of the switch signal generator circuit for receiving another switch signal, and a second drive signal output node for outputting a second drive signal; a second switching transistor having a second drive node connected to the second drive signal output node for receiving the second drive signal, a second high side connected to the input voltage node through a second inductor, and a second low side connected to the bias voltage node; and A second output rectifier is connected between the second high side of the second switching transistor and the signal output node of the amplifier circuit.

13. The open loop switch mode boost converter of claim 1 , wherein: The filter circuit includes a low pass filter circuit selected from a group consisting of a Chebyshev filter circuit, a Butterworth filter circuit, a Bessel filter circuit, and an elliptic filter circuit.

14. The open loop switch mode boost converter of claim 13, wherein: The 3 dB cut-off frequency of the low pass filter circuit is greater than the first maximum frequency component of the time varying input signal.

15. The open loop switch mode boost converter of claim 1 , wherein the filter circuit comprises: a first filter capacitor connected in parallel between the filter input node and a bias voltage node; a first filter inductor having a first terminal connected to the filter input node and a second terminal connected to the filter output node; and A second filter capacitor is connected in parallel between the second terminal of the first filter inductor and the bias voltage node.

16. The open loop switch mode boost converter of claim 15, wherein the filter circuit further comprises: a second filter inductor connected in series between the second terminal of the first filter inductor and the filter output node; a third filter capacitor connected in parallel between the first terminal of the second filter inductor and the bias voltage node; and A fourth filter capacitor is connected in parallel between the second terminal of the second filter inductor and the bias voltage node.

17. The open loop switch mode boost converter of claim 1, wherein: The linear relationship between the time-varying input signal and the time-varying output signal is based on a first amplitude of the time-varying input signal and a second amplitude of the time-varying output signal, the second amplitude being substantially linearly proportional to the first amplitude of the time-varying output signal.

18. The open loop switch mode boost converter of claim 1 further comprising: an audio input circuit, to which the signal input node of the switch signal generator circuit is connected to receive an audio signal; and an audio transducer circuit connected to the filter output node of the filter circuit to receive the amplified audio signal; in: The time-varying input signal is the audio signal; and The amplified audio signal is the filtered time-varying output signal.

19. The open loop switch mode boost converter of claim 1 further comprising: an envelope detector circuit having a signal input node for receiving an input signal, and an envelope signal output node connected to the signal input node of the switching signal generator circuit to output an envelope signal, the envelope signal being a signal envelope of the input signal; and a power amplifier (PA) circuit having a PA signal input node for receiving the input signal, a PA signal output node for outputting an amplified signal, a PA low-side bias node, and a PA high-side bias node connected to the filter output node of the filter circuit to receive the amplified envelope signal; in: The time-varying input signal is the envelope signal; and The amplified envelope signal is the filtered time-varying output signal.

20. A method for amplifying a time-varying signal, the method comprising: receiving a time-varying input signal at a signal input node of a switching signal generator circuit; generating a switching signal using the switching signal generator circuit, wherein a duty cycle of the switching signal has a first non-linear relationship with an amplitude of the time-varying input signal; outputting the switch signal from a switch signal output node of the switch signal generator circuit; receiving the switching signal from the switching signal output node of the switching signal generator circuit at a switch driver input node of a switch-mode boost amplifier circuit; receiving an input voltage at an input voltage node of the amplifier circuit; outputting a time-varying output signal from a signal output node of the amplifier circuit, the amplitude of the time-varying output signal having a second nonlinear relationship with the duty cycle of the switching signal, and the time-varying output signal having a linear relationship with the time-varying input signal based on the first nonlinear relationship and the second nonlinear relationship; receiving the time-varying output signal from the signal output node of the amplifier circuit at a filter input node of a filter circuit, the filter circuit being of a higher order than a second order filter; as well as outputting a filtered time-varying output signal from a filter output node of the filter circuit; in: The switch signal generator circuit is communicatively isolated from the signal output node and the filter output node; The time-varying input signal has a first maximum frequency component, and the first maximum frequency component is significantly greater than DC; and The filtered time-varying output signal has a second maximum frequency component that is substantially the same as the first maximum frequency component.

Images