Thin film transistor array substrate and organic light emitting display device including the same

Abstract

The present invention provides a thin film transistor array substrate and an organic light-emitting display device including the same. The thin film transistor array substrate includes a substrate, at least one thin film transistor, a capacitor, an interlayer insulating layer and a node connection line. At least one thin film transistor is located on the substrate. The capacitor is located on the substrate and includes: a lower electrode located on the substrate; an upper electrode overlapping the lower electrode, the upper electrode including an opening having a single closed curve shape; and a dielectric layer located between the lower electrode and the upper electrode. The interlayer insulating layer covers the capacitor. The node connection line is located on the interlayer insulating layer and electrically connects the capacitor to at least one thin film transistor. The overlapping area of ​​the lower electrode and the upper electrode is divided into two discrete areas by the opening.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0012342, filed on January 31, 2018, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] One or more exemplary embodiments relate generally to a display apparatus, and more particularly, to a thin film transistor array substrate and an organic light emitting display device including the same. Background Art

[0004] An organic light-emitting display device generally includes two electrodes and an organic emission layer between the two electrodes. Electrons injected through one electrode and holes injected through the other electrode combine in the organic emission layer to generate excitons, which release energy to emit light. Such an organic light-emitting display device may include a plurality of pixels, and the plurality of pixels include an organic light-emitting device that is a self-luminous device. A capacitor and a plurality of thin-film transistors are formed in each pixel to drive the organic light-emitting device. However, there is a need to ensure that the performance of the organic light-emitting display device is uniform and exhibits uniform characteristics despite process errors.

[0005] The above information disclosed in this section is only for understanding the background of the present inventive concept and therefore it may contain information that does not constitute prior art. Summary of the invention

[0006] One or more exemplary embodiments can provide a thin film transistor array substrate including a capacitor providing capacitance that is insensitive to process variations.

[0007] One or more exemplary embodiments can provide an organic light emitting display device including a thin film transistor array substrate including a capacitor providing capacitance that is insensitive to process variations.

[0008] Additional aspects will be set forth in the detailed description which follows, and in part will be obvious from the disclosure, or may be learned by practice of the inventive concepts.

[0009] According to some exemplary embodiments, a thin film transistor array substrate includes a substrate, at least one thin film transistor, a capacitor, an interlayer insulating layer, and a node connection line. At least one thin film transistor is located on the substrate. The capacitor is located on the substrate and includes: a lower electrode located on the substrate; an upper electrode overlapping the lower electrode, the upper electrode including an opening having a single closed curve shape; and a dielectric layer located between the lower electrode and the upper electrode. The interlayer insulating layer covers the capacitor. The node connection line is located on the interlayer insulating layer and electrically connects the capacitor to at least one thin film transistor. The overlapping area of ​​the lower electrode and the upper electrode is divided into two discrete areas by the opening.

[0010] In some exemplary embodiments, the opening may expose opposite ends of the lower electrode in one direction.

[0011] In some exemplary embodiments, when viewed in a plan view, an edge of the upper electrode may be spaced outward from an edge of the lower electrode, and the edge of the upper electrode may surround an edge of the lower electrode.

[0012] In some exemplary embodiments, the thin film transistor array substrate may further include a node contact hole located in the opening and passing through the interlayer insulating layer and the dielectric layer. The first end of the node connection line may be connected to the lower electrode through the node contact hole.

[0013] In some exemplary embodiments, the size of the opening may be larger than the size of the node contact hole when viewed in a plan view.

[0014] In some exemplary embodiments, the thin film transistor array substrate may further include: a scan line extending in a first direction and a data line extending in a second direction crossing the first direction. The opening may have a rectangular shape including a longer side in the first direction.

[0015] In some exemplary embodiments, the thin film transistor array substrate may further include: a scan line extending in a first direction and a data line extending in a second direction crossing the first direction. The opening may have a rectangular shape including a longer side in the second direction.

[0016] In some exemplary embodiments, the thin film transistor array substrate may further include a driving voltage line located in the same layer as the node connection line. The driving voltage may be transmitted through the driving voltage line. The upper electrode may be connected to the driving voltage line through a contact hole.

[0017] In some exemplary embodiments, the thin film transistor array substrate may further include a driving thin film transistor overlapping the capacitor. The lower electrode may form a driving gate electrode of the driving thin film transistor, and the lower electrode is equivalent to the driving gate electrode.

[0018] In some exemplary embodiments, a driving semiconductor layer of the driving thin film transistor may have a bent shape.

[0019] In some exemplary embodiments, the at least one thin film transistor may include a compensation thin film transistor, a first end of the node connection line may be connected to the lower electrode, and a second end of the node connection line may be connected to a compensation drain region of the compensation thin film transistor.

[0020] According to some exemplary embodiments, an organic light-emitting display device includes a substrate, a driving voltage line, a scan line, a data line, a pixel circuit, an interlayer insulating layer, and a node connection line. The driving voltage line is located on the substrate. The driving voltage line is configured to transmit a driving voltage. The scan line extends on the substrate in a first direction. The data line is insulated from the scan line and extends in a second direction intersecting the first direction. The pixel circuit electrically connects the driving voltage line, the scan line, and the data line. The pixel circuit includes a capacitor and at least one thin film transistor. The capacitor includes: a lower electrode located on the substrate; an upper electrode overlapping the lower electrode, the upper electrode including an opening having a single closed curve shape; and a dielectric layer located between the lower electrode and the upper electrode. The interlayer insulating layer covers the capacitor. The node connection line is arranged on the interlayer insulating layer and electrically connects the capacitor to at least one thin film transistor. The overlapping area of ​​the lower electrode and the upper electrode is divided into two discrete areas by the opening.

[0021] In some exemplary embodiments, the opening may expose opposite ends of the lower electrode on one aspect.

[0022] In some exemplary embodiments, when viewed in a plan view, an edge of the upper electrode may be spaced outward from an edge of the lower electrode, and the edge of the upper electrode may surround an edge of the lower electrode.

[0023] In some exemplary embodiments, the organic light emitting display device may further include a node contact hole located in the opening and passing through the interlayer insulating layer and the dielectric layer. The first end of the node connection line may be connected to the lower electrode through the node contact hole.

[0024] In some exemplary embodiments, a size of the opening may be larger than a size of the node contact hole.

[0025] In some exemplary embodiments, the opening may extend in the first direction or the second direction.

[0026] In some exemplary embodiments, the driving voltage line may be located in the same layer as the node connection line, and the upper electrode may be connected to the driving voltage line through a contact hole.

[0027] In some exemplary embodiments, the at least one thin film transistor may include a driving thin film transistor overlapping the capacitor, and the lower electrode may form a driving gate electrode of the driving thin film transistor, and the lower electrode and the driving gate electrode may be a single unit.

[0028] In some exemplary embodiments, the at least one thin film transistor may further include a compensation thin film transistor, a first end of the node connection line may be connected to the lower electrode, and a second end of the node connection line may be connected to a compensation drain region of the compensation thin film transistor.

[0029] The foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the inventive concept and together with the description serve to explain the principles of the inventive concept.

[0031] Figure 1 is a schematic diagram of an organic light emitting display device according to some exemplary embodiments.

[0032] Figure 2 is a schematic block diagram illustrating an organic light emitting display device according to some exemplary embodiments.

[0033] Figure 3 According to some exemplary embodiments, Figure 1 An equivalent circuit diagram of a pixel in an organic light emitting display device.

[0034] Figure 4 is a schematic layout diagram illustrating positions of a capacitor and a plurality of thin film transistors included in a pixel circuit according to some exemplary embodiments.

[0035] Figure 5 , Figure 6 , Figure 7 and Figure 8 are respectively layers such as Figure 4 A schematic layout diagram of the components of the capacitor and multiple thin film transistors is shown.

[0036] Fig. 9 According to some exemplary embodiments, the cross-sectional view is taken along the section lines II' and II-II'. Figure 4 Cross-sectional view of .

[0037] Fig.10 is a diagram illustrating a method according to some exemplary embodiments Figure 4 A plan view of the lower and upper electrodes of the capacitor shown.

[0038] Fig.11 FIG. 1 illustrates a method according to some exemplary embodiments. Figure 4 The overlapping area between the lower electrode and the upper electrode of the capacitor.

[0039] Fig.12 The diagram shows the Fig.10 A comparative example of the exemplary embodiment of FIG.

[0040] Fig.13 is a schematic layout diagram illustrating positions of a capacitor and a plurality of thin film transistors included in a pixel circuit according to some exemplary embodiments.

[0041] Fig.14 FIG. 1 illustrates a method according to some exemplary embodiments. Fig.13 The overlapping area between the lower electrode and the upper electrode of the capacitor. DETAILED DESCRIPTION

[0042] In the following description, for the purpose of illustration, many specific details are set forth to provide a comprehensive understanding of each exemplary embodiment. However, it is to be understood that each exemplary embodiment can be practiced without these specific details or with one or more equivalent arrangements. In other examples, well-known structures and devices are shown in the form of block diagrams to avoid unnecessary obscurity of each exemplary embodiment. In addition, each exemplary embodiment can be different, but not necessarily mutually exclusive. For example, the specific shape, configuration and characteristics of an exemplary embodiment can be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0043] Unless otherwise specified, the illustrated exemplary embodiments should be understood as providing exemplary features of different details of some exemplary embodiments. Therefore, unless otherwise specified, the various illustrated features, components, modules, layers, films, panels, regions, aspects, etc. (hereinafter individually or collectively referred to as "elements") can be combined, separated, interchanged and / or rearranged without departing from the concept of the present invention.

[0044] The use of cross hatching and / or shading in the drawings is generally provided to make the boundaries between adjacent elements clear. Therefore, unless otherwise specified, the presence or absence of cross hatching or shading does not express or indicate any preference or requirement for a specific material, material property, size, ratio, commonality between the illustrated elements and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for clarity and / or description purposes. When the exemplary embodiments can be implemented differently, a specific process sequence may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously, or in an order opposite to the described order. In addition, the same reference numerals represent the same elements.

[0045] When an element is referred to as being "on", "connected to" or "coupled to" another element, it may be directly located on, directly connected to or coupled to another element, or there may be an intermediate element. However, when an element is referred to as being "directly located" on, "directly connected to" or "directly coupled to" another element, there is no intermediate element. Other terms and / or phrases used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" to "directly between", "adjacent" to "directly adjacent", "on" to "directly on", etc. In addition, the term "connection" may refer to physical connection, electrical connection and / or fluid connection. For the purpose of this disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" may be interpreted as any combination of only X, only Y, only Z or two or more of X, Y and Z, such as, for example, XYZ, XYY, YZ and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0046] Although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, the first element discussed below can be referred to as the second element without departing from the teachings of the present disclosure.

[0047] For descriptive purposes, spatially relative terms such as "below," "below," "under," "down," "above," "above," "higher," "side" (e.g., as in "sidewall"), etc. may be used herein and thereby describe the relationship of one element illustrated in the accompanying drawings to another element. Spatially relative terms are intended to encompass different orientations of the device when in use, in operation, and / or in manufacture other than the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, an element described as being "below" or "below" other elements or features will be "above" the other elements or features. Thus, the exemplary term "below" may include both above and below orientations. Moreover, the device may be oriented in other directions (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein are therefore interpreted accordingly.

[0048] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, the singular "one" and "the" are intended to also include plural forms, unless the context clearly states otherwise. In addition, when used in this specification, the terms "include" and / or "comprise" indicate the existence of the described features, integral bodies, steps, operations, elements, parts and / or combinations thereof, but do not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, parts and / or combinations thereof. It should also be noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as approximate terms and are not used as terms of degree, and are therefore used to consider the inherent deviations of the values ​​that will be recognized by those of ordinary skill in the art, measured, calculated and / or provided.

[0049] Various exemplary embodiments are described herein with reference to cross-sectional illustrations and / or exploded illustrations, which are schematic illustrations of idealized exemplary embodiments and / or intermediate structures. Therefore, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances may be expected. Therefore, the exemplary embodiments disclosed herein should not be interpreted as limited to the shapes of the regions of the particular illustrations, but will include deviations in shapes due to, for example, manufacturing. In this manner, the regions illustrated in the accompanying drawings are schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and are therefore not intended to be limiting.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure belongs. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0051] As is customary in the art, some exemplary embodiments are described and illustrated in the accompanying drawings from the perspective of functional blocks, units and / or modules. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (e.g., logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements and wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques). In the case where blocks, units and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware that performs certain functions and processors (e.g., one or more programmed microprocessors and associated circuits) that perform other functions. In addition, each block, unit and / or module in some exemplary embodiments can be physically divided into two or more interactive and discrete blocks, units and / or modules without departing from the inventive concept. Furthermore, the blocks, units and / or modules of some exemplary embodiments may be physically combined into more complex blocks, units and / or modules without departing from the inventive concept.

[0052] Figure 1 is a schematic diagram of an organic light emitting display device according to some exemplary embodiments.

[0053] refer to Figure 1 , the organic light emitting display device includes a display area DA and a peripheral area PA as a non-display area. A plurality of pixels PX including an organic light emitting device (OLED) may be arranged in the display area DA to provide a certain image. The peripheral area PA does not provide an image and includes a scan driver (see FIG. 1 ) that provides an electrical signal to be applied to the pixels PX of the display area DA. Figure 2 ) and data drivers (see Figure 2 ) etc., and includes a power line, through which power such as a driving voltage and a common voltage is supplied.

[0054] Figure 2 is a schematic block diagram illustrating an organic light emitting display device according to some exemplary embodiments.

[0055] like Figure 2 As can be seen in FIG. 1 , the organic light emitting display device includes a display unit 10 , a scan driver 20 , a data driver 30 , an emission control driver 40 , and a controller 50 . The display unit 10 includes a plurality of pixels PX.

[0056] The display unit 10 is arranged in the display area DA (see Figure 1) and includes a plurality of pixels PX, which are located at the intersections of a plurality of scan lines SL1 to SLn+1, a plurality of data lines DL1 to DLm, and a plurality of emission control lines EL1 to ELn. The pixels PX may be arranged roughly in a matrix form. A plurality of scan lines SL1 to SLn+1 and a plurality of emission control lines EL1 to ELn extend in a first direction as a row direction, and a plurality of data lines DL1 to DLm and a driving voltage line ELVDDL extend in a second direction as a column direction. On one line, the value of "n" of a plurality of scan lines SL1 to SLn+1 may be different from the value of "n" of a plurality of emission control lines EL1 to ELn.

[0057] Each of the pixels PX is connected to three scan lines among the plurality of scan lines SL1 to SLn+1 extending to the display unit 10. The scan driver 20 generates at least three scan signals and transmits the scan signals to the pixels PX through the plurality of scan lines SL1 to SLn+1. That is, the scan driver 20 sequentially supplies the scan signals to the scan lines SL2 to SLn, the previous scan lines SL1 to SLn-1, or the next scan lines SL3 to SLn+1.

[0058] The initialization voltage line IL may receive an initialization voltage from an external power source VINT and supply the initialization voltage to each of the pixels PX. In addition, each of the plurality of pixels PX is connected to one of the plurality of data lines DL1 to DLm connected to the display unit 10, and is connected to one of the plurality of emission control lines EL1 to ELn connected to the display unit 10.

[0059] The data driver 30 transmits a data signal to each of the pixels PX through a plurality of data lines DL1 to DLm. Each time a scan signal is supplied to the scan lines SL2 to SLn, the data signal is supplied to the pixel selected by the scan signal.

[0060] The emission control driver 40 generates an emission control signal and transmits the emission control signal to each pixel in the pixel PX through a plurality of emission control lines EL1 to ELn. The emission time of each pixel in the pixel PX is controlled by the emission control signal. Depending on the structure (e.g., internal structure) of the pixel PX, the emission control driver 40 may be omitted.

[0061] The controller 50 changes a plurality of image signals IR, IG, and IB received from the outside into a plurality of image data signals DR, DG, and DB, and transmits the plurality of image data signals DR, DG, and DB to the data driver 30. In addition, the controller 50 receives a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a clock signal MCLK to generate control signals, respectively, to control driving of the scan driver 20, the data driver 30, and the emission control driver 40, and transmits the control signals to the scan driver 20, the data driver 30, and the emission control driver 40. That is, the controller 50 generates a scan driving control signal SCS for controlling the scan driver 20, a data driving control signal DCS for controlling the data driver 30, and an emission driving control signal ECS for controlling the emission control driver 40, and transmits the control signals to the scan driver 20, the data driver 30, and the emission control driver 40, respectively.

[0062] Each of the plurality of pixels PX receives a driving power voltage ELVDD and a common power voltage ELVSS from the outside (see Figure 3 ). The driving power voltage ELVDD may be a determined high level voltage, and the common power voltage ELVSS may be lower than the driving power voltage ELVDD or the ground voltage. The driving power voltage ELVDD is supplied to each of the pixels PX through the driving voltage line ELVDDL.

[0063] Each of the plurality of pixels PX emits light of determined brightness according to a driving current supplied to the light emitting device according to a data signal received through the plurality of data lines DL1 to DLm.

[0064] Figure 3 According to some exemplary embodiments, Figure 1 The equivalent circuit diagram of a pixel in an organic light-emitting display device is shown in FIG. Figure 3 The pixel PX can represent Figure 1 and Figure 2 A pixel PX of an organic light emitting display device.

[0065] refer to Figure 3 , the pixel PX includes signal lines 121, 122, 123 and 151, a plurality of thin film transistors (TFTs) T1, T2, T3, T4, T5, T6 and T7, a capacitor Cst, an initialization voltage line 131, a driving voltage line 152 and an organic light emitting device OLED.

[0066] Although all the signal lines 121, 122, 123 and 151, the initialization voltage line 131 and the driving voltage line 152 are included Figure 3For example, at least one of the signal lines 121, 122, 123, and 151 and / or the initialization voltage line 131 may be shared with one or more adjacent pixels.

[0067] The TFTs T1, T2, T3, T4, T5, T6, and T7 may include a driving TFT T1, a switching TFT T2, a compensation TFT T3, a first initialization TFT T4, an operation control TFT T5, an emission control TFT T6, and a second initialization TFT T7.

[0068] The signal lines 121, 122, 123 and 151 include a scan line 121, a previous scan line 122, an emission control line 123 and a data line 151, a scan signal Sn is transmitted through the scan line 121, a previous scan signal Sn-1 is transmitted to the first initialization TFT T4 and the second initialization TFT T7 through the previous scan line 122, an emission control signal En is transmitted to the operation control TFT T5 and the emission control TFT T6 through the emission control line 123, a data line 151 crosses the scan line 121, and a data signal Dm is transmitted through the data line 151. A driving power voltage ELVDD is transmitted to the driving TFT T1 through the driving voltage line 152, and an initialization voltage Vint is transmitted through the initialization voltage line 131, and the driving TFT T1 and the pixel electrode are initialized by the initialization voltage Vint.

[0069] The driving gate electrode G1 of the driving TFT T1 is connected to the first electrode Cst1 of the capacitor Cst, the driving source electrode S1 of the driving TFT T1 is connected to the driving voltage line 152 through the operation control TFT T5, and the driving drain electrode D1 of the driving TFT T1 is electrically connected to the pixel electrode of the organic light emitting device OLED through the emission control TFT T6. The driving TFT T1 receives the data signal Dm according to the switching operation of the switching TFT T2 to switch the driving current I OLED Supplied to the organic light emitting device OLED.

[0070] A switching gate electrode G2 of the switching TFT T2 is connected to the scan line 121, a switching source electrode S2 of the switching TFT T2 is connected to the data line 151, and a switching drain electrode D2 of the switching TFT T2 is connected to the driving source electrode S1 of the driving TFT T1, and is also connected to the driving voltage line 152 through the operation control TFT T5. The switching TFT T2 is turned on according to the scan signal Sn received through the scan line 121 to perform a switching operation of transmitting the data signal Dm transmitted to the data line 151 to the driving source electrode S1 of the driving TFT T1.

[0071] The compensation gate electrode G3 of the compensation TFT T3 is connected to the scan line 121, the compensation source electrode S3 of the compensation TFT T3 is connected to the driving drain electrode D1 of the driving TFT T1, and is also connected to the pixel electrode of the organic light emitting device OLED through the emission control TFT T6, and the compensation drain electrode D3 of the compensation TFT T3 is connected to the first electrode Cst1 of the capacitor Cst, the first initialization source electrode S4 of the first initialization TFT T4, and the driving gate electrode G1 of the driving TFT T1. The compensation TFT T3 is turned on according to the scan signal Sn transmitted through the scan line 121 to electrically connect the driving gate electrode G1 of the driving TFT T1 to the driving drain electrode D1 to form a diode connection of the driving TFT T1.

[0072] A first initialization gate electrode G4 of the first initialization TFT T4 is connected to the previous scan line 122, and a first initialization drain electrode D4 of the first initialization TFT T4 is connected to the second initialization drain electrode D7 of the second initialization TFT T7 and the initialization voltage line 131. A first initialization source electrode S4 of the first initialization TFT T4 is connected to the first electrode Cst1 of the capacitor Cst, the compensation drain electrode D3 of the compensation TFT T3, and the driving gate electrode G1 of the driving TFT T1. The first initialization TFT T4 is turned on according to the previous scan signal Sn-1 received through the previous scan line 122 to transmit the initialization voltage Vint to the driving gate electrode G1 of the driving TFT T1 so as to perform an initialization operation of initializing the voltage of the driving gate electrode G1 of the driving TFT T1.

[0073] An operation control gate electrode G5 of the operation control TFT T5 is connected to the emission control line 123, an operation control source electrode S5 of the operation control TFT T5 is connected to the driving voltage line 152, and an operation control drain electrode D5 of the operation control TFT T5 is connected to the driving source electrode S1 of the driving TFT T1 and the switching drain electrode D2 of the switching TFT T2.

[0074] The emission control gate electrode G6 of the emission control TFT T6 is connected to the emission control line 123, the emission control source electrode S6 of the emission control TFT T6 is connected to the driving drain electrode D1 of the driving TFT T1 and the compensation source electrode S3 of the compensation TFT T3, and the emission control drain electrode D6 of the emission control TFT T6 is electrically connected to the second initialization source electrode S7 of the second initialization TFT T7 and the pixel electrode of the organic light emitting device OLED.

[0075] The operation control TFT T5 and the emission control TFT T6 are simultaneously turned on according to the emission control signal En received through the emission control line 123, so that the driving power voltage ELVDD is transmitted to the organic light emitting device OLED to make the driving current IOLED Flows through the organic light emitting device OLED.

[0076] The second initialization gate electrode G7 of the second initialization TFT T7 is connected to the previous scan line 122, the second initialization source electrode S7 of the second initialization TFT T7 is connected to the emission control drain electrode D6 of the emission control TFT T6 and the pixel electrode of the organic light emitting device OLED, and the second initialization drain electrode D7 of the second initialization TFT T7 is connected to the first initialization drain electrode D4 of the first initialization TFT T4 and the initialization voltage line 131. The second initialization TFT T7 is turned on according to the previous scan signal Sn-1 received through the previous scan line 122 to initialize the pixel electrode of the organic light emitting device OLED.

[0077] Although Figure 3 An exemplary embodiment in which the first initialization TFT T4 and the second initialization TFT T7 are connected to the previous scan line 122 is illustrated, but the exemplary embodiment is not limited thereto. For example, the first initialization TFT T4 may be connected to the previous scan line 122 to be driven according to the previous scan signal Sn-1, and the second initialization TFT T7 may be connected to an additional signal line (e.g., a subsequent scan line) to be driven according to a signal transmitted to the additional signal line. In addition, depending on the transistor type (p-type or n-type), the first initialization TFT T4 may be connected to the previous scan line 122 to be driven according to the previous scan signal Sn-1, and the second initialization TFT T7 may be connected to an additional signal line (e.g., a subsequent scan line) to be driven according to a signal transmitted to the additional signal line. Figure 3 The positions of the source electrodes S1 to S7 and the drain electrodes D1 to D7 are shown.

[0078] The operation of each pixel PX according to some exemplary embodiments will now be described in more detail.

[0079] During the initialization period, when a previous scan signal Sn-1 is supplied through the previous scan line 122 , the first initialization TFT T4 is turned on according to the previous scan signal Sn-1, and the driving TFT T1 is initialized according to the initialization voltage Vint received through the initialization voltage line 131 .

[0080] During the data programming period, when the scan signal Sn is supplied through the scan line 121, the switching TFT T2 and the compensation TFT T3 are turned on according to the scan signal Sn. The driving TFT T1 is diode-connected by the turned-on compensation TFT T3 and is forward biased.

[0081] Then, a compensation voltage (Dm+Vth, where Vth is a (−) value) which is a voltage obtained by subtracting a threshold voltage Vth of the driving TFT T1 from the data signal Dm supplied through the data line 151 is applied to the driving gate electrode G1 of the driving TFT T1 .

[0082] The driving power voltage ELVDD and the compensation voltage Dm+Vth are applied to both ends of the capacitor Cst, and charges corresponding to a voltage difference between the both ends are stored in the capacitor Cst.

[0083] During the emission period, the operation control TFT T5 and the emission control TFT T6 are turned on according to the emission control signal En supplied through the emission control line 123. The driving current I is generated according to the voltage difference between the voltage of the driving gate electrode G1 of the driving TFT T1 and the driving power voltage ELVDD. OLED , and the driving current I OLED The light is supplied to the organic light emitting device OLED through the emission control TFT T6.

[0084] Figure 4 is a schematic layout diagram illustrating positions of a capacitor and a plurality of thin film transistors included in a pixel circuit according to some exemplary embodiments. Figures 5 to 8 are respectively layers such as Figure 4 A schematic layout diagram of the components of the capacitor and multiple thin film transistors is shown. Fig. 9 According to some exemplary embodiments, the cross-sectional view is taken along the section lines II' and II-II'. Figure 4 Cross-sectional view of .

[0085] Figures 5 to 8 The arrangement of wiring, electrodes and semiconductor layers in each layer of the pixel circuit is illustrated separately, and the insulating layer may be located Figures 5 to 8 For example, the first gate insulating layer 112 (see Fig. 9 ) can be located in Figure 5 The layers shown are Figure 6 The layers shown in FIG. 1 and the second gate insulating layer 113 (see FIG. Fig. 9 ) can be located in Figure 6 The layers shown are Figure 7 between the layers shown, and an interlayer insulating layer 114 (see Fig. 9 ) can be located in Figure 7 The layers shown are Figure 8 between the layers shown. Figures 5 to 8 The illustrated layers may be electrically connected to each other through contact holes defined in at least some of the above-mentioned insulating layers.

[0086] See also Figure 4 , Figure 5 and Fig. 9, the semiconductor layers AS1 to AS7 of the driving TFT T1, the switching TFT T2, the compensating TFT T3, the first initialization TFT T4, the operation control TFT T5, the emission control TFT T6, and the second initialization TFT T7 are arranged in the same horizontal plane and include the same material. For example, the semiconductor layers AS1 to AS7 may be formed of polycrystalline silicon.

[0087] The semiconductor layers AS1 to AS7 are arranged on a buffer layer 111 (see Fig. 9 ). The substrate 110 may be formed of a glass material, a metal material, or a plastic material (such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyimide). The buffer layer 111 may include a silicon oxide (SiO x ) layer and / or an oxide layer such as silicon nitride (SiN x ) layer of nitride layer.

[0088] The substrate 110 may include a glass material, a ceramic material, a metal material, or a flexible or bendable material. When the substrate 110 is flexible or bendable, the substrate 110 may include a polymer resin such as polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), and at least one of cellulose acetate propionate (CAP). The substrate 110 may have a single-layer structure or a multi-layer structure of the above-mentioned materials, and the multi-layer structure may further include an inorganic layer. In some exemplary embodiments, the substrate 110 may have a structure of an organic material / inorganic material / organic material.

[0089] The buffer layer 111 may enhance the flatness of the upper surface of the substrate 110 , and may include an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0090] A barrier layer (not shown) may be further included between the substrate 110 and the buffer layer 111. The barrier layer may prevent or minimize the penetration of impurities from the substrate 110, etc. into the semiconductor layers AS1 to AS7. The barrier layer may include an inorganic material such as an oxide or a nitride, or an organic material, or an organic-inorganic hybrid material, and may have a single-layer structure or a multi-layer structure of an inorganic material and an organic material.

[0091] The driving semiconductor layer AS1 of the driving TFT T1, the switching semiconductor layer AS2 of the switching TFT T2, the compensation semiconductor layer AS3 of the compensation TFT T3, the first initialization semiconductor layer AS4 of the first initialization TFT T4, the operation control semiconductor layer AS5 of the operation control TFT T5, the emission control semiconductor layer AS6 of the emission control TFT T6, and the second initialization semiconductor layer AS7 of the second initialization TFT T7 may be connected to one another and bent into various shapes.

[0092] The semiconductor layers AS1 to AS7 may include a channel region and a source region and a drain region respectively located at opposite sides of the channel region. For example, the source region and the drain region may be doped with impurities that may include N-type impurities or P-type impurities. The source region and the drain region correspond to a source electrode and a drain electrode, respectively. Hereinafter, the terms "source region" and "drain region" will be used instead of "source electrode" and "drain electrode", respectively.

[0093] The driving semiconductor layer AS1 includes a driving channel region A1 and a driving source region S1 and a driving drain region D1 respectively located on both sides of the driving channel region A1. The driving semiconductor layer A1 has a curved shape so that the driving channel region A1 can be longer than other channel regions (e.g., channel regions A2 to A7). For example, since the driving semiconductor layer AS1 has a shape with multiple curved portions (like an omega shape or the letter "S"), a long channel length can be provided in a narrow space. Due to the long length of the driving channel region A1, the driving range of the gate voltage applied to the driving gate electrode G1 is extended, thereby allowing accurate control of the grayscale of light emitted from the organic light emitting device OLED and higher display quality.

[0094] The switching semiconductor layer AS2 includes a switching channel region A2 and a switching source region S2 and a switching drain region D2 respectively located at both sides of the switching channel region A2. The switching drain region D2 is connected to the driving source region S1.

[0095] The compensation semiconductor layer AS3 includes compensation channel regions A3a and A3c and a compensation source region S3 and a compensation drain region D3 located at opposite sides of the compensation channel regions A3a and A3c, respectively. The compensation TFT T3 formed in the compensation semiconductor layer AS3 is a double TFT and includes two compensation channel regions A3a and A3c, and a region A3b between the compensation channel regions A3a and A3c is a doped region and partially corresponds to a source region of one of the double TFTs and a drain region of the other.

[0096] The first initialization semiconductor layer AS4 includes first initialization channel regions A4a and A4c and first initialization source region S4 and first initialization drain region D4 located at opposite sides of the first initialization channel regions A4a and A4c, respectively. The first initialization TFT T4 formed in the first initialization semiconductor layer AS4 is a double TFT having two first initialization channel regions A4a and A4c, and a region A4b between the first initialization channel regions A4a and A4c is a doped region and partially corresponds to a source region of one of the double TFTs and a drain region of the other.

[0097] The operation control semiconductor layer AS5 includes an operation control channel region A5, and an operation control source region S5 and an operation control drain region D5 respectively located at opposite sides of the operation control channel region A5. The operation control drain region D5 may be connected to the driving source region S1.

[0098] The emission control semiconductor layer AS6 includes an emission control channel region A6, and an emission control source region S6 and an emission control drain region D6 respectively located at opposite sides of the emission control channel region A6. The emission control source region S6 may be connected to the driving drain region D1.

[0099] The second initialization semiconductor layer AS7 includes a second initialization channel region A7 and a second initialization source region S7 and a second initialization drain region D7 respectively located at opposite sides of the second initialization channel region A7.

[0100] The first gate insulating layer 112 is located on the semiconductor layers AS1 to AS7. The first gate insulating layer 112 may include an inorganic material, and the inorganic material may include an oxide or a nitride. For example, the first gate insulating layer 112 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and zinc oxide (ZnO 2 ) etc.

[0101] According to some exemplary embodiments, semiconductor layers AS1 to AS7 of each of the plurality of pixels PX are formed separately from each other. For example, semiconductor layers AS1 to AS7 of the first pixel PX1 are formed to be separated from semiconductor layers AS1 to AS7 of the second pixel PX2.

[0102] refer to Figure 4 , Figure 6 and Fig. 9, the scan line 121, the previous scan line 122, the emission control line 123, and the driving gate electrode G1 are arranged on the first gate insulating layer 112. The scan line 121, the previous scan line 122, the emission control line 123, and the driving gate electrode G1 are arranged on the same layer and include the same material. For example, the scan line 121, the previous scan line 122, the emission control line 123, and the driving gate electrode G1 may include molybdenum (Mo), copper (Cu), or titanium (Ti), etc., and may have a single-layer or multi-layer structure.

[0103] The driving gate electrode G1 is an island-type electrode and is arranged to overlap the driving channel region A1 of the driving semiconductor layer AS1. The driving gate electrode G1 can be used not only as a gate electrode of the driving TFT T1, but also as a lower electrode C1 of the capacitor Cst. That is, the driving gate electrode G1 and the lower electrode C1 can be regarded as a single element.

[0104] A portion or a protruding portion of the scan line 121 , the previous scan line 122 , and the emission control line 123 corresponds to the gate electrodes G2 to G7 of the TFTs T2 to T7 .

[0105] The region of the scan line 121 overlapping with the switch channel region A2 and the compensation channel regions A3a and A3c corresponds to the switch gate electrode G2 and the compensation gate electrodes G3a and G3b, respectively. The region of the previous scan line 122 overlapping with the first initialization channel regions A4a and A4c and the second initialization channel region A7 corresponds to the first initialization gate electrodes G4a and G4b and the second initialization gate electrode G7, respectively. The region of the emission control line 123 overlapping with the operation control channel region A5 and the emission control channel region A6 corresponds to the operation control gate electrode G5 and the emission control gate electrode G6, respectively.

[0106] The compensation gate electrodes G3 a and G3 b are double gate electrodes including a first compensation gate electrode G3 a and a second compensation gate electrode G3 b , and may prevent or reduce generation of leakage current.

[0107] The second gate insulating layer 113 is located on the scan line 121, the previous scan line 122, the emission control line 123 and the driving gate electrode G1. The second gate insulating layer 113 may include an inorganic material, and the inorganic material includes an oxide or a nitride. For example, the second gate insulating layer 113 may be made of silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and zinc oxide (ZnO 2) etc. are formed.

[0108] See also Figure 4 , Figure 7 and Fig. 9 , an upper electrode C2 of the capacitor Cst and the initialization voltage line 131 are located on the second gate insulating layer 113 .

[0109] The upper electrode C2 of the capacitor Cst and the initialization voltage line 131 are arranged on the same layer and may include the same material. For example, the upper electrode C2 of the capacitor Cst and the initialization voltage line 131 may include a conductive material (including molybdenum (Mo), copper (Cu) and / or titanium (Ti), etc.), and may have a single-layer or multi-layer structure including the above materials.

[0110] The upper electrode C2 of the capacitor Cst is arranged to overlap with the lower electrode C1 and has an opening OP1. The opening OP1 is formed by removing a portion of the upper electrode C2 and may have a single closed curve shape. Here, a single closed curve means a closed figure such as a polygon or a circle having a start point and an end point that meet when a point is drawn on a straight line or a curve. The upper electrode C2 having the opening OP1 may be regarded as having a ring shape.

[0111] The second gate insulating layer 113 disposed between the upper electrode C2 and the lower electrode C1 may be used as a dielectric layer of the capacitor Cst. The width of the upper electrode C2 in the first direction and the second direction may be greater than the width of the lower electrode C1 in the first direction and the second direction. Both ends of the lower electrode C1 in the second direction may be exposed through the opening OP1 defined in the upper electrode C2.

[0112] According to some exemplary embodiments, by including the capacitor Cst of the upper electrode C2 having the opening OP1, even when an overlay deviation and a critical dimension deviation occur during a manufacturing process of the organic light emitting display device, a capacitance variation can be minimized. This will be referred to later. Fig.10 and Fig.11 describe.

[0113] The interlayer insulating layer 114 is located on the upper electrode C2 of the capacitor Cst and the initialization voltage line 131. The interlayer insulating layer 114 may include an inorganic material including an oxide or a nitride. For example, the interlayer insulating layer 114 may be made of silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2) and zinc oxide (ZnO 2 ) etc. are formed.

[0114] See also Figure 4 , Figure 8 and Fig. 9 , a second connection wiring extending in the second direction is arranged on the interlayer insulating layer 114. The second connection wiring is insulated from the first connection wiring by the interlayer insulating layer 114. The second connection wiring may include a data line 151, a driving voltage line 152, a first node connection line 153, a second node connection line 154, and a connection electrode 155.

[0115] The data line 151, the driving voltage line 152, the first node connection line 153, the second node connection line 154 and the connection electrode 155 are arranged on the same layer and include the same material. For example, the data line 151, the driving voltage line 152, the first node connection line 153, the second node connection line 154 and the connection electrode 155 can be formed of a highly conductive material such as a metal or a conductive oxide.

[0116] The data line 151 is connected to the switching source region S2 of the switching TFT T2 through a contact hole CNT8 passing through the interlayer insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112. The data line 151 may connect a plurality of pixels arranged in the second direction.

[0117] The driving voltage line 152 is connected to the operation control source region S5 of the operation control TFT T5 through a contact hole CNT6 passing through the interlayer insulating layer 114 , the second gate insulating layer 113 , and the first gate insulating layer 112 .

[0118] In addition, the driving voltage line 152 is connected to the upper electrode C2 of the capacitor Cst through a contact hole CNT7 passing through the interlayer insulating layer 114. The driving voltage line 152 may connect a plurality of pixels arranged in the second direction.

[0119] The first node connection line 153 connects the driving gate electrode G1 and the compensation drain region D3 of the compensation TFT T3 through the contact holes CNT1 and CNT2. The driving gate electrode G1 as an island type may be electrically connected to the compensation TFT T3 through the first node connection line 153. Since the driving gate electrode G1 serves as the lower electrode C1 of the capacitor Cst, the first node connection line 153 may be regarded as being connected to the lower electrode C1.

[0120] The first end of the first node connection line 153 is connected to the lower electrode C1 through the contact hole CNT1. The contact hole CNT1 may be arranged in the opening OP1 of the upper electrode C2 to connect the first end of the first node connection line 153 to the lower electrode C1. The opening OP1 may have a larger size than the contact hole CNT1 so that the contact hole CNT1 may not contact the upper electrode C2.

[0121] The second end of the first node connection line 153 is connected to the compensation TFT T3 through the contact hole CNT2. The contact hole CNT2 is formed to penetrate the interlayer insulating layer 114, the second gate insulating layer 113 and the first gate insulating layer 112 so that the second end of the first node connection line 153 is connected to the compensation drain region D3 of the compensation TFT T3.

[0122] The second node connection line 154 transmits an initialization voltage Vint for initializing the driving TFT T1 and the pixel electrode 210. The second node connection line 154 is connected to the first initialization TFT T4 and the second initialization TFT T7 through a contact hole CNT3 passing through the interlayer insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112, and is connected to the initialization voltage line 131 through a contact hole CNT4 passing through the interlayer insulating layer 114.

[0123] The connection electrode 155 may be connected to the emission control drain region D6 of the emission control TFT T6 through the contact hole CNT5 passing through the interlayer insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112. The connection electrode 155 may be connected to the pixel electrode 210 to transmit a signal applied through the emission control TFT T6 to the pixel electrode 210.

[0124] The planarization layer 116 is located above the data line 151, the driving voltage line 152, the first node connection line 153, the second node connection line 154, and the connection electrode 155. The planarization layer 116 may include an organic material such as at least one of acryl, benzocyclobutene (BCB), polyimide (PI), and hexamethyldisiloxane (HMDSO). Alternatively, the planarization layer 116 may include an inorganic material. The planarization layer 116 may substantially planarize the upper portion of the protective layer covering the TFTs T1 to T7. The planarization layer 116 may have a single-layer or multi-layer structure.

[0125] An organic light emitting device OLED having a pixel electrode 210 , an opposing electrode 230 , and an intermediate layer 220 disposed between the pixel electrode 210 and the opposing electrode 230 and including an emission layer may be disposed on the planarization layer 116 .

[0126] The pixel electrode 210 is connected to the connection electrode 155 through a contact hole defined in the planarization layer 116 , and is connected to the emission control drain region D6 of the emission control TFT T6 through the connection electrode 155 .

[0127] The pixel defining layer 117 may be disposed on the planarization layer 116. The pixel defining layer 117 has an opening corresponding to each of the pixels or sub-pixels, that is, an opening exposing at least the central portion of the pixel electrode 210, thereby defining the pixel. The pixel defining layer 117 may increase the distance between the edge of the pixel electrode 210 and the counter electrode 230 above the pixel electrode 210, thereby preventing arcing at the edge of the pixel electrode 210, etc. The pixel defining layer 117 may be formed of an organic material such as polyimide or HMDSO.

[0128] The intermediate layer 220 of the organic light emitting device OLED may include a low molecular weight material or a polymer material. When a low molecular weight material is included, the intermediate layer 220 may have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an organic emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL) are stacked in a single layer or a multilayer structure, and may include various organic materials such as copper phthalocyanine (CuPc), N,N'-di(naphthalene-1-yl)-N,N'-biphenyl-benzidine (NPB), and tri-8-hydroxyquinoline aluminum (Alq 3 ) These layers can be formed using vacuum deposition methods; however, any suitable process can be utilized.

[0129] When the intermediate layer 220 includes a polymer material, the intermediate layer 220 may generally have a structure including a hole transport layer (HTL) or an organic emission layer (EML). The hole transport layer (HTL) may include poly (3,4-ethylene-dioxythiophene) (PEDOT), and the emission layer may include a polymer material such as a polyphenylene vinylene (PPV)-based material or a polyfluorene-based material. The intermediate layer 220 may be formed using, for example, a screen printing method, an inkjet printing method, or a laser induced thermal imaging (LITI) method.

[0130] The intermediate layer 220 is not limited to the above and may have various structures. For example, the intermediate layer 220 may include a single layer covering the plurality of pixel electrodes 210 or layers patterned to correspond to the plurality of pixel electrodes 210 , respectively.

[0131] The counter electrode 230 is disposed on the display area DA and may be disposed to cover the display area DA, such as Fig. 9 That is, the counter electrode 230 may be integrally formed with respect to a plurality of organic light emitting devices (OLEDs), and correspond to a plurality of pixel electrodes 210 .

[0132] Since the organic light emitting device OLED may be easily damaged by moisture or oxygen from the outside, the encapsulation layer 300 may cover and protect the organic light emitting device OLED. The encapsulation layer 300 may cover the display area DA and extend out of the display area DA. The encapsulation layer 300 may include a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330.

[0133] The first inorganic encapsulation layer 310 covers the counter electrode 230 and may include ceramic, metal oxide, metal nitride, metal carbide, metal oxynitride, indium oxide (In 2 O 3 ), tin oxide (SnO 2 ), indium tin oxide (ITO), silicon oxide, silicon nitride and / or silicon oxynitride, etc. Other layers such as a cap layer (not shown) may also be optionally located between the first inorganic encapsulation layer 310 and the counter electrode 230. The first inorganic encapsulation layer 310 is formed along the structure below the first inorganic encapsulation layer 310, and therefore, the upper surface of the first inorganic encapsulation layer 310 is uneven.

[0134] The organic encapsulation layer 320 covers the first inorganic encapsulation layer 310. Unlike the first inorganic encapsulation layer 310, the organic encapsulation layer 320 may have a substantially flat upper surface. For example, the upper surface of the organic encapsulation layer 320 may be substantially flat at a portion corresponding to the display area DA. The organic encapsulation layer 320 may be formed of at least one material selected from the group consisting of acrylic resin, methacrylic acid, polyester, polyethylene, polypropylene, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and HMDSO.

[0135] The second inorganic encapsulation layer 330 covers the organic encapsulation layer 320 and can be made of ceramic, metal oxide, metal nitride, metal carbide, metal oxynitride, indium oxide (In 2 O 3 ), tin oxide (SnO 2 ), indium tin oxide (ITO), silicon oxide, silicon nitride and / or silicon oxynitride.

[0136] Since the encapsulation layer 300 includes the first inorganic encapsulation layer 310, the organic encapsulation layer 320, and the second inorganic encapsulation layer 330, according to such a multi-layer structure of the encapsulation layer 300, even when cracks occur in the encapsulation layer 300, it is possible to prevent the cracks from being connected between the first inorganic encapsulation layer 310 and the organic encapsulation layer 320 or between the organic encapsulation layer 320 and the second inorganic encapsulation layer 330. Therefore, it is possible to prevent or minimize the formation of a path through which moisture, oxygen, etc. penetrate from the outside into the display area DA.

[0137] Although not shown, spacers for preventing mask imprinting may be further included on the pixel defining layer 117 , and various functional layers (such as a polarizing layer for reducing external light reflection, a black matrix, a color filter, and / or a touch screen layer having a touch electrode) may be included on the encapsulation layer 300 .

[0138] Fig.10 is a diagram illustrating a method according to some exemplary embodiments Figure 4 A plan view of the lower and upper electrodes of the capacitor shown. Fig.11 FIG. 1 illustrates a method according to some exemplary embodiments. Figure 4 The overlapping area between the lower electrode and the upper electrode of the capacitor. Fig.12 The diagram shows the Fig.10 A comparative example of the exemplary embodiment of FIG.

[0139] Fig.10 The diagram is included in Figure 4 1 is a plan view of a lower electrode C1 and an upper electrode C2 of a capacitor Cst in a pixel circuit shown. Fig.11 Pictured Figure 4 The overlapping area between the lower electrode C1 and the upper electrode C2 of the capacitor Cst of the pixel circuit. Fig.12 The diagram is based on the Fig.10 Schematic plan view of an overlapping area of ​​a lower electrode C1 ′ and an upper electrode C2 ′ of a capacitor according to a comparative example of the exemplary embodiment of FIG.

[0140] See also Fig.10 , when viewed in a plan view, the edge of the upper electrode C2 of the capacitor Cst is spaced outward from the edge of the lower electrode C1 to surround the lower electrode C1. The edge of the upper electrode C2 is spaced from the edge of the lower electrode C1 by at least a first spacing distance sd1 relative to the second direction, and the edge of the upper electrode C2 is spaced from the edge of the lower electrode C1 by at least a second spacing distance sd2 relative to the first direction. The width w21 of the upper electrode C2 in the first direction is greater than the width w11 of the lower electrode C1 in the first direction, and the width w22 of the upper electrode C2 in the second direction is greater than the width w12 of the lower electrode C1 in the second direction.

[0141] The first spacing distance sd1 and the second spacing distance sd2 may be designed by considering the maximum overlay deviation that may occur during one or more manufacturing processes. Here, when two or more layers overlapping each other are formed and each layer is shifted in the upward, downward, leftward, and rightward directions, the overlapping area of ​​the shifted layers is different from the overlapping area originally designed, and this difference in the overlapping area is called overlay deviation. When a conductive layer is formed on a substrate and a photolithography process is performed on the conductive layer, an overlay deviation may occur due to misalignment between the substrate and the mask or misalignment between the substrate and the exposure device.

[0142] According to some exemplary embodiments, the edge of the upper electrode C2 is spaced outward from the edge of the lower electrode C1, and therefore, even if the upper electrode C2 is displaced relative to the lower electrode C1 about the design value, the overlapping area between the lower electrode C1 and the upper electrode C2 can be kept constant. That is, despite the presence of superposition deviation, the capacitor Cst according to various exemplary embodiments can provide a constant capacitance. In addition, according to various exemplary embodiments, the upper electrode C2 has an opening OP1, the opening OP1 has a single closed curve shape, and the overlapping area of ​​the upper electrode C2 and the lower electrode C1 is divided into two areas by the opening OP1, namely, a first area CA1 and a second area CA2.

[0143] exist Fig.10 The opening OP1 is formed to have a long width in the second direction, thereby exposing both ends of the lower electrode C1 arranged in the second direction. Therefore, an overlapping region of the upper electrode C2 and the lower electrode C1 may be divided into two regions, namely, a first region CA1 and a second region CA2.

[0144] exist Fig.10 In the embodiment, the opening OP1 has a rectangular shape having a longer width in the second direction, but the exemplary embodiment is not limited thereto and various modifications may be made. For example, the opening OP1 may have rounded edges, and the width of the opening OP1 in the first direction may not be constant.

[0145] The capacitance of the capacitor Cst is determined by the following Formula 1. In Formula 1, C represents capacitance, ε represents dielectric constant, A1 and A2 represent areas of the first and second regions CA1 and CA2, respectively, and d represents a distance between the lower electrode C1 and the upper electrode C2.

[0146] C=ε(A1+A2) / d…Formula 1

[0147] That is, the capacitance of the capacitor Cst according to some exemplary embodiments is determined by the dielectric constant ε of the second gate insulating layer 113, the distance d between the lower electrode C1 and the upper electrode C2, and the area A1+A2 of the overlapping region of the lower electrode C1 and the upper electrode C2. Therefore, when the area A1+A2 of the overlapping region changes, the capacitance changes.

[0148] Therefore, if the overlap area changes according to the threshold change, the capacitance of the capacitor changes. Threshold deviation refers to a size deviation that is difficult to control by an etching process. When patterning is performed by a photolithography process and an etching process, a threshold deviation may occur according to the size of the photoresist due to the photolithography process and etching conditions, etc. According to some exemplary embodiments, even if a threshold deviation occurs, the capacitance change can be minimized.

[0149] If the opening OP1 ′ in the upper electrode C2 ′ is disposed inside the lower electrode C1 ′ so that the upper electrode C2 ′ and the lower electrode C1 ′ are not separated by the opening OP1 ′, the capacitance value may be sensitively changed according to the threshold deviation.

[0150] For example, due to the threshold deviation, the opening OP1' may be formed in which the opening is etched further by Δx than the design value in the first direction and further by Δy than the design value in the second direction. In this case, the overlap region is affected by both Δx and Δy.

[0151] However, according to various exemplary embodiments, Fig.11 As shown, if the overlapped area is separated by the opening OP1, the overlapped area is only affected by Δx. Therefore, a capacitance variation of the capacitor Cst included in the organic light emitting display device according to various exemplary embodiments may be insensitive to process errors.

[0152] Fig.13 is a schematic layout diagram illustrating positions of a capacitor and a plurality of thin film transistors included in a pixel circuit according to some exemplary embodiments. Fig.14 FIG. 1 illustrates a method according to some exemplary embodiments. Fig.13 The overlapping area between the lower electrode and the upper electrode of the capacitor. Fig.13 and Fig.14 In an exemplary embodiment of Figure 4 The same reference numerals as in the drawings denote the same elements, and thus, their repeated description will be omitted.

[0153] See also Fig.13 and Fig.14 , a capacitor Cst_1 included in the organic light emitting display device includes a lower electrode C1 and an upper electrode C2_1 , and the upper electrode C2_1 includes an opening OP2 having a single closed curve shape.

[0154] A contact hole CNT1 passing through the interlayer insulating layer 114 and the second gate insulating layer 113 is formed in the opening OP2 to be connected to the lower electrode C1. The opening OP2 is larger in size than the contact hole CNT1 so that the contact hole CNT1 may not contact the upper electrode C2_1.

[0155] A first end of the first node connection line 153 may be connected to the lower electrode C1 through a contact hole CNT1. A second end of the first node connection line 153 may be connected to the compensation drain region D3 of the compensation TFT T3 through a contact hole CNT2 passing through the interlayer insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112.

[0156] The upper electrode C2_1 may be connected to the driving voltage line 152 through the contact hole CNT7_1 , and the driving voltage is transmitted through the driving voltage line 152 .

[0157] When viewed in plan, the edge of the upper electrode C2_1 is outwardly spaced from the edge of the lower electrode C1 and surrounds the lower electrode C1. The width of the upper electrode C2_1 in the first direction is greater than that of the lower electrode C1 in the first direction, and the width of the upper electrode C2_1 in the second direction is greater than that of the lower electrode C1 in the second direction.

[0158] Due to these characteristics, the overlapping area of ​​the lower electrode C1 and the upper electrode C2_1 can be kept constant despite the presence of superposition deviation.

[0159] In addition, according to various exemplary embodiments, the upper electrode C2_1 has an opening OP2 having a single closed curve shape, and an overlapping region of the upper electrode C2_1 and the lower electrode C1 is divided into two regions, ie, a first region CA1_1 and a second region CA2_1 , by the opening OP2 .

[0160] The width of the opening OP2 is longer in the first direction than in the second direction, thereby exposing both ends of the lower electrode C1 arranged in the first direction. Therefore, the overlapping area of ​​the upper electrode C2_1 and the lower electrode C1 may be divided into two areas, namely, a first area CA1_1 and a second area CA2_1.

[0161] See also Fig.13 and Fig.14 Although the opening OP2 has a rectangular shape having a longer width in the second direction, the exemplary embodiment is not limited thereto, and other various modifications may be made. For example, the opening OP2 may have rounded corners, or the width of the opening OP2 in the second direction may not be constant.

[0162] Due to these characteristics, the overlap area of ​​the lower electrode C1 and the upper electrode C2_1 of the capacitor Cst_1 according to various exemplary embodiments is only affected by Δy. Therefore, the capacitance variation of the capacitor Cst included in the organic light emitting display device according to various exemplary embodiments may be insensitive to process errors.

[0163] According to various exemplary embodiments, in a capacitor included in an organic light emitting display device, since an overlap region of an upper electrode and a lower electrode is separated by an opening portion of the upper electrode, even when an overlay deviation and a critical dimension deviation occur during manufacturing of the organic light emitting display device, a capacitance variation can be minimized. However, the scope of the present disclosure is not limited by the above effects.

[0164] Although specific exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but is limited to the broader scope of the appended claims and various obvious modifications and equivalent arrangements, which will be apparent to those of ordinary skill in the art.

Claims

1. A thin film transistor array substrate, comprising: substrate; at least one thin film transistor located on the substrate; A capacitor on the substrate, the capacitor comprising: a lower electrode on the substrate; an upper electrode overlapping the lower electrode, the upper electrode comprising an opening having a single closed curve shape; and a dielectric layer between the lower electrode and the upper electrode; an interlayer insulating layer covering the capacitor; and a node connection line located on the interlayer insulating layer and electrically connecting the capacitor to the at least one thin film transistor, wherein the overlapping area of ​​the lower electrode and the upper electrode is divided into two separate areas by the opening, and Wherein, when viewed in a plan view, the opening exposes opposite ends of the lower electrode.

2. The thin film transistor array substrate according to claim 1, wherein: When viewed in a plan view, an edge of the upper electrode is spaced outward from an edge of the lower electrode, and the edge of the upper electrode surrounds the edge of the lower electrode.

3. The thin film transistor array substrate according to claim 1, further comprising: a node contact hole located in the opening and passing through the interlayer insulating layer and the dielectric layer, The first end of the node connection line is connected to the lower electrode through the node contact hole.

4. The thin film transistor array substrate according to claim 3, wherein: When viewed in a plan view, a size of the opening is larger than a size of the node contact hole.

5. The thin film transistor array substrate according to claim 1, further comprising: a scan line extending in a first direction; as well as A data line extending in a second direction intersecting the first direction, The opening has a rectangular shape including longer sides in the first direction.

6. The thin film transistor array substrate according to claim 1, further comprising: a scan line extending in a first direction; as well as A data line extending in a second direction intersecting the first direction, wherein the opening has a rectangular shape including a longer side in the second direction.

7. The thin film transistor array substrate according to claim 1, further comprising: a driving voltage line located in the same layer as the node connection line, wherein a driving voltage is transmitted through the driving voltage line, and The upper electrode is connected to the driving voltage line through a contact hole.

8. The thin film transistor array substrate according to claim 1, further comprising: a driving thin film transistor overlapping the capacitor, The lower electrode forms a driving gate electrode of the driving thin film transistor, and the lower electrode is equivalent to the driving gate electrode.

9. The thin film transistor array substrate according to claim 8, wherein: The driving semiconductor layer of the driving thin film transistor has a bent shape.

10. The thin film transistor array substrate according to claim 8, wherein: The at least one thin film transistor comprises a compensation thin film transistor; A first end of the node connection line is connected to the lower electrode; and The second end of the node connection line is connected to the compensation drain region of the compensation thin film transistor.

11. An organic light emitting display device, comprising: substrate; a driving voltage line located on the substrate, the driving voltage line being configured to transmit a driving voltage; a scan line extending on the substrate in a first direction; a data line insulated from the scan line and extending in a second direction intersecting the first direction; a pixel circuit electrically connected to the driving voltage line, the scanning line and the data line, the pixel circuit comprising a capacitor and at least one thin film transistor, the capacitor comprising: a lower electrode located on the substrate; an upper electrode overlapping the lower electrode, the upper electrode comprising an opening having a single closed curve shape; and a dielectric layer located between the lower electrode and the upper electrode; an interlayer insulating layer covering the capacitor; and a node connection line disposed on the interlayer insulating layer and electrically connecting the capacitor to the at least one thin film transistor, wherein the overlapping area of ​​the lower electrode and the upper electrode is divided into two separate areas by the opening, and Wherein, when viewed in a plan view, the opening exposes opposite ends of the lower electrode.

12. The organic light emitting display device according to claim 11, wherein: When viewed in a plan view, an edge of the upper electrode is spaced outward from an edge of the lower electrode, and the edge of the upper electrode surrounds the edge of the lower electrode.

13. The organic light emitting display device according to claim 11, further comprising: a node contact hole located in the opening and passing through the interlayer insulating layer and the dielectric layer, The first end of the node connection line is connected to the lower electrode through the node contact hole.

14. The organic light emitting display device according to claim 13, wherein: The size of the opening is larger than the size of the node contact hole.

15. The organic light emitting display device according to claim 11, wherein: The opening extends in the first direction or the second direction.

16. The organic light emitting display device according to claim 11, wherein: The driving voltage line and the node connection line are located in the same layer; and The upper electrode is connected to the driving voltage line through a contact hole.

17. The organic light emitting display device according to claim 11, wherein: The at least one thin film transistor includes a driving thin film transistor overlapping the capacitor; and The lower electrode forms a driving gate electrode of the driving thin film transistor, and the lower electrode and the driving gate electrode are a single unit.

18. The organic light emitting display device according to claim 17, wherein: The at least one thin film transistor further comprises a compensation thin film transistor; A first end of the node connection line is connected to the lower electrode; and The second end of the node connection line is connected to the compensation drain region of the compensation thin film transistor.

Images