Using the system abstraction layer to provide multi-protocol storage devices

Abstract

A multi-protocol storage device using a system abstraction layer is provided. The provided storage device includes a control component and an NVM storage medium coupled to the control component, the control component includes a CPU, a host interface and a medium interface, an operating system and one or more tasks are run on the CPU, the tasks use services provided by the operating system through a system abstraction layer interface provided by the operating system, the operating system includes one or more drivers, and the operating system schedules one or more tasks; the one or more tasks run by the CPU process IO commands to access the storage device.

Description

Technical Field

[0001] The present application relates to a storage device, and in particular, to a storage device that provides support for multiple storage protocols based on a system abstraction layer of the storage device. Background Art

[0002] Figure 1 The block diagram of the solid-state storage device is shown. The solid-state storage device 102 is coupled to the host to provide storage capacity for the host. The host and the solid-state storage device 102 can be coupled in a variety of ways, including but not limited to connecting the host and the solid-state storage device 102 through, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe), NVMe (NVM Express), Ethernet, Fiber Channel, wireless communication network, etc. The host can be an information processing device that can communicate with the storage device in the above manner, such as a personal computer, a tablet computer, a server, a portable computer, a network switch, a router, a cellular phone, a personal digital assistant, etc. The storage device 102 includes an interface 103 , a control component 104 , one or more NVM chips 105 , and a DRAM (Dynamic Random Access Memory) 110 .

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), XP oint memory, etc. are common NVMs.

[0004] The interface 103 may be adapted to exchange data with the host via, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, etc.

[0005] The control component 104 is used to control data transmission between the interface 103, the NVM chip 105 and the DRAM 110, and is also used for storage management, host logical address to flash physical address mapping, erase leveling, bad block management, etc. The control component 104 can be implemented in a variety of ways such as software, hardware, firmware or a combination thereof. For example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit) or a combination thereof. The control component 104 can also include a processor (CPU) or a controller, in which software is executed to manipulate the hardware of the control component 104 to process IO (Input / Output) commands. The control component 104 can also be coupled to the DRAM 110 and can access the data of the DRAM 110. The FTL table and / or the data of the cached IO commands can be stored in the DRAM.

[0006] The control component 104 includes a flash memory interface controller (or medium interface controller, flash memory channel controller), which is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in a manner that complies with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI" and the like.

[0007] A memory target is one or more logic units (LUNs) within a NAND flash package that share a CE (Chip Enable) signal. A NAND flash package may include one or more dies. Typically, a logic unit corresponds to a single die. A logic unit may include multiple planes. Multiple planes within a logic unit can be accessed in parallel, and multiple logic units within a NAND flash chip can execute commands and report status independently of each other.

[0008] Data is usually stored and read on a storage medium in pages. Data is erased in blocks. A block (also called a physical block) contains multiple pages. A block contains multiple pages. A page on a storage medium (called a physical page) has a fixed size, such as 17664 bytes. A physical page can also have other sizes.

[0009] A chunk contains physical blocks from each of multiple logical units (LUNs), also called logical unit groups. Each logical unit can provide one physical block for a chunk. For example, Figure 2In the schematic diagram of the block shown, the block is constructed on every 16 logical units (LUNs). Each block includes 16 physical blocks from the 16 logical units (LUNs). Figure 2 In the example of , chunk 0 includes physical chunk 0 from each of the 16 logical units (LUNs), and chunk 1 includes physical chunk 1 from each logical unit (LUN). Chunks may also be structured in a variety of other ways.

[0010] For example, page stripes are constructed in large blocks, and physical pages with the same physical address in each logical unit (LUN) constitute a "page stripe". Figure 2 In , physical pages P0-0, P0-1, ... and P0-x constitute page stripe 0, wherein physical pages P0-0, P0-1, ... and P0-14 are used to store user data, and physical pages P0-x are used to store check data calculated based on all user data in the stripe. Similarly, Figure 2 In the embodiment, physical page P2-0, physical page P2-1, ... and physical page P2-x constitute page stripe 2. The physical page for storing the check data can be located at any position in the page stripe. As another example, in the Chinese patent application with application number 201710752321.0, Figure 3 A and its instructions Figure 3 In the related description of A, another construction method of large blocks is provided.

[0011] In a solid-state storage device, the FTL (Flash Translation Layer) is used to maintain the mapping information from the logical address to the physical address. The logical address constitutes the storage space of the solid-state storage device perceived by the upper-layer software such as the operating system. The physical address is the address used to access the physical storage unit of the solid-state storage device. In the related art, the address mapping can also be implemented using the intermediate address form. For example, the logical address is mapped to the intermediate address, and then the intermediate address is further mapped to the physical address.

[0012] The table structure that stores the mapping information from logical addresses to physical addresses is called an FTL table. The FTL table is an important metadata in a solid-state storage device. The FTL table includes multiple FTL table entries (or table items). In one case, each FTL table entry records the correspondence between a logical page address and a physical page. In another case, each FTL table entry records the correspondence between a plurality of continuous logical page addresses and a plurality of continuous physical pages. In yet another case, each FTL table entry records the correspondence between a logical block address and a physical block address. In still yet another case, the FTL table records the mapping relationship between a logical block address and a physical block address, and / or the mapping relationship between a logical page address and a physical page address.

[0013] When processing a read command from the host, the solid-state storage device uses the logical address carried in the read command to obtain the corresponding physical address from the FTL table, and sends a read request to the NVM chip based on the physical address, and receives the data output by the NVM chip in response to the read request. When processing a write command from the host, the solid-state storage device assigns a physical address to the write command, records the correspondence between the logical address of the write command and the assigned physical address in the FTL table, and sends a write request to the NVM chip based on the assigned physical address.

[0014] There are many storage protocols (also called storage interface protocols) according to which storage devices are accessed. For example, the SCSI (Small Computer System Interface) protocol and the NVMe (NVM Express) protocol. In the SCSI protocol and the NVMe protocol, the storage device exposes a linear logical address space to the electronic device (such as a host) coupled thereto. The host uses the logical address to access the storage device.

[0015] There is also an OCSSD (Open Channel Solid State Drive) storage protocol ("Open Channel Solid Drive Specification" Revision 2.0, January 29, 2018, available from http: / / lightnvm.io / docs / OCSS D-2_0-20180129.pdf), which exposes more physical information related to the NVM storage medium to the electronic device coupled with the storage device, so that the host uses the addressing method defined by OCSSD to access the storage medium of the storage device. The addressing method defined by the OCSSD protocol can be used in the NVMe protocol.

[0016] The addressing methods defined by OCSSD include PU (Parallel Unit), group, chunk, logical block and write unit, and their respective meanings can be obtained from the OCSSD protocol. Summary of the invention

[0017] There are a variety of available control components, NVM chips, memories, etc. for constructing storage devices. In order to adapt to changes in control components, NVM chips, memories, etc., it is necessary to change or redevelop the software (or firmware) running in the processor of the control component, which prolongs the development cycle of the storage device, increases the development cost, and introduces more defects in the development process. It is hoped that a system abstraction layer will be provided to provide a unified system architecture for the software (or firmware) running in the processor of the control component. The unified system architecture is used for a variety of storage devices with different control components, NVM chips, and memories, and is used by or interacts with the software (or firmware) running in the processor of the control component. The system architecture includes a unified form of NVM storage medium, a unified interface for using control components and memories, etc.

[0018] It is hoped that a unified NVM storage medium can be provided to solve the problem of the introduction of diverse NVM chips. NVM chips come from different manufacturers, are accessed with different interface commands, and have different capacities and storage unit configurations (number of physical blocks, number of physical pages included in a physical page, size of a physical page, etc.). The unified NVM storage medium shields the above differences, allowing the software (or firmware) running in the processor of the control component to access the NVM chip in a unified manner without taking into account the changes in the NVM chip.

[0019] Storage protocols are also diverse, such as OCSSD protocol, NVMe protocol, SCSI protocol, etc. The storage protocols supported by storage devices limit the use of storage devices. It is hoped that storage devices support multiple storage protocols so that storage devices can be applied to multiple scenarios and matched with multiple computers / servers without significantly increasing the complexity of control components and the cost of obtaining storage devices.

[0020] According to a first aspect of the present application, a first storage device is provided, comprising a control component and an NVM storage medium coupled to the control component, the control component comprising a CPU, a host interface and a medium interface, an operating system and one or more tasks running on the CPU, the tasks using services provided by the operating system through a system abstraction layer interface provided by the operating system, the operating system comprising one or more drivers, the operating system scheduling one or more tasks; the one or more tasks running on the CPU process IO commands to access the storage device.

[0021] According to the first storage device of the first aspect of the present application, a second storage device according to the first aspect of the present application is provided, wherein the task calls the driver through the system abstraction layer interface to obtain the IO command from the host interface.

[0022] According to the second storage device of the first aspect of the present application, a third storage device according to the first aspect of the present application is provided, wherein the task calls a driver of the host interface to obtain an IO command from the host interface.

[0023] According to the second storage device of the first aspect of the present application, a fourth storage device according to the first aspect of the present application is provided, wherein the task calls a queue driver to obtain an IO command from a queue of a host interface.

[0024] According to one of the first to fourth storage devices of the first aspect of the present application, a fifth storage device according to the first aspect of the present application is provided, wherein one or more tasks run at the same privilege level as the operating system.

[0025] According to one of the first to fourth storage devices of the first aspect of the present application, a sixth storage device according to the first aspect of the present application is provided, wherein one or more tasks and the operating system run at a different privilege level.

[0026] According to the sixth storage device of the first aspect of the present application, there is provided a seventh storage device according to the first aspect of the present application, wherein a privilege level switch occurs in response to a task calling a system abstraction layer interface.

[0027] According to one of the first to seventh storage devices of the first aspect of the present application, there is provided an eighth storage device according to the first aspect of the present application, wherein the task calls a media interface driver to access an NVM storage medium.

[0028] According to one of the first to eighth storage devices of the first aspect of the present application, a ninth storage device according to the first aspect of the present application is provided, wherein the media interface driver includes a virtual media layer program, and the virtual media layer program maps addresses that comply with the OCSSD protocol to physical addresses of the NVM chip.

[0029] According to the ninth storage device of the first aspect of the present application, a tenth storage device according to the first aspect of the present application is provided, wherein one or more tasks provide an address complying with the OCSSD protocol to a media interface driver to access the NVM chip.

[0030] According to the tenth storage device of the first aspect of the present application, an eleventh storage device according to the first aspect of the present application is provided, wherein the IO command indication received by the task from the host interface complies with the address of the OCSSD protocol, and the task provides the address complies with the OCSSD protocol to the media interface driver.

[0031] According to one of the ninth to eleventh storage devices of the first aspect of the present application, a twelfth storage device according to the first aspect of the present application is provided, wherein the IO command received by the task from the host interface indicates a logical address, and the task obtains an address corresponding to the logical address and complies with the OCSSD protocol and provides it to the media interface driver.

[0032] According to one of the first to twelfth storage devices of the first aspect of the present application, a thirteenth storage device according to the first aspect of the present application is provided, wherein the task identifies the storage protocol followed by the IO command received from the host interface, and forwards the IO command to the corresponding task according to the storage protocol followed by the IO command.

[0033] According to one of the first to twelfth storage devices of the first aspect of the present application, a fourteenth storage device according to the first aspect of the present application is provided, wherein the host interface identifies the storage protocol followed by the received IO command, and notifies the corresponding task to process the IO command according to the storage protocol followed by the IO command.

[0034] According to one of the first to fourteenth storage devices of the first aspect of the present application, a fifteenth storage device according to the first aspect of the present application is provided, wherein one or more tasks are applications, and the application provides addresses that comply with the OCSSD protocol to a media interface driver to access the storage space of the storage device.

[0035] According to one of the ninth to twelfth storage devices of the first aspect of the present application, a sixteenth storage device according to the first aspect of the present application is provided, wherein the virtual media layer maps a group of addresses following the OCSSD protocol into a channel coupled to a control component, maps parallel units (PUs) following the OCSSD protocol into a logical unit coupled to the control component, and maps small blocks (blocks) of addresses following the OCSSD protocol into physical blocks coupled to the logical units.

[0036] According to the sixteenth storage device of the first aspect of the present application, a seventeenth storage device according to the first aspect of the present application is provided, wherein the virtual media layer also maps the logical blocks of addresses that comply with the OCSSD protocol to physical pages in the physical blocks, or maps the write units of addresses that comply with the OCSSD protocol to physical pages in the physical blocks.

[0037] According to one of the ninth to twelfth storage devices of the first aspect of the present application, an eighteenth storage device according to the first aspect of the present application is provided, wherein a task identifies the storage protocol followed by an IO command received from a host interface, and if the IO command follows the OCSSD protocol, the task obtains an address that follows the OCSSD protocol from the IO command, and provides the address that follows the OCSSD protocol to a media interface driver; if the IO command follows the NVMe protocol, the task obtains a logical address that follows the NVMe protocol from the IO command, obtains an address that follows the OCSSD protocol corresponding to the logical address, and provides the address that follows the OCSSD protocol to the media interface driver.

[0038] According to the sixteenth or seventeenth storage device of the first aspect of the present application, a nineteenth storage device according to the first aspect of the present application is provided, wherein the virtual medium layer maps a parallel unit (PU) of an address complying with the OCSSD protocol to multiple logical units coupled to a control component, or maps multiple parallel units (PU) of an address complying with the OCSSD protocol to one logical unit coupled to a control component.

[0039] According to the nineteenth storage device of the first aspect of the present application, there is provided a twentieth storage device according to the first aspect of the present application, wherein the virtual medium layer maps small blocks (chunks) of addresses complying with the OCSSD protocol to multiple physical blocks of the NVM storage medium.

[0040] According to the twentieth storage device of the first aspect of the present application, there is provided a twenty-first storage device according to the first aspect of the present application, wherein a plurality of physical blocks mapped to the same chunk are organized into a chunk.

[0041] According to one of the first to twenty-first storage devices of the first aspect of the present application, a twenty-second storage device according to the first aspect of the present application is provided, wherein one of the tasks is a reliable virtual media management task, which organizes multiple PUs and / or small blocks (chunks) that comply with the OCSSD protocol into large blocks.

[0042] According to the twenty-second storage device of the first aspect of the present application, a twenty-third storage device according to the first aspect of the present application is provided, wherein the PU and the logical block are obtained from the large block provided by the reliable virtual media management task, and are used to carry the data to be written by the write IO command.

[0043] According to the twenty-second or twenty-third storage device of the first aspect of the present application, a twenty-fourth storage device according to the first aspect of the present application is provided, wherein in response to the presence of an uncorrectable error in the data read from the first logical block, a first large block to which the first logical block belongs is obtained from a reliable virtual media management task, and data is read from other logical blocks of the first large block to recover the data stored in the first logical block. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0045] Figure 1 is a block diagram of a solid-state storage device in the related art;

[0046] Figure 2 A schematic diagram of the bulk is shown;

[0047] Figure 3 is a schematic diagram of a storage device according to an embodiment of the present application;

[0048] Figure 4 is a schematic diagram of a storage device according to another embodiment of the present application;

[0049] Figure 5 is a schematic diagram of a storage device according to still another embodiment of the present application;

[0050] Figure 6 is a schematic diagram of a storage device according to yet another embodiment of the present application; and

[0051] Figure 7 is a schematic diagram of a storage device according to another embodiment of the present application. DETAILED DESCRIPTION

[0052] The following is a clear and complete description of the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0053] Figure 3 is a schematic diagram of a storage device according to an embodiment of the present application.

[0054] The storage device includes a control component coupled to a NVM storage medium and a memory (e.g., DRAM). Optionally, SRAM is used to partially or completely replace DRAM. SRAM can be integrated inside the control component. The control includes one or more CPUs, a media interface, a host interface, a storage controller for accessing the memory, an error checking unit (ECC), and optionally one or more accelerators. The media interface is used to access the NVM storage medium.

[0055] The host interface is used to exchange commands and data with the host. For example, the host and the storage device communicate through the NVMe / PCIe protocol, the host interface processes the PCIe protocol data packet, extracts the NVMe protocol command, and returns the processing result of the NVMe protocol command to the host. As another example, the host interface couples the storage device to the network, such as through Ethernet, wireless Ethernet, and Fibre Channel. The error checking unit is, for example, a BCH or LDPC codec, which is used to perform error checking encoding on data written to the NVM storage medium and error checking decoding on data read from the NVM storage medium. The accelerator includes one or more hardware accelerators, such as an AI (artificial intelligence) accelerator, a multimedia accelerator, a linked list / tree structure access accelerator, etc.

[0056] The software is run on the CPU of the control component, and the software cooperates with other hardware of the control component to process the IO commands received from the host interface to provide the storage function of the storage device, and optionally other functions. The software includes an operating system and one or more tasks. The operating system provides a system abstraction layer interface, and one or more tasks use the services provided by the operating system by using the system abstraction layer interface. One or more tasks are used to process IO requests alone or in collaboration. For example, one task is an FTL task, which is used to access the FTL table and output the physical address according to the received logical address; one task is a GC (garbage collection) task, which is used to recycle valid data in the NVM storage medium and erase the physical storage unit in the NVM storage medium; one task is a storage protocol (such as NVMe) task, which is used to identify the received IO commands or other commands that follow the storage protocol, request other tasks to assist in processing the command, and provide the command processing results to the issuer of the command in a manner that follows the storage protocol. Still optionally, one or more tasks running on the CPU are applications. The application provides multiple capabilities such as numerical calculation, keyword retrieval, image feature extraction, etc. As an example, the host and the application communicate through private commands or extended commands of the NVMe protocol. The processing results of the application are provided to the host through the host interface.

[0057] The operating system provides services (or functions) such as memory allocation, task management (creation, deletion, scheduling, etc.), inter-task communication, interrupt management, critical resource management, and provides services to tasks through the system abstraction layer interface. The operating system is, for example, an operating system that exists in the prior art or will be produced in the future. In one embodiment, the operating system does not distinguish between user-state tasks and kernel-state tasks, the operating system and the tasks run at the same privilege level of the CPU, and the tasks use the system abstraction layer interface without causing the switching of user-state and kernel-state, thereby improving the efficiency of task processing. In another embodiment, the operating system distinguishes between user-state tasks and kernel-state tasks, the operating system and the tasks run at different privilege levels of the CPU, and one or more tasks that process IO requests are run in kernel state, while the application (task) is run in user state, thereby ensuring the execution efficiency of the task that processes IO requests and preventing the application (task) from endangering the security of the operating system. When the task running in kernel state uses the system abstraction layer interface, it does not cause the switching of the system state (kernel state and user state), while when the application (task) uses the system abstraction layer interface, it causes the switching of the system state (from user state to kernel state, and then from kernel state back to user state after the operating system processing is completed).

[0058] The operating system also includes one or more drivers, such as a host interface driver, a media interface driver, a queue driver, a memory driver, etc. The driver provides a simplified way to use the hardware to facilitate tasks and operating systems to use the hardware. One or more system abstraction layer interfaces are used to access the hardware (host interface, media interface, memory controller, accelerator, error checking unit, etc.). The system abstraction layer interface uses the driver to complete the access to the hardware according to the received hardware access request and obtain the access result.

[0059] Optionally, the system abstraction layer interface also provides a standard operating system interface such as POSIX (Portable Operating System Interface), and / or a standard interface for high-level programming languages ​​such as STL (Standard Template Library).

[0060] Figure 4 is a schematic diagram of a storage device according to another embodiment of the present application.

[0061] according to Figure 4 The embodiment of Figure 3 Compared with the embodiment shown, the software running on the storage component also includes a virtual media layer. As an example, the media interface driver uses the virtual media layer to expose a unified addressing method that complies with the OCSSD protocol to one or more tasks through the system abstraction layer interface. It can be understood that the virtual media layer is a program running on the CPU.

[0062] As an example, the addressing method presented by the virtual media layer exposes the physical address of the NVM storage medium coupled to the control component as a group, PU (parallel unit), chunk, and logical block defined by the OCSSD protocol. Thus, for an IO request that complies with the OCSSD protocol, the task can directly access the media interface driver using the physical address obtained from the IO request without querying the FTL table.

[0063] Optionally, the virtual media layer displays an addressing method that exposes the physical address of the NVM storage medium coupled to the control component as a virtual NVM chip. The virtual NVM chip is partially addressed using channels, logical units (LUNs), physical blocks, and physical pages.

[0064] Figure 5 is a schematic diagram of a storage device according to yet another embodiment of the present application.

[0065] For the purpose of clarity, Figure 5 The host interface and the medium interface of the control component of the storage device according to the embodiment of the present application are shown, and the host interface driver, the medium interface driver and the task of processing the OCSSD protocol of the software running on the CPU of the control component are shown. Optionally, the software running on the CPU of the control component also includes an application program.

[0066] The host interface couples the storage device to the host through, for example, a PCIe link (not shown), and the media interface couples the control component to the NVM chip of the storage device. The NVM chip is coupled to the control component through multiple channels. The NVM chip is, for example, a NAND flash memory. Figure 5 Four channels are shown in Figure 1. Four logic cells are coupled to each channel.

[0067] The virtual media layer maps the group of physical addresses to the channel for coupling the NVM chip, maps the PU of the physical address to the logical unit (LUN) of the NVM chip, maps the chunk to the physical block of the NVM chip, and maps the logical block to the physical page of the NVM chip. Optionally, the virtual media layer maps the logical block to a portion of the physical page (called a data frame), and maps the write unit to the physical page. Thus, the virtual media layer obtains the storage unit of the NVM chip to be accessed according to the physical address that complies with the OCSSD protocol. In one example, the virtual media layer obtains the number of channels of the NVM chip coupled to the control component in the storage device, numbers each channel, and maps the group to the channel number to address a channel according to the group. Similarly, the virtual media layer obtains the number of logical units in the channel, numbers each logical unit, and maps the PU to the logical unit number to address a specified logical unit on the specified channel according to the group and the PU. Optionally, each channel coupled to the control unit has the same configuration (e.g., each channel includes the same number of logic units, and each logic unit is also the same). Still optionally, each channel coupled to the control unit has a different configuration (e.g., each channel includes a different number of logic units, and / or each logic unit is different). Still optionally, each channel is coupled to a different NVM chip, for example, a 3D NAND flash memory is coupled to an NVM chip of one channel, and a 3D XPoint chip or an MRAM chip is coupled to another channel.

[0068] In one embodiment, the virtual media layer directly provides a media interface with the received physical address to access the NVM chip. In one example, the virtual media layer obtains parts corresponding to groups, PUs (parallel units), chunks, and logical blocks from the received physical address, and maps the parts to channels, logical units, physical blocks, and physical pages, respectively. The mapping is, for example, a mapping through analytical conversion or a mapping through a lookup table.

[0069] In another embodiment, the mapping from groups, PUs (parallel units), chunks, and portions of logical blocks to channels, logical units, physical blocks, and physical pages is a one-to-many or many-to-one mapping. For example, multiple groups are mapped to the same channel, and one PU is mapped to multiple logical units. Optionally, multiple embodiments of mapping virtual LUNs to logical units are provided in Chinese Patent Application (201710915806.7), the entire text of which is incorporated by reference into this application, and PUs are mapped to logical units in the same manner as virtual LUNs are mapped to logical units by using PUs as substitutes for virtual LUNs. Thus, multiple PUs can be mapped to the same logical unit, or one PU can be mapped to multiple logical units.

[0070] In another example, in the virtual NVM storage medium presented by the virtual media layer, the group includes, for example, 8 PUs, and the PU includes, for example, 1024 small blocks (chunks). Two NVM chips are coupled to each channel coupled to the control component, each NVM chip includes a logical unit, and each logical unit includes 512 physical blocks. The virtual media layer, according to the mapping relationship shown in Table 1, maps the physical address (group, PU, ​​small block) according to the OCSSD protocol to the physical address (channel, logical unit, physical block) of the NVM chip, and directly uses the logical block address of the OCSSD protocol as the physical page address of the NVM chip.

[0071] Therefore, those skilled in the art will appreciate that, through the address mapping of the virtual media layer, the storage medium presented by the physical address following the OCSSD protocol is provided by NVM chips with the same or different configurations (e.g., different numbers of logical units in each chip, different numbers of physical blocks in each LUN, different numbers of physical pages in each physical block, sizes of physical pages, etc.). Optionally, the virtual media layer maps NVM chips of different configurations to the same storage medium presented by the physical address following the OCSSD protocol. Therefore, when the NVM chip of the storage device changes, the application / host using the storage device does not need to be modified, and the various tasks in the solid-state storage device that access the NVM chip through the virtual media layer do not need to be modified. For example, each LUN in one NVM chip (A) includes 512 physical blocks, while each LUN in another NVM chip (B) includes 384 physical blocks. The virtual media layer maps both NVM chips to storage media represented by physical addresses following the OCSSD protocol with 512 small blocks per PU, maps one PU to one logical unit of NVM chip A, and maps one PU to two logical units of NVM chip B, and some of the 512 physical blocks in the two logical units of NVM chip B are discarded or used for other purposes and not provided to users. And the mapping mode of the virtual media layer is changed through configuration.

[0072] Optionally, the virtual media layer maps a logical block of a physical address that complies with the OCSSD protocol to a data unit in a physical page of the NVM chip, where the physical page includes one or more data units, and the virtual media layer maps a write unit of a physical address that complies with the OCSSD protocol to a physical page of the NVM chip.

[0073]

[0074] Table 1

[0075] Continue to view Figure 5 , the host sends IO commands to the storage device according to the OCSSD protocol. The host interface receives the IO commands provided by the host. The task of processing the OCSSD protocol recognizes that a command appears on the host interface based on polling or interrupting the host interface status, and calls the host interface driver to access the host interface (①). The host interface driver provides the IO command obtained from the host interface to the task of processing the OCSSD protocol (②). Taking the read command as an example, the task of processing OCSSD analyzes the IO command, extracts the physical address that complies with the OCSSD protocol, and provides the physical address to the media interface driver (③). The media interface controls the reception of the physical address, and the virtual media layer performs necessary mapping on the physical address before accessing the media interface to access the NVM chip (④).

[0076] Figure 6 is a schematic diagram of a storage device according to yet another embodiment of the present application.

[0077] according to Figure 6 The storage device of the embodiment supports both IO commands that comply with the OCSSD protocol and IO commands that comply with the NVMe protocol. The host command acquisition task, the task of processing the OCSSD protocol, and the task of processing the NVMe protocol are run on the CPU of the storage component, and the latter two respectively process the IO commands that comply with the OCSSD protocol and the IO commands that comply with the NVMe protocol. Optionally, the same task processes both the acquisition of host commands, the processing of commands that comply with the OCSSD protocol, and the processing of IO commands that comply with the NVMe protocol.

[0078] according to Figure 6 In an embodiment, the host command acquisition task distinguishes the storage protocols (OCSSD protocol, NVMe protocol, and optionally other storage protocols) followed by the received IO commands, and optionally, according to the type of storage protocol identified, adds a flag indicating the storage protocol used to the IO command, and / or distributes the IO command to the task processing the OCSSD protocol or the task processing the NVMe protocol.

[0079] The host sends an IO command to the storage device according to the storage protocol. The host interface receives the IO command provided by the host. The host command acquisition task recognizes that a command appears on the host interface based on polling or interruption of the host interface status, and calls the host interface driver to access the host interface (5). The host interface driver provides the IO command obtained from the host interface to the host command acquisition task (6).

[0080] Taking the read command as an example, the host command acquisition task analyzes the IO command and identifies the storage protocol it follows. If the IO command follows the OCSSD protocol, the host command acquisition task transfers the IO command to the task that processes the OCSSD protocol (7). The task that processes the OCSSD protocol extracts the physical address that follows the OCSSD protocol from the received IO command and provides the physical address to the media interface driver (8). The media interface control receives the physical address, and the virtual media layer performs necessary mapping on the physical address before accessing the media interface to access the NVM chip (9).

[0081] If the IO command complies with the NVMe protocol, the host command acquisition task recognizes that a command appears in the host interface, calls the host interface driver to access the host interface (10), and the host interface driver provides the IO command obtained from the host interface to the host command acquisition task (11). The host command acquisition task analyzes the IO command, identifies that it complies with the NVMe storage protocol, and transfers the IO command to the task that processes the NVMe protocol (12). The task that processes the NVMe protocol extracts the logical address that complies with the NVMe protocol in the received IO command, and provides the logical address to the FTL task (13). The FTL task outputs the physical address corresponding to the logical address based on the received logical address and returns it to the task that processes the NVMe protocol (13). Optionally, the physical address provided by the FTL task has the same format and meaning as the physical address that complies with the OCSSD protocol. In other words, the physical address provided by the FTL task is the physical address that complies with the OCSSD protocol exposed by the virtual media layer. The task that processes the NVMe protocol accesses the media interface driver based on the received physical address (14). The media interface control receives the physical address, and the virtual media layer performs necessary mapping on the physical address, and then accesses the media interface to access the NVM chip (15).

[0082] In an optional embodiment, the storage device is dynamically or statically configured to know the storage protocol followed by the IO command. Thereby, the host command acquisition task is omitted, and the state of the IO command to be processed on the host interface is bound to the OCSSD protocol processing task or the NVMe protocol processing task. In response to the IO command to be processed by the host interface, the OCSSD protocol processing task or the NVMe protocol processing task accesses the host interface driver to obtain the IO command and processes it. Although the storage protocol followed by the IO command is not identified, depending on the binding relationship, the IO command obtained by the OCSSD protocol processing task always follows the IO command of the OCSSD protocol, and the IO command obtained by the NVMe protocol processing module always follows the IO command of the NVMe protocol. The binding relationship between the host interface and the OCSSD protocol processing task or the NVMe protocol processing task can be changed when the solid-state storage device is working.

[0083] In another optional implementation, the same task (referred to as a combined task) processes both host command acquisition, processing commands that comply with the OCSSD protocol, and processing IO commands that comply with the NVMe protocol. Multiple combined tasks are run in the control component of the storage device, and each combined task processes IO commands separately, thereby processing multiple IO commands simultaneously, improving the throughput of storage device IO command processing and reducing IO command processing delays caused by task switching.

[0084] In still another optional implementation, the host interface identifies the storage protocol followed by the received IO command, and based on the identification result, indicates that the OCSSD protocol processing task or the NVMe protocol processing task has pending IO commands. For example, the host interface maintains command queues for IO commands that follow the OCSSD protocol and IO commands that follow the NVMe protocol, respectively, and fills the IO commands into their respective command queues according to the protocol followed by the IO commands. The command queue for the OCSSD protocol is bound to the task of processing the OCSSD protocol, and the command queue for the NVMe protocol is bound to the task of processing the NVMe protocol. In response to the appearance of pending IO commands in the command queue, the task of processing the OCSSD and the task of processing the NVMe protocol recognize that there are commands appearing in the command queues bound to them based on polling or interruption of the command queue status.

[0085] The IO commands that follow the NVMe protocol use the logical address to access the storage device, and the physical address corresponding to the logical address needs to be obtained through the FTL task. The IO commands that follow the OCSSD protocol use the physical address that follows the OCSSD protocol to access the storage device, so there is no need to go through the FTL task for address conversion. According to an embodiment of the present application, the virtual media layer accepts the physical address that follows the OCSSD protocol for accessing the NVM chip, so that the task of processing the NVMe protocol and the task of processing the OCSSD protocol use the same format of the physical address that follows the OCSSD protocol to access the media interface driver. In this way, in a single storage device, both the OCSSD storage protocol and the NVMe storage protocol are supported. Optionally, or further, the storage device also runs tasks that process the SCSI protocol, and / or tasks that process other storage protocols. These tasks that process different storage protocols, if necessary, convert the address carried in the received IO command into a physical address that follows the OCSSD protocol, and access the media interface driver. Therefore, the storage device according to the embodiment of the present application can easily support multiple storage protocols, and when supporting a single storage protocol, it does not lose performance or efficiency due to being able to support other storage protocols. Tasks handling different storage protocols share the same media interface driver.

[0086] Figure 7 is a schematic diagram of a storage device according to another embodiment of the present application.

[0087] according to Figure 7 The storage device of the embodiment according to Figure 6Compared with the storage device of the embodiment of the present invention, a reliable virtual media management task is also run on the CPU of the storage component. The reliable virtual media management task organizes multiple PUs and / or small blocks (chunks) that comply with the OCSSD protocol into large blocks to provide enhanced data protection for the storage device. Optionally, the functions of the reliable virtual media management task are merged into other tasks such as FTL tasks, so that when large block related functions are used, there is no need for task switching. Still optionally, the functions of the reliable virtual media management task are merged into the virtual media layer, and small blocks (chunks) that comply with the OCSSD protocol are mapped to multiple physical blocks of the NVM chip, and multiple physical blocks mapped to the same small block (chunk) are organized into large blocks, so that small blocks that comply with OCSSD are mapped to large blocks with enhanced data reliability.

[0088] Continue to view Figure 7 , the virtual media layer maps PU0 following the physical address of the OCSSD to the logical unit 710, maps PU1 to the logical unit 712, maps PU2 to the logical unit 714, and maps PU3 to the logical unit 716. The reliable virtual media management task constructs a PU group (denoted as PUG0) with PU0, PU1, PU2, and PU3, and constructs a large block in the PU group (PUG0). For example, according to Figure 2 The method of showing the structure of the large block, or according to the Chinese patent application with application number 201710752321.0 Figure 3 A and its instructions Figure 3 The large block is constructed in the manner described in relation to A, or the large block is constructed in the manner provided by the prior art.

[0089] Taking a write IO command (also called a write command) as an example, the large block provided by the reliable virtual media management task is used to carry the data of the write command. The FTL task allocates available physical addresses from the large block (and the page stripe on the large block (or referred to as a logical block stripe according to the OCSSD protocol, the logical block stripe includes multiple logical blocks, on which user data and verification data configured according to RAID are stored)) provided by the reliable virtual media management task, and the form of the available physical addresses follows the OCSSD protocol. For example, the reliable virtual media management task provides the PU group (PUG0) and the available page stripes therein to the FTL task. When the FTL task allocates a physical address for a write command, it obtains the physical address from the available page stripe of the PU group (PUG0), and records the allocated physical address in the FTL table in association with the logical address. In response to the available page stripe of the PU group (PUG0) being exhausted, the reliable virtual media management task also provides another available PU group.

[0090] For a read command, when an error occurs in the data obtained from the NVM chip according to the read command and the error check unit cannot correct it, the reliable virtual medium management task is requested to provide the addresses of each logical block in the page stripe where the data read by the read command is located, and the data to be read by the read command is restored from the data stored in each logical block of the page stripe.

[0091] The reliable virtual media management task also records metadata related to the large block and / or page stripe in each small block or logical block of the large block. Figure 3 B and its instructions Figure 3 The meaning and usage of metadata are provided in the relevant description of B.

[0092] According to an embodiment of the present application, a solid-state storage device is also provided, which includes a controller and a non-volatile memory chip, wherein the controller executes any one of the processing methods provided in the embodiments of the present application.

[0093] According to an embodiment of the present application, there is also provided a program stored on a readable medium, which, when executed by a controller of a solid-state storage device, enables the solid-state storage device to execute any one of the processing methods provided according to the embodiments of the present application.

[0094] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application. Obviously, those skilled in the art may make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A storage device, comprising a control component and an NVM storage medium coupled to the control component, wherein the control component comprises a CPU, a host interface and a medium interface, an operating system and one or more tasks are run on the CPU, the tasks use services provided by the operating system through a system abstraction layer interface provided by the operating system, the operating system comprises one or more drivers, and the operating system schedules one or more tasks; the one or more tasks run by the CPU process IO commands to access the storage device; wherein, The media interface driver uses a virtual media layer, which maps NVM chips of different configurations to the same storage medium represented by physical addresses that follow the OCSSD protocol, and exposes a unified addressing method to one or more tasks through the system abstraction layer interface; The addressing mode displayed by the virtual medium layer exposes the physical address of the NVM storage medium coupled to the control component as a virtual NVM chip; When the storage device supports both IO commands that follow the OCSSD protocol and IO commands that follow the NVMe protocol, The task identifies the storage protocol followed by the IO command received from the host interface, and forwards the IO command to the corresponding task according to the storage protocol followed by the IO command; The host interface identifies the storage protocol followed by the received IO command, and notifies the corresponding task to process the IO command according to the storage protocol followed by the IO command. According to the type of storage protocol identified, a flag indicating the storage protocol used is added to the IO command, and / or the IO command is distributed to the task processing the OCSSD protocol or the task processing the NVMe protocol.

2. The storage device according to claim 1, wherein the task calls a driver through a system abstraction layer interface to obtain an IO command from a host interface.

3. The storage device according to claim 2, wherein: The task calls the driver of the host interface and obtains IO commands from the host interface.

4. The storage device according to claim 2, wherein: The task calls the queue driver to obtain IO commands from the queue of the host interface.

5. The storage device according to any one of claims 1 to 4, wherein: One or more tasks run at the same privilege level as the operating system.

6. The storage device according to claim 4, wherein: One or more tasks run at a different privilege level than the operating system.

7. The storage device according to claim 6, wherein: In response to a task calling a system abstraction layer interface, a privilege level switch occurs.

8. The storage device according to claim 1, wherein the task calls a media interface driver to access the NVM storage medium, wherein the media interface driver includes a virtual media layer program, and the virtual media layer program maps addresses that comply with the OCSSD protocol to physical addresses of the NVM chip.

9. The storage device of claim 8, wherein the one or more tasks provide an address complying with the OCSSD protocol to the media interface driver to access the NVM chip.

10. The storage device according to claim 9, wherein the IO command received by the task from the host interface indicates an address following the OCSSD protocol, and the task provides the address following the OCSSD protocol to the media interface driver.

11. The storage device according to claim 10, wherein the IO command received by the task from the host interface indicates a logical address, and the task obtains an address compliant with the OCSSD protocol corresponding to the logical address and provides it to the media interface driver.

12. The storage device according to any one of claims 1-4, wherein one or more tasks are applications, and the applications provide addresses complying with the OCSSD protocol to a media interface driver to access storage space of the storage device.

13. The storage device according to claim 8, wherein the virtual media layer maps groups of addresses complying with the OCSSD protocol into channels coupled to a control component, maps parallel units (PUs) of addresses complying with the OCSSD protocol into logical units coupled to a control component, and maps small blocks of addresses complying with the OCSSD protocol into physical blocks coupled to logical units.

14. The storage device according to claim 13, wherein the virtual medium layer further maps the logical block of the address following the OCSSD protocol to the physical page in the physical block, or maps the write unit of the address following the OCSSD protocol to the physical page in the physical block.

15. The storage device according to claim 13, wherein the virtual media layer maps a parallel unit (PU) of an address complying with the OCSSD protocol to a plurality of logical units coupled to a control component, or maps a plurality of parallel units (PU) of an address complying with the OCSSD protocol to a logical unit coupled to a control component.

16. The storage device according to claim 11, wherein the task identifies the storage protocol followed by the IO command received from the host interface, and if the IO command follows the OCSSD protocol, the task obtains the address following the OCSSD from the IO command, and provides the address following the OCSSD protocol to the media interface driver; if the IO command follows the NVMe protocol, the task obtains the logical address following the NVMe protocol from the IO command, obtains the address following the OCSSD protocol corresponding to the logical address, and provides the address following the OCSSD protocol to the media interface driver.

17. The storage device of claim 16, wherein the virtual media layer maps small blocks of addresses complying with the OCSSD protocol to a plurality of physical blocks of the NVM storage medium.

18. The storage device of claim 17, wherein a plurality of physical blocks mapped to the same chunk are organized into a chunk.

19. The storage device according to claim 1, wherein one of the tasks is a reliable virtual medium management task that organizes a plurality of PUs and / or small chunks that comply with an OCSSD protocol into a large chunk.

20. The storage device according to claim 19, wherein the PU and the logic block are obtained from a large block provided by the reliable virtual medium management task, and are used to carry the data to be written by the write IO command.

21. A storage device according to claim 19 or 20, wherein in response to the presence of an uncorrectable error in the data read from the first logical block, a first large block to which the first logical block belongs is obtained from a reliable virtual media management task, and data is read from other logical blocks of the first large block to recover the data stored in the first logical block.

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