Control signal generator for sense amplifier and memory device including the same

Abstract

A control signal generator for a sense amplifier is provided, the control signal generator comprising a replica circuit including replica transistors corresponding to transistors included in the sense amplifier and configured to receive at least one input signal of the sense amplifier and a first control signal for enabling a sense operation of the sense amplifier; and an amplification circuit configured to output a second control signal for enabling an amplification operation of the sense amplifier after the sense operation is enabled by amplifying an output signal from the replica circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0031714 filed on March 19, 2018, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2018-0111021 filed on September 17, 2018, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The inventive concept relates to control of a sense amplifier, and more particularly, to a control signal generator for the sense amplifier and a memory device including the same. Background Art

[0004] The memory device may include a memory cell having different states depending on the stored data, and may output the data stored in the memory cell by detecting the state of the memory cell in response to a read command. In order to detect the state of the memory cell, the memory device may include a sense amplifier to sense and amplify a signal, such as a voltage and / or a current, provided via a bit line connected to the memory cell. The operation of the sense amplifier may be controlled by a control signal, and when the control signal is accurately generated, an erroneous operation of the sense amplifier is reduced or prevented, so that the reliability of the read operation can be maintained. Summary of the invention

[0005] The inventive concept relates to control of a sense amplifier and provides a control signal generator capable of accurately controlling the sense amplifier by using a replica circuit of the sense amplifier, and a memory device including the control signal generator.

[0006] According to one aspect of the inventive concept, a control signal generator for a sense amplifier is provided, the control signal generator comprising a replica circuit, the replica circuit comprising replica transistors corresponding to transistors included in the sense amplifier and configured to receive at least one input signal of the sense amplifier and a first control signal for enabling a sense operation of the sense amplifier; and an amplification circuit, configured to output a second control signal for enabling an amplification operation of the sense amplifier after enabling the sense operation by amplifying an output signal from the replica circuit.

[0007] According to another aspect of the inventive concept, a control signal generator for a sense amplifier is provided, the control signal generator including a replica circuit including replica transistors corresponding to transistors included in the sense amplifier and configured to generate an output signal for simulating an output from the sense amplifier in response to a first control signal for enabling a sense operation of the sense amplifier; and an amplification circuit configured to output a second control signal for enabling an amplification operation of the sense amplifier after enabling the sense operation by amplifying the output signal from the replica circuit.

[0008] According to another aspect of the inventive concept, a memory device is provided, comprising: a memory cell; a sense amplifier configured to sense and amplify a data input signal that varies according to data stored in the memory cell; a controller configured to generate a first control signal for enabling a sense operation of the sense amplifier; and a control signal generator configured to generate a second control signal for enabling an amplification operation of the sense amplifier according to the first control signal, wherein the control signal generator comprises a replica circuit corresponding to the sense amplifier, and an amplification circuit configured to generate a second control signal by amplifying an output signal from the replica circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram illustrating a memory device according to an example embodiment;

[0011] Figure 2 is a timing diagram illustrating signals in a read operation of a memory device according to example embodiments;

[0012] Figure 3 is a block diagram of a signal generator for generating an amplification enable signal according to a readout enable signal according to a comparative example;

[0013] Figure 4 is a diagram showing a method according to an example embodiment Figure 1 A block diagram of an example of a control signal generator;

[0014] Figure 5 is a diagram showing a method according to an example embodiment Figure 1 A circuit diagram of an example of a sense amplifier;

[0015] Fig. 6A and 6B is a diagram showing a method according to an example embodiment Figure 4 A circuit diagram of an example of a control signal generator;

[0016] Figure 7is a diagram showing a method according to an example embodiment Fig. 6A and 6B A timing diagram of the operation of the control signal generator;

[0017] Figure 8 is a diagram showing a method according to an example embodiment Figure 1 A circuit diagram of an example of a sense amplifier;

[0018] Fig. 9 is a diagram showing a method according to an example embodiment Figure 4 A circuit diagram of an example of a control signal generator;

[0019] Fig.10 is a diagram showing a method according to an example embodiment Figure 8 The sense amplifier and Fig. 9 A timing diagram of the operation of the control signal generator;

[0020] Fig.11 is a diagram showing a method according to an example embodiment Figure 1 A diagram of an example of a memory cell;

[0021] Fig.12 is a diagram showing a method including Fig.11 A block diagram of a memory device having a memory unit;

[0022] Fig.13 is a flowchart illustrating a reading method of a memory device according to an example embodiment;

[0023] Fig.14 is a block diagram illustrating a memory system including a memory device according to example embodiments; and

[0024] Fig.15 is a block diagram illustrating a System on Chip (SoC) including a memory device according to example embodiments. DETAILED DESCRIPTION

[0025] Figure 1 is a block diagram illustrating a memory device 100 according to an example embodiment. For example, Figure 1 Components included in the memory device 100 are shown, including the cell array 110 , the row decoder 120 , the controller 130 , the control signal generator 140 , and / or the read circuit 150 in a read operation.

[0026] The memory device 100 may receive commands and addresses from an external source, and may receive or output data. For example, the memory device 100 may receive commands such as write commands, read commands, etc., and addresses corresponding to the commands. The memory device 100 may receive data in response to a write command, and may output data in response to a read command. In some example embodiments, commands, addresses, and data may be received or sent via independent channels, and in some example embodiments, at least two of the commands, addresses, and data may be received or sent via the same channel.

[0027] The cell array 110 may include a memory cell M, and the memory cell M may be connected to a word line WLi and a bit line BLj. The memory cell M is an element capable of storing data and may have a state corresponding to the stored data. In some example embodiments, the memory cell M may include a memory cell M as described below. Fig.11 The variable resistance element described herein may have a resistance corresponding to data stored in the memory cell M. In some example embodiments, the memory cell M, such as a dynamic random access memory (DRAM), may include a capacitor, and the capacitor may have a charge corresponding to the data stored in the memory cell M. In some example embodiments, the memory cell M, such as a flash memory, may include a floating gate transistor, and the floating gate transistor may have a threshold voltage corresponding to the data stored in the memory cell M.

[0028] The memory cell M may be selected by a word line WLi, and a signal corresponding to the state of the memory cell M may be provided via a bit line BLj. For example, memory cells included in the same row in the cell array 110 may share one word line, and memory cells included in the same column may share one bit line. In some example embodiments, when the memory cell M includes a variable resistance element, the memory cell M selected by the activated word line WLi may provide a read voltage in response to a read current. In some example embodiments, when the memory cell M includes a capacitor, the memory cell M selected by the activated word line WLi may provide a read voltage by providing a charge to the bit line BLj or withdrawing a charge from the bit line BLj. In some example embodiments, when the memory cell M includes a floating gate transistor, the memory cell M selected by the activated word line WLi may provide a read voltage by transferring a voltage received from a source line to the bit line BLj or blocking the voltage. Throughout the specification, as Figure 1 As shown, the signal provided from the memory cell M via the bit line BLj in the read operation may also be referred to as a data input signal DIN.

[0029] The row decoder 120 may activate one of the plurality of word lines WL according to an address received together with a read command or a write command, and may select a memory cell connected to the activated word line. For example, the row decoder 120 may activate one of the plurality of word lines WL (e.g., word line WLi) according to an address (or a row address), and may activate the plurality of word lines WL in a mutually exclusive manner, for example. Thus, a memory cell included in a row from among the memory cells included in the cell array 110 may be selected.

[0030] The read circuit 150 may be connected to the cell array 110 via a bit line, and may determine data stored in a memory cell of the cell array 110 in response to a signal received via the bit line. Figure 1 As shown, the read circuit 150 may include a sense amplifier 151, and the sense amplifier 151 may receive a data input signal DIN via a bit line BLj. Also, the sense amplifier 151 may receive a reference signal REF, and may determine data corresponding to the data input signal DIN based on the reference signal REF, thereby generating a data output signal DOUT. Figure 1 As shown, throughout the specification, the data input signal DIN and the reference signal REF provided to the sense amplifier 151 may be collectively referred to as the input signal SAIN of the sense amplifier 151. In some example embodiments, when the memory cell M stores at least two bits of data, the sense amplifier 151 may process the data input signal DIN at least twice by using the reference signal REF having at least two different levels. In some example embodiments, the read circuit 150 may include a register storing data, such as a latch, a flip-flop, etc., and the register may receive the data output signal DOUT and may temporarily store the data. Although Figure 1 Only the read circuit 150 is shown, but the memory device 100 may also include a write circuit to provide a write signal for writing data to the memory cell M, and in some example embodiments, the memory device 100 may include a write / read circuit in which the write circuit and the read circuit 150 are implemented as one block.

[0031] The sense amplifier 151 can sequentially perform multiple operations to process the reference signal REF and the data input signal DIN. Figure 2As described above, the sense amplifier 151 may standby until the data input signal DIN is developed at the bit line BLj, and after the data input signal DIN is developed at the bit line BLj, the sense amplifier 151 may start the operation of sensing the data input signal DIN (e.g., a sensing operation). Depending on the size of the memory cell M, the power consumption of the memory cell M, etc., the difference between the states of the memory cell M depending on the stored data and the difference between the levels of the data input signal DIN corresponding to the states may not be large. Therefore, the sense amplifier 151 may perform the operation of sensing the data input signal DIN in advance, and in some example embodiments, the sensing operation may also be referred to as a pre-sensing operation or a pre-charging operation. Thereafter, the sense amplifier 151 may perform the operation of generating the data output signal DOUT by amplifying the sensing result of the sensing operation (e.g., an amplifying operation). As described above, the data output signal DOUT may be provided to the register, and according to the amplifying operation of the sense amplifier 151, the data output signal DOUT may have a level to be recognized by the register. In some example embodiments, the amplifying operation may also be referred to as a post-sensing operation or a latching operation.

[0032] The sense amplifier 151 of the memory device 100 may be requested to separately perform each of the plurality of operations at an appropriate time point. For example, when some operation periods of the sense amplifier 151 are reduced, an error may occur in the read operation, and on the other hand, when some operation periods of the sense amplifier 151 are increased, power consumption may increase and / or the read speed of the memory device 100 may decrease. In response to at least one control signal, the sense amplifier 151 may start or end each of the plurality of operations, and thus, a control signal to be provided to the sense amplifier 151 may be generated to allow the sense amplifier 151 to appropriately perform the plurality of operations. For example, as Figure 1 As shown, the sense amplifier 151 may receive a sense enable signal SEN for controlling a sense operation and an amplification enable signal AEN for controlling an amplification operation. Throughout the specification, the sense enable signal SEN may also be referred to as a first control signal, and the amplification enable signal AEN may also be referred to as a second control signal.

[0033] The controller 130 may control components included in the memory device 100 according to a command received by the memory device 100. The controller 130 may generate a sense enable signal SEN, and in response to a read command, may provide the activated sense enable signal SEN to the sense amplifier 151. The sense amplifier 151 may perform a read operation in response to the activated sense enable signal SEN.

[0034] The control signal generator 140 may receive the read enable signal SEN from the controller 130 and may generate the amplification enable signal AEN. In some example embodiments, the control signal generator 140 may provide the activated amplification enable signal AEN to the sense amplifier 151 in response to the activated read enable signal SEN so as to allow the sense amplifier 151 to perform an amplification operation during an appropriate period after performing a read operation. Figure 2 As described, a period in which the sense amplifier 151 performs a read operation may be equal to or less than several ns (eg, approximately 2 ns), and it may not be easy to generate the amplification enable signal AEN from the sense enable signal SEN via a delay counted using a clock signal or the like.

[0035] Hereinafter, as will be described below with reference to the accompanying drawings, the control signal generator 140 may activate the amplification enable signal AEN at appropriate timing by emulating the sense amplifier 151. For example, the control signal generator 140 may include a replica circuit (e.g., Figure 4 The memory device 100 may include a replica circuit 141 of the memory device 100, and may generate an amplification enable signal AEN based on an output signal from the replica circuit. Therefore, the amplification enable signal AEN may be activated based on the state of the sense amplifier 151 according to the activated read enable signal SEN. Also, the amplification enable signal AEN may be activated at an accurate timing because the sense amplifier 151 and the replica circuit may experience the same changes regarding process, voltage, temperature, etc., so that errors in a read operation may be reduced or prevented. Also, a margin included in the read time may be deleted to compensate for changes in process, voltage, temperature, etc., so that the read time may be reduced. Also, a component for compensating for changes in process, voltage, temperature, etc. may be excluded from the memory device 100, and an operation of correcting the timing of the amplification enable signal AEN may be skipped during the manufacturing process of the memory device 100.

[0036] Figure 2 is a timing diagram showing signals in a read operation of the memory device 100 according to an example embodiment. For example, Figure 2 Shows the time provided to Figure 1 1 , a data input signal DIN, a reference signal REF, a sense enable signal SEN, and an amplification enable signal AEN of a sense amplifier 151 of a memory device 100, and a data output signal DOUT generated by the sense amplifier 151 are shown. Throughout the specification, the sense enable signal SEN and the amplification enable signal AEN may be activated high signals. Hereinafter, reference will now be made to Figure 1 describe Figure 2 .

[0037] refer to Figure 2 , the development of the data input signal DIN may start at time t21. For example, at time t21, the bit line BLj may be electrically connected to the read circuit 150 according to the read command. Between time t21 and time t22, the level of the data input signal DIN may gradually shift to a level corresponding to the state of the memory cell M, and the period during which the level of the data input signal DIN is shifted (e.g., between time t21 and time t22) may also be referred to as a development period. Figure 2 As shown, during the development period, the level of the data input signal DIN may rise relatively steeply or may rise relatively gently according to the data stored in the memory cell M. Figure 2 An example is shown in which the data input signal DIN gradually rises during the development period, but in some example embodiments, the data input signal DIN may gradually fall. Between time t21 and time t22, for example, during the development period, the read enable signal SEN and the amplification enable signal AEN may remain in an inactivated state.

[0038] The read enable signal SEN may be activated at time t22. Figure 2 As shown in FIG. 1 , when the development period ends, the data input signal DIN may have a level higher or lower than that of the reference signal REF. The controller 130 may activate the read enable signal SEN after a period corresponding to the development period has passed since time t21. In response to the activated read enable signal SEN, the sense amplifier 151 may perform a read operation, and as shown in FIG. Figure 2 As shown, the level of the data output signal DOUT may change. In some example embodiments, when the level of the data input signal DIN is higher than the level of the reference signal REF at time t22, the level of the data output signal DOUT may rise relatively sharply, whereas when the level of the data input signal DIN is lower than the level of the reference signal REF at time t22, the level of the data output signal DOUT may rise relatively gently. On the other hand, in some example embodiments, when the level of the data input signal DIN is lower than the level of the reference signal REF at time t22, the level of the data output signal DOUT may rise relatively sharply, whereas when the level of the data input signal DIN is higher than the level of the reference signal REF at time t22, the level of the data output signal DOUT may rise relatively gently.

[0039] The amplification enable signal AEN may be activated at time t23. Figure 2As shown, the data output signal DOUT may have different levels at time t23 according to the level of the data input signal DIN. The control signal generator 140 may generate the amplification enable signal AEN at time t23, and the sense amplifier 151 may perform an amplification operation in response to the activated amplification enable signal AEN. Figure 2 As shown, between time t23 and time t24, the level of the data output signal DOUT may gradually move toward a high level, or may gradually move toward a low level. Figure 1 As described above, the control signal generator 140 may generate the amplification enable signal AEN by emulating the sense amplifier 151 , thereby providing an optimized period D in which an error in a read operation is reduced or prevented and power consumption and a read time are reduced.

[0040] The read enable signal SEN and the amplification enable signal AEN may be deactivated at time t24. Figure 2 As shown, before time t24, the data output signal DOUT may have a high level or a low level according to the amplification operation of the sense amplifier 151, and data according to the level of the data output signal DOUT may be stored in the register. Thereafter, at timing t24, according to the deactivated sense enable signal SEN and the deactivated amplification enable signal AEN, the data output signal DOUT may have a level equal to that before time t22.

[0041] Figure 3 is a block diagram of a signal generator 20 for generating an amplification enable signal AEN according to a readout enable signal SEN according to a comparative example. For example, Figure 3 An example is shown in which the amplification enable signal AEN is generated according to the read enable signal SEN by using the delay unit 22. Figure 3 As shown, the signal generator 20 may include an inverter 21 , a delay unit 22 and / or a NAND gate 23 .

[0042] As above reference Figure 2 As described above, the delay unit 22 may be used to generate the activated amplification enable signal AEN after the sensing enable signal SEN is activated and then the period D passes. The delay unit 22 may generate the second signal SIG2 by delaying the first signal SIG1 output from the inverter 21. Therefore, the amplification enable signal AEN may be generated via the NAND gate 23 according to the first signal SIG1 inverted from the activated sensing enable signal SEN and the second signal SIG2 obtained by delaying the first signal SIG1.

[0043] The delay unit 22 may include passive elements such as resistors, capacitors, diodes, etc. and / or active elements such as transistors. The delay provided by the delay unit 22 according to the characteristics of the passive elements and / or active elements included in the delay unit 22 may vary according to the process, voltage, temperature, etc., so that when the amplification enable signal AEN is Figure 3 The signal generator 20 generates, Figure 2 The period D of the delay unit 22 may be changed. For example, when the delay provided by the delay unit 22 decreases due to process, voltage, temperature, etc., the period D may be reduced, and at time t23, the data output signal DOUT may not rise to the level required for the amplification operation of the sense amplifier 151. Therefore, the level of the data output signal DOUT may be moved to a low level after time t23 regardless of the data input signal DIN. On the other hand, when the delay provided by the delay unit 22 increases due to process, voltage, temperature, etc., the period D may increase, and power consumption and read time may increase due to the read operation.

[0044] Figure 4 is a diagram showing a method according to an example embodiment Figure 1 A block diagram of an example of the control signal generator 140 is shown above. Figure 1 As stated, Figure 4 The control signal generator 140' may receive the read enable signal SEN and may generate the amplification enable signal AEN. Figure 1 describe Figure 4 .

[0045] refer to Figure 4 , the control signal generator 140′ may include a replica circuit 141 of the sense amplifier 151, and an amplification circuit 142. The replica circuit 141 may have a structure equal to at least some parts of the sense amplifier 151. In some example embodiments, the replica circuit 141 may include replica transistors that are equal to (or identical to) at least some transistors included in the sense amplifier 151. Figure 4 As shown, the replica circuit 141 can receive the reference signal REF and the sense enable signal SEN of the sense amplifier 151, and can receive a signal equal to the deactivated amplification enable signal AEN, such as the positive power supply voltage VDD as a high level signal. The replica circuit 141 can provide the output signal OUT to the amplification circuit 142.

[0046] The amplification circuit 142 may generate the amplification enable signal AEN by amplifying the output signal OUT of the replica circuit 141. In some example embodiments, the amplification circuit 142 may be configured to amplify the output signal OUT of the replica circuit 141 when the output signal OUT of the replica circuit 141 corresponds to the data output signal DOUT of the sense amplifier 151, which provides a maximum gain in the amplification operation of the sense amplifier 151. Therefore, the amplification enable signal AEN may be activated at a time point when the maximum gain is available in the amplification operation of the sense amplifier 151, and as a result, the control signal generator 140′ may provide Figure 2 The optimized period D. Fig. 6A , 6B 9 describe an example of the control signal generator 140'.

[0047] Figure 5 is a diagram showing a method according to an example embodiment Figure 1 The circuit diagram of an example of the sense amplifier 151 is shown above. Figure 1 As stated, Figure 5 The sense amplifier 151' can receive the data input signal DIN and the reference signal REF as the input signal SAIN, and can receive the sense enable signal SEN and the amplification enable signal AEN as the control signal. And, the sense amplifier 151' can generate the data output signal DOUT including the positive signal DOUTp and the negative signal DOUTn as the differential signal. Figure 5 As shown, the sense amplifier 151' may include a plurality of transistors T1 to T10 (also referred to as first transistor T1 to tenth transistor T10), and hereinafter, reference will now be made to Figure 1 and 2 describe Figure 5 .

[0048] The first transistor T1 and the second transistor T2 are PMOS transistors and may each have a gate receiving a data input signal DIN and a reference signal REF. Also, the first transistor T1 and the second transistor T2 may each have a source to which a positive power supply voltage VDD is applied, and may have respective drains connected to a first node N1 and a second node N2 to which a data output signal DOUT is output, respectively. Throughout the specification, the first transistor T1 and the second transistor T2 may also be referred to as input transistors and may be collectively referred to as an input stage.

[0049] The third transistor T3 is an NMOS transistor and can electrically connect the first node N1 to the second node N2 in response to a deactivated read enable signal SEN (e.g., a read enable signal SEN having a high level). Therefore, before performing a read operation (e.g., before the read enable signal SEN is activated), the first node N1 and the second node N2 can have the same potential. Throughout the specification,

[0050] The third transistor T3 may also be referred to as an equalization transistor. In some example embodiments, the equalization transistor may be excluded.

[0051] The fourth transistor T4 and the fifth transistor T5 are NMOS transistors and may apply the negative power supply voltage VSS as a constant potential to the first node N1 and the second node N2 in response to a deactivated readout enable signal SEN (e.g., a readout enable signal SEN having a high level). Therefore, before performing a readout operation, the first node N1 and the second node N2 may have the negative power supply voltage VSS. Throughout the specification, the fourth transistor T4 and the fifth transistor T5 may also be referred to as reset transistors.

[0052] like Figure 5 As shown, the seventh transistor T7 to the tenth transistor T10 can form such a structure, wherein the two inverters are connected to each other input and output, and the two inverters provide positive feedback to each other, thereby amplifying the voltage of the first node N1 and the second node N2. Throughout the specification, the seventh transistor T7 to the tenth transistor T10 may also be referred to as an amplifying transistor. In some example embodiments, the two inverters may have the same current drive capacity. For example, the seventh transistor T7 and the ninth transistor T9 constituting the first inverter may each have the same size (e.g., channel width) as the eighth transistor T8 and the tenth transistor T10 constituting the second inverter.

[0053] The sixth transistor T6 may block the positive power supply voltage VDD to the amplifying transistor in response to a deactivated amplifying enable signal AEN (e.g., an amplifying enable signal AEN having a high level), and may provide the positive power supply voltage VDD to the amplifying transistor in response to an activated amplifying enable signal AEN (e.g., an amplifying enable signal AEN having a low level). Throughout the specification, the sixth transistor T6 may also be referred to as an amplifying enable transistor.

[0054] Fig. 6A and 6B is a diagram showing a method according to an example embodiment Figure 4 The circuit diagram of an example of the control signal generator 140' is shown in FIG. Fig. 6A and 6BThe circuit diagram shows control signal generators 140a and 140b, which respectively include corresponding Figure 5 The replica circuits 141a and 141b of the sense amplifier 151' are shown in FIG. Figure 5 describe Fig. 6A and 6B , and in Figure 5 , 6A and 6B, the redundant description is provided only once.

[0055] refer to Fig. 6A , the control signal generator 140a may include a replica circuit 141a and an amplifying circuit 142a. The replica circuit 141a may include a plurality of replica transistors T1' to T10' corresponding to the plurality of transistors T1 to T10 of the sense amplifier 151'. The plurality of replica transistors T1' to T10' (also referred to as the first transistor T1' to the tenth transistor T10') of the replica circuit 141a may have the same size as the corresponding plurality of transistors T1 to T10 of the sense amplifier 151'.

[0056] like Fig. 6A As shown, Figure 5 Compared with the sense amplifier 151' of the replica circuit 141a, the first transistor T1' and the second transistor T2' as the input transistors of the replica circuit 141a can receive the reference signal REF in common. And the sixth transistor T6' as the amplification enable transistor of the replica circuit 141a can have a gate to which the positive power supply voltage VDD corresponding to the deactivated amplification enable signal AEN is applied. Therefore, as will be described below with reference to Figure 7 As described above, when the sense amplifier 151 ′ performs an amplification operation, the first node N1 ′ and the second node N2 ′ of the replica circuit 141 a may have the same voltage as the second node N2 of the sense amplifier 151 ′.

[0057] The amplification circuit 142a may function as an inverter that outputs the amplification enable signal AEN by inverting the output signal OUT of the replica circuit 141a. In some example embodiments, the transistors T11 and T12 (also referred to as the eleventh transistor T11 and the twelfth transistor T12) included in the amplification circuit 142a may have the same size as the amplification transistor of the replica circuit 141a (or the amplification transistor of the sense amplifier 151'). For example, the eleventh transistor T11 of the amplification circuit 142a, which is a PMOS transistor, may have the same size as the seventh transistor T7' (or the eighth transistor T8') of the replica circuit 141a, and the twelfth transistor T12 of the amplification circuit 142a, which is an NMOS transistor, may have the same size as the ninth transistor T9' (or the tenth transistor T10') of the replica circuit 141a. Therefore, the amplification circuit 142a may start an amplification operation according to the level of the output signal OUT of the replica circuit 141a, and the amplification transistor of the sense amplifier 151' may start an amplification operation in response to the amplification enable signal AEN activated according to the amplification operation of the amplification circuit 142a.

[0058] refer to Figure 6B , the control signal generator 140b may include a replica circuit 141b and an amplifier circuit 142b. Fig. 6A Compared with the control signal generator 140a, Figure 6B The replica circuit 141b in the control signal generator 140b may include a balancing transistor that is always turned on. Figure 6B As shown, as an equalizing transistor, the third transistor T3' of the replica circuit 141b may have a gate to which the positive power supply voltage VDD corresponding to the deactivated sensing enable signal SEN is applied. Therefore, the first node N1' and the second node N2' may have the same potential.

[0059] Figure 7 is a diagram showing a method according to an example embodiment Fig. 6A and 6B The timing diagram of the operation of the control signal generators 140a and 140b is shown below. Figure 5 and Figure 6B describe Figure 7 , and no relative Figure 2 The description is redundant.

[0060] refer to Figure 7 , the development of the reference signal REF may start at time t71. In some example embodiments, as will be described below with reference to Fig.12As described above, the reference signal REF may have a level that moves in a development period (eg, between time t71 and time t72) in a manner similar to the data input signal DIN. On the other hand, in some example embodiments, Figure 5 In a different manner than shown, when the data input signal DIN is being developed, the reference signal REF may have a constant level, for example, a level equal to a level after time t72.

[0061] The read enable signal SEN may be enabled at time t72 so that the level of the output signal OUT of the replica circuit 141b may rise. Fig. 6A and 6B As described above, the level of the output signal OUT may be shifted in substantially the same manner as the level of the second node N2 of the sense amplifier 151 ′.

[0062] At time t73, the level of the output signal OUT may cross the threshold voltage Vth of the twelfth transistor T12 as an NMOS transistor, and thus the twelfth transistor T12 is turned on, so that the amplification enable signal AEN may be converted to a low level. The twelfth transistor T12 may have the same size as the ninth transistor T9 and the tenth transistor T10 of the sense amplifier 151', and thus the threshold voltage Vth of the twelfth transistor T12 may be equal to the threshold voltage of the ninth transistor T9 and the tenth transistor T10 of the sense amplifier 151'. The level of the output signal OUT of the replica circuit 141b is equal to the level of the second node N2 of the sense amplifier 151', and thus the ninth transistor T9 and the tenth transistor T10 of the sense amplifier 151' may be turned on at time t73, and the sense amplifier 151' may start an amplification operation in response to the activated amplification enable signal AEN. Therefore, the amplification operation of the amplification transistor of the sense amplifier 151' may be performed at a time point where the maximum gain is provided, and as a result, the control signal generator 140b may provide an optimized period D.

[0063] At time t74, the read enable signal SEN may be deactivated so that the first node N1' and the second node N2' of the replica circuit 141a may have a level corresponding to the negative power supply voltage VSS, and the output signal OUT may also have a low level. In response to the output signal OUT having a low level, the amplification circuit 142b may output a deactivated amplification enable signal AEN.

[0064] Figure 8 is a diagram showing a method according to an example embodiment Figure 1 1 is a circuit diagram of an example of a sense amplifier 151. Figure 5 The sense amplifier 151' is compared to Figure 8The sense amplifier 151" can also receive an input enable signal SAEN. In the following, no information is provided with respect to Figure 5 The description is redundant Figure 8 Description.

[0065] refer to Figure 8 , the sense amplifier 151" may include Figure 5 The transistors of the sense amplifier 151' are similar to the first transistor T1 to the tenth transistor T10, and may further include an input enable transistor T0 having a gate to which an input enable signal SAEN is applied. In some example embodiments, Figure 1 The controller 130 may generate an input enable signal SAEN, and the input enable signal SAEN may set the memory device 100 to perform a read operation. Figure 1 In response to the activated input enable signal SAEN, the bit line BLj may be electrically connected to the read circuit 150, and a signal for reading data stored in the memory cell M may be applied to the read circuit 150. Throughout the specification, the input enable signal SAEN may also be referred to as a third control signal.

[0066] like Figure 8 As shown, the input enable transistor T0 may block the positive power supply voltage VDD to the first transistor T1 and the second transistor T2 as input transistors in response to the deactivated input enable signal SAEN (e.g., the input enable signal SAEN having a high level), and may provide the positive power supply voltage VDD to the first transistor T1 and the second transistor T2 in response to the activated input enable signal SAEN. Therefore, power consumption of the first transistor T1 and the second transistor T2 may not occur in a period in which the read operation is not performed.

[0067] Fig. 9 is a diagram showing a method according to an example embodiment Figure 4 The circuit diagram of an example of the control signal generator 140' is shown in FIG. Fig. 9 The circuit diagram shows the Figure 8 The control signal generator 140c of the replica circuit 141c corresponding to the sense amplifier 151" is not provided here. Fig. 6A , 6B The description of 8 is redundant Fig. 9 Description.

[0068] refer to Fig. 9 , the control signal generator 140c may include a replica circuit 141c and an amplifier circuit 142c. The replica circuit 141c may include Figure 6BThe control signal generator 140b of the replica circuit 141b is similar to the first transistor T1' to the tenth transistor T10', and may also include Figure 8 The input of the sense amplifier 151" enables the replica transistor T0 corresponding to the transistor T0.

[0069] Fig.10 is a diagram showing a method according to an example embodiment Figure 8 The sense amplifier 151" and Fig. 9 The timing diagram of the operation of the control signal generator 140c is shown below. Figure 8 and Fig. 9 describe Fig.10 , and no relative Figure 2 and Figure 7 The description is redundant Fig.10 Description.

[0070] refer to Fig.10 , at time t91, the input enable signal SAEN may be activated. Thus, the development period may begin, and the development of the data input signal DIN may begin. Prior to time t91, in response to the deactivated input enable signal SAEN, power consumption of the input transistors of the sense amplifier 151″ and the replica circuit 141c may not occur.

[0071] At time t92, the read enable signal SEN may be activated, and the level of the output signal OUT of the replica circuit 141c and the level of the data output signal DOUT of the sense amplifier 151″ may be shifted. At time t93, the level of the output signal OUT of the replica circuit 141c may be shifted across the transistors (e.g., Fig. 9 The threshold voltage Vth of the twelfth transistor T12) of the replica circuit 141c is increased, so that the amplification enable signal AEN can be activated. In response to the activated amplification enable signal AEN, the sense amplifier 151" can perform an amplification operation, and the level of the data output signal DOUT can be shifted to a high level or a low level. At time t94, the input enable signal SAEN and the read enable signal SEN can be deactivated. Therefore, the output signal OUT of the replica circuit 141c can have a low level, and the amplification enable signal AEN can be deactivated.

[0072] Fig.11 is a diagram showing a method according to an example embodiment Figure 1 FIG. 1 is a diagram of an example of a memory cell M. Fig.12 is a diagram showing a method including Fig.11 1 is a block diagram of a memory device 200 having a memory cell M'. For example, Fig.11A memory cell M' including a magnetic tunnel junction (MTJ) as a variable resistance element is shown. Fig.12 Some components of the memory device 200 during a read operation are shown.

[0073] refer to Fig.11 , the memory cell M' may include a variable resistance element MTJ and a cell transistor CT connected in series between a source line SLj and a bit line BLj. Fig.11 As shown, the variable resistance element MTJ and the cell transistor CT may be sequentially connected between the source line SLj and the bit line BLj. Fig.11 Different from the illustration in FIG. , the cell transistor CT and the variable resistance element MTJ may be sequentially connected between the source line SLj and the bit line BLj.

[0074] The variable resistance element MTJ may include a free layer (FL) and a pinned layer (PL), and may further include a barrier layer between the free layer FL and the pinned layer PL. Fig.11 As shown by using arrows, the magnetization direction of the pinned layer PL may be fixed, and the magnetization direction of the free layer FL may be equal to or opposite to the magnetization direction of the pinned layer PL. When the pinned layer PL and the free layer FL have magnetization directions in one direction, the variable resistance element MTJ may be referred to as being in a parallel state P, and when the pinned layer PL and the free layer FL have magnetization directions in opposite directions, the variable resistance element MTJ may be referred to as being in an antiparallel state AP. In some example embodiments, the variable resistance element MTJ may further include an antiferromagnetic layer to allow the pinned layer PL to have a fixed magnetization direction. The variable resistance element MTJ may have a relatively low resistance R in the parallel state P. P , and can have a relatively high resistance R in the antiparallel state AP AP Throughout the specification, it is assumed that the variable resistance element MTJ in the parallel state P has a low resistance R P When the memory cell M' stores 0, and when the variable resistance element MTJ in the antiparallel state AP has a high resistance R AP , memory cell M' stores 1.

[0075] The cell transistor CT may have a gate (or control terminal) connected to the word line WLi, and a source and a drain connected to the bit line BLj and the variable resistance element MTJ. Depending on the voltage applied to the word line WLi, the cell transistor CT may electrically connect or disconnect the variable resistance element MTJ and the bit line BLj. For example, in a write operation, in order to write 0 to the memory cell M', the activated word line WLi may have a positive power supply voltage VDD, so that the cell transistor CT may be turned on and the current flowing from the source line SLj to the bit line BLj may pass through the variable resistance element MTJ via the cell transistor CT. And, in order to write 1 to the memory cell M', the activated word line WLi may have a positive power supply voltage VDD, so that the cell transistor CT may be turned on and the current flowing from the bit line BLj to the source line SLj may pass through the variable resistance element MTJ via the cell transistor CT. In a read operation, the cell transistor CT may be turned on, and a current flowing from the source line SLj to the bit line BLj or a current flowing from the bit line BLj to the source line SLj (e.g., a read current) may pass through the cell transistor CT and the variable resistance element MTJ. Throughout the specification, it is assumed that the read current flows from the bit line BLj to the source line SLj.

[0076] refer to Fig.12 , the memory device 200 may include a cell array 210, a controller 230, a control signal generator 240, a read circuit 250 and / or a reference resistor 260. Fig.11As described, the cell array 210 may include a memory cell Mi including a variable resistance element, and therefore, the memory device 200 may also be referred to as a resistive memory device or a resistive random access memory (RRAM or ReRAM) device. For example, the memory device 200 may include, but is not limited to, a cell array 210 having a structure such as a phase change random access memory (Phase Change Random Access Memory, PRAM), a ferroelectric random access memory (FRAM), or may include, but is not limited to, a cell array 210 having a magnetic random access memory (MRAM) structure such as a spin transfer torque magnetic random access memory (Spin-Transfer Torque Magnetic Random Access Memory, STT-MRAM), a spin torque transfer magnetization switching RAM (Spin Torque Transfer Magnetization Switching RAM, Spin-RAM), a spin momentum transfer RAM (Spin Momentum Transfer, SMT-RAM), or the like.

[0077] The cell array 210 may include not only the memory cell Mi but also the reference cell Ri connected to the word line WLi to which the memory cell Mi is also connected. In some example embodiments, the reference cell Ri may have a structure of the memory cell Mi that does not include a variable resistance element and may also be referred to as a short cell. The memory cell Mi may be connected to the bit line BLj and the source line SLj, and the reference cell Ri may also be connected to the bit line BLr and the source line SLr. Fig.12 As shown, during a read operation, a negative power supply voltage VSS may be applied to the memory cell Mi via the source line SLj, and the memory cell Mi may be connected to the read circuit 250 via the bit line BLj. Also, the reference cell Ri may be connected to the reference resistor 260 via the source line SLr, and may be connected to the read circuit 250 via the bit line BLr.

[0078] The read circuit 250 may include a sense amplifier 251 and a first current source 252 and a second current source 253. The first current source 252 may generate a first read current I RD1 , and the first read current I RD1The negative power supply voltage VSS may flow in through the bit line BLj, the memory cell Mi, and the source line SLj. The second current source 253 may generate a second read current I RD2 , and the second reading current I RD2 The negative power supply voltage VSS may flow in through the bit line BLr, the reference cell Ri, the source line SLr, and the reference resistor 260. In some example embodiments, the first read current I RD1 and the second read current I RD2 The data input signal DIN may have a value determined by the resistance of the variable resistance element included in the memory cell Mi and the first read current I RD1 The voltage level generated, and the reference signal REF may have a voltage level generated by the reference resistor 260 and the second read current I RD2 Therefore, before the read operation of the sense amplifier 251, not only the data input signal DIN but also the reference signal REF may be developed. The sense amplifier 251 may amplify the difference between the voltage level of the data input signal DIN and the voltage level of the reference signal REF, thereby generating a data output signal DOUT.

[0079] The controller 230 may generate a sense enable signal SEN for controlling a sense operation of the sense amplifier 251. The sense enable signal SEN may be provided to the sense amplifier 251 and the control signal generator 240. The control signal generator 240 may include a replica circuit 241 obtained by replicating at least some portion of the sense amplifier 251, and an amplification circuit 242, and the replica circuit 241 may generate an output signal OUT according to a reference signal REF and the sense enable signal SEN. The amplification circuit 242 may generate an amplification enable signal AEN by amplifying (e.g., inverting) the output signal OUT of the replica circuit 241, and may provide the amplification enable signal AEN to the sense amplifier 251.

[0080] Fig.13 is a flowchart illustrating a method for reading a memory device according to an example embodiment. Fig.13 The reading method can be Figure 1 100 is executed by the memory device 100. In the following, reference will now be made to Figure 1 and 10 describe Fig.13 .

[0081] refer to Fig.13In operation S10, an operation of receiving a read command may be performed. For example, the memory device 100 may receive a read command and an address. The controller 130 may recognize the read command and may generate a control signal for the read operation. Also, the row decoder 120 may select the memory cell M by activating the word line WLi corresponding to the address.

[0082] In operation S20, an operation of enabling the input stage of the sense amplifier 151 may be performed. For example, the controller 130 may generate an input enable signal SAEN activated at time t91. In response to the activated input enable signal SAEN, the input stage (eg, Figure 8 The first transistor T1 and the second transistor T2) are powered.

[0083] In operation S30, an operation of determining whether the development period has ended may be performed. For example, the controller 130 may include a counter and may count the clock signal starting from time t91. When the count value reaches a preset value, the controller 130 may determine that the development period has ended. When the development period has ended, operation S40 may be performed thereafter.

[0084] In operation S40, an operation of enabling a read operation of the sense amplifier 151 may be performed. For example, when the development period has ended, the controller 130 may generate a read enable signal SEN activated at time t92. In response to the activated read enable signal SEN, the read operation of the sense amplifier 151 may be performed.

[0085] In operation S50, an operation of enabling an amplification operation of the sense amplifier 151 may be performed. For example, the control signal generator 140 may include a replica circuit obtained by replicating at least some portions of the sense amplifier 151, and may emulate an output from the sense amplifier 151. Therefore, the control signal generator 140 may generate an amplification enable signal AEN activated at time t93 based on an output signal OUT from the replica circuit, wherein the level of the output signal OUT is changed after the sense enable signal SEN is activated.

[0086] In operation S60, an operation of determining whether the readout period has ended may be performed. For example, the controller 130 may include a counter and may count the clock signal starting from time t92. When the count value reaches a preset value, the controller 130 may determine that the readout period has ended. When the readout period has ended, operation S70 may be performed thereafter.

[0087] In operation S70, an operation of disabling the input stage and operation of the sense amplifier 151 may be performed. For example, the controller 130 may generate an input enable signal SAEN and a sense enable signal SEN that are deactivated at time t94 when the readout period has ended. Thus, the input stage and the readout operation of the sense amplifier 151 may be disabled. Also, the control signal generator 140 may generate a deactivated amplification enable signal AEN in response to the deactivated readout enable signal SEN, and may disable the amplification operation of the sense amplifier 151.

[0088] Fig.14 is a block diagram illustrating a memory system 30 including a memory device 32 according to an example embodiment. Fig.14 As shown, the memory system 30 may communicate with a host 40 and may include a controller 31 and a memory device 32 .

[0089] The interface 50 through which the memory system 30 communicates with the host 40 may use electrical signals and / or optical signals, and may be implemented as, but not limited to, a Serial Advanced Technology Attachment (SATA) interface, a SATA Express (SATAe) interface, a Serial Attached Small Computer System Interface; a Serial Attached SCSI (SAS), a Peripheral Component Interconnect Express (PCIe) interface, a Non-Volatile Memory Express (NVMe) interface, an Advanced Host Controller Interface (AHCI) or a combination thereof.

[0090] In some example embodiments, the memory system 30 may be removably combined with the host 40, thereby communicating with the host 40. The memory device 32 as a resistive memory may be a non-volatile memory, and the memory system 30 may also be referred to as a storage system. For example, the memory system 30 may be implemented as, but not limited to, a solid-state drive or solid-state disk (SSD), an embedded SSD (eSSD), a multimedia card (MMC), an embedded multimedia card (eMMC), etc.

[0091] The controller 31 may control the memory device 32 in response to a request received from the host 40 via the interface 50. For example, in response to a write request, the controller 31 may write data, which is received together with the write request, to the memory device 32, and may provide the host 40 with data stored in the memory device 32 in response to a read request.

[0092] The memory system 30 may include at least one memory device 32, and the memory device 32 may include a control signal generator configured to generate a control signal during a read operation. As described above, the control signal generator may generate an activated amplification enable signal at a time delayed from the time when the read enable signal is activated, and the delay between the read enable signal and the amplification enable signal may be improved or optimized. Therefore, regardless of changes in process, voltage, temperature, etc., the value stored in the memory cell may be read faster and / or more accurately. As a result, the operating speed and / or operating reliability of the memory system 30 may be improved.

[0093] Fig.15 60 includes a memory device according to an example embodiment. SoC 60 may refer to an integrated circuit that integrates components of a computing system or other electronic system. For example, an application processor (AP) as one of SoC 60 may include components for a processor and other functions. Fig.15 As shown, SoC 60 may include a core 61, a digital signal processor (DSP) 62, a graphics processing unit (GPU) 63, an embedded memory 64, a communication interface 65 and / or a memory interface 66. The components of SoC 60 may communicate with each other via a bus 67.

[0094] The core 61 may process instructions and may control the operations of components included in the SoC 60. For example, the core 61 may drive an operating system by processing a series of instructions and run an application on the operating system. The DSP 62 may generate useful data by processing a digital signal (e.g., a digital signal provided from the communication interface 65). The GPU 63 may generate data for image output via a display device according to image data provided from the embedded memory 64 or the memory interface 66, and may encode the image data.

[0095] The embedded memory 64 may store data required for the operation of the core 61, the DSP 62, and the GPU 63. The embedded memory 64 may include a control signal generator according to one or more example embodiments of the inventive concept, and thus, values ​​stored in memory cells of the embedded memory 64 may be read faster and / or more accurately regardless of changes in process, voltage, temperature, etc. As a result, the operation speed and / or operation reliability of the SoC 60 may be improved.

[0096] The communication interface 65 may provide an interface for a communication network or one-to-one communication. The memory interface 66 may provide an interface for an external memory of the SoC 60, for example, an interface for a dynamic random access memory (DRAM), a flash memory, and the like.

[0097] Although the inventive concept has been specifically shown and described with reference to the exemplary embodiments of the inventive concept, it will be understood by those skilled in the art that various changes may be made in form and detail without departing from the spirit and scope of the inventive concept as defined by the appended claims. The exemplary embodiments should be considered in a descriptive sense only and not for the purpose of limitation. Therefore, the scope of the inventive concept is not limited by the detailed description of the inventive concept, but by the appended claims, and all differences within the scope will be interpreted as included in the inventive concept.

Claims

1. A control signal generator for a sense amplifier, the sense amplifier being configured to receive a first control signal and a second control signal, the control signal generator comprising: a replica circuit including replica transistors corresponding to at least some of the plurality of transistors included in the sense amplifier and configured to receive at least one input signal of the sense amplifier and the first control signal for enabling a read operation of the sense amplifier; and an amplification circuit configured to output the second control signal for enabling the amplification operation of the sense amplifier after the sense operation is enabled by amplifying the output signal from the replica circuit.

2. The control signal generator according to claim 1, wherein The sense amplifier is configured to receive a reference signal and a data input signal, the data input signal varying according to data stored in the memory cell, and The replica circuits are further configured to commonly receive the reference signal.

3. The control signal generator according to claim 1, wherein: The replica circuit includes a replica transistor corresponding to an amplification enable transistor of the sense amplifier receiving the second control signal and configured to receive a signal equal to the deactivated second control signal.

4. The control signal generator according to claim 1, wherein: The replica circuit includes a replica transistor corresponding to an equalizing transistor of the sense amplifier that equalizes differential output signals in response to an activated first control signal and configured to receive a signal equal to the activated first control signal.

5. The control signal generator according to claim 1, wherein: The replica circuit includes a replica transistor corresponding to a reset transistor of the sense amplifier, the reset transistor of the sense amplifier resets a differential output signal in response to an activated first control signal, and the replica circuit is configured to receive the first control signal.

6. The control signal generator according to claim 1, wherein: The replica circuit is further configured to receive a third control signal for enabling an input transistor of the sense amplifier receiving the at least one input signal.

7. The control signal generator according to claim 1, wherein The replica circuit includes a replica transistor corresponding to an amplifying transistor of the sense amplifier, the amplifying transistor being used for an amplifying operation, and The amplifying circuit includes transistors having the same sizes as the amplifying transistors, respectively.

8. The control signal generator according to claim 1, wherein: The amplification circuit includes an inverter configured to output the second control signal by inverting an output signal from the replica circuit.

9. A control signal generator for a sense amplifier, the sense amplifier being configured to receive a first control signal and a second control signal, the control signal generator comprising: a replica circuit including a replica transistor corresponding to a transistor included in a sense amplifier and configured to generate an output signal for emulating an output from the sense amplifier in response to the first control signal for enabling a read operation of the sense amplifier; and an amplification circuit configured to output the second control signal for enabling the amplification operation of the sense amplifier after the sense operation is enabled by amplifying the output signal from the replica circuit.

10. The control signal generator according to claim 9, wherein The sense amplifier is configured to receive a reference signal and a data input signal, the data input signal varying according to data stored in the memory cell, and The replica circuits are further configured to commonly receive the reference signal.

11. The control signal generator according to claim 9, wherein: The amplification circuit is also configured to amplify an output signal from the replica circuit when the output signal from the replica circuit corresponds to an output from the sense amplifier, wherein the output provides maximum gain through an amplification transistor of the sense amplifier and the amplification transistor is used for an amplification operation.

12. A memory device comprising: Memory unit; a sense amplifier configured to sense and amplify a data input signal that varies according to data stored in the memory cell and to receive a first control signal and a second control signal; a controller configured to generate the first control signal for enabling a read operation of the sense amplifier; and a control signal generator configured to generate the second control signal for enabling an amplification operation of the sense amplifier according to the first control signal, The control signal generator includes a replica circuit corresponding to the sense amplifier, and an amplification circuit configured to generate the second control signal by amplifying an output signal from the replica circuit.

13. The memory device of claim 12, wherein The sense amplifier is further configured to receive a reference signal and the data input signal, and The replica circuits are configured to commonly receive the reference signal.

14. The memory device of claim 13, wherein The memory cell is configured to store data according to a resistance value of a variable resistance element included in the memory cell, and a read voltage is supplied to the sense amplifier as the data input signal, and The memory device also includes a reference circuit including a reference resistor and configured to generate a reference voltage as the reference signal.

15. The memory device of claim 12, wherein The sense amplifier includes an amplification enable transistor configured to receive the second control signal, and The replica circuit includes a replica transistor corresponding to the amplification enabling transistor, the replica transistor being configured to receive a signal equal to a deactivated second control signal.

16. The memory device of claim 12, wherein The sense amplifier includes an equalization transistor configured to equalize the differential output signal in response to the activated first control signal, and The replica circuit includes a replica transistor corresponding to the equalizing transistor, the replica transistor being configured to receive a signal equal to the activated first control signal.

17. The memory device of claim 12, wherein The sense amplifier includes a reset transistor configured to reset the differential output signal in response to the activated first control signal, and The replica circuit includes a replica transistor corresponding to the reset transistor, the replica transistor being configured to receive the first control signal.

18. The memory device of claim 12, wherein The sense amplifier includes an input transistor configured to receive the data input signal, The controller is further configured to generate a third control signal for enabling the input transistor, and The replica circuit is configured to receive the third control signal.

19. The memory device of claim 18, wherein the controller is further configured to activate the second control signal after activating the third control signal.

20. The memory device of claim 12, wherein The sense amplifier includes an amplifying transistor for the amplifying operation, The replica circuit includes a replica transistor corresponding to the amplifying transistor, and The amplifying circuit includes transistors having the same sizes as the amplifying transistors, respectively.

Images