Non-volatile memory device and initialization information reading method thereof

Abstract

A method for reading initialization information from a nonvolatile memory device is disclosed. In the method, when power-on is detected, the nonvolatile memory device divides a source voltage to generate a low read pass voltage to be provided to an unselected word line in an initialization information read operation. The low read pass voltage is set to at least one voltage between a ground voltage and a source voltage. The nonvolatile memory device allows the source voltage to not be pumped in an initialization information read operation based on power-on. In the initialization information read operation, the nonvolatile memory device provides a low read pass voltage to an unselected word line and provides a read voltage to a selected word line to read the initialization information stored in a memory cell.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2018-0042921 filed on April 12, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present invention is conceived to relate to a nonvolatile memory device, and more particularly, to a nonvolatile memory device, a voltage generating method, a reading method, and a memory system and an electronic device each including a nonvolatile memory device, which can reduce the consumption current when performing an initialization information reading operation for the nonvolatile memory device. Background Art

[0004] Solid-state drives (SSDs) are high-performance and high-speed storage devices that can store data in nonvolatile memory devices. Non-Volatile Memory Express (NVMe) is an ultra-high-speed data transmission standard optimized for accessing SSDs, and NVMe is being applied to SSDs. NVMe provides direct input / output (I / O) access to storage devices (or nonvolatile memory devices) equipped in a Peripheral Component Interconnect Express (PCIe) interface.

[0005] The amount of content imposed on storage systems including storage devices and hosts is increasing. Therefore, the requirements for large-capacity storage devices are increasing. NVMe SSDs are large-capacity storage devices, each of which includes multiple non-volatile memory devices, and each non-volatile memory device includes flash memory cells. Structurally, NVMe (NVMe-oF) is a storage array based on NVMe SSDs and can be expanded into fabrics that can communicate in a massively parallel manner.

[0006] In a nonvolatile memory device, initialization information including product content can be stored in a NAND flash memory cell and can be read in a boot operation to power the device. When the number of nonvolatile memory devices included in an NVMe SSD or NVMe-oF increases significantly, the number of nonvolatile memory devices required to read the initialization information increases, and thus, the consumption current and the peak consumption current based on the initialization information reading operation increase. Summary of the invention

[0007] The inventive concept provides a nonvolatile memory device, a voltage generating method, a reading method, and a memory system and an electronic device each including the nonvolatile memory device, which can reduce consumption current when performing an initialization information reading operation.

[0008] According to one aspect of the inventive concept, a nonvolatile memory device is provided, comprising: a memory cell array configured to store initialization information for the nonvolatile memory device in memory cells connected to a plurality of word lines; a control circuit configured to: in an initialization information read operation for reading the initialization information, control application of a first read voltage to a selected word line, and control application of a second read voltage to unselected word lines; and a voltage generator configured to reduce a source voltage to generate the second read voltage in response to a voltage control signal provided from the control circuit in the initialization information read operation.

[0009] According to another aspect of the inventive concept, a memory system is provided, comprising at least one nonvolatile memory device and a memory controller configured to control the at least one nonvolatile memory device, wherein the at least one nonvolatile memory device comprises: a memory cell array configured to store initialization information for the nonvolatile memory device in memory cells connected to a plurality of word lines; a control circuit configured to control application of a first read voltage to a selected word line and control application of a second read voltage to an unselected word line in an initialization information read operation for reading the initialization information; and a voltage generator configured to reduce a source voltage to generate the second read voltage in response to a voltage control signal provided from the control circuit in the initialization information read operation.

[0010] According to another aspect of the inventive concept, a method for reading a nonvolatile memory device is provided, the method comprising: detecting power-on; in response to the detected power-on, reading initialization information for the nonvolatile memory device stored in a memory cell of the nonvolatile memory device; and when reading the initialization information, generating a first read voltage to be provided to a selected word line among a plurality of word lines connected to the memory cell, and a second read voltage to be provided to an unselected word line among the plurality of word lines connected to the memory cell, wherein the second read voltage is generated by reducing a source voltage.

[0011] According to another aspect of the present invention, a method is provided, including: a non-volatile memory device detects a power-on state for the memory device; and in response to detecting the power-on state, the non-volatile memory device reads initialization information for the non-volatile memory device stored in a first memory cell of a memory cell array of the non-volatile memory device, and sets the initialization information for the non-volatile memory device in a setting register of the non-volatile memory device. Reading the initialization information for the non-volatile memory device stored in a first memory cell of a memory cell array of the non-volatile memory device includes: applying a first read voltage having a voltage level for distinguishing an erase state and a program state of the first memory cell to a selected word line connected to the first memory cell; and applying a second read voltage having a voltage level less than the program state of the first memory cell to an unselected word line not connected to the first memory cell when the first read voltage is applied to the selected word line. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0013] Figure 1 A conceptual embodiment of a data processing system as an electronic device to which an embodiment of a nonvolatile memory device is applied is shown.

[0014] Figure 2 is a block diagram showing a schematic configuration of a solid state drive (SSD), which is a memory system including an embodiment of a nonvolatile memory device.

[0015] Figure 3 Is used to describe Figure 2 A block diagram of an embodiment of a non-volatile memory device is shown.

[0016] Figure 4 and Figure 5 Is used to describe Figure 3 A diagram of a first memory storage block.

[0017] Figure 6 is a diagram for conceptually describing an embodiment of initialization information reading.

[0018] Figure 7 , Figure 8 and Fig. 9 Is used to describe Figure 3 FIG. 1 is a diagram of an exemplary embodiment of a low voltage generating circuit.

[0019] Fig.10 , Fig.11 and Fig.12 Is used to describe Figure 3 FIG. 1 is a diagram of another exemplary embodiment of a low voltage generating circuit.

[0020] Fig.13 It shows Figure 3 A flow chart of an embodiment of a method for reading initialization information of a non-volatile memory device is shown in FIG.

[0021] Fig.14 It shows that based on Fig.13 FIG. 1 is a table of examples of word line voltages applied during an initialization information read operation.

[0022] Fig.15 It shows that when using Figure 3 FIG. 1 is a diagram of a consumption current pattern when an initialization information read operation is performed according to an embodiment of a nonvolatile memory device shown in FIG.

[0023] Fig.16 is a block diagram showing a server system to which a storage device including an embodiment of a nonvolatile memory device is applied.

[0024] Fig.17 is a block diagram illustrating a storage cluster to which a storage device including an embodiment of a non-volatile memory device is applied.

[0025] Fig.18 is a block diagram illustrating a system including an embodiment of a non-volatile memory device.

[0026] Fig.19 is a block diagram showing an example in which an embodiment of a nonvolatile memory device is applied to a memory card system. DETAILED DESCRIPTION

[0027] Figure 1 A conceptual embodiment of a data processing system 100 is shown as an electronic device to which an embodiment of a nonvolatile memory device is applied.

[0028] refer to Figure 1 , data processing system 100 may include multiple peers 110 and 120 that communicate with each other by using a remote direct memory access (RDMA) protocol. Peers 110 and 120 may each be a storage system or a computer system that sends or receives data through network 130. Peers 110 and 120 may be provided as, for example, clients, servers, server palmtops, server clusters, application servers, or message servers.

[0029] Peers 110 and 120 are shown as server 110 and client 120. Server 110 may represent a peer that receives requests from client 120 over network 130, performs services, and sends results of the services to client 120. Client 120 may represent a peer that issues requests to server 110 and waits for responses. Client 120 may be referred to as a host.

[0030] RDMA can perform data transmission from one memory to another device or memory of the system. Data transmission can be performed through the network 130 without a central processing unit (CPU) (or processor) or an operating system (OS), and achieve high throughput, low latency and low overhead data transmission.

[0031] The network 130 is shown as a separate single network, but can be any type of network as understood by those of ordinary skill in the art. The network 130 can be for personal use or public use, can be a wired network or a wireless network, or can be an entire network or a portion of a network. According to an embodiment, the network 130 can be a global network such as the Internet or the World Wide Web (referred to as the Web), a wide area network (WAN), or a local area network (LAN).

[0032] The server 110 may include an RDMA network integrated circuit (RNIC) and a storage device 114 connected to a peripheral component interconnect express (PCIe) bus 111. PCIe is a high-speed serial computer expansion bus standard designed to replace the PCI, PCI-X, and Accelerated Graphics Port (AGP) bus standards. Compared to other standards, PCIe may include improved expansion performance and more detailed error detection and reporting mechanisms to achieve higher maximum system bus throughput, lower input / output (I / O) pin counts, and smaller physical throughput and bus devices.

[0033] The RNIC 112 may be a network interface controller that supports a network interface card, a network adapter, and / or RDMA. The storage device 114 connected to the RNIC 112 may be implemented using RDMA with a non-volatile memory express (NVMe) storage protocol. The NVMe storage protocol may include, for example, one of the Internet Wide Area RDMA Protocol (iWARP), infiniband, and RDMA over Converged Ethernet (RoCE).

[0034] The storage device 114 may include a plurality of storage elements 115 to 118, and the storage elements 115 to 118 may be configured with an NVMe solid-state drive (NVMe SSD) or a PCIe SSD. The storage device 114 may be implemented with NVMe over Fabric (NVMe-oF). NVMe may be an extensible host controller interface designed to handle the needs of companies, data centers, and client systems capable of using SSDs. NVMe may be used as an SSD device interface for presenting a storage entity interface to the host. NVMe may define a register interface, a command set, and a feature set optimized for NVMe SSDs, may use the functionality of NVMe SSDs, and may be located at a location for a standardized NVMe SSD interface.

[0035] The client 120 may include an RNIC 122, a memory 124, and a processor (or CPU) 126. The memory 124 may include a system memory, a main memory, a volatile memory, and a non-volatile memory. The memory 124 may be a volatile computer storage medium, a non-volatile computer storage medium, an attachable / removable computer storage medium, or a non-removable computer storage medium, which is implemented based on any method or technology for storing computer-readable commands, data structures, program modules, or other data. The computer storage medium may include a random access memory (RAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, or other memory technology (a compact disk ROM (CD-ROM), a digital versatile disk (DVD), or another optical storage device, a cassette, a magnetic tape, a magnetic disk storage device, or another magnetic storage device, or another arbitrary medium for storing the desired information and accessible by a computer system, but is not limited thereto.

[0036] The processor 126 may control the overall operation of the data processing system 100. The processor 126 may include a plurality of processing cores, and the plurality of processing cores may each include a plurality of processing entries. The processor 126 may command a write operation to write data in the storage device 114 of the server 110 or a read operation to read data from the storage device 114 of the server 110 based on the processing entry. For example, the processor 126 may send a command to the server 110 through the network 130, wherein the command causes the server 110 to start data transmission (e.g., transmit data stored in the storage device 114).

[0037] RNIC 122 may be a network interface controller that supports a network interface card, a network adapter, and / or RDMA similar to RNIC 112 of server 110. RNICs 112 and 122 may support an RDMA protocol. RNICs 112 and 122 may support an RDMA protocol that allows data to be sent directly from storage device 114 to memory 124 and / or directly from memory 124 to storage device 114. Data transmission may not require or include supervision by processor 126. Therefore, the RDMA protocol may have good characteristics such as high bandwidth, low latency, and low overhead.

[0038] In the data processing system 100, when power-on is detected in booting, the storage elements (i.e., SSDs) 115 to 118 of the server 110 may perform an initialization operation. The initialization operation of each of the SSDs 115 to 118 may include an operation of reading initialization information stored in one or more nonvolatile memory devices embedded in the corresponding SSD and setting the initialization information in a setting register of the nonvolatile memory device.

[0039] As the capacity of SSD increases, the number of nonvolatile memory devices increases significantly, and therefore, if the nonvolatile memory devices simultaneously perform an initialization information read operation, the consumption current of the server 110 increases. Therefore, it is desirable to develop a method for reducing the consumption current based on the initialization information read operation of each nonvolatile memory device in the initialization operation of a large-capacity SSD.

[0040] Figure 2 is a block diagram showing a schematic configuration of an SSD 200 , which is a memory system including an embodiment of a nonvolatile memory device. Figure 2 The SSD 200 can be used with Figure 1 corresponds to each of the storage elements 115 to 118.

[0041] refer to Figure 2 , the SSD 200 may include a memory controller 210, a plurality of nonvolatile memory devices 220 to 22n, and a volatile memory device 230. The memory controller 210 may control a read operation, a program operation, an erase operation, and / or an initialization information read operation of the plurality of nonvolatile memory devices 220 to 22n, which operations may be responsive to a request from a host connected to the SSD 200. The host may communicate with Figure 1 Corresponding to the client 120.

[0042] According to an embodiment, the host can be any computing system, such as a personal computer (PC), a server computer, a workstation, a laptop computer, a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a digital television (TV), a set-top box, a music player, a portable game console, a navigation system, etc.

[0043] The plurality of nonvolatile memory devices 220 to 22n may be used as storage media of the SSD 200. Each of the plurality of nonvolatile memory devices 220 to 22n may be, for example, a NAND flash memory device. The plurality of nonvolatile memory devices 220 to 22n may be connected to the memory controller 210 through a channel. In response to a request provided by the host through the channel, each of the plurality of nonvolatile memory devices 220 to 22n may perform a read operation, a program operation, and an erase operation, and at boot time, may perform an initialization information read operation.

[0044] The volatile memory device 230 may temporarily store write data provided from the host or data read from each of the plurality of non-volatile memory devices 220 to 22n. The volatile memory device 230 may store metadata or cache data to be stored in the plurality of non-volatile memory devices 220 to 22n. The volatile memory device 230 may include a dynamic RAM (DRAM), a static random access memory (SRAM), or the like.

[0045] The plurality of nonvolatile memory devices 220 to 22n may each include a memory cell array 310 and a setting register 320. Initialization information indicating the product content of the corresponding nonvolatile memory device and read by an initialization information read operation at boot time may be set in the setting register 320. In addition, the setting register 320 may store data received from the memory controller 210 and control signals received from the memory controller 210 for operation options, functions, characteristics, and operation modes of the corresponding nonvolatile memory device.

[0046] Each of the plurality of nonvolatile memory devices 220 to 22n may store protection information on prohibiting or permitting a program / erase operation, trimming data for trimming an operation voltage level in an operation mode, column repair information for repairing a failed bit line, and a portion of the memory cell array 310 (see Figure 3The trimming data may be data for voltage control in an operation mode (i.e., a read operation, a program operation, and an erase operation) for each of the plurality of nonvolatile memory devices 220 to 22n, and further, may be data for controlling a sense amplifier or a page buffer or setting initialization of a reference cell.

[0047] When power-on is detected in booting, the SSD 200 may perform an initialization information read operation for each of the plurality of nonvolatile memory devices 220 to 22n. In the SSD 220 having a large capacity, when the number of the nonvolatile memory devices 220 to 22n increases significantly, the plurality of nonvolatile memory devices 220 to 22n may simultaneously perform the initialization information read operation, and thereby, a consumption current peak occurs, and the amount of consumption current may exceed an allowable value or limit. At least one reason for this is because a pumping operation simultaneously performed by the nonvolatile memory devices 220 to 22n generates a read pass voltage required for the initialization information read operation. However, when the read pass voltage required for the initialization information read operation is generated without a pumping operation in the nonvolatile memory devices 220 to 22n, the consumption current peak and the amount of consumption current may be reduced.

[0048] In the following, the following will be described in detail Figure 2 22 is an example configuration of the nonvolatile memory device 220 among the nonvolatile memory devices 220 to 22n.

[0049] Figure 3 Is used to describe Figure 2 A block diagram of an example embodiment of a non-volatile memory device 220 is shown.

[0050] refer to Figure 3 , the nonvolatile memory device 220 may include a memory cell array 310, a control circuit 330, an address decoder 340, a read circuit 350, and a voltage generator 360. Although not shown, the nonvolatile memory device 220 may also include a write circuit and an I / O circuit. The write circuit may be configured with a write driver that receives a data from the memory controller 210 (see FIG. 1 ) via an I / O line. Figure 2 ) and stores the received data in the memory cell array 310. The I / O circuit may temporarily store commands, addresses, control signals, and data provided through the I / O lines from the memory controller 210. The I / O circuit may temporarily store read data of the nonvolatile memory device 220 and may output the read data to the memory controller 210 through the I / O lines at a predetermined time.

[0051] The memory cell array 310 may include a plurality of memory cells, and for example, the plurality of memory cells may be flash memory cells. Hereinafter, an example in which the plurality of memory cells are NAND flash memory cells is described as an example of an embodiment. The memory cell array 310 may include a three-dimensional (3D) memory cell array including a plurality of NAND strings.

[0052] The 3D memory cell array may be a circuit including an active area disposed on a silicon substrate and associated with the operation of each memory cell, and may be configured in a monolithic type at the physical level of at least one memory cell array, each memory cell array including a circuit disposed on or in a substrate. The monolithic type may mean that the layers of the levels of the configuration array are stacked only on the layers of the lower levels of the array. In an embodiment, the 3D memory cell array may include a plurality of NAND strings arranged in a vertical direction so that at least one memory cell is disposed on another memory cell. At least one memory cell may include a charge trapping layer. U.S. Patents 7,679,133, 8,553,466, 8,654,587, and 8,559,235 and U.S. Patent Application Publication No. 2011 / 0233648 disclose suitable elements of a 3D memory array including a plurality of levels and sharing word lines and / or bit lines between the plurality of levels. These documents are incorporated herein by reference.

[0053] The memory cell array 310 may include a plurality of memory storage blocks (e.g., a first memory storage block to an nth memory storage block) BLK1 to BLKn. The plurality of memory storage blocks BLK1 to BLKn may be connected to a string selection line SSL, a word line WL, a ground selection line GSL, and a bit line BL. The plurality of memory storage blocks BLK1 to BLKn may be connected to an address decoder 340 through a string selection line SSL, a word line WL, and a ground selection line GSL, and may be connected to a read circuit 350 through a bit line BL.

[0054] The first memory storage block BLK1 may include a plurality of NAND strings NS, and the plurality of NAND strings NS may each include a string selection transistor SST, a plurality of memory cells MC, and a ground selection transistor GST connected in series. The string selection transistor SST may be connected to a string selection line SSL, each of the plurality of memory cells MC may be connected to a corresponding word line WL1 to WL8, and the ground selection transistor GST may be connected to a ground selection line GSL. The string selection transistor SST may be connected to corresponding bit lines BL1 to BLi, and the ground selection transistor GST may be connected to a common source line CSL.

[0055] The number of columns and rows of the NAND string NS of the first memory storage block BLK1 may increase or decrease. As the number of columns of the NAND string NS changes, the number of word lines WL may change. As the number of rows of the NAND string NS changes, the number of bit lines BL connected to the columns of the NAND string NS and the number of NAND strings NS connected to a string selection line SSL may change. The height of each NAND string NS may increase or decrease. For example, the number of memory cells stacked in each NAND string NS may increase or decrease.

[0056] 1-bit data may be stored in a memory cell of the first memory storage block BLK1. A memory cell for storing 1-bit data in one memory cell may be referred to as a single-level cell or a single-bit cell.

[0057] The first memory storage block BLK1 may be set as a storage block storing initialization information about the nonvolatile memory device 220. For example, it may be assumed that the initialization information about the nonvolatile memory device 220 is stored in the entire portion or a portion 312 of the first memory storage block BLK1. Memory cells storing the initialization information may be referred to as "first memory cells", and word lines connected to these first memory cells may be referred to as selected word lines, and other word lines not connected to the first memory cells may be referred to as unselected word lines.

[0058] Similar to the first memory storage block BLK1, the second memory storage block BLK2 to the nth memory storage block BLKn may each include a plurality of memory cells and a plurality of selection transistors. Each of the second memory storage block BLK2 to the nth memory storage block BLKn may be set as a storage block for storing data transmitted from the memory controller 210. The memory cell of each of the second memory storage block BLK2 to the nth memory storage block BLKn may be configured as a multi-level cell (or multi-bit cell) for storing two or more bits of data in a single-level cell or one memory cell.

[0059] The control circuit 330 may control the overall operation of the nonvolatile memory device 220. The control circuit 330 may control a read operation, a program operation, and / or an erase operation on the memory cell array 310 based on a command, an address, and a control signal received from the memory controller 210.

[0060] The control circuit 330 may provide a row address to the address decoder 340, a column address to the read circuit 350, and a voltage control signal CTRL_Vol to the voltage generator 360. The control circuit 330 may detect power-up to generate the voltage control signal CTRL_Vol.

[0061] The control circuit 330 may control an operation of reading initialization information stored in the first memory storage block BLK1 of the memory cell array 310. The control circuit 330 may control a read pass voltage Vread level required to perform the initialization information read operation. Based on the voltage control signal CTRL_Vol provided from the voltage generator 360, the control circuit 330 may perform control in the initialization information read operation so that the read pass voltage Vread level is less than or equal to the source voltage VDD level.

[0062] The control circuit 330 may include a setting register 320 to store initialization information read by an initialization information reading operation. It is obvious to those skilled in the art that in other embodiments, the setting register 320 may not be embedded in the control circuit 330 .

[0063] The address decoder 340 may select a memory storage block from among a plurality of memory storage blocks BLK1 to BLKn of the memory cell array 310, and may apply a word line voltage to each word line WL of the selected memory storage block. In a programming operation, a programming voltage Vpgm may be applied to a selected word line, and a pass voltage Vpass may be applied to an unselected word line. In a read operation, a read voltage Vrd may be provided to a selected word line, and a high read pass voltage Vread_H having a high voltage level higher than a source voltage VDD level may be provided to an unselected word line. In an initialization information read operation, a read voltage Vrd may be provided to a selected word line, and a low read pass voltage Vread_L generated by dividing a source voltage VDD may be provided to an unselected word line. In this specification, the read voltage Vrd may be referred to as a first read voltage, and the read pass voltage Vread may be referred to as a second read voltage.

[0064] In a read operation, the read circuit 350 may read data from each of the second memory storage block BLK2 to the nth memory storage block BLKn of the memory cell array 310, and may transmit the read data to the data I / O circuit, which outputs the read data to the memory controller 210. In addition, in an initialization information read operation, the read circuit 350 may read the initialization information stored in the first memory storage block BLK1 of the memory cell array 310, and may set the read initialization information in the setting register 320 of the control circuit 330. The read circuit 350 may include an element that performs data reading (e.g., a page register or a page buffer), and a column selection circuit that selects the bit line BL.

[0065] In response to the control of the control circuit 330, the voltage generator 360 may generate a voltage (i.e., a word line voltage) to be provided to the word line WL of the memory cell array 310. In a programming operation, the voltage generator 360 may generate a programming voltage Vpgm to be provided to a selected word line and a pass voltage Vpass to be provided to an unselected word line. In a read operation, the voltage generator 360 may generate a read voltage Vrd to be provided to a selected word line and a high read pass voltage Vread_H to be provided to an unselected word line. The voltage generator 360 may pump a source voltage VDD to generate a high voltage, and may generate a programming voltage Vpgm, a pass voltage Vpass, and a high read pass voltage Vread_H according to the generated high voltage. In some embodiments, the source voltage VDD may be provided to the voltage generator 360 from the memory controller 210. According to other embodiments, the source voltage VDD may not be provided to the voltage generator 360 through the memory controller 210.

[0066] The voltage generator 360 may include a low voltage generating circuit 362 that generates a low read pass voltage Vread_L to be provided to an unselected word line in an initialization information read operation in response to a voltage control signal CTRL_Vol provided from the control circuit 330. The low voltage generating circuit 362 may generate a low read pass voltage Vread_L to be provided to an unselected word line in an initialization information read operation based on a source voltage VDD. The low voltage generating circuit 362 may generate the low read pass voltage Vread_L as a voltage generated by dividing the source voltage VDD (e.g., using a voltage divider such as a resistor divider or a ladder). Reference will be made to the following. Figures 7 to 12 An embodiment of the low voltage generating circuit 362 is described in detail.

[0067] Figure 4 and Figure 5 Is used to describe Figure 3 FIG. 1 is a diagram of a first memory storage block BLK1. Figure 4 is a circuit diagram of a NAND string NS storing initialization information in a first memory storage block BLK1. Figure 5 is a graph showing the threshold voltage distribution of a single level cell of the first memory storage block BLK1. Figure 5 , the abscissa axis represents the threshold voltage Vth, and the ordinate axis represents the number of memory cells.

[0068] refer to Figure 4 The NAND string NS may include a string selection transistor SST, first to eighth memory cells MC1 to MC8, and a ground selection transistor GST. For example, initialization information may be stored in fourth and fifth memory cells MC4 and MC5 of the first to eighth memory cells MC1 to MC8.

[0069] Before the initialization information is stored in the fourth memory cell MC4 and the fifth memory cell MC5, that is, before the fourth memory cell MC4 and the fifth memory cell MC5 are programmed, the first memory cell MC1 to the eighth memory cell MC8 may be in an erased state by first performing an erase operation. Subsequently, a programming operation may be performed in the fourth memory cell MC4 and the fifth memory cell MC5 in which the initialization information is stored in the first memory cell MC1 to the eighth memory cell MC8. Therefore, the fourth memory cell MC4 and the fifth memory cell MC5 may be in a programmed state, and the first memory cell MC1 to the third memory cell MC3 and the sixth memory cell MC6 to the eighth memory cell MC8 may be in an erased state.

[0070] In the initialization information read operation, in order to read the initialization information stored in the fourth memory cell MC4 and the fifth memory cell MC5, the read voltage Vrd may be applied to the selected fourth word line WL4 and the fifth word line WL5 according to a predetermined order, and the read pass voltage Vread may be applied to the unselected first to third word lines WL1 to WL3 and the sixth to eighth word lines WL6 to WL8. In addition, a voltage (e.g., a read pass voltage Vread) for turning on the string selection transistor SST and the ground selection transistor GST may be applied to the string selection line SSL and the ground selection line GSL.

[0071] For example, the read voltage Vrd may be a voltage for determining a program state of the first to eighth memory cells MC1 to MC8 , and may have a level between threshold voltage distributions based on the program states of the first to eighth memory cells MC1 to MC8 .

[0072] In a general read method, the read pass voltage Vread may be a voltage for turning on each of the first to eighth memory cells MC1 to MC8 regardless of a program state of the first to eighth memory cells MC1 to MC8 , and may be a high voltage.

[0073] The first to eighth memory cells MC1 to MC8 storing initialization information may be single-level cells. Figure 5As shown, it may have one of the erase state E and the program state P. Therefore, the ground voltage (i.e., a voltage of 0V) between the distribution based on the erase state E and the distribution based on the program state P may be set as the read voltage Vrd applied to the selected fourth word line WL4 and the fifth word line WL5. Based on a general read method, a high read pass voltage Vread_H may be applied to the unselected first to third word lines WL1 to WL3 and the sixth to eighth word lines WL6 to WL8. The high read pass voltage Vread_H may be a voltage higher than the threshold voltage distribution based on the program state P.

[0074] In this case, the voltage generator 360 (see Figure 3 ) can perform a pumping operation using the source voltage VDD to generate a high read pass voltage Vread_H. Therefore, the nonvolatile memory device 220 (see Figure 3 ) may perform a pumping operation to generate a high read pass voltage Vread_H in an initialization information read operation, whereby a consumption current may be increased.

[0075] Figure 6 is a diagram for conceptually describing an embodiment of an initialization information reading method.

[0076] refer to Figure 4 and Figure 6 , when the first memory storage block BLK1 storing the initialization information (see Figure 3 ) is a single-level cell, the distribution of the threshold voltage Vth of the memory cell is shown. Figure 4 In the NAND string NS, the fourth memory cell MC4 and the fifth memory cell MC5 may be in the programmed state P, and the first to third memory cells MC1 to MC3 and the sixth to eighth memory cells MC6 to MC8 may be in the erased state E. The memory cells MC1 to MC3 and MC6 to MC8 having the erased state E may have a negative (-) threshold voltage Vth, and thus, as shown, even when one of the first to fifth read pass voltages Vread_L0 to Vread_L4 is applied to the unselected word lines WL1 to WL3 and WL6 to WL8, the memory cells MC1 to MC3 and MC6 to MC8 may be turned on.

[0077] For example, the first read pass voltage Vread_L0 may be set to 0V (ie, the ground voltage VSS level), and the fifth read pass voltage Vread_L4 may be set to the source voltage VDD level. Figure 6The number of read pass voltages Vread_L0 to Vread_L4 between the ground voltage VSS and the source voltage VDD shown in FIG. 5 is five, but the embodiment is not limited thereto. According to an embodiment, the low read pass voltage Vread_L in the initialization information read operation may be set to at least one voltage between the low read pass voltage Vread_L and the ground voltage VSS.

[0078] The first to fifth read pass voltages Vread_L0 to Vread_L4 may be provided from the low voltage generation circuit 362 that divides the source voltage VDD. Figures 7 to 12 The detailed configuration of the low voltage generating circuit 362 is described.

[0079] Figures 7 to 9 It is used to describe illustrative Figure 3 FIG. 360 is a diagram of an embodiment of a low voltage generating circuit 362 .

[0080] refer to Figure 7 , the low voltage generating circuit 362 may include a voltage divider 710 and a selector 720. The voltage divider 710 may include a plurality of resistors R0 to R3 connected in series between a source voltage VDD and a ground voltage VSS. The voltage across each of the plurality of resistors R0 to R3 may be output as a first read pass voltage Vread_L0 to a fifth read pass voltage Vread_L4.

[0081] When the plurality of resistors R0 to R3 have the same resistance value, the first to fifth read pass voltages Vread_L0 to Vread_L4 may have equal voltage differences (eg, Figure 6 For example, when the plurality of resistors R0 to R3 have different resistance values, the first read pass voltage Vread_L0 to the fifth read pass voltage Vread_L4 may have different voltage differences (eg, Figure 8 or Fig. 9 shown).

[0082] exist Figure 8 , when the relationship of the resistance values ​​of the plurality of resistors R0 to R3 is R3>R2>R1>R0, the first to fifth read pass voltages Vread_L0 to Vread_L4 output from the voltage divider 710 are shown.

[0083] exist Fig. 9 , when the relationship of the resistance values ​​of the plurality of resistors R0 to R3 is R3<R2<R1<R0, the first to fifth read pass voltages Vread_L0 to Vread_L4 output from the voltage divider 710 are shown.

[0084] In response to the voltage control signal CTRL_Vol provided from the control circuit 330 , the selector 720 may select one read pass voltage among the first to fifth read pass voltages Vread_L0 to Vread_L4 output from the voltage divider 710 , and may output the selected read pass voltage as the low read pass voltage Vread_L.

[0085] Therefore, in the initialization information read operation, the low voltage generation circuit 362 may generate one of the first to fifth read pass voltages Vread_L0 to Vread_L4 between the ground voltage VSS and the source voltage VDD as the low read pass voltage Vread_L in response to the voltage control signal CTRL_Vol.

[0086] Figures 10 to 12 It is used to describe illustrative Figure 3 FIG. 360 is a diagram of other embodiments of the low voltage generating circuit 362 .

[0087] refer to Fig.10 , the low voltage generating circuit 362a may include a first resistor Ra and a second resistor Rb connected in series between a source voltage VDD and a ground voltage VSS, and may output a low read pass voltage Vread_L to a connection node between the first resistor Ra and the second resistor Rb. The resistance value of the second resistor Rb may vary according to a voltage control signal CTRL_Vol provided from the control circuit 330.

[0088] In the initialization information read operation, the low voltage generation circuit 362 a may generate a low read pass voltage Vread_L as a voltage generated by dividing the source voltage VDD via the first resistor Ra and the second resistor Rb.

[0089] refer to Fig.11 , the low voltage generating circuit 362b may include a first resistor R and a plurality of resistors RS0 to RS3 connected in series between a source voltage VDD and a ground voltage VSS, and a plurality of transistors MS0 to MS3 connected between the plurality of resistors RS0 to RS3. A voltage corresponding to the voltage control signal code CTRL_Vol[0:3] provided from the control circuit 330 as bit information may be applied to the gate of each of the transistors MS0 to MS3.

[0090] The low voltage generating circuit 362b may output a low read pass voltage Vread_L to a connection node between the first resistor R and the plurality of resistors RS0 to RS3. The first resistor R and the plurality of resistors RS0 to RS3 may have the same resistance value. According to an embodiment, the first resistor R and the plurality of resistors RS0 to RS3 may have different resistance values.

[0091] In the initialization information read operation, the low voltage generation circuit 362 b may generate a low read pass voltage Vread_L as a voltage generated by dividing a source voltage VDD through a plurality of resistors RS0 to RS3 short-circuited based on the voltage control signal code CTRL_Vol[0:3].

[0092] refer to Fig.12 , the low voltage generating circuit 362c may include a first resistor R, a plurality of resistors RP0 to RP3 connected in parallel between the first resistor R and the ground voltage VSS, and a plurality of transistors MP0 to MP3 connected between the plurality of resistors RP0 to RP3. A voltage corresponding to the voltage control signal code CTRL_Vol[0:3] provided from the control circuit 330 may be applied to the gate of each of the transistors MP0 to MP3.

[0093] The low voltage generating circuit 362c may output a low read pass voltage Vread_L to a connection node between the first resistor R and the plurality of resistors RP0 to RP3. The first resistor R and the plurality of resistors RP0 to RP3 may have the same resistance value. According to an embodiment, the first resistor R and the plurality of resistors RP0 to RP3 may have different resistance values.

[0094] In the initialization information read operation, the low voltage generation circuit 362 c may generate a low read pass voltage Vread_L as a voltage generated by dividing the source voltage VDD through the resistors RP0 to RP3 short-circuited based on the voltage control signal code CTRL_Vol[0:3].

[0095] Fig.13 It shows Figure 3 0 is a flow chart of an embodiment of a method for reading initialization information of a memory device 220 shown in FIG.

[0096] refer to Fig.13 In operation S1310, the nonvolatile memory device ( Figure 3 The nonvolatile memory device 220 may detect power-on. The nonvolatile memory device 220 may generate a voltage control signal CTRL_Vol based on power-on.

[0097] In operation S1320, in response to the voltage control signal CTRL_Vol, the nonvolatile memory device 220 may divide the source voltage VDD to generate a low read pass voltage Vread_L to be provided to the unselected word line in the initialization information read operation. The low read pass voltage Vread_L may be set to at least one voltage between the ground voltage VSS and the source voltage VDD. In response to the voltage control signal CTRL_Vol, the nonvolatile memory device 220 may allow the source voltage VDD not to be pumped during the initialization information read operation.

[0098] In operation S1330, the nonvolatile memory device 220 may provide a low read pass voltage Vread_L to unselected word lines and may provide a read voltage Vrd to a selected word line to read initialization information stored in memory cells of the first memory storage block BLK1. The nonvolatile memory device 220 may set the read initialization information in a setting register.

[0099] Fig.14 It shows that based on Fig.13 FIG. 1 is a table of examples of word line voltages applied during an initialization information read operation. Fig.14 The expression shows that by comparing the above Figure 5 The exemplary initialization information reading operation of the non-volatile memory device performed is similar to the above-mentioned Figure 6 The results obtained from an example initialization information read operation of the non-volatile memory device.

[0100] refer to Fig.14 The table and Figure 4 In a conventional initialization information reading method, a high read pass voltage Vread_H may be applied to the unselected first to third word lines WL1 to WL3 and the sixth to eighth word lines WL6 to WL8. The high read pass voltage Vread_H may be a voltage generated by pumping the source voltage VDD. The read voltage Vrd may be applied to the selected fourth word line WL4 and the fifth word line WL5 according to a predetermined sequence. The read voltage Vrd may be a voltage for determining a programming state of the first to eighth memory cells MC1 to MC8. The first to eighth memory cells MC1 to MC8 storing the initialization information may be single-level cells, and therefore, as Figure 5 As shown, it may have one of an erase state E and a program state P. Therefore, a voltage of 0V between the distribution based on the erase state E and the distribution based on the program state P may be set as a read voltage Vrd applied to the selected fourth and fifth word lines WL4 and WL5 .

[0101] In contrast to the above example, in the initialization information reading method disclosed herein, a low read pass voltage Vread_L may be applied to the unselected first to third word lines WL1 to WL3 and the sixth to eighth word lines WL6 to WL8. The low read pass voltage Vread_L may be a voltage generated by dividing the source voltage VDD, and Figure 6 , Fig. 9 and Fig.10 As shown, it can be set to one of the first read pass voltage Vread_L0 to the fifth read pass voltage Vread_L4.

[0102] Fig.15 It shows that when using Figure 3 FIG. 1 is a diagram of a consumption current pattern when an initialization information read operation is performed according to an embodiment of a nonvolatile memory device shown in FIG.

[0103] refer to Fig.15 , in the nonvolatile memory device 220 (see Figure 3 ), a consumption current pattern 1510 is shown when a low read pass voltage Vread_L, which is a voltage generated by dividing a source voltage VDD, is applied to an unselected word line. In addition, a consumption current pattern 1520 is shown when a high read pass voltage Vread_H generated by pumping the source voltage VDD is applied to the unselected word line. A consumption current peak 1522 caused by a pumping operation to generate the high read pass voltage Vread_H can be observed in the consumption current pattern 1520.

[0104] Compared with the consumption current pattern 1520 when the high read pass voltage Vread_H generated in the case of high pumping voltage is applied, it can be seen that the consumption current is significantly reduced in the consumption current pattern 1510 when the low read pass voltage Vread_L generated by dividing the source voltage VDD is applied to the unselected word line. In addition, since the high voltage pumping operation is not performed, the consumption current peak is not shown in the consumption current pattern 1510.

[0105] Therefore, when the SSD uses the nonvolatile memory device 220 that applies the low read pass voltage Vread_L generated by dividing the source voltage VDD to the unselected word line in the initialization information read operation, the consumption current can be easily reduced. In addition, in the large-capacity SSD, although the number of nonvolatile memory devices 220 increases, the consumption current peak may not occur in the initialization information read operation, and therefore, the large-capacity SSD can stably perform the initialization operation.

[0106] Fig.16is a block diagram illustrating a server system 1600 to which a storage device including an embodiment of a nonvolatile memory device is applied.

[0107] refer to Fig.16 , the server system 1600 may include a plurality of servers 110_1 to 110_N. The plurality of servers 110_1 to 110_N may be connected to the manager 1610. Each of the plurality of servers 110_1 to 110_N may be connected to the manager 1610. Figure 1 The servers 110 described are the same or similar.

[0108] A plurality of servers 110_1 to 110_N may each include a plurality of large-capacity SSDs, and the large-capacity SSDs may include a plurality of non-volatile memory devices. The non-volatile memory device may store initialization information in a memory cell of a first memory storage block including a single-level cell among a plurality of memory storage blocks, and may store user data in other memory storage blocks. When power-on is detected at boot time, the non-volatile memory device may divide the source voltage to generate a low read pass voltage to be provided to an unselected word line in an initialization information read operation. The low read pass voltage may be set to at least one voltage between a ground voltage and a source voltage. The non-volatile memory device may allow the source voltage VDD not to be pumped in an initialization information read operation based on power-on. In an initialization information read operation, the non-volatile memory device may select a first memory storage block, provide a low read pass voltage to an unselected word line, and provide a read voltage to a selected word line, thereby reading the initialization information stored in the memory cell of the first memory storage block. The non-volatile memory device may set the read initialization information in a setting register.

[0109] Fig.17 is a block diagram illustrating a storage cluster 1700 to which a storage device including an embodiment of a non-volatile memory device is applied.

[0110] refer to Fig.17 In the era of big data and artificial intelligence (AI), the storage cluster 1700 has attracted attention as a high-performance computing infrastructure for quickly computing massive amounts of data. The storage cluster 1700 can configure a parallel computing environment through a large-scale cluster to maximize computing performance. The storage cluster 1700 can provide a network-attached storage device or a storage area network based on the number of storage memories and the flexibility and reconfigurable arrangement of physical components.

[0111] The storage cluster 1700 may include a data center 1705 implemented using a plurality of server systems 1600_1 to 1600_N. Each of the plurality of server systems 1600_1 to 1600_N may be connected to Fig.16The server system 1600 shown in FIG. 1 is the same as or similar to the server system 1600 shown in FIG.

[0112] The plurality of server systems 1600_1 to 1600_N may communicate with the respective storage nodes 1720_1 to 1720_M via a network 1710 such as a computer network (e.g., a LAN or WAN) or the Internet. According to some embodiments, the storage nodes 1720_1 to 1720_M may not be arranged sequentially or may not be adjacent to each other. For example, the storage nodes 1720_1 to 1720_M may be one of a client computer, a server, a remote data center, and a storage system.

[0113] One server system among the plurality of server systems 1600_1 to 1600_N that receives a request from each of the storage nodes 1720_1 to 1720_M may include a plurality of large-capacity SSDs, and the large-capacity SSD may include a plurality of non-volatile memory devices. The non-volatile memory device may store initialization information in a memory cell of a first memory storage block including a single-level cell among a plurality of memory storage blocks, and may store user data in other memory storage blocks. When power-on is detected at boot time, the non-volatile memory device may divide the source voltage to generate a low read pass voltage to be provided to an unselected word line in an initialization information read operation. The low read pass voltage may be set to at least one voltage between a ground voltage and a source voltage. The non-volatile memory device may allow the source voltage VDD not to be pumped in an initialization information read operation based on power-on. In the initialization information read operation, the nonvolatile memory device can select a first memory storage block, provide a low read pass voltage to an unselected word line, and provide a read voltage to a selected word line, thereby reading the initialization information stored in the memory cell of the first memory storage block. The nonvolatile memory device can set the read initialization information in a setting register.

[0114] Fig.18 is a block diagram illustrating a system 1800 including a nonvolatile memory device according to an embodiment.

[0115] refer to Fig.18 , the system 1800 may include a processing unit 1810, a volatile memory unit 1820, a resistive memory unit 1830, and a mass storage unit 1840. In addition, the system 1800 may be a mobile device, a PC, a server computer, a programmable appliance, or a general or special purpose computer system such as a main frame computer.

[0116] In order to achieve independence, the functional units described in this embodiment can be classified into module storage blocks. For example, the module storage block can be implemented as a computing very large scale integration (VLSI) circuit or a hardware circuit including a semiconductor (e.g., a gate array, a logic chip, a transistor, or a discrete component). The module storage block can be implemented as a programmable hardware device, such as a programmable gate array, a programmable gate logic, or a programmable gate device. In addition, the module storage block can be implemented as software including executable code, an object, a process, or a function.

[0117] The processing unit 1810 may execute an OS and a plurality of software systems, and may perform calculations or tasks. The processing unit 1810 may be a microprocessor or a CPU.

[0118] The volatile memory unit 1820, cache memory, or working memory of the system 1800 may represent a medium for temporarily or short-term storage of data. The volatile memory unit 1820 may include one or more memory devices, and may include, for example, a DRAM.

[0119] The resistance memory unit 1830 may be used to act as a cache for the large-capacity storage unit 1840. The resistance memory unit 1830 may store some data of frequently accessed applications or OS. The resistance memory unit 1830 may include one or more memory devices, and may include DRAM, for example.

[0120] The mass storage unit 1840 may be implemented as an SSD, a PCIe memory module storage block, or NVMe. Optionally, one or more layers of the mass storage unit 1840 may be implemented with one or more network accessible devices and / or services (e.g., clients, servers, server PDAs, server clusters, application servers, or message servers) accessed based on NVMe-oF and / or RDMA. The mass storage unit 1840 may represent a storage medium that stores user data in the system 1800 for a long time. The mass storage unit 1840 may store applications, program data, etc.

[0121] The large-capacity storage unit 1840 may include a plurality of large-capacity SSDs, and the large-capacity SSD may include a plurality of non-volatile memory devices. The non-volatile memory device may store initialization information in a memory cell of a first memory storage block including a single-level cell among a plurality of memory storage blocks, and may store user data in other memory storage blocks. When power-on is detected at boot time, the non-volatile memory device may divide the source voltage to generate a low read pass voltage to be provided to an unselected word line in an initialization information read operation. The low read pass voltage may be set to at least one voltage between a ground voltage and a source voltage. The non-volatile memory device may allow the source voltage VDD not to be pumped in an initialization information read operation based on power-on. In an initialization information read operation, the non-volatile memory device may select a first memory storage block, provide a low read pass voltage to an unselected word line, and provide a read voltage to a selected word line, thereby reading the initialization information stored in the memory cell of the first memory storage block. The non-volatile memory device may set the read initialization information in a setting register.

[0122] Fig.19 is a block diagram showing an example in which an embodiment of a nonvolatile memory device 1900 is applied to a memory card system.

[0123] refer to Fig.19 , the memory card system 1900 may include a host 1910 and a memory card 1920. The host 1910 may include a host controller 1911 and a host connector 1912. The memory card 1920 may include a card connector 1921, a card controller 1922, and a memory device 1923.

[0124] The host 1910 may write data into the memory card 1920 or read data stored in the memory card 1920. The host controller 1911 may transmit a command CMD, a clock signal CLK, and data DATA to the memory card 1920 through the host connector 1912.

[0125] In response to the command CMD received through the card connector 1921, the card controller 1922 may store data in the memory device 1923 in synchronization with the clock signal generated by the clock generator included in the card controller 1922. The memory device 1923 may store data sent from the host 1910. The memory device 1923 may include a plurality of large-capacity SSDs, and the large-capacity SSD may include a plurality of non-volatile memory devices. The non-volatile memory device may store initialization information in a memory cell of a first memory storage block including a single-level cell among a plurality of memory storage blocks, and may store user data in other memory storage blocks. When power-on is detected at boot time, the non-volatile memory device may divide the source voltage to generate a low read pass voltage to be provided to an unselected word line in an initialization information read operation. The low read pass voltage may be set to at least one voltage between a ground voltage and a source voltage. The non-volatile memory device may allow the source voltage VDD not to be pumped in an initialization information read operation based on power-on. In the initialization information read operation, the nonvolatile memory device can select a first memory storage block, provide a low read pass voltage to an unselected word line, and provide a read voltage to a selected word line, thereby reading the initialization information stored in the memory cell of the first memory storage block. The nonvolatile memory device can set the read initialization information in a setting register.

[0126] The memory card 1920 may be implemented with a compact flash card (CFC), a micro drive, a smart media card (SMC), a multimedia card (MMC), a secure digital card (SDC), a memory stick, a universal serial bus (USB) flash drive, etc.

[0127] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A non-volatile memory device, comprising: a memory cell array configured to store initialization information for the nonvolatile memory device in memory cells connected to a plurality of word lines; a control circuit configured to control the application of a first read voltage to a selected word line and control the application of a second read voltage to an unselected word line in an initialization information reading operation of reading the initialization information; as well as a voltage generator configured to reduce a source voltage to generate the second read voltage in response to a voltage control signal provided from the control circuit in the initialization information read operation, In a non-initialization information reading operation, the second reading voltage is greater than the source voltage, and in the initialization information reading operation, the second reading voltage is less than or equal to the source voltage.

2. The nonvolatile memory device according to claim 1, wherein: The memory cell is a single-level cell storing 1-bit data.

3. The nonvolatile memory device according to claim 2, wherein: The first read voltage is set to have a voltage level for distinguishing an erase state and a program state of the single level cell.

4. The nonvolatile memory device according to claim 3, wherein: The first read voltage is set to a ground voltage.

5. The nonvolatile memory device according to claim 1, wherein: The control circuit is configured to detect power-up to generate the voltage control signal.

6. The nonvolatile memory device according to claim 1, wherein: The voltage generator is configured to allow the source voltage not to be pumped during the initialization information reading operation in response to the voltage control signal.

7. The nonvolatile memory device according to claim 1, wherein: The voltage generator comprises: a voltage divider including a plurality of resistors connected in series between the source voltage and a ground voltage, the voltage divider being configured to generate a divided voltage across both ends of each of the plurality of resistors; and A selector is configured to output one of the divided voltages as the second read voltage in response to the voltage control signal.

8. The nonvolatile memory device according to claim 1, wherein: The voltage generator comprises: a first resistor connected between the source voltage and a node outputting the second read voltage; a plurality of resistors connected in series between the node and a ground voltage; and A plurality of transistors are connected across the plurality of resistors, and the voltage control signal is provided as bit information to a gate of each of the plurality of transistors.

9. The nonvolatile memory device according to claim 1, wherein: The voltage generator comprises: a first resistor connected between the source voltage and a node outputting the second read voltage; a plurality of resistors connected in parallel between the node and a ground voltage; and A plurality of transistors are connected across the plurality of resistors, and the voltage control signal is provided as bit information to a gate of each of the plurality of transistors.

10. The nonvolatile memory device according to claim 1, further comprising: A register is set to store the initialization information read by the initialization information reading operation.

11. The nonvolatile memory device according to claim 1, wherein: The initialization information includes protection information related to prohibiting or allowing a programming operation or an erasing operation performed on the memory cell array, trimming data for trimming an operating voltage level in a programming operation mode, a read operation mode, or an erase operation mode of the nonvolatile memory device, column repair information for repairing a failed bit line of the nonvolatile memory device, or bad storage block information identifying bad memory cells of the nonvolatile memory device.

12. A method for reading a non-volatile memory device, the method comprising: Detect power on; In response to the detected power-up, reading initialization information for the non-volatile memory device stored in a memory cell of the non-volatile memory device; as well as In the initialization information reading operation of reading the initialization information, generating a first read voltage to be provided to a selected word line among a plurality of word lines connected to the memory cell, and generating a second read voltage to be supplied to unselected word lines among the plurality of word lines connected to the memory cell, wherein the second read voltage is generated by reducing the source voltage, and In a non-initialization information reading operation, the second reading voltage is greater than the source voltage, and in the initialization information reading operation, the second reading voltage is less than or equal to the source voltage.

13. The reading method according to claim 12, further comprising: In response to a voltage control signal associated with the power-up, the source voltage is allowed to not be pumped during the initialization information reading operation.

14. The reading method according to claim 12, wherein: Generating the second read voltage includes: dividing the source voltage in response to a voltage control signal to generate the second read voltage.

15. The reading method according to claim 12, wherein: The memory cell is a single-level cell storing 1-bit data.

16. The reading method according to claim 15, wherein: The first read voltage is set to have a voltage level for distinguishing an erase state and a program state of the single level cell.

17. The reading method according to claim 16, wherein: The first read voltage is set to a ground voltage.

18. The reading method according to claim 17, wherein: The second read voltage is set to have at least one voltage level between a ground voltage and the source voltage.

19. The reading method according to claim 12, further comprising: Set the initialization information read in the setup register.

20. The reading method according to claim 12, wherein: The initialization information includes protection information related to prohibiting or allowing a programming operation or an erasing operation on the nonvolatile memory device, trimming data for trimming an operating voltage level in a programming operation mode, a reading operation mode, or an erasing operation mode of the nonvolatile memory device, column repair information for repairing a failed bit line of the nonvolatile memory device, or bad storage block information identifying bad memory cells of the nonvolatile memory device.

21. A method comprising: The non-volatile memory device detects a power-on state for the non-volatile memory device; as well as In response to detecting the power-on state, the nonvolatile memory device reads initialization information for the nonvolatile memory device stored in a first memory cell of a memory cell array of the nonvolatile memory device, and sets the initialization information for the nonvolatile memory device in a setting register of the nonvolatile memory device, Wherein, reading the initialization information for the non-volatile memory device stored in the first memory cell of the memory cell array of the non-volatile memory device comprises: applying a first read voltage having a first read voltage level to a selected word line connected to the first memory cell, the first read voltage level being used to distinguish between an erase state and a programmed state of the first memory cell; and When the first read voltage is applied to the selected word line, a second read voltage having a second read voltage level is applied to unselected word lines not connected to the first memory cell, the second read voltage level being lower than a voltage level of a programmed state of the first memory cell, and The second read voltage is generated by a voltage generator that receives a source voltage. In a non-initialization information reading operation, the second read voltage is greater than the source voltage. In an initialization information reading operation that reads the initialization information, the second read voltage is less than or equal to the source voltage.

22. The method according to claim 21, further comprising: The non-volatile memory device performs the following operations: receiving a source voltage that is less than a voltage level of a programmed state of the first memory cell; as well as The source voltage is applied to a low voltage generating circuit to generate the second read voltage which is lower than a voltage level of a programmed state of the first memory cell.

23. The method according to claim 22, wherein: The second read voltage level is between a ground voltage level and a level of the source voltage.

24. The method according to claim 21, wherein: The first read voltage level is a ground voltage level.

25. The method according to claim 21, wherein: The initialization information includes protection information related to prohibiting or allowing a programming operation or an erasing operation on the nonvolatile memory device, trimming data for trimming an operating voltage level in a programming operation mode, a reading operation mode, or an erasing operation mode of the nonvolatile memory device, column repair information for repairing a failed bit line of the nonvolatile memory device, or bad storage block information identifying bad memory cells of the nonvolatile memory device.

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