Programmable Power Generator

Abstract

A device is provided, comprising: a first group of devices, which are digitally controlled by a first feedback loop including a first comparator; and a second group of devices, which are controlled by an analog circuit, which is part of a second feedback loop including an amplifier, wherein the first group of devices are coupled in parallel to the second group of devices.

Description

[0001] Priority declaration

[0002] This application claims priority to U.S. Patent Application Serial No. 15 / 479,217, filed on April 4, 2017, and entitled “PROGRAMMABLE SUPPLY GENERATOR,” which is hereby incorporated by reference in its entirety.

[0003] background

[0004] Today, integrated circuit (IC) designs contain a large number of power domains and require many low dropout circuits (LDOs), where the required specifications are varied. For example, some applications in the Internet of Things (IoT) space require very small quiescent current for their LDOs, and performance parameters such as power supply rejection ratio (PSRR) are not very important. On the other hand, applications like RF (radio frequency) and high-speed input and output (IO) transceivers may require high PSRR LDO designs. Therefore, several LDO designs are required to meet those targets resulting in huge design efforts. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The embodiments of the present disclosure will be more fully understood from the detailed description given below and from the drawings of various embodiments of the present disclosure, which however should not be used to limit the present disclosure to the specific embodiments but are only for explanation and understanding.

[0006] Figure 1 A high-level architecture of a modular low dropout (LDO) circuit according to some embodiments of the present disclosure is shown.

[0007] Figure 2 Some embodiments of the present disclosure are shown Figure 1 Schematic diagram of a modular LDO.

[0008] Figure 3 Some embodiments of the present disclosure are shown Figure 1 Schematic diagram of a modular LDO.

[0009] Figure 4 A graph illustrating the operation of a modular LDO according to some embodiments of the present disclosure is shown.

[0010] Figure 5 A graph illustrating step loading and unloading behavior of a modular LDO according to some embodiments of the present disclosure is shown.

[0011] Figure 6 A graph illustrating the power supply rejection ratio (PSRR) of a modular LDO is shown according to some embodiments of the present disclosure.

[0012] Figure 7 A schematic diagram of an asynchronous LDO circuit with a clamp function and an unclamp function according to some embodiments of the present disclosure is shown.

[0013] Fig. 8A -B shows graphs respectively illustrating clamping action and releasing action of an asynchronous LDO circuit according to some embodiments of the present disclosure.

[0014] Fig. 9 A schematic diagram of an asynchronous LDO circuit with modular clamping and unclamping functions according to some embodiments of the present disclosure is shown.

[0015] Fig.10 Some embodiments of the present disclosure are shown Fig. 9 A graph of the operation of an asynchronous LDO.

[0016] Fig.11 A smart device or computer system or SoC (system on chip) with modular and / or asynchronous LDO circuits according to some embodiments is shown. DETAILED DESCRIPTION

[0017] Various embodiments describe modular and configurable LDO circuits (hereinafter “LDO”) to provide desired specifications of low quiescent current or high power supply rejection ratio (PSRR). A digital LDO (D-LDO) circuit or module (hereinafter “D-LDO”) is inherently modular because it uses multiple power p-type switches and decides how many power p-type switches to turn on for a given load. Various embodiments use this inherent modularity in the D-LDO to provide programmable PSRR. In some embodiments, one or more analog LDO circuits or modules (hereinafter “analog LDO”) are used that can provide a unit load current equal to or slightly greater than the resolution of the unit p-type switch of the D-LDO.

[0018] Herein, the term "analog LDO" generally refers to a circuit including an LDO architecture having at least one transistor that can be controlled by a non-rail-to-rail signal (e.g., a signal having a voltage level between a power supply level and a ground level). The non-rail-to-rail signal here is also referred to as an analog signal. Herein, the term "analog signal" generally refers to a continuous signal for which the time-varying characteristics of the signal are a representation of some other time-varying variable. For example, the analog signal is a bias signal having a continuous voltage level between a power supply level and a ground level.

[0019] Herein, the term "digital LDO" generally refers to a circuit that includes an LDO architecture having at least one transistor that can be controlled by a non-rail-to-rail signal (e.g., a signal having a voltage level between a power supply level and a ground level). This rail-to-rail signal is also referred to as a digital signal. Herein, the term "digital signal" generally refers to a sequence of discrete signals that can have two possible values ​​- a logic high value equal to the power supply rail level and a logic low value equal to the ground rail level. Digital signals typically switch rail-to-rail (e.g., from the power supply level to the ground level).

[0020] In some embodiments, when the load application requires a higher or lower PSRR, the digital power p-type switch is replaced with a unit analog LDO as needed to provide the lowest current for a given PSRR requirement. In some embodiments, a single or "N" analog LDO can be enabled based on the need for PSRR, where "N" is an integer greater than or equal to 2. For example, for a higher PSRR, more analog LDOs of block 102 can be enabled to operate with D-LDO 101. The architecture of some embodiments not only provides modularity with a single unit analog LDO design, but also uses the load to scale the quiescent current consumption for obtaining the best current consumption at different load currents. The architecture of some embodiments uses a digital controller to program the number of unit analog LDOs (or a group of analog LDOs) to give the best current consumption for a given PSRR requirement. Therefore, the LDO architecture of various embodiments provides programmability to PSRR with a modular architecture to easily adapt to the design of a low quiescent current LDO or a high PSRR LDO with the same design. The term "set" herein generally refers to one or more things with common properties. For example, a group of analog LDOs includes one or more analog LDOs.

[0021] Conventional D-LDOs usually adopt a synchronous control scheme, in which a clock signal is used to achieve operation. In such D-LDOs, the voltage tracking speed can be increased by increasing the operating frequency of the clock signal. However, the increase in clock frequency leads to increased power consumption. There is a trade-off between voltage tracking speed and current efficiency in synchronous D-LDO regulator design.

[0022] Various embodiments also describe an asynchronous D-LDO that avoids large voltage droops caused by large load step changes. The asynchronous D-LDO of some embodiments allows voltage droop limitation when the load is increased or unloaded. In some embodiments, the asynchronous D-LDO uses two (e.g., high and low) reference voltage thresholds to determine clamping (e.g., turning on all power switches) and releasing (e.g., turning off all power switches) operations. In some embodiments, when the output voltage (e.g., the voltage provided to the load) becomes lower than the low reference voltage, the clamping operation is performed. In some embodiments, when the output voltage becomes higher than the high reference voltage, the release function is adopted. In some embodiments, when the output voltage is between the low reference voltage and the high reference voltage, the shift register value determines the strength of the power device (e.g., a p-type device, an n-type device, or a combination thereof). In some embodiments, the shift register value is determined by the clamp signal and the release signal, respectively. For example, the shift register value increases with the assertion of the clamp signal and decreases with the assertion of the release signal.

[0023] In a conventional synchronous or asynchronous D-LDO design, the shift register allows only one power switch to be turned on or off during regulation. In this case, the speed of the loop determines the maximum voltage drop. In some embodiments, the clamping operation turns on all power switches, while the release operation turns off all power switches in the event of a load step change. In this example, in a large step load / unload change, the power devices are turned on / off immediately, so that the maximum voltage drop or voltage overshoot can be reduced or minimized. In some embodiments, the D-LDO is a clock-free design, thus allowing further reduction in power consumption than a conventional synchronous D-LDO. Other technical effects will be apparent from the various figures and embodiments.

[0024] In the following description, many details are discussed to provide a more thorough explanation of the embodiments of the present disclosure. However, it will be apparent to those skilled in the art that the embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the embodiments of the present disclosure.

[0025] Note that in the corresponding figures of the embodiments, lines are used to represent signals. Some lines may be thicker to indicate more component signal paths, and / or have arrows at one or more ends to indicate the main information flow direction. This indication is not intended to be restrictive. Instead, such lines are used in conjunction with one or more exemplary embodiments to help more easily understand circuits or logic units. As indicated by design needs or preferences, any represented signal may actually include one or more signals that can propagate in either direction, and may be implemented using any suitable type of signal scheme.

[0026] Throughout the specification, and in the claims, the term "connected" refers to a direct connection (e.g., electrical, mechanical, or magnetic connection) between connected objects without any intervening devices. The term "coupled" refers to a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between connected objects, or an indirect connection through one or more passive or active intervening devices. The term "circuit" or "module" may refer to one or more passive and / or active components arranged to cooperate with each other to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meaning of "a", "an", and "the" includes plural references. The meaning of "in" includes "in" and "on".

[0027] The terms "substantially", "close", "approximately", "near", and "about" generally refer to within + / -10% of a target value (unless otherwise specified). Unless otherwise specified, the use of ordinal adjectives "first", "second", "third", etc. to describe common objects merely indicates that different instances of the same object are mentioned, and is not intended to imply that the objects so described must be in a given sequence either temporally, spatially, in ranking, or in any other manner.

[0028] For purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For purposes of this disclosure, the phrases "A, B, and / or C" mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0029] For the purpose of the embodiment, the transistors in the various circuits and logic blocks described herein are metal oxide semiconductor (MOS) transistors and their derivatives, wherein the MOS transistors include drains, sources, gates and boost terminals. The transistors and / or MOS transistor derivatives also include tri-gate and fin FET (FinFET) transistors, gate-all-around cylindrical transistors (GateAll Around Cylindrical Transistors), tunnel FETs (TFETs), square wires, or rectangular ribbon transistors, ferroelectric FETs (FeFETs) or other devices that implement transistor functions similar to carbon nanotubes or spintronics devices. The symmetrical source and drain terminals of MOSFETs are identical terminals and are used interchangeably here. On the other hand, TFET devices have asymmetric source and drain terminals. It will be appreciated by those skilled in the art that other transistors (e.g., bipolar junction transistors—BJT PNP / NPN, BiCMOS, CMOS, eFETs, etc.) may be used without departing from the scope of the present disclosure. The term “MN” denotes an n-type transistor (eg, NMOS, NPN BJT, etc.), and the term “MP” indicates a p-type transistor (eg, PMOS, PNP BJT, etc.).

[0030] Figure 1 A high-level architecture of a modular LDO 100 according to some embodiments of the present disclosure is shown. In some embodiments, modular LDO 100 includes D-LDO 101, analog LDO 102, control logic or circuit 103, PSSR programmability logic or circuit 104, a first power node 105 (e.g., a non-gated power node), a second power node 106 (e.g., a gated power node), (multiple) D-LDO control signal lines 107, (multiple) control logic or circuit control signal lines 108, (multiple) reference voltages 109, (multiple) analog LDO control signal lines 110, reference voltages 111, load capacitors 112 (which may be located inside or outside the modular LDO boundary), and loads 113 (e.g., a processing core, logic, or any power domain).

[0031] In some embodiments, D-LDO 101 includes p-type power transistors coupled between first power supply node 105 and second power supply node 106. In some embodiments, these p-type power transistors are digitally controlled by a digital controller that compares the voltage (or the derivative of the voltage) on second power supply node 106 with one or more reference voltages 109 and turns on / off the power transistors (e.g., p-type transistors, n-type transistors, or a combination thereof) accordingly. Here, the term "digital control" generally refers to controlling a device by a signal of logic high (e.g., a line carrying a signal is charged to a power supply level) or logic low (e.g., a line or node carrying a signal is discharged to a ground level) to completely turn off or turn on the device. In some embodiments, D-LDO 101 includes one or more comparators that compare the voltage (or the derivative of the voltage) on second power supply node 106 with one or more reference voltages 109. In some embodiments, a shift register receives the output of the comparator, and the shift register increments or decrements its output according to the comparison result.

[0032] In some embodiments, the analog LDO 102 includes one or more p-type devices coupled between a first power supply node 105 and a second power supply node 106 and can be controlled by an analog signal. One or more p-type devices can also be replaced by n-type devices or a combination of p-type and n-type devices. Here, the term "analog signal" generally refers to a non-rail-to-rail signal. For example, the analog signal can be a voltage between the voltage level of the power supply at node 105 and the voltage level of ground. In some embodiments, the analog LDO 102 includes a comparator or amplifier that compares the voltage on node 106 (or the derivative of the voltage) with a voltage reference 111. Therefore, the current through the p-type device of the analog LDO 102 is adjusted, which in turn adjusts the voltage on node 106. In some embodiments, the analog LDO 102 is always turned on. Here, the term "always turned on" device generally refers to a device that is active or operated under normal conditions using the power supply level.

[0033] In some embodiments, analog LDO 102 includes multiple analog LDOs, where at least one of the LDOs is always on, and the other LDOs can be turned on / off (e.g., enabled) by a control signal on line 110. Here, the labels of nodes and signals are used interchangeably. For example, 110 can refer to node 110 or a signal on a node or line 110 depending on the context of the sentence. In some embodiments, all analog LDOs in block 102 can be enabled or disabled by control signal 110.

[0034] In some embodiments, when the load 113 requires a higher or lower PSRR, the digital power switch of the D-LDO 101 is replaced and / or supplemented with an analog LDO (e.g., the LDO of block 102) as necessary to provide the lowest current for a given PSRR requirement. In some embodiments, a single or "N" analog LDOs in block 102 may be enabled based on the need for PSRR, where "N" is an integer greater than or equal to 2.

[0035] For example, for higher PSRR, more analog LDOs of block 102 can be enabled to operate with D-LDO 101. The architecture of some embodiments not only provides modularity with a single unit analog LDO design, but also uses the load to scale the quiescent current consumption for obtaining the best current consumption at different load currents. The architecture of some embodiments uses a digital controller (e.g., D-LDO 101 and / or part of control circuit 103) to program the number of unit analog LDOs of block 102 to give the best current consumption for a given PSRR requirement. Therefore, the LDO architecture of various embodiments provides programmability to PSRR with a modular architecture to easily adapt to the design of a low quiescent current LDO or a high PSRR LDO with the same design. In some embodiments, the programmability of PSRR is provided by logic 104, which can determine the number of analog LDOs of block 102 to be enabled.

[0036] Figure 2 Some embodiments of the present disclosure are shown Figure 1 Schematic diagram 200 of a modular LDO. It should be noted that Figure 2 Those elements having the same reference numbers (or names) as elements of any other figure may operate or function in any manner similar to that described, but are not limited to such.

[0037] In some embodiments, the D-LDO 101 includes comparators 201a and 201b, a shift register 201e, and a power device 201 g1-N, where "N" is an integer. Any suitable comparator design can be used to implement comparators 201a and 201b. In some embodiments, voltage reference 109 represents two reference voltages 109a and 109b, which are provided to the non-inverting terminals of comparators 201a and 201b, respectively. For example, reference voltage 109a is Vef+offset, while reference voltage 109b is Vref-offset, where "offset" can be a programmable or predetermined voltage level (e.g., 35mV). In some embodiments, shift register 201e can decrement or increment its output value at node 201f / 108 based on outputs 201c and 201d, respectively. For example, when the output on node 201c is high and the output on node 201d is low, then shift register 201e subtracts 1 from the output value on node 201f / 108. In some embodiments, this value is an N-bit value and is used to turn on / off power device 201 g1-N In some embodiments, one or more bits of the output code 201 f / 108 may be used to enable one or more analog LDOs 102 .

[0038] Although the embodiment shows one p-type transistor MPd per power device, any number of transistors can be packaged per power device. For example, transistors can be coupled in parallel in each power device. In some embodiments, transistors in each power device are stacked or cascaded. For example, when the power supply on node 105 is higher than the allowable power supply range of the processing node, in order to protect the transistors in the power device, the transistors can be stacked between nodes 105 and 106. Various embodiments are not limited to p-type transistors of power devices. For example, in some embodiments, the power device includes an n-type device, a p-type device, or a combination thereof.

[0039] In some embodiments, the output codes 201f / 108 are masked by logic 103 according to control signals 205a / b from PSSR logic 104. For example, when a higher PSSR is desired, PSSR logic 104 may cause selection line 205b to enable one or more analog LDOs. In some embodiments, analog LDO block 102 includes one or more analog LDOs 202 1-N , where “N” is an integer (which may be the same as or different from the number “N” of p-type power devices of D-LDO 101). In some embodiments, analog LDO 2021 includes transistors coupled to nodes 105 and 106 and a comparator or operational amplifier 202. 1a In some embodiments, the comparator or operational amplifier 202 1a The driving strength of transistor MPa is adjusted so that the voltage on node 106 (or its derivative) is the same as reference voltage 111 .

[0040] In some embodiments, control logic 103 includes multiplexers 203a and 203b, which receive inputs 201f / 108 (e.g., the output of shift register 201e) and receive predetermined or programmable inputs 203d and 203c, respectively. In some embodiments, multiplexers 203a and 203b can be controlled by selection signals 205b and 205a, respectively. According to some embodiments, the logic values ​​of selection signals 205b and 205a are determined by logic 104 based on the desired PSSR. In some embodiments, a certain number (or all) of power devices 201 can be disconnected. g1-N , and more analog LDOs can be turned on by multiplexers 203b and 202a, respectively, to increase PSSR. In some embodiments, output 203e (same as 107) of multiplexer 203b is used to control power device 201 g1-N In some embodiments, output 203f (same as 110) of multiplexer 203a is used to control (eg, enable or disable) analog LDO 202 1-N .

[0041] Figure 3 Some embodiments of the present disclosure are shown Figure 1 Schematic diagram 300 of a modular LDO. It should be noted that Figure 3 Those elements having the same reference numbers (or names) as elements of any other figure may operate or function in any manner similar to that described, but are not limited to such.

[0042] In some embodiments, the D-LDO 101 includes a clamping and / or releasing function provided by the control logic 103. Here, the term "clamping" or "releasing" generally refers to a function in which a feedback loop is overridden. For example, when the output voltage on the output power supply node is outside of a threshold level (e.g., above or below), a clamping or releasing condition occurs, in which the power transistor of the LDO can be forced to turn on or off regardless of the feedback loop dynamics of the LDO. In some embodiments, the control logic 103 includes NOR gates 303a and 303b, and an inverter 303c. In some embodiments, the output 201f / 108 of the shift register 201e is inverted by the inverter 303c. In some embodiments, the output of the inverter 303c is provided as an input to the NOR gate 303a, which also receives the output 201c of the comparator 201a as an input. Here, the logic level of the output 201c indicates a release action (e.g., whether the release action is enabled or disabled). In some embodiments, the output of NOR gate 303a is provided as an input to NOR gate 303b, which also receives output 201d of comparator 201b as an input. Here, the logic level of output 201d indicates a clamping action (e.g., whether the clamping action is enabled or disabled). In some embodiments, the output of NOR gate 303b is used to control power gate device 201 g1-N In some embodiments, the output 201f / 108 of the shift register 201e is also used to enable or disable the analog LDO 202 1-N In some embodiments, analog LDO 202 1-N In one example, when "N" associated with block 102 is 5, analog LDO 2021 is always on, and four analog LDOs 202 2-5 Can be operated to enable or disable.

[0043] In some embodiments, most of the current of the load 113 is provided by the D-LDO 101, and the remainder is provided by the analog LDO block 102. In some embodiments, during a load step change, the D-LDO 101 includes a clamping / releasing action that can turn on / off all power devices 201. g1-N The output voltage at the node 106 is fixed within a certain tolerance band. During this period, the shift register value 201f / 108 is incremented / decremented to make the power device 201 g1-N According to some embodiments, the analog LDO 102 provides the power device 201 with the correct amount. g1-N Any remaining load current not provided (e.g., because power device 201 g1-NThus, the analog LDO 102 eventually regulates the output voltage to the target reference voltage 111, eliminating the inherent triggering behavior of the D-LDO 101. Thus, in addition to all other benefits previously described, various embodiments also reduce the switching current caused by the gate charging and discharging of the power switch in the D-LDO 101 by adding the analog LDO 102 in parallel.

[0044] In some embodiments, when the output voltage (Vout) at the node 106 is between the high and low reference voltages 109a and 109b, respectively, the shift register 201e controls the power switch 201e. g1-N When Vout is lower than the low reference voltage, the clamp signal 201d turns on all power switches 201 g1-N And the count of shift register 201e is increased by 1. When Vout is higher than the high reference voltage, the release signal 201c turns off all power switches 201. g1-N And the count of the shift register 201e is reduced by 1.

[0045] Figure 4 A graph 400 illustrating the operation of the modular LDO 300 according to some embodiments of the present disclosure is shown. It is noted that, Figure 4 Those elements in the drawings having the same reference numbers (or names) as elements of any other figure can operate or function in any manner similar to that described, but are not limited thereto.

[0046] Here, the x-axis is time and the y-axis is the voltage of waveforms 109a, 109b, 201c, and 201d. The numbers on 201f / 108 represent the change in the shift register output value over time. The numbers on MPd represent the number of p-type power devices that are turned on in D-LDO 101. Graph 400 shows a timing diagram of a modular LDO 300 with a single normally-on analog LDO. In this example, each unit digital power switch 201 g1-N 1 mA can be provided, and the analog LDO cell module 102 (eg, 2021) can also provide 1 mA. The timing diagram illustrates a situation where the required load current is 4.5 mA, so a combination of analog and digital LDOs is required.

[0047] In this configuration, the idea is that the D-LDO 101 provides most of the current and the analog LDO 2011 provides the remainder of the current. During a load step change, the D-LDO 101 also includes a clamping / unclamping action that can turn on / off all the power p-type devices to fix the output voltage within a certain tolerance band. Here, the tolerance band is between 109a and 109b (e.g., + / -35mV). The time Δtc indicates the propagation delay of the comparator of the D-LDO 101. When Vout (Vout) (e.g., the voltage on node 106) is lower than Vref 109b, the signal on node 201c is asserted, indicating that the p-type device 201 g1-N Therefore, the voltage on node 106 starts to rise. When Vout (V output) (eg, the voltage on node 106) is lower than Vref 109b, the signal on node 201c is asserted, indicating that p-type device 201 g1-N Needs to be disconnected (eg, released).

[0048] In some embodiments, a digital machine (e.g., a finite state machine or some suitable controller) turns on the analog LDO 2011 so that the output at node 206 is stable and maintained within the voltage tolerance band. In this example, during the clamping / unclamping action, the shift register 201e value 201f / 108 is incremented / decremented to bring the number of power p-type devices to the correct amount, in this case 4. In this example, since the required load current is 4.5mA, the remaining 0.5mA is provided by the analog LDO 2011, ultimately regulating the output voltage to the target reference voltage, thereby eliminating the inherent triggering behavior of the digital LDO.

[0049] Figure 5 A graph 500 showing the step loading and unloading behavior of a modular LDO according to some embodiments of the present disclosure is shown. It should be noted that Figure 5 Those elements having the same reference numerals (or names) as elements of any other figure may operate or function in any manner similar to that described, but are not limited to such a manner. Here, the x-axis is time, the y-axis of sub-graph 501 is current, which represents the load current (i.e., Iload), the y-axis of sub-graph 502 is voltage, which represents the voltage on node 106 (i.e., Vout) for various LDO configurations, the y-axis of sub-graph 503 is the number of p-type devices of D-LDO 101 turned on (i.e., #MPOS_ON), ​​and the y-axis of sub-graph 504 is the number of analog LDOs 102 enabled (i.e., ALDO_ON).

[0050] Graph 500 shows a step loading and unloading simulation for 1, 2, 3, and 4 analog LDO use cases. In this example, by default, one analog LDO is always on. The switching or ripple on Vout is caused by the D-LDO operation after the load current changes from 1 mA to 10 mA. The various waveforms are superimposed on each other because different numbers of analog LDOs are turned on. The various configurations that produce these superimposed waveforms are: a) 2 analog LDOs, where every 6 ALDO_ON signals turn on the analog LDO, b) 3 analog LDOs, where every 4 ALDO_ON signals turn on the analog LDO, and c) 4 analog LDOs, where every 3 ALDO_ON signals turn on the analog LDO.

[0051] Figure 6 A graph 600 showing the power supply rejection ratio (PSRR) of the modular LDO 200 is shown according to some embodiments of the present disclosure. Here, the x-axis is frequency and the y-axis is PSRR in dB. As more analog LDOs are enabled, the PSRR decreases.

[0052] Table 1 shows Figure 1 Figure 2. Comparison of the ISO's modular LDO architecture with a traditional analog LDO. For the ISO comparison with the analog LDO, the following assumptions were made: maximum load current is 10mA, output capacitance is 200pF, and maximum voltage droop is 150mV.

[0053] Table 1

[0054]

[0055]

[0056]

[0057] Table 1 shows a modular LDO architecture of various embodiments with a single normally-on analog LDO that can reduce current by 4 times compared to an analog LDO given the same requirements, 1) various embodiments use low power to make the digital LDO asynchronous, and 2) remove the p-type device switching current by adding analog LDO 102.

[0058] Figure 7 FIG. 7 is a schematic diagram of an asynchronous LDO circuit 700 having a clamping function and an unclamping function according to some embodiments of the present disclosure. It should be noted that Figure 7 Those elements of the same reference numerals (or names) as those of any other figure may operate or function in any manner similar to that described, but are not limited to such a manner. In addition to removing the analog LDO block 102, Figure 7 Similar to Figure 3 In various embodiments, the p-type power device 201 g1-N The control is asynchronous (ie, independent of clock transitions).

[0059] In some embodiments, the asynchronous D-LDO 700 avoids large voltage droops caused by large load step changes. Some embodiments of the asynchronous D-LDO 700 allow for voltage drop limitation when the load is increased or decreased. In some embodiments, the asynchronous D-LDO 700 uses two (e.g., high and low) reference voltage thresholds 109a and 109b, respectively, to determine clamping (e.g., turning on all power switches) and releasing (e.g., turning off all power switches) operations. In some embodiments, when the output voltage on node 106 (e.g., the voltage provided to the load) becomes lower than the low reference voltage 109b, the clamping operation is taken. In some embodiments, when the output voltage becomes higher than the high reference voltage 109a, the releasing function is taken. In some embodiments, when the output voltage is between the low reference voltage and the high reference voltage, the shift register value 201f determines the p-type power device 201 g1-N In some embodiments, the shift register value is determined by the clamp and release signals 201c and 201d, respectively. For example, the shift register value 201f increases with the assertion of the clamp signal 201c and decreases with the assertion of the release signal 201d.

[0060] In conventional synchronous or asynchronous D-LDO designs, the shift register allows only one power switch to be turned on or off during regulation. In this case, the speed of the loop determines the maximum voltage droop. In some embodiments, the clamping operation turns on all power switches 201. g1-N , while the release operation disconnects all power switches 201 in the case of load step changes g1-N In one example, during a large step load / unload change, the power p-type device 201 is immediately turned on / off g1-N , so that the maximum voltage droop or voltage overshoot can be reduced or minimized. In some embodiments, D-LDO 700 is a clock-less design, thus allowing for further reduction in power consumption over conventional synchronous D-LDOs.

[0061] Fig. 8A-B shows graphs 800 and 820 respectively showing the clamping action and the releasing action of the asynchronous LDO circuit according to some embodiments of the present disclosure. Graph 800 shows four sub-graphs—801, 802, 803, 804, and 805. Sub-graph 801 shows the load current increasing from, for example, 0.5 mA to 4.5 mA. Sub-graph 802 shows the voltage on node 106. Sub-graph 803 shows the clamping signal 201d. Sub-graph 804 shows the releasing signal 201c. Sub-graph 805 shows the p-type power device 201 being turned on. g1-N The graph 800 shows that the D-LDO 700 can be operated by fixing the p-type power switch 201 under step load changes. g1-N To minimize or reduce the maximum voltage droop on node 106 and eventually stabilize.

[0062] Graph 820 shows four sub-graphs—821, 822, 823, 824, and 825. Sub-graph 821 shows a load current dropping from, for example, 4.5 mA to 0.5 mA. Sub-graph 822 shows the voltage on node 106. Sub-graph 823 shows clamping signal 201 d. Sub-graph 824 shows release signal 201 c. Sub-graph 825 shows p-type power device 201 turned on. g1-N In this example, the D-LDO 700 releases all p-type power switches 201 in the event of a step load change. g1-N To minimize the voltage overshoot on node 106 and eventually stabilize.

[0063] Fig. 9 Schematic diagram of an asynchronous LDO 900 circuit with modular clamping and releasing functions according to some embodiments of the present disclosure is shown. It should be noted that Fig. 9 Those elements of the same reference numerals (or names) as elements of any other figure may operate or function in any manner similar to that described, but are not limited to such a manner. According to some embodiments, the asynchronous LDO circuit 900 can handle supply voltage variations. During supply voltage variations, it may be necessary to adjust the p-type power switch 201 g1-N strength to meet the maximum load current requirements.

[0064] and Figure 7 In contrast, according to some embodiments, the control logic 103 is divided into two parts for the p-type power switch 201. g1-N "N" logic circuits 903 1-N For example, the logic circuit 9031 drives the p-type power switch 201 g1 , the logic circuit 9032 drives the p-type power switch 201 g2, and so on. In some embodiments, each logic circuit (e.g., 9031) includes an AND gate 903a, a NOR gate 303a, an OR gate 903b, and a NAND gate 903c coupled together as shown. In some embodiments, the NOR gate 303a is also controlled by the release signal 201c. In some embodiments, the OR gate 903b is also controlled by the release signal 201d. In some embodiments, the shift register 201e controls a total of "N" logic units 903 1-N , and each cell controls "M" p-type switches (eg, each power switch 201 g1 Each logic cell receives a control bit (e.g., On-en<M-1:0> 903d and Clamp_en<M-1:0> 903e), which controls the strength of the p-type switch.

[0065] Fig.10 A graph 1000 showing the operation of asynchronous LDO 900 according to some embodiments of the present disclosure is shown. Graph 1000 shows four sub-graphs—1001, 1002, 1003, and 1004. Sub-graph 1001 is the voltage ramp on the input power supply at node 105. Sub-graph 1002 is the load current through load 113. Sub-graph 1003 shows the adjustment of the strength of the p-type power device (e.g., 2011). Sub-graph 1004 shows the voltage on node 106. In this example, as the power supply voltage increases, as shown in sub-graph 1001, the strength of the unit p-type switch (e.g., switch 2011) becomes stronger, triggering a series of unclamping and clamping actions. After the strength of the unit p-type switch (e.g., switch 2011) is adjusted to 0.9 μs, the voltage peak decreases.

[0066] Table 2 compares the performance of the LDO 900 with a traditional analog LDO. For the ISO comparison with the analog LDO, the following assumptions were made: maximum load current is 10mA, output capacitance is 200pF, and maximum voltage droop is 150mV.

[0067] Table 2

[0068]

[0069]

[0070] Table 2 shows that LDO 900 can reduce the current by a factor of 2 compared to an analog LDO given the same requirements.

[0071] Fig.11 A smart device or computer system or SoC (system on chip) with a modular and / or asynchronous LDO circuit according to some embodiments is shown. It should be noted that Fig.11Those elements having the same reference numbers (or names) as elements of any other figure may operate or function in any manner similar to that described, but are not limited to such.

[0072] Fig.11 A block diagram of an embodiment of a mobile device that may use a flat surface interface connector is shown. In some embodiments, computing device 1600 represents a mobile computing device (such as a computing tablet, a mobile phone or smartphone, a wireless-enabled e-reader, or other wireless mobile device). It should be understood that certain components are shown generally and not all components of this device are shown in computing device 1600.

[0073] In some embodiments, computing device 1600 includes a first processor 1610 having a modular and / or asynchronous LDO circuit as discussed in some embodiments. According to some embodiments, other blocks of computing device 1600 may also include modular and / or asynchronous LDO circuits. Various embodiments of the present disclosure may also include a network interface (such as a wireless interface) within 1670 so that the system embodiment can be incorporated into a wireless device (e.g., a cellular phone or a personal digital assistant).

[0074] In some embodiments, processor 1610 may include one or more physical devices, such as a microprocessor, an application processor, a microcontroller, a programmable logic device, or other processing means. Processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and / or device functions are executed. Processing operations include operations related to I / O (input / output) with a human user or with other devices, operations related to power management, and / or operations related to connecting computing device 1600 to another device. Processing operations may also include operations related to audio I / O and / or display I / O.

[0075] In some embodiments, computing device 1600 includes audio subsystem 1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions may include speaker and / or headphone outputs, and microphone input. Devices for these functions may be integrated into computing device 1600, or connected to computing device 1600. In one embodiment, a user interacts with computing device 1600 by providing audio commands that are received and processed by processor 1610.

[0076] In some embodiments, computing device 1600 includes a display subsystem 1630. Display subsystem 1630 represents hardware (e.g., display device) and software (e.g., driver) components that provide a visual and / or tactile display for a user to interact with computing device 1600. Display subsystem 1630 includes a display interface 1632, which includes a specific screen or hardware device for providing a display to a user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touchpad) device that provides output and input to a user.

[0077] In some embodiments, computing device 1600 includes I / O controller 1640. I / O controller 1640 represents hardware devices and software components related to interaction with a user. I / O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and / or display subsystem 1630. In addition, I / O controller 1640 shows connection points for additional devices connected to computing device 1600, through which a user can interact with the system. For example, devices that can be attached to computing device 1600 may include microphone devices, speakers or stereo systems, video systems or other display devices, keyboards or keypad devices, or other I / O devices for specific applications (such as card readers or other devices).

[0078] As mentioned above, I / O controller 1640 can interact with audio subsystem 1620 and / or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of computing device 1600. In addition, audio output can be provided instead of or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be managed at least in part by I / O controller 1640. There can also be additional buttons or switches on computing device 1600 for providing I / O functions managed by I / O controller 1640.

[0079] In some embodiments, I / O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that may be included in computing device 1600. The input may be part of direct user interaction, as well as providing environmental input to the system to affect its operation (such as filtering noise, adjusting the display for brightness detection, applying a flash to a camera, or other features).

[0080] In some embodiments, computing device 1600 includes power management 1650 that manages battery power usage, battery charging, and features related to power conservation operations. Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include non-volatile (state does not change if the memory device is powered off) and / or volatile (state is indeterminate if the memory device is powered off) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of applications and functions of computing device 1600.

[0081] The elements of the embodiments are also provided as a machine-readable medium (e.g., memory 1660) for storing computer-executable instructions (e.g., instructions for implementing any other process discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disk, CD-ROM, DVD ROM, RAM, EPROM, EEPROM, magnetic or optical card, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the present disclosure may be downloaded as a computer program (e.g., BIOS), which may be transmitted to a requesting computer (e.g., client) from a remote computer (e.g., server) in the form of a data signal via a communication link (e.g., a modem or a network connection).

[0082] In some embodiments, computing device 1600 includes connections 1670. Connections 1670 include hardware devices (e.g., wireless and / or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable computing device 1600 to communicate with external devices. Computing device 1600 can be a standalone device (such as other computing devices, wireless access points or base stations) as well as peripheral devices (such as head-mounted devices, printers, or other devices).

[0083] Connection 1670 may include a variety of different types of connections. For purposes of overview, computing device 1600 is shown with cellular connection 1672 and wireless connection 1674. Cellular connection 1672 generally refers to a cellular network connection provided by a wireless carrier, such as a cellular network connection provided via GSM (Global System for Mobile Communications) or a variant or derivative thereof, CDMA (Code Division Multiple Access) or a variant or derivative thereof, TDM (Time Division Multiplexing) or a variant or derivative thereof, or other cellular service standards. Wireless connection (or wireless interface) 1674 refers to a non-cellular wireless connection and may include a personal area network (such as Bluetooth, near field, etc.), a local area network (such as Wi-Fi) and / or a wide area network (e.g., WiMAX), or other wireless communications.

[0084] In some embodiments, computing device 1600 includes peripheral connections 1680. Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) for making peripheral connections. It should be understood that computing device 1600 can be a peripheral device that goes to other computing devices ("to" 1682), and can have peripheral devices connected to it ("from" 1684). Computing device 1600 typically has a "docking" connector for connecting to other computing devices for purposes such as managing (e.g., downloading and / or uploading, changing, synchronizing) content on computing device 1600. In addition, the docking connector can allow computing device 1600 to connect to certain peripherals that allow computing device 1600 to control, for example, content output to an audio-visual or other system.

[0085] In addition to a dedicated docking connector or other dedicated connection hardware, computing device 1600 can make peripheral connections 1680 via common or standards-based connectors. Common types may include Universal Serial Bus (USB) connectors (which may include any number of different hardware interfaces), DisplayPort including Mini DisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[0086] References in this specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" mean that the particular features, structures, or characteristics described in conjunction with these embodiments are included in at least some embodiments, but not necessarily in all embodiments. Multiple occurrences of "an embodiment," "one embodiment," or "some embodiments" do not necessarily all refer to the same embodiment. If the specification states that a component, feature, configuration, or characteristic "may," "might," or "can" be included, that particular component, feature, configuration, or characteristic need not be included. If the specification or claims refer to "a" or "an" element, it does not mean that there is only one element. If the specification or claims refer to "additional" elements, that does not exclude the presence of more than one additional element.

[0087] In addition, specific features, structures, functions or characteristics may be combined in any suitable manner in one or more embodiments. For example, the first embodiment may be combined with the second embodiment as long as the specific features, structures, functions or characteristics associated with the first embodiment and the second embodiment are not mutually exclusive.

[0088] Although the present disclosure has been described in conjunction with specific embodiments of the present disclosure, many alternatives, modifications and variations of such embodiments will be apparent to those skilled in the art from the foregoing description. The embodiments of the present disclosure are intended to cover all such alternatives, modifications and changes that fall within the broad scope of the appended claims.

[0089] In addition, for simplicity of illustration and discussion and in order not to obscure the present disclosure, known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the presented drawings. In addition, the arrangement may be shown in the form of a block diagram to avoid obscuring the present disclosure, and also in view of the fact that the details of the implementation of completing such a block diagram arrangement are highly dependent on the platform in which the present disclosure is implemented (i.e., such details should be completely within the vision of those skilled in the art). Specific details (e.g., circuits) are set forth to describe exemplary embodiments of the present disclosure, and it should be apparent to those skilled in the art that the present disclosure can be practiced without these details or with variations of these embodiment details. Therefore, the description is considered to be illustrative, not restrictive.

[0090] The following examples relate to further embodiments. The details in these examples may be used anywhere in one or more embodiments. All optional features of the device described herein may also be implemented with respect to a method or process. Various embodiments here may be combined with any other embodiment, thereby allowing various combinations.

[0091] Example 1 is a device comprising: a first group of devices, which are digitally controlled by a first feedback loop including a first comparator; and a second group of devices, which are controlled by an analog circuit, which is part of a second feedback loop including an amplifier, wherein the first group of devices are coupled in parallel to the second group of devices.

[0092] Example 2 includes all of the features of Example 1, wherein the first group of devices and the second group of devices are coupled to a first power supply node and a second power supply node, and wherein the second power supply node is for coupling to a load.

[0093] Example 3 includes all of the features of Example 1, wherein at least one device in the second group of devices is always on or is on when an input power source is on.

[0094] Example 4 includes all of the features of Example 1, wherein the first feedback loop includes a second comparator, wherein the first comparator and the second comparator are to receive a first reference and a second reference, and wherein the first reference is different from the second reference.

[0095] Example 5 includes all of the features of Example 4, wherein the first feedback loop includes a shift register having a first input for receiving an output of the first comparator, and a second input for receiving an output of the amplifier.

[0096] Example 6 includes all of the features of Example 5, wherein an output of the shift register is used to control the first group of devices.

[0097] Example 7 includes all of the features of Example 6, wherein the output of the shift register is a bus having at least two bits.

[0098] Example 8 includes all of the features of Example 6, wherein the output of the shift register is masked by an output of the first comparator and / or the amplifier.

[0099] Example 9 includes all of the features of Example 6, wherein the apparatus of Example 6 includes a first set of multiplexers for receiving the output of the shift register and the first predetermined signal, wherein the output of the first set of multiplexers is for digitally controlling the first set of devices.

[0100] Example 10 includes all the features of Example 9, wherein the device of Example 10 includes a second set of multiplexers for receiving the output of the shift register and a second predetermined signal, wherein the output of the second set of multiplexers is used to turn on or off at least one device in the second set of devices.

[0101] Example 11 includes all of the features of Example 10, wherein the first set of multiplexers and the second set of multiplexers are controlled by a programmable control.

[0102] Example 12 includes all of the features of Example 1, wherein the amplifier is used to generate an output between a power supply level and a ground level, and wherein the output is used to control a second set of devices.

[0103] Example 13 includes all the features of Example 1, wherein the first group of devices and the second group of devices include p-type transistors, n-type transistors, or a combination thereof.

[0104] Example 14 is a device comprising: a digital low dropout (LDO) coupled to an input power node and an output power node; and a group of analog LDOs coupled in parallel with the digital LDO, wherein at least one analog LDO in the group is always on.

[0105] Example 15 includes all the features of Example 14, wherein the apparatus of Example 15 includes a digital controller for controlling the digital LDO and the set of analog LDOs.

[0106] Example 16 includes all the features of Example 14, wherein the device of Example 14 comprises logic for masking an output of the digital controller based on a desired power supply rejection ratio (PSRR).

[0107] Example 17 includes all of the features of Example 14, wherein the set of analog LDOs includes p-type devices controlled by non-rail-to-rail outputs, and wherein the digital LDOs include p-type devices controlled by rail-to-rail outputs.

[0108] Embodiment 18 is a system comprising: a memory; a processor coupled to the memory, wherein the processor comprises a processor core powered by a power generator, wherein the power generator comprises: a first group of devices, the first group of devices being digitally controlled by a first feedback loop comprising a first comparator; and a second group of devices, the second group of devices being controlled by an analog circuit, the analog circuit being part of a second feedback loop comprising an amplifier, wherein the first group of devices is coupled in parallel to the second group of devices; and a wireless interface for allowing the processor to communicate with another device.

[0109] Example 19 includes all of the features of Example 18, wherein the first group of devices and the second group of devices are coupled to a first power supply node and a second power supply node, and wherein the second power supply node is for coupling to a processor core.

[0110] Example 20 includes all of the features of Example 18, wherein at least one device in the second group of devices is always on.

[0111] Example 21 is a device comprising: a digital low dropout (LDO) coupled to an input power node and an output power node; and a group of analog LDOs coupled in parallel with the digital LDO, wherein the digital LDO and the group of analog LDOs are controllable to obtain a target power supply rejection ratio (PSRR).

[0112] Example 22 includes all of the features of Example 21, wherein the set of analog LDOs includes p-type devices controlled by non-rail-to-rail outputs, and wherein the digital LDO includes p-type devices controlled by rail-to-rail outputs.

[0113] Example 23 includes all of the features of Example 21, wherein the apparatus of Example 23 includes circuitry for overriding a feedback loop of the digital LDO when an output at an output supply node is outside of a threshold limit.

[0114] Example 24 includes all of the features of Example 21, wherein the apparatus of Example 23 comprises a circuit for overriding a feedback loop of the digital LDO when an output at an output power supply node is above or below a threshold.

[0115] Example 25 is a method comprising: controlling a digital low dropout (LDO) coupled to an input power node and an output power node; and controlling a set of analog LDOs coupled in parallel to the digital LDO to obtain a target power supply rejection ratio (PSRR).

[0116] Example 26 includes all of the features of Example 25, wherein the set of analog LDOs includes p-type devices controlled by non-rail-to-rail outputs, and wherein the digital LDO includes p-type devices controlled by rail-to-rail outputs.

[0117] Example 27 includes all of the features of Example 25, wherein the method of Example 27 includes overriding a feedback loop of the digital LDO when the output at the output power supply node is outside of a threshold limit.

[0118] Example 28 includes all of the features of Example 25, wherein the method of Example 28 includes overriding a feedback loop of the digital LDO when the output at the output power supply node is outside of a threshold limit.

[0119] Example 29 is a device comprising: a device for controlling a digital low dropout (LDO) coupled to an input power node and an output power node; and a device for controlling a group of analog LDOs coupled in parallel to the digital LDO to obtain a target power supply rejection ratio (PSRR).

[0120] Example 30 includes all of the features of Example 29, wherein the set of analog LDOs includes p-type devices controlled by non-rail-to-rail outputs, and wherein the digital LDO includes p-type devices controlled by rail-to-rail outputs.

[0121] Example 31 includes all of the features of Example 29, wherein the apparatus of Example 31 comprises means for overriding a feedback loop of the digital LDO when the output at the output supply node is outside of a threshold limit.

[0122] Example 32 includes all of the features of Example 29, wherein the apparatus of Example 31 comprises means for overriding a feedback loop of the digital LDO when the output at the output supply node is outside of a threshold limit.

[0123] Example 33 is a system comprising: a memory; a processor coupled to the memory, wherein the processor comprises a processor core powered by a power generator, wherein the power generator comprises a device according to any one of Examples 1 to 13, Examples 14 to 17, Examples 21 to 24, or Examples 29 to 32; and a wireless interface for allowing the processor to communicate with another device.

[0124] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. This abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

Claims

1. A device comprising: a first group of devices digitally controlled by a first feedback loop including a first comparator; as well as A second group of devices, the second group of devices is controlled by an analog circuit, the analog circuit is part of a second feedback loop including an amplifier, wherein the first group of devices is coupled in parallel to the second group of devices, wherein the first group of devices and the second group of devices are coupled to a first power supply node and a second power supply node, and wherein the second power supply node is for coupling to a load.

2. The device according to claim 1, characterized in that At least one device in the second group of devices is always on.

3. The device according to claim 1 or 2, characterized in that The first feedback loop includes a second comparator, wherein the first comparator and the second comparator are configured to receive a first reference and a second reference, and wherein the first reference is different from the second reference.

4. The device according to claim 3, characterized in that The first feedback loop includes a shift register having a first input for receiving the output of the first comparator and a second input for receiving the output of the amplifier.

5. The device according to claim 4, characterized in that The output of the shift register is used to control the first group of devices.

6. The device according to claim 5, characterized in that The output of the shift register is a bus having at least two bits.

7. The device according to claim 5, characterized in that The output of the shift register is masked by the output of the first comparator and / or amplifier.

8. The apparatus of claim 5, comprising a first set of multiplexers for receiving said output of said shift register and a first predetermined signal, wherein said output of said first set of multiplexers is used to digitally control said first set of devices.

9. The apparatus of claim 8, comprising a second set of multiplexers for receiving the output of the shift register and a second predetermined signal, wherein the output of the second set of multiplexers is used to turn on or off at least one device in the second set of devices.

10. The device according to claim 9, characterized in that The first set of multiplexers and the second set of multiplexers are controlled by a programmable control.

11. The device according to claim 1 or 2, characterized in that The amplifier is used to generate an output between a power supply level and a ground level, and wherein the output is used to control the second group of devices.

12. The device according to claim 1 or 2, characterized in that The first group of devices and the second group of devices include p-type transistors, n-type transistors, or a combination thereof.

13. A system comprising: Memory; a processor coupled to the memory, wherein the processor comprises a processor core powered by a power generator, wherein the power generator comprises: a first group of devices digitally controlled by a first feedback loop including a first comparator; and a second set of devices controlled by an analog circuit that is part of a second feedback loop including an amplifier, wherein the first set of devices is coupled in parallel to the second set of devices; and A wireless interface allows the processor to communicate with another device, wherein the first group of devices and the second group of devices are coupled to a first power supply node and a second power supply node, and wherein the second power supply node is used to couple to the processor core.

14. The system of claim 13, wherein: At least one device in the second group of devices is always on.

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