Semiconductor Modules

Abstract

A semiconductor module includes: a module substrate having a first side extending in a first direction; a plurality of upper packages provided on a top surface of the module substrate and arranged in a plurality of rows extending in the first direction; and a passive element provided on the top surface of the module substrate. At least a portion of the passive element overlaps one of the upper packages in a plan view, and the upper packages in a first row are arranged to be shifted in the first direction relative to the upper packages in a second row.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2018-0049006, filed on April 27, 2018, and Korean Patent Application No. 10-2018-0097116, filed on August 21, 2018, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] Exemplary embodiments of the inventive concept relate to a semiconductor module, and more particularly, to a semiconductor module including a memory package. Background Art

[0004] As the demand for high-capacity electronic products such as smartphones and laptop computers continues to grow, the demand for high-capacity semiconductor modules used in such electronic products is also increasing to meet the demand. Relatedly, the size of the semiconductor package provided on such a high-capacity semiconductor module is also increasing to realize the high-capacity semiconductor module. Therefore, the size of the semiconductor module can be increased, and the length of the signal line in the semiconductor module can also be increased. Summary of the invention

[0005] Exemplary embodiments of the inventive concept may provide a semiconductor module capable of improving operation speed and reliability.

[0006] According to an exemplary embodiment of the present inventive concept, a semiconductor module includes: a module substrate having a first side extending in a first direction; a plurality of upper packages disposed on a top surface of the module substrate and arranged in a plurality of rows extending in the first direction; and a passive element disposed on the top surface of the module substrate. At least a portion of the passive element overlaps one of the upper packages in a plan view, and an upper package belonging to a first row of the plurality of rows is arranged to be shifted in the first direction relative to an upper package belonging to a second row of the plurality of rows.

[0007] According to an exemplary embodiment of the inventive concept, a semiconductor module includes: a module substrate having a first side, a second side opposite to the first side, a third side adjacent to the first side, and a fourth side opposite to the third side; a plurality of convex tabs disposed on a top surface of the module substrate adjacent to the first side; a plurality of memory packages mounted on the top surface of the module substrate and arranged in a plurality of rows extending in a first direction; and a passive element mounted on the top surface of the module substrate. The first side of the module substrate extends in the first direction, and at least a portion of the passive element overlaps one of the memory packages at an angle in a plan view. The memory element includes: a plurality of first packages disposed in a first row belonging to the plurality of rows in a plan view; and a plurality of second packages disposed in a second row belonging to the plurality of rows in a plan view. The second package is closer to the convex tab than the first package. The minimum distance between the third side and the first package is smaller than the minimum distance between the third side and the second package, and the minimum distance between the fourth side and the first package is smaller than the minimum distance between the fourth side and the second package.

[0008] According to an exemplary embodiment of the inventive concept, a semiconductor module includes: a module substrate having a first side extending in a first direction and a second side extending in the first direction; a plurality of protrusions disposed on a top surface of the module substrate adjacent to the first side; a plurality of memory packages mounted on the top surface of the module substrate and arranged in a plurality of rows extending in the first direction; and a passive element mounted on the top surface of the module substrate. At least a portion of the passive element overlaps with one of the memory packages at an angle of a plan view, the memory element including: a plurality of first packages disposed in a first row belonging to the plurality of rows in a plan view; and a plurality of second packages disposed in a second row belonging to the plurality of rows in a plan view. The second package is closer to the protrusion than the first package. Each of the first packages has a long axis parallel to a second direction, and each of the second packages has a long axis parallel to the first direction, the second direction being perpendicular to the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other features of the present inventive concept will become more apparent by describing in detail exemplary embodiments of the present inventive concept with reference to the accompanying drawings, in which:

[0010] Figure 1A is a plan view illustrating a top surface of a semiconductor module according to an exemplary embodiment of the inventive concept.

[0011] Figure 1B It is shown Figure 1AA top view of the electrical connection between the upper tab and the upper package of a semiconductor module.

[0012] Figure 1C is along Figure 1A A cross-sectional view taken along line II'.

[0013] Figure 1D yes Figure 1A Magnified view of region II.

[0014] Figure 1E is along Figure 1D A cross-sectional view taken along line III-III'.

[0015] Figure 1F is along Figure 1D A cross-sectional view taken along line IV-IV'.

[0016] Figure 1G It is shown Figure 1A A bottom view of the bottom surface of a semiconductor module.

[0017] Figure 1H is a bottom view showing the electrical connection between the lower tab and the lower package.

[0018] Fig. 1I is a cross-sectional view illustrating one of an upper package and a first passive element provided in a semiconductor module according to an exemplary embodiment of the inventive concept.

[0019] Figure 2 is corresponding to Figure 1D 1 and 2. A cross-sectional view taken along line III-III' of FIG. 1 and illustrating the installation of a second passive element according to an exemplary embodiment of the inventive concept.

[0020] Figure 3A is corresponding to Figure 1D 1 and 2. A cross-sectional view taken along line III-III' of FIG. 1 is shown, and illustrates a semiconductor module according to an exemplary embodiment of the inventive concept.

[0021] Figure 3B is corresponding to Figure 1D 1 and 2. A cross-sectional view taken along line IV-IV' of FIG. 1 is shown, and illustrates a semiconductor module according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0022] Exemplary embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may denote like elements throughout the drawings.

[0023] Spatially relative terms such as "below," "under," "lower," "below," "above," "upper," and the like may be used herein to facilitate describing the relationship of one element or feature relative to another element(s) or feature(s) as shown in the accompanying drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, elements described as being "below" or "below" or "below" other elements or features would be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "below" may encompass both above and below orientations.

[0024] It should be understood that the terms "first", "second", "third", etc. are used herein to distinguish one element from another element, and the elements are not limited by these terms. Therefore, in another exemplary embodiment, the "first" element in the exemplary embodiment can be described as the "second" element.

[0025] It will be further understood that one of ordinary skill in the art will understand that when two components or directions are described as extending substantially parallel or perpendicular to each other, the two components or directions extend exactly parallel or perpendicular to each other, or extend approximately parallel or perpendicular to each other within measurement error.

[0026] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0027] Figure 1A is a plan view illustrating a top surface of a semiconductor module according to an exemplary embodiment of the inventive concept. Figure 1B It is shown Figure 1A A top view of the electrical connection between the upper tab and the upper package of a semiconductor module. Figure 1C is along Figure 1A A cross-sectional view taken along line II'. Figure 1D yes Figure 1A Magnified view of region II. Figure 1E is along Figure 1D A cross-sectional view taken along line III-III'. Figure 1F is along Figure 1D A cross-sectional view taken along line IV-IV'. Figure 1G It is shown Figure 1A A bottom view of the bottom surface of a semiconductor module. Figure 1H is a bottom view showing the electrical connection between the lower tab and the lower package.

[0028] Reference Figures 1A to 1H, the semiconductor module 1 may include a module substrate 100, upper protrusions 210, 220 and 230, a semiconductor package 310, a semiconductor device 320, an upper package 400, a passive component 600, lower protrusions 211, 221 and 231, and a lower package 401. The upper protrusions 210, 220 and 230 and the lower protrusions 211, 221 and 231 may also be referred to herein as contact terminals.

[0029] The module substrate 100 may be a printed circuit board (PCB) having a circuit pattern. The module substrate 100 may have a top surface 100a and a bottom surface 100b opposite to each other. The module substrate 100 may have a first side 101, a second side 102, a third side 103, and a fourth side 104. The first side 101 and the second side 102 of the module substrate 100 may be opposite to each other and may extend along a first direction D1. The first direction D1 may be substantially parallel to the top surface 100a of the module substrate 100, and the second direction D2 may be substantially parallel to the top surface 100a of the module substrate 100 and substantially perpendicular to the first direction D1. The third direction D3 may be substantially parallel to the top surface 100a of the module substrate 100, and may indicate a direction opposite to the first direction D1. The third side 103 of the module substrate 100 may be adjacent to the first side 101 and the second side 102 , the third side 103 and the fourth side 104 of the module substrate 100 may be opposite to each other, and may extend in the second direction D2 .

[0030] The upper protrusions 210, 220 and 230 may be disposed on the top surface 100a of the module substrate 100. The upper protrusions 210, 220 and 230 may be disposed adjacent to the first side 101 of the module substrate 100. The upper protrusions 210, 220 and 230 may be aligned and arranged along the first direction D1 to form a row extending in the first direction D1. From the perspective of the plan view, each of the upper protrusions 210, 220 and 230 may have a major axis substantially parallel to the second direction D2. For example, each of the upper protrusions 210, 220 and 230 may extend lengthwise in the second direction D2. The upper protrusions 210, 220 and 230 may include a metal, such as copper or aluminum. Figure 1C As shown, the upper tabs 210, 220, and 230 may be portions of the conductive pattern of the module substrate 100 exposed by the passivation layer 109. However, exemplary embodiments of the inventive concept are not limited thereto.

[0031] The upper protrusions 210, 220 and 230 may include a first upper protrusion 210, a second upper protrusion 220 and a third upper protrusion 230. The functions and arrangements of the upper protrusions 210, 220 and 230 may be standardized. For example, the functions and arrangements of the upper protrusions 210, 220 and 230 may meet the Joint Electronic Device Engineering Council (JEDEC) standard. The first upper protrusion 210 may be closer to the third side 103 of the module substrate 100 than the second upper protrusion 220 and the third upper protrusion 230. The second upper protrusion 220 may be closer to the fourth side 104 of the module substrate 100 than the third upper protrusion 230. The first upper protrusion 210 and the second upper protrusion 220 may be used as input / output terminals for data signals. At the angle of the plan view, the third upper protrusion 230 may be disposed between the first upper protrusion 210 and the second upper protrusion 220. The third upper protrusion 230 may be used as a transmission path for command / address (C / A) signals.

[0032] The semiconductor package 310 may be mounted on the top surface 100a of the module substrate 100. In a plan view, the semiconductor package 310 may be disposed in a central region of the top surface 100a of the module substrate 100. The semiconductor package 310 may be used as a logic package or a buffer package. Figure 1C As shown, the semiconductor package 310 may include a first package substrate 311, a first semiconductor chip 312, and a first mold pattern 313. The first package substrate 311 may be, for example, a PCB or a redistribution layer. The first semiconductor chip 312 may be mounted on the first package substrate 311. The first semiconductor chip 312 may include a logic circuit and may be used as, for example, at least one of a logic chip or a buffer chip. The first mold pattern 313 may be disposed on the first package substrate 311 and may seal the first semiconductor chip 312. At least one connection terminal 500 may be disposed between the module substrate 100 and the first package substrate 311 and may connect the module substrate 100 and the semiconductor package 310. The connection terminal 500 may include, for example, at least one of a column, a bump, or a solder ball. The connection terminal 500 may include a conductive material. The first semiconductor chip 312 may be electrically connected to the interconnection line 150 in the module substrate 100 through the first package substrate 311 and the connection terminal 500. The interconnection line 150 may include a conductive pattern and a through hole.

[0033] The semiconductor package 310 may be electrically connected to the third upper bump 230 through the interconnection line 150 in the module substrate 100. Therefore, the command / address signal may be transmitted between the third upper bump 230 and the first semiconductor chip 312. The semiconductor package 310 may be electrically connected to the upper package 400 and the lower package 401 through the interconnection line 150 in the module substrate 100. The semiconductor package 310 may control the upper package 400 and the lower package 401. Here, it should be understood that when an element or component is electrically connected to the module substrate 100, it may be electrically connected to the interconnection line 150 in the module substrate 100. The interconnection line 150 may be electrically connected to the upper package 400 and the lower package 401. Figure 1C It should be understood that the arrangement and shape of the interconnection line 150 may be modified in various ways. Figure 1C The interconnection line 150 is omitted in other figures.

[0034] The semiconductor device 320 may be mounted on the top surface 100a of the module substrate 100. In the perspective of the plan view, the semiconductor device 320 may be spaced apart from the semiconductor package 310. The semiconductor device 320 may include, for example, a serial presence detection (SPD) chip. For example, information related to the semiconductor module 1 may be stored in the SPD chip of the semiconductor device 320. The information related to the semiconductor module 1 may include, for example, information indicating the memory type of the semiconductor module 1 and / or the timing of accessing the memory. In an exemplary embodiment, the SPD chip may be used as the semiconductor device 320. In this case, the SPD chip may be directly mounted on the top surface 100a of the module substrate 100. In an exemplary embodiment, a package including the SPD chip may be used as the semiconductor device 320. In this case, the semiconductor device 320 may include a second package substrate, an SPD chip mounted on the second package substrate, and a second mold pattern covering the SPD chip on the second package substrate. The semiconductor device 320 may be electrically connected to the semiconductor package 310 through the module substrate 100.

[0035] The upper package 400 may be mounted on the top surface 100a of the module substrate 100. The upper package 400 may be spaced apart from the semiconductor package 310, the semiconductor device 320, and the upper convex pieces 210, 220, and 230. The upper packages 400 may be spaced apart from each other. Each upper package 400 may be a memory package. The upper packages 400 may be identical to each other. For example, the upper packages 400 may have the same planar area, the same shape, and the same storage capacity as each other. Each upper package 400 may include an upper substrate 470, an upper semiconductor chip 480, and an upper molding layer 490. The upper semiconductor chip 480 may be a memory chip. For example, the upper semiconductor chip 480 may include a dynamic random access memory (DRAM), a static random access memory (SRAM), a synchronous dynamic random access memory (SDRAM), or a magnetic random access memory (MRAM). The upper semiconductor chip 480 may be mounted on the upper substrate 470. The upper molding layer 490 may be disposed on the upper substrate 470 and may cover the upper semiconductor chip 480. The upper connection terminals 501 may be disposed between the module substrate 100 and the upper package 400 . Each of the upper connection terminals 501 may include, for example, at least one of a pillar, a bump, or a solder ball. The upper package 400 may be electrically connected to the module substrate 100 through the upper connection terminals 501 .

[0036] like Figure 1A and Figure 1B As shown, the upper packages 400 may be arranged along a plurality of rows X1 and X2. Each of the rows X1 and X2 may extend in the first direction D1. Each of the rows X1 and X2 may include a plurality of upper packages 400. Figure 1B , the solid line between the upper connection terminal 501 and the first upper convex piece 210 and the second upper convex piece 220 schematically represents the electrical connection between the upper package 400 and the first upper convex piece 210 and the second upper convex piece 220. The upper package 400 can send signals to / receive signals from an external system or device through the module substrate 100 and the first upper convex piece 210 and the second upper convex piece 220. The signal between the upper package 400 and the first upper convex piece 210 and the second upper convex piece 220 can be a data (DQ) signal. As the length of the signal path between the upper package 400 and the first upper convex piece 210 and the second upper convex piece 220 is reduced, the operating speed and reliability of the semiconductor module 1 can be improved. A high-capacity memory package can be used as the upper package 400.

[0037] In an exemplary embodiment, the upper package 400 may be displaced in the second direction D2. For example, in an exemplary embodiment, the upper package 400 may be arranged so that the minimum distance A10 between the upper package 400 and the upper protrusions 210, 220, and 230 may be smaller than the minimum distance A20 between the upper package 400 and the second side 102 of the module substrate 100. Therefore, the length of the signal path between the upper package 400 and the first upper protrusion 210 and the second upper protrusion 220 may be reduced.

[0038] The upper package 400 may include a first package 410 and a second package 420. The first package 410 may correspond to the upper package 400 disposed in the first row X1, and the second package 420 may correspond to the upper package 400 disposed in the second row X2. The second package 420 may be closer to the first side 101 of the module substrate 100 and the upper protrusions 210, 220, and 230 than the first package 410. The number of the second packages 420 may be equal to the number of the first packages 410. However, exemplary embodiments of the inventive concept are not limited thereto. Each second package 420 may have a major axis substantially parallel to the first direction D1. For example, the width W of each second package 420 may be greater than the length L of each second package 420. Therefore, the length of the signal path between the second package 420 and the first upper protrusion 210 and the second upper protrusion 220 may be further reduced. Here, the width of a component may refer to the distance between both ends of the component in the first direction D1, and the length of a component may refer to the distance between both ends of the component in the second direction D2.

[0039] Some upper packages 400 may constitute a first group G10, and other upper packages 400 may constitute a second group G20. In the plan view, the upper packages 400 of the first group G10 may be disposed between the semiconductor package 310 and the third side 103 of the module substrate 100. Figure 1B As shown, the upper package 400 of the first group G10 can be electrically connected to the first upper protrusion 210 through the module substrate 100. In an exemplary embodiment, the upper package 400 of the first group G10 is not electrically connected to the second upper protrusion 220 and the third upper protrusion 230. Referring to the upper package 400 of the first group G10, the signal path S10 (see Figure 1B ) may correspond to a maximum signal path length, the signal path S10 being located between the first package 410 closest to the fourth side 104 of the module substrate 100 and the first upper protrusion 210 connected to the first package 410.

[0040] In an exemplary embodiment, referring to the upper package 400 of the first group G10, the first package 410 may be shifted in the first direction D1 relative to the second package 420. For example, in an exemplary embodiment, the upper package 400 may be arranged so that a minimum distance B10 between the third side 103 of the module substrate 100 and the first package 410 may be smaller than a minimum distance B20 between the third side 103 of the module substrate 100 and the second package 420.

[0041] Here, when some upper packages 400 are described as being displaced in a certain direction relative to other upper packages 400, it should be understood that some upper packages 400 and another upper package 400 may be arranged such that some upper packages 400 and other upper packages 400 are not aligned with each other in a certain direction. Figure 1A and Figure 1B In an exemplary embodiment, the first packages 410 disposed in the first row X1 and the second packages 420 disposed in the second row X2 are not aligned with each other in the first direction D1. For example, the boundaries of the first packages 410 disposed in the first row X1 are not aligned with the boundaries of the second packages 420 disposed in the second row X2.

[0042] Furthermore, in an exemplary embodiment, the first package 410 and the second package 420 are not aligned such that a distance between the first package 410 closest to the third side 103 of the module substrate 100 and the third side 103 is different from a distance between the second package 420 closest to the third side 103 of the module substrate 100 and the third side 103. For example, Figure 1A and Figure 1B As shown, in an exemplary embodiment, a minimum distance B10 between the third side 103 of the module substrate 100 and the closest first package 410 may be smaller than a minimum distance B20 between the third side 103 of the module substrate 100 and the closest second package 420 .

[0043] Although the first packages 410 arranged in the first row X1 and the second packages 420 arranged in the second row X2 are oriented in Figure 1A and Figure 1B For example, in an exemplary embodiment, the first packages 410 disposed in the first row X1 and the second packages 420 disposed in the second row X2 may be disposed in the same orientation and not aligned with each other.

[0044] Referring to the upper package 400 of the first group G10, the number of the first package 410 may be equal to the number of the second package 420. Still referring to the upper package 400 of the first group G10, in an exemplary embodiment, the upper package 400 may be arranged so that the maximum distance between the third side 103 of the module substrate 100 and the first package 410 may be smaller than the maximum distance between the third side 103 of the module substrate 100 and the second package 420. Therefore, according to an exemplary embodiment, the length of the signal path S10 between the first package 410 closest to the fourth side 104 of the module substrate 100 and the first upper protrusion 210 connected to the first package 410 may be reduced. As a result, according to an exemplary embodiment, the maximum signal path length between the first upper protrusion 210 and the upper package 400 of the first group G10 may be reduced.

[0045] In an exemplary embodiment, in the first group G10 , the first package 410 is misaligned with respect to the second package 420 in the second direction D2 , and in the second group G20 , the first package 410 is misaligned with respect to the second package 420 in the second direction D2 .

[0046] In the perspective of the plan view, the upper package 400 of the second group G20 may be disposed between the semiconductor package 310 and the fourth side 104 of the module substrate 100. The upper package 400 of the second group G20 may be electrically connected to the second upper protrusion 220 through the module substrate 100. In an exemplary embodiment, the upper package 400 of the second group G20 is not electrically connected to the first upper protrusion 210 and the third upper protrusion 230. Referring to the upper package 400 of the second group G20, the signal path S20 (see Figure 1B) may correspond to a maximum signal path length, and the signal path S20 is located between the first package 410 closest to the third side 103 of the module substrate 100 and the second upper protrusion 220 connected thereto. In an exemplary embodiment, referring to the upper package 400 of the second group G20, the first package 410 may be displaced relative to the second package 420 in the third direction D3. For example, in an exemplary embodiment, the upper package 400 may be arranged so that the minimum distance C10 between the fourth side 104 of the module substrate 100 and the first package 410 of the second group G20 may be less than the minimum distance C20 between the fourth side 104 of the module substrate 100 and the second package 420 of the second group G20. Referring to the upper package 400 of the second group G20, the number of the first package 410 may be equal to the number of the second package 420. Still referring to the upper package 400 of the second group G20, in an exemplary embodiment, the upper package 400 may be arranged so that the maximum distance between the fourth side 104 of the module substrate 100 and the first package 410 may be smaller than the maximum distance between the fourth side 104 of the module substrate 100 and the second package 420. As a result, according to an exemplary embodiment, the maximum signal path length between the second upper tab 220 and the upper package 400 of the second group G20 may be reduced.

[0047] like Figure 1A As shown, the module substrate 100 may include a first region R1, a second region R2, and a third region R3. The first region R1 of the module substrate 100 may be disposed between the first package 410 and the upper protrusions 210, 220, and 230. The second region R2 of the module substrate 100 may be disposed between the first package 410 and the second package 420. One of the third regions R3 of the module substrate 100 may be disposed between the third side 103 of the module substrate 100 and an outermost first package 410 of the first package 410 of the first group G10, and between the third side 103 of the module substrate 100 and an outermost second package 420 of the second package 420 of the first group G10. Another third region R3 in the third region R3 of the module substrate 100 can be set between the fourth side 104 of the module substrate 100 and the outermost second package 420 in the first package 410 of the second group G20, and between the fourth side 104 of the module substrate 100 and the outermost second package 420 in the second package 420 of the second group G20.

[0048] The passive component 600 may be mounted on the top surface 100a of the module substrate 100. The passive component 600 may include, for example, at least one of a resistor, a capacitor, or an inductor. The passive component 600 may be provided in plurality, and at least one of the passive components 600 may overlap one of the upper packages 400 at an angle of the plan view. The passive component 600 may include a first passive component 610, a second passive component 620, and a third passive component 630. The arrangement of the passive component 600 and the upper package 400 will be described below. For ease of explanation and description, reference will be made to Figure 1D , Figure 1E and Figure 1F Describes a single upper package.

[0049] like Figure 1A , Figure 1D and Figure 1E As shown, the first passive component 610 may include a first portion 610A and a second portion 610B connected to each other. In an exemplary embodiment, in a plan view, the first portion 610A of the first passive component 610 overlaps one of the upper packages 400, and the second portion 610B of the first passive component 610 does not overlap the upper package 400. In an exemplary embodiment, in a plan view, the second portion 610B of the first passive component 610 may overlap the first region R1 of the module substrate 100 (see Figure 1D ). In an exemplary embodiment, as Figure 1A As shown, from the perspective of the plan view, the second portion 610B of the first passive component 610 overlaps with the second region R2 of the module substrate 100. In an exemplary embodiment, from the perspective of the plan view, the second portion 610B of the first passive component 610 overlaps with the third region R3 of the module substrate 100. Figure 1D and Figure 1F As shown, in an exemplary embodiment, from the perspective of the plan view, the second passive component 620 can completely overlap with the upper package 400. For example, as shown in FIG. Figure 1D As shown, in an exemplary embodiment, at the angle of the plan view, the first passive component 610 partially overlaps the upper package 400, and the second passive component 620 completely overlaps the upper package 400. According to an exemplary embodiment, at the angle of the plan view, the upper package 400 may overlap the first passive component 610 and the second passive component 620, and thus, the size of the semiconductor module 1 may be reduced.

[0050] According to an exemplary embodiment of the present inventive concept, since the upper package 400 overlaps with the first passive component 610 and the second passive component 620 in a plan view, the upper package 400 is not limited by the arrangement and position of the first passive component 610 and the second passive component 620, and can be freely set regardless of the arrangement and position of the first passive component 610 and the second passive component 620. For example, since the upper package 400 overlaps with the first passive component 610 and the second passive component 620, the upper package 400 can be further shifted in the second direction D2. In this case, at the angle of the plan view, the second portion 610B of the first passive component 610 can overlap with the first region R1 or the second region R2. Since the upper package 400 overlaps with the first passive component 610 and the second passive component 620, in the first group G10, the first package 410 can be further shifted relative to the second package 420 along the first direction D1. In the second group G20, the first package 410 can be further shifted relative to the second package 420 in the third direction D3. In this case, the second portion 610B of the first passive element 610 may overlap the third region R3 in a plan view. Therefore, the length of the signal path between the upper package 400 and the first and second upper tabs 210 and 220 may be reduced to improve the electrical characteristics of the semiconductor module 1 .

[0051] The first passive component 610 and the second passive component 620 may be disposed in a gap between the module substrate 100 and the upper package 400, as shown in FIG. Figure 1E and Figure 1F As shown. The top surfaces of the first passive element 610 and the second passive element 620 may be disposed at the same level or lower than the bottom surface of the upper package 400. The first passive element 610 and the second passive element 620 may be spaced apart from the upper connection terminal 501. Therefore, an electrical short circuit may be prevented from occurring between the upper connection terminal 501 and the first passive element 610 and the second passive element 620.

[0052] An external force may be applied to the upper package 400. For example, an external force may be applied to the upper package 400 during a process of manufacturing the semiconductor module 1, a process of transferring the semiconductor module 1, and / or a process of operating the semiconductor module 1. The edge portion of the upper package 400 may be bent by the external force. If the edge portion of the upper package 400 is excessively bent, the upper package 400 may be damaged. However, according to an exemplary embodiment of the present invention, at an angle of a plan view, the first passive element 610 and / or the second passive element 620 may overlap with the edge portion of the upper package 400. For example, the first passive element 610 may be disposed between the bottom surface of the edge portion of the upper package 400 and the top surface 100a of the module substrate 100. Therefore, in an exemplary embodiment, the upper package 400 may be prevented from being excessively bent.

[0053] like Figure 1E and Figure 1F As shown, the first pad 151 and the second pad 152 may be disposed on the top surface 100a of the module substrate 100. The first pad 151 and the second pad 152 may include, for example, a conductive material such as a metal. In an exemplary embodiment, each of the first passive element 610 and the second passive element 620 may include a first electrode 601 and a second electrode 602 spaced apart from each other. The second electrode 602 may be electrically isolated from the first electrode 601. The insulator 603 may be disposed between the first electrode 601 and the second electrode 602. However, the structure and components of the passive element 600 are not limited thereto, and various modifications may be made. The first connection portion 510 may be disposed between the first electrode 601 and the first pad 151. The first electrode 601 may be electrically connected to the module substrate 100 through the first connection portion 510. The second connection portion 520 may be disposed between the second electrode 602 and the second pad 152. The second electrode 602 may be electrically connected to the module substrate 100 through the second connection portion 520.

[0054] The first connection portion 510, the second connection portion 520, and the upper connection terminal 501 may include, for example, a solder material. The solder material may include, for example, at least one of tin, silver, gold, or bismuth. In an exemplary embodiment, the formation of the first connection portion 510 may include: setting a solder material between the first pad 151 and the first electrode 601; and welding the solder material. The formation of the second connection portion 520 may include: setting a solder material between the second pad 152 and the second electrode 602, and welding the solder material. Forming the upper connection terminal 501 may include: providing a solder material between the module substrate 100 and the upper package 400, and welding the solder material. The first connection portion 510, the second connection portion 520, and the upper connection terminal 501 may be formed using a single welding process. The welding process may be performed by heat treatment. During the welding process, the first electrode 601 and / or the second electrode 602 may be able to be excessively spaced apart from the module substrate 100 by the tension between the solder material and the electrodes 601 and 602. In this case, formation of the first connection portion 510 and / or the second connection portion 520 may be difficult.

[0055] However, according to an exemplary embodiment of the inventive concept, the bottom surface of the upper package 400 may be disposed on the first passive element 610. In the process of mounting the first passive element 610, the upper package 400 may prevent the first electrode 601 and / or the second electrode 602 of the first passive element 610 from being excessively spaced apart from the module substrate 100. Therefore, the first connection portion 510 and the second connection portion 520 may be sufficiently connected to the first electrode 601 and the second electrode 602, respectively. Similarly, the upper package 400 may be disposed on the top surface of the second passive element 620. As a result, the first electrode 601 and / or the second electrode 602 of the second passive element 620 may be prevented from being excessively spaced apart from the module substrate 100.

[0056] Refer again Figure 1A In an exemplary embodiment, the third passive component 630 does not overlap with the upper package 400 from the perspective of the plan view, but is spaced apart from the upper package 400. The third passive component 630 may be disposed in one of the first region R1, the second region R2, and the third region R3 of the module substrate 100. Alternatively, from the perspective of the plan view, the third passive component 630 may be disposed between the first packages 410. In an exemplary embodiment, the third passive component 630 may be omitted. In an exemplary embodiment, one of the first passive component 610 and the second passive component 620 may be omitted.

[0057] The lower tabs 211, 221, and 231 may be disposed on the bottom surface 100b of the module substrate 100, as shown in FIG. Figure 1G and Figure 1H As shown. Figure 1CAs shown, the lower protrusions 211, 221 and 231 may be portions of the conductive pattern of the module substrate 100 exposed by the passivation layer 109 disposed on the bottom surface 100b. However, exemplary embodiments of the inventive concept are not limited thereto. The lower protrusions 211, 221 and 231 may include metal. The planar arrangement of the lower protrusions 211, 221 and 231 may correspond to the planar arrangement of the upper protrusions 210, 220 and 230. For example, the lower protrusions 211, 221 and 231 may be adjacent to the first side 101 of the module substrate 100. The lower protrusions 211, 221 and 231 may be spaced apart from each other and may be electrically isolated from each other. The lower protrusions 211, 221 and 231 may include a first lower protrusion 211, a second lower protrusion 221 and a third lower protrusion 231. The first lower protrusion 211 may be closer to the third side 103 of the module substrate 100 than the second lower protrusion 221 and the second lower protrusion 231. The second lower protrusion 221 may be closer to the fourth side 104 of the module substrate 100 than the third lower protrusion 231. The first lower protrusion 211 and the second lower protrusion 221 may be used as input / output terminals of data signals of the lower package 401. The third lower protrusion 231 may be disposed between the first lower protrusion 211 and the second lower protrusion 221. The third lower protrusion 231 may be used as a transmission path of a command / address signal.

[0058] Each lower package 401 may be a memory package. For example, the lower packages 401 may have the same size, shape, and storage capacity as each other. In an exemplary embodiment, the lower package 401 may have the same size, shape, and storage capacity as the upper package 400. Each lower package 401 may include a lower substrate 471, a lower semiconductor chip 481, and a lower molding layer 491, such as Figure 1C As shown. The lower semiconductor chip 481 may be a memory chip. The lower semiconductor chip 481 may be mounted on the lower substrate 471. The type of the lower semiconductor chip 481 may be the same as the type of the upper semiconductor chip 480. However, exemplary embodiments of the inventive concept are not limited thereto. The lower molding layer 491 may be disposed on the lower substrate 471 and may cover the lower semiconductor chip 481. The lower connection terminal 502 may be disposed between the module substrate 100 and the lower package 401. The lower package 401 may be electrically connected to the module substrate 100 through the lower connection terminal 502.

[0059] The lower package 401 may be spaced apart from the lower tabs 211, 221, and 231. The planar arrangement of the lower package 401 may correspond to the planar arrangement of the upper package 400. Figure 1G and Figure 1HAs shown, the lower packages 401 may be arranged along a plurality of rows X1' and X2'. Each of the rows X1' and X2' may extend in the first direction D1. Each of the rows X1' and X2' may include a plurality of lower packages 401. For example, the row X1' may include an upper package 411, and the row X2' may include an upper package 421 (see Figure 1G and Figure 1H ). The number of lower packages 401 in the second row X2' may be equal to the number of lower packages 401 in the first row X1'. The lower package 401 may send a signal to / receive a signal from an external system or device through the first lower protrusion 211 and the second lower protrusion 221. As the length of the signal path between the lower package 401 and the first lower protrusion 211 and the second lower protrusion 221 is reduced, the operating speed and reliability of the semiconductor module 1 may be improved. The signal between the lower package 401 and the first lower protrusion 211 and the second lower protrusion 221 may be a data (DQ) signal. In an exemplary embodiment, the lower package 401 may be shifted in the second direction D2. For example, in an exemplary embodiment, the lower package 401 may be arranged so that the minimum distance A11 between the lower package 401 and the lower protrusions 211, 221 and 231 may be less than the minimum distance A21 between the lower package 401 and the second side 102 of the module substrate 100. Therefore, the length of the signal path between the lower package 401 and the first and second lower tabs 211 and 221 may be reduced.

[0060] The lower package 401 of the second row X2' can be closer to the lower protrusions 211, 221 and 231 than the lower package 401 of the first row X1'. Each lower package 401 of the second row X2' can have a major axis substantially parallel to the first direction D1. For example, the width of each lower package 401 of the second row X2' can be greater than the length of each lower package 401 of the second row X2'. Therefore, the lower package 401 can be closer to the lower protrusions 211, 221 and 231. As a result, the length of the signal path between the lower package 401 and the first lower protrusion 211 and the second lower protrusion 221 can be reduced. Each lower package 401 of the first row X1' can have a major axis substantially parallel to the second direction D2. For example, each lower package 401 of the first row X1' can extend longitudinally in the second direction D2.

[0061] Therefore, in an exemplary embodiment, the orientation of each lower package 401 of the second row X2 ′ may be different from the orientation of each lower package 401 of the first row X1 ′.

[0062] Some lower packages 401 may constitute a first group G11, while other lower packages 401 may constitute a second group G21. In the plan view, the lower packages 401 of the first group G11 may be closer to the third side 103 of the module substrate 100 than to the fourth side 104 of the module substrate 100. Figure 1H , the solid lines between the lower connection terminals 502 and the first and second lower protrusions 211, 221 schematically indicate electrical connections between the lower package 401 and the first and second lower protrusions 211, 221. In an exemplary embodiment, the lower package 401 of the first group G11 may be electrically connected to the first lower protrusion 211 through the module substrate 100, and the lower package 401 of the first group G11 is not electrically connected to the second and third lower protrusions 221, 231.

[0063] In the lower package 401 of the first group G11, the signal path S11 (see Figure 1H ) may correspond to a maximum signal path length, and the signal path S11 is located between the lower package 401 of the first row X1' closest to the fourth side 104 and the first lower protrusion 211 connected to the lower package 401. In an exemplary embodiment, among the lower packages 401 of the first group G11, the lower packages 401 of the first row X1' may be shifted in the first direction D1 relative to the lower packages 401 of the second row X2'. For example, the minimum distance B11 between the third side 103 of the module substrate 100 and the lower packages 401 of the first row X1' may be smaller than the minimum distance B21 between the third side 103 of the module substrate 100 and the lower packages 401 of the second row X2'. In the first group G11, the number of the lower packages 401 of the first row X1' may be equal to the number of the lower packages 401 of the second row X2'. In the first group G11, the maximum distance between the third side 103 of the module substrate 100 and the lower package 401 of the first row X1' may be smaller than the maximum distance between the third side 103 of the module substrate 100 and the lower package 401 of the second row X2'. Therefore, in an exemplary embodiment, the maximum signal path length between the first lower tab 211 and the lower package 401 of the first group G11 may be reduced.

[0064] In the perspective of the plan view, the lower package 401 of the second group G21 may be closer to the fourth side 104 of the module substrate 100 than the third side 103 of the module substrate 100. In an exemplary embodiment, the lower package 401 of the second group G21 may be electrically connected to the second lower protrusion 221 through the module substrate 100, and the lower package 401 of the second group G21 is not electrically connected to the first lower protrusion 211 and the third lower protrusion 231. In the lower package 401 of the second group G21, the signal path S21 (see Figure 1H) may correspond to a maximum signal path length, the signal path S21 being between the lower package 401 of the first row X1' closest to the third side 103 and the second lower protrusion 221 connected to the lower package 401. In an exemplary embodiment, among the lower packages 401 of the second group G21, the lower packages 401 of the first row X1' may be shifted relative to the lower packages 401 of the second row X2' in the third direction D3. For example, the minimum distance C11 between the fourth side 104 of the module substrate 100 and the lower packages 401 of the first row X1' may be smaller than the minimum distance C21 between the fourth side 104 of the module substrate 100 and the lower packages 401 of the second row X2'. Therefore, in an exemplary embodiment, the maximum signal path length between the second lower protrusion 221 and the lower package 401 of the second group G21 may be reduced.

[0065] In an exemplary embodiment, the semiconductor package 310 , the semiconductor device 320 , and the passive element 600 are not disposed on the bottom surface 100 b of the module substrate 100 .

[0066] In an exemplary embodiment, the total number of upper packages 400 and lower packages 401 may be 2n+A, where n is an integer equal to or greater than 1, and A is an integer equal to or greater than 0. Some of the upper packages 400 and lower packages 401 may be used as memory packages. For example, the total number of upper packages 400 and lower packages 401 used as memory packages may be 2n. Other upper packages 400 and lower packages 401 may be used as preliminary memory packages, which are arranged for situations where memory packages are not operated. For example, when a memory package is activated, a preliminary memory package may be deactivated. The total number of preliminary memory packages may be A. However, the number and function of the upper packages 400 and lower packages 401 are not limited thereto.

[0067] Fig. 1I is a cross-sectional view illustrating one of an upper package and a first passive element provided in a semiconductor module according to an exemplary embodiment of the inventive concept.

[0068] In the following, for the convenience of explanation, a single upper package will be described. In addition, for the convenience of explanation, further description of previously described components and technical features may be omitted.

[0069] refer to Figure 1E and Fig. 1I, the upper package 400 may include an upper substrate 470, an upper semiconductor chip 480, and an upper molding layer 490. The upper substrate 470 may include an insulating layer and a metal pattern 475. The metal pattern 475 may be disposed in the insulating layer and may be used as an electrical connection path. Some metal patterns 475 may be exposed at the sidewalls of the upper substrate 470. The sidewalls of the upper substrate 470 may correspond to the lower portion of the sidewalls 400s of the upper package 400. The upper semiconductor chip 480 may be sealed by the upper molding layer 490, and therefore, in an exemplary embodiment, the upper semiconductor chip 480 is not exposed at the sidewalls 400s of the upper package 400. The sidewalls of the upper molding layer 490 may correspond to the upper portion of the sidewalls 400s of the upper package 400. The upper molding layer 490 may include, for example, an insulating polymer.

[0070] As described above, a portion of the first passive element 610 may overlap with the upper package 400. In an exemplary embodiment, the first passive element 610 may overlap with the sidewall 400s of the upper package 400 at an angle of a plan view. The first passive element 610 may be disposed between the module substrate 100 and the upper substrate 470. The first passive element 610 may be spaced apart from the exposed portion of the metal pattern 475. For example, in an exemplary embodiment, at an angle of a plan view, the exposed surface of the metal pattern 475 does not overlap with the first passive element 610. Therefore, even if a slight error occurs in the process of manufacturing the semiconductor module 1, an electrical short circuit may be prevented from occurring between the first passive element 610 and the exposed portion of the metal pattern 475. For example, in an exemplary embodiment, one of the electrodes 601 and 602 of the first passive element 610 and / or one of the connection portions 510 and 520 does not contact the exposed surface of the metal pattern 475.

[0071] Figure 2 is corresponding to Figure 1D 1 and 2. A cross-sectional view taken along line III-III' of FIG. 1 and illustrating the installation of a second passive element according to an exemplary embodiment of the inventive concept.

[0072] In the following, for the convenience of explanation, a single upper package will be described. In addition, for the convenience of explanation, further description of previously described components and technical features may be omitted.

[0073] refer to Figure 1A , Figure 1D and Figure 2 In an exemplary embodiment, the second passive element 620 may overlap the upper package 400 in a plan view. Figure 1F Unlike the exemplary embodiment of the present invention, the second passive component 620 may be mounted on the bottom surface of the upper package 400, such as Figure 2 shown.

[0074] The conductive pad 473 , the first pad 151 , and the second pad 152 may be disposed on the bottom surface of the upper package 400 . The conductive pad 473 , the first pad 151 , and the second pad 152 may include a conductive material such as metal. The conductive pad 473 may be connected to the upper connection terminal 501 .

[0075] The first pad 151 and the second pad 152 may be spaced apart from the conductive pad 473. The first connection portion 510 may be disposed between the first pad 151 and the first electrode 601 of the second passive element 620. The second connection portion 520 may be disposed between the second pad 152 and the second electrode 602 of the second passive element 620. The second passive element 620 may be electrically connected to the upper package 400 through the first connection portion 510 and the second connection portion 520. The second passive element 620 may be spaced apart from the top surface 100a of the module substrate 100. For example, as Figure 2 As shown, in an exemplary embodiment, the second passive component 620 is disposed on the bottom surface of the upper package 400 , and there is a space between the second passive component 620 and the top surface 100 a of the module substrate 100 .

[0076] Figure 3A is corresponding to Figure 1D 1 and 2. A cross-sectional view taken along line III-III' of FIG. 1 is shown, and illustrates a semiconductor module according to an exemplary embodiment of the inventive concept.

[0077] Figure 3B is corresponding to Figure 1D 1 and 2. A cross-sectional view taken along line IV-IV' of FIG. 1 is shown, and illustrates a semiconductor module according to an exemplary embodiment of the inventive concept.

[0078] In the following, for the convenience of explanation, a single upper package will be described. In addition, for the convenience of explanation, further description of previously described components and technical features may be omitted.

[0079] refer to Figure 1A , Figure 1D and Figure 3A In an exemplary embodiment, the first support portion 710 may be disposed between the first passive component 610 and the upper package 400. The first support portion 710 may be in physical contact with the first passive component 610 and the upper package 400. The first support portion 710 may include an insulating material, and in an exemplary embodiment, the first support portion 710 is not electrically connected to the first passive component 610 and the upper package 400. The configuration of the first support portion 710 and the first passive component 610 may prevent the upper package 400 from bending or warping.

[0080] refer to Figure 1A , Figure 1D and Figure 3BIn an exemplary embodiment, the second support portion 720 may be disposed between the second passive component 620 and the upper package 400. The second support portion 720 may be in physical contact with the second passive component 620 and the upper package 400. The second support portion 720 may include an insulating material, and in an exemplary embodiment, the second support portion 720 is not electrically connected to the second passive component 620 and the upper package 400. The configuration of the second support portion 720 and the second passive component 620 may prevent the upper package 400 from bending or warping.

[0081] According to an exemplary embodiment of the present invention, at least a portion of the passive element may overlap one of the upper packages at an angle of the plan view. In addition, the arrangement of the upper package may be adjusted to reduce the length of the signal path between the protrusion and the upper package. Therefore, the operating speed and reliability of the semiconductor module may be improved. In addition, the semiconductor module may have a high capacity.

[0082] While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the inventive concept as defined in the appended claims.

Claims

1. A semiconductor module, comprising: a module substrate having a first side extending in a first direction; a plurality of upper packages disposed on the top surface of the module substrate and arranged in a plurality of rows extending in the first direction, wherein the upper packages belonging to a first row of the plurality of rows are arranged to be shifted in the first direction relative to the upper packages belonging to a second row of the plurality of rows, The module substrate includes: a first region, which is arranged between a first side of the module substrate and the upper package of the second row; a second region, which is arranged between the upper package of the first row and the upper package of the second row; a third region, which is arranged between the other side of the module substrate and the outermost upper package of the first row, and between the other side and the outermost upper package of the second row; a first passive component comprising a first portion and a second portion, wherein a first portion of the first passive element is disposed between a bottom surface of one of the upper packages in the second row and a top surface of the module substrate, and a second portion of the first passive element is disposed in the first region and is not disposed between the bottom surface of the one of the upper packages in the second row and the top surface of the module substrate; a second passive component comprising a first portion and a second portion, wherein a first portion of the second passive element is disposed between a bottom surface of one of the upper packages in the first row and a top surface of the module substrate, and a second portion of the second passive element is disposed in the second region and is not disposed between the bottom surface of the one of the upper packages in the first row and the top surface of the module substrate; and a third passive component, comprising a first portion and a second portion, wherein a first portion of the third passive element is disposed between a bottom surface of the outermost upper package of the first row and a top surface of the module substrate, and a second portion of the third passive element is disposed in the third region and is not disposed between a bottom surface of the outermost upper package of the first row and a top surface of the module substrate.

2. The semiconductor module according to claim 1, further comprising: a plurality of tabs disposed on the top surface of the module substrate adjacent to the first side, Wherein, in the perspective of the plan view, the first area is arranged between the plurality of protrusions and the upper package of the second row, wherein the upper package of the second row is closer to the plurality of protrusions than the upper package of the first row, and The other side of the module substrate extends in a direction different from the first direction and is adjacent to the first side.

3. The semiconductor module according to claim 2, in, The upper packages of the first row have a long axis parallel to the second direction, wherein the upper package of the second row has a long axis parallel to the first direction, and The second direction is perpendicular to the first direction.

4. The semiconductor module according to claim 2, in, A minimum distance between the plurality of protrusions and the plurality of upper packages is smaller than a minimum distance between the second side of the module substrate and the plurality of upper packages, and The second side of the module substrate is opposite to the first side.

5. The semiconductor module according to claim 1, further comprising: a plurality of lower packages disposed on the bottom surface of the module substrate and arranged in a plurality of additional rows extending in the first direction, Wherein, the lower packages belonging to a first row of the plurality of additional rows are arranged to be shifted in the first direction relative to the lower packages belonging to a second row of the plurality of additional rows.

6. The semiconductor module according to claim 1, wherein: Each of the plurality of upper packages comprises: Package substrate; a memory chip mounted on the packaging substrate; and A molding layer covers the memory chip on the packaging substrate.

7. The semiconductor module according to claim 1, further comprising: a connecting portion disposed between the one upper package in the second row of upper packages and the first passive element, The first passive element is connected to the one upper package in the second row of upper packages through the connecting portion.

8. A semiconductor module, comprising: a module substrate having a first side, a second side opposite to the first side, a third side adjacent to the first side, a fourth side opposite to the third side, and a first region; a plurality of tabs disposed on a top surface of the module substrate adjacent to the first side; a plurality of memory packages mounted on the top surface of the module substrate and arranged in a plurality of rows extending in a first direction; as well as a passive component, comprising a first portion and a second portion, and mounted on the top surface of the module substrate, wherein the first side of the module substrate extends in the first direction, Wherein, the plurality of memory packages include: a plurality of first packages arranged in a first row belonging to the plurality of rows in plan view; and a plurality of second packages arranged in a second row belonging to the plurality of rows in a plan view, wherein the plurality of second packages are closer to the plurality of tabs than the plurality of first packages, Wherein, from the perspective of the plan view, the first area is arranged between the plurality of protrusions and the plurality of second packages, and wherein the first portion of the passive element is disposed between a bottom surface of one of the plurality of second packages and a top surface of the module substrate, and the second portion of the passive element is disposed in the first region and not between the bottom surface of the one of the plurality of second packages and the top surface of the module substrate.

9. The semiconductor module according to claim 8, in, at least one memory package of the plurality of memory packages belongs to a first group, and other memory packages of the plurality of memory packages belong to a second group, and memory packages of the second group are closer to the fourth side of the module substrate than memory packages of the first group, Wherein, the plurality of convex pieces include: a plurality of first tabs adjacent to the third side; and a plurality of second protrusions, closer to the fourth side than the plurality of first protrusions, The plurality of first tabs are electrically connected to the memory packages of the first group, and the plurality of second tabs are electrically connected to the memory packages of the second group.

10. The semiconductor module according to claim 9, in, In the first group, the plurality of first packages are shifted relative to the plurality of second packages in the first direction, and in the second group, the plurality of first packages are shifted relative to the plurality of second packages in a direction opposite to the first direction.

11. The semiconductor module according to claim 10, further comprising: a logic package mounted on the top surface of the module substrate, In the plan view, the logic package is disposed between the memory packages of the first group and the memory packages of the second group.

12. The semiconductor module according to claim 11, wherein The plurality of tabs further comprises: A third bump is disposed between the plurality of first bumps and the plurality of second bumps, wherein the third bump is electrically connected to the logic package.

13. The semiconductor module according to claim 11, further comprising: A semiconductor device is mounted on the top surface of the module substrate, wherein the semiconductor device includes a serial presence detect chip.

14. The semiconductor module according to claim 8, in, A minimum distance between the third side and the plurality of first packages is smaller than a minimum distance between the third side and the plurality of second packages, and Wherein, a minimum distance between the fourth side and the plurality of first packages is smaller than a minimum distance between the fourth side and the plurality of second packages.

15. A semiconductor module, comprising: a module substrate having a first side extending in a first direction and a second side extending in the first direction; a plurality of tabs disposed on a top surface of the module substrate adjacent to the first side; a plurality of memory packages mounted on the top surface of the module substrate and arranged in a plurality of rows extending in the first direction; as well as a passive component, comprising a first portion and a second portion, and mounted on the top surface of the module substrate, Wherein, the plurality of memory packages include: a plurality of first packages arranged in a first row belonging to the plurality of rows in plan view; and a plurality of second packages arranged in a second row belonging to the plurality of rows in plan view, wherein the plurality of second packages are closer to the plurality of protrusions than the plurality of first packages, each of the plurality of first packages has a long axis parallel to a second direction, and each of the plurality of second packages has a long axis parallel to the first direction, the second direction being perpendicular to the first direction, Wherein, from the perspective of the plan view, the area of ​​the module substrate is arranged between the plurality of first packages and the plurality of second packages, and wherein the first portion of the passive element is disposed between a bottom surface of a first package among the plurality of first packages and a top surface of the module substrate, and the second portion of the passive element is disposed in the region and not between a bottom surface of a second package among the plurality of second packages and a top surface of the module substrate.

16. The semiconductor module according to claim 15, in, The module substrate also has a third side adjacent to the first side and a fourth side opposite to the third side, and Wherein, a minimum distance between the third side and the plurality of first packages is smaller than a minimum distance between the third side and the plurality of second packages.

17. The semiconductor module according to claim 16, wherein: A minimum distance between the fourth side and the plurality of first packages is smaller than a minimum distance between the fourth side and the plurality of second packages.

18. The semiconductor module according to claim 15, wherein: A minimum distance between the plurality of tabs and the plurality of memory packages is less than a minimum distance between the second side of the module substrate and the plurality of memory packages.

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