Substrate, semiconductor device package, and method of manufacturing the same

Abstract

A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent the first surface of the second dielectric layer. Wherein a width of the first end of the first conductive via is less than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is less than the width of the first end of the first conductive via.

Description

Technical Field

[0001] This disclosure generally relates to a substrate, a semiconductor device package, and a method for manufacturing the same. Background Technology

[0002] In semiconductor device packaging, conductive vias can serve as electrical interconnects between different patterned conductive layers. The patterned conductive layers may have conductive vias and via pads. The size of the via pad depends on the size of the conductive via. The size of the via pad may be related to the layout of the patterned conductive layers (e.g., width, spacing, etc.). The via pad may have notches / recesses or protrusions created during manufacturing, which may adversely affect structures subsequently formed on it (e.g., another conductive via). To address these issues, the via pad can be extended to have a relatively flat or smooth surface to accommodate structures formed thereon. However, such solutions may increase the size of the semiconductor device package. Summary of the Invention

[0003] In some embodiments, according to one aspect, a substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface adjacent to the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite to the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. The width of the first end of the first conductive via is smaller than the width of the second end of the first conductive via, and the width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.

[0004] In some embodiments, according to another aspect, a device package includes a substrate and a die on the substrate. The substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface adjacent to the first dielectric layer. The substrate further includes a first conductive via embedded in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite to the first end, and a second conductive via embedded in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. The width of the first end of the first conductive via is smaller than the width of the second end of the first conductive via, and the width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.

[0005] In some embodiments, according to another aspect, a method for manufacturing a substrate includes providing a first dielectric layer having a first surface. The method further includes providing a first conductive via embedded in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite to the first end, wherein the width of the first end of the first conductive via is smaller than the width of the second end of the first conductive via. The method further includes providing a second dielectric layer having a first surface adjacent to the first surface of the first dielectric layer. The method further includes removing a portion of the second dielectric layer to expose a portion of the first end of the first conductive via. The method further includes providing a second conductive via within the removed portion of the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer; wherein the width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, various aspects of this disclosure will be readily understood from the following detailed description. It should be noted that the various components may not be drawn to scale, and the dimensions of the various components may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1A This is a schematic diagram illustrating a cross-sectional view of a substrate according to some embodiments of the present disclosure.

[0008] Figure 1B This is a schematic diagram illustrating a portion of a semiconductor package structure according to some embodiments of the present disclosure.

[0009] Figure 1C This is a schematic diagram illustrating a portion of a semiconductor package structure according to some embodiments of the present disclosure.

[0010] Figure 1D This is a schematic diagram illustrating a portion of a semiconductor package structure according to some embodiments of the present disclosure.

[0011] Figure 1E This is a schematic diagram illustrating a portion of a semiconductor package structure according to some embodiments of the present disclosure.

[0012] Figure 1F This is a schematic diagram illustrating a portion of a semiconductor package structure according to some embodiments of the present disclosure.

[0013] Figure 1G This is a schematic diagram illustrating a portion of a semiconductor package structure according to some embodiments of the present disclosure.

[0014] Figure 1H This is a schematic diagram illustrating a cross-sectional view of a substrate according to some embodiments of the present disclosure.

[0015] Figure 1IThis is a schematic diagram illustrating a portion of a semiconductor package structure according to some embodiments of the present disclosure.

[0016] Figure 1J This is a schematic diagram illustrating a portion of a semiconductor package structure according to some embodiments of the present disclosure.

[0017] Figure 1K This is a schematic diagram illustrating a portion of a semiconductor package structure according to some embodiments of the present disclosure.

[0018] Figure 1L This is a schematic diagram illustrating a cross-sectional view of a substrate according to some embodiments of the present disclosure.

[0019] Figure 2A This is a schematic diagram illustrating a cross-sectional view of a substrate according to some embodiments of the present disclosure.

[0020] Figure 2B This is a schematic diagram illustrating a cross-sectional view of a substrate according to some embodiments of the present disclosure.

[0021] Figure 2C This is a schematic diagram illustrating a cross-sectional view of a substrate according to some embodiments of the present disclosure.

[0022] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H , Figure 3I , Figure 3K , Figure 3L and Figure 3M Methods for manufacturing substrates according to some embodiments of the present disclosure are described.

[0023] Figure 3J This is an explanation Figure 3I A schematic diagram of a portion of the substrate within the dashed box A.

[0024] Figure 3N A cross-sectional view of a substrate according to some embodiments of the present disclosure is shown.

[0025] Figure 3O A cross-sectional view of a substrate according to some embodiments of the present disclosure is shown.

[0026] Figure 3P A cross-sectional view of a substrate according to some embodiments of the present disclosure is shown.

[0027] Figure 4 This is a schematic diagram illustrating a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0028] Figure 4A , Figure 4B , Figure 4C , Figure 4D as well as Figure 4E A method for manufacturing a semiconductor device package according to some embodiments of the present disclosure is described.

[0029] Figure 5A This is a schematic diagram illustrating a cross-sectional view of a substrate according to some embodiments of the present disclosure.

[0030] Figure 5B This is a schematic diagram illustrating a cross-sectional view of a substrate according to some embodiments of the present disclosure.

[0031] Figure 5C This is a schematic diagram illustrating a cross-sectional view of a substrate according to some embodiments of the present disclosure. Detailed Implementation

[0032] Embodiments of this disclosure and their use are discussed in detail below. However, it should be understood that the embodiments illustrate many applicable concepts that can be embodied in a wide variety of specific contexts. It should be understood that the following disclosure provides many different embodiments or instances of different features implementing various embodiments. Specific examples of components and arrangements are described below for illustrative purposes. Of course, these are merely examples and are not intended to be limiting.

[0033] Spatial descriptions containing terms such as "above," "below," "up," "left," "right," "down," "top," "bottom," "vertical," "horizontal," "side," "higher," "lower," "upper," "over," and "under," unless otherwise specified, are used herein in relation to the orientation shown in the corresponding figures. It should be understood that the spatial descriptions used herein are for illustrative purposes, and actual embodiments of the structures described herein can be arranged spatially in any orientation or manner, provided that the advantages of the embodiments of this disclosure are not affected by such arrangement.

[0034] The following uses specific language to disclose the embodiments or examples illustrated in the figures. However, it will be understood that the embodiments and examples described are not intended to be limiting. As will be apparent to those skilled in the art, any changes and modifications to the disclosed embodiments and any further application of the principles disclosed herein fall within the scope of this disclosure.

[0035] Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed herein.

[0036] This disclosure provides a substrate, a semiconductor device package, and a method for manufacturing the same. Embodiments of the methods and structures described herein provide relatively small vias. The relatively small vias reduce the size of the via pads, and therefore reduce the spacing of the patterned conductive layers formed. The novel interconnect scheme provides better electrical connectivity in the semiconductor device package. Interfaces between or near two stacked vias avoid voids or gaps.

[0037] Figure 1A This is a schematic diagram illustrating a cross-sectional view of a substrate according to some embodiments of the present disclosure. Reference Figure 1A The substrate includes a dielectric layer 120, a dielectric layer 140, a patterned conductive layer 110 on one surface of the dielectric layer 120, a patterned conductive layer 130 embedded / buried in the dielectric layer 120, and a patterned conductive layer 150 on the dielectric layer 140.

[0038] refer to Figure 1A The thickness of dielectric layer 140 is less than the thickness of dielectric layer 120. Dielectric layer 120 may contain (but is not limited to) molding compounds or prepreg composite fibers (e.g., prepregs). Dielectric layer 140 is similar to or the same as dielectric layer 120. In other embodiments of this application, dielectric layer 140 may differ from dielectric layer 120. Examples of molding compounds may contain (but are not limited to) epoxy resin in which fillers are dispersed. Examples of prepregs may contain (but are not limited to) multilayer structures formed by stacking or laminating a plurality of prepreg materials / sheets.

[0039] In some embodiments, dielectric layer 120 comprises polypropylene (PP) or Ajinomoto build-up film (ABF). In some embodiments, dielectric layer 140 comprises a photosensitive dielectric material. In some embodiments, dielectric layer 140 comprises polyimide (PI) or polyacrylate (PA).

[0040] The patterned conductive layer 110 is a conductive material such as a metal or metal alloy, or contains a conductive material such as a metal or metal alloy. Examples include gold (Au), silver (Ag), aluminum (Al), copper (Cu), or alloys thereof. In some embodiments, the patterned conductive layer 110 includes a conductive foil layer 110a, a seed layer 110b, and a conductive layer 110c. In some embodiments, the substrate includes a conductive via 112 integrally formed with the conductive layer 110c. The conductive via 112 includes an end 112t and an end 112s opposite to the end 112t. In some embodiments, the width of the end 112t is greater than the width of the end 112s. In some embodiments, in a cross-sectional view, a portion of the conductive via 112 includes a trapezoidal shape. In some embodiments, the patterned conductive layer 110 includes a via pad 111 integrally formed with the conductive via 112.

[0041] In some embodiments, the substrate includes a trace 131 at least partially embedded in / surrounded by a conductive via 112. In some embodiments, the trace 131 is at least partially embedded in / surrounded by a seed layer 110b. Reference Figure 1A The substrate further includes a conductive via 152 integrally formed with the patterned conductive layer 150. The conductive via 152 is smaller in size than the conductive via 112.

[0042] refer to Figure 1A The conductive via 152 includes an end 152t and an end 152s opposite to the end 152t. In some embodiments, the width of the end 152s is greater than the width of the trace 131. In some embodiments, the width of the end 152t is greater than the width of the end 152s. In some embodiments, in a cross-sectional view, a portion of the conductive via 152 includes a trapezoidal shape.

[0043] Patterned conductive layers 130 and 150 are, for example, conductive materials such as metals or metal alloys, or contain conductive materials such as metals or metal alloys. Examples include gold (Au), silver (Ag), aluminum (Al), copper (Cu), or alloys thereof. In some embodiments, patterned conductive layer 130 includes a plurality of traces and / or pads. In some embodiments, the spacing of patterned conductive layer 130 is P1. In some embodiments, patterned conductive layer 150 includes a plurality of traces and / or pads 151. In some embodiments, the spacing of patterned conductive layer 150 is P2. In some embodiments, spacing P1 is greater than spacing P2. Figure 1A The dashed boxes A and B, as well as the dashed circle C, will be discussed further in subsequent paragraphs.

[0044] It should be noted that, Figure 1AIn the illustrated embodiment, no via pads are provided at the interface between dielectric layers 120 and 140. That is, the fabrication of the patterned conductive layer 130 does not include forming via pads together with the patterned conductive layer 130. The elimination of via pads can therefore reduce the spacing of the patterned conductive layer 130.

[0045] Figure 1B This is a schematic diagram illustrating a portion of a semiconductor package structure according to some embodiments of the present disclosure. Figure 1B illustrate Figure 1A The top view of the structure within the dashed box A. (Reference) Figure 1B The area occupied by end 112s is larger than the area occupied by end 152s, and the area occupied by end 152s is within the area occupied by end 112s.

[0046] Figure 1C This is a schematic diagram illustrating a portion of a semiconductor package structure according to some embodiments of the present disclosure. Figure 1C illustrate Figure 1A A top view of the exemplary structure within dashed box B. (Reference) Figure 1C A portion of trace 131 is enclosed by conductive vias 112 and 152, and a portion of trace 131 extends beyond end 112s. (See reference) Figure 1C The area occupied by end 112s is larger than the area occupied by end 152s, and the area occupied by end 152s is within the area occupied by end 112s.

[0047] Figure 1D This is a schematic diagram illustrating a portion of a semiconductor package structure according to some embodiments of the present disclosure. Figure 1D illustrate Figure 1A A top view of the exemplary structure within dashed box B. (Reference) Figure 1D Trajectory 131 forms a physical connection between conductive via 112 and conductive via 152. In some embodiments, the area occupied by end 112s does not overlap with the area occupied by end 152s.

[0048] Figure 1E This is a schematic diagram illustrating a portion of a semiconductor package structure according to some embodiments of the present disclosure. Figure 1E illustrate Figure 1A The exemplary structure within the dashed circle C. (Reference) Figure 1E The through-hole pad 111 has a generally flat surface. Figure 1F This is a schematic diagram illustrating a portion of a semiconductor package structure according to some embodiments of the present disclosure. Figure 1F illustrate Figure 1A The exemplary structure within the dashed circle C. (Reference) Figure 1F The through-hole pad 111 includes a recess / notch 144 created by manufacturing. Figure 1GThis is a schematic diagram illustrating a portion of a semiconductor package structure according to some embodiments of the present disclosure. Figure 1G illustrate Figure 1A The exemplary structure within the dashed circle C. (Reference) Figure 1G The through-hole pad 111 includes a protrusion 116 created during manufacturing.

[0049] Figure 1H This is a schematic diagram illustrating a cross-sectional view of a substrate according to some embodiments of the present disclosure. Reference Figure 1H The semiconductor package structure includes a dielectric layer 120, a dielectric layer 140, and a patterned conductive layer 130 embedded / buried in the dielectric layer 120. Figure 1H The dashed box A includes a conductive via 152 that is integrally formed with the trace 151 and stacked on a conductive via 112 that is integrally formed with the via pad 111. Figure 1H The dashed box B includes a conductive via 152 that is integrally formed with the trace 151 and stacked on a conductive via 112 that is integrally formed with the via pad 111. Figure 1H The dashed box B further includes traces 131 that are at least partially embedded in / surrounded by the conductive via 112. Figure 1H The dashed box C includes a conductive via 152 integrally formed with and stacked on the trace 137. The trace 137 is at least partially embedded in / surrounded by the conductive via 112, and a connection is formed between the conductive via 112 and 152. Figure 1H The dashed boxes A, B, and C will be discussed further in subsequent paragraphs.

[0050] Figure 1I This is a schematic diagram illustrating a portion of a semiconductor package structure according to some embodiments of the present disclosure. Figure 1I illustrate Figure 1H The top view of the structure within the dashed box A. (Reference) Figure 1I The area occupied by end 112s is larger than the area occupied by end 152s, and the area occupied by end 152s is within the area occupied by end 112s. In some embodiments, one terminal of trace 151 contacts through hole 152, and the other terminal of trace 151 extends in a first direction.

[0051] Figure 1J This is a schematic diagram illustrating a portion of a semiconductor package structure according to some embodiments of the present disclosure. Figure 1J illustrate Figure 1H The diagram shows a top view of the structure within the dashed box B. In some embodiments, one terminal of trace 131 contacts through holes 112 and 152, and the other terminal of trace 131 extends in a first direction. In some embodiments, one terminal of trace 151 contacts through hole 152, and the other terminal of trace 151 extends in a cross-sectional direction.

[0052] Figure 1K This is a schematic diagram illustrating a portion of a semiconductor package structure according to some embodiments of the present disclosure. Figure 1K illustrate Figure 1H The top view of the structure within the dashed box C. (Reference) Figure 1K Trace 137 includes portions 137a and 137b. The area of ​​portion 137b is larger than end 152s of via 152. In some embodiments, trace 137 connects via 112 and via 152. In some embodiments, one terminal of trace 151 contacts conductive via 152, and the other terminal of trace 151 extends in a first direction. In some embodiments, trace 151' is disposed above conductive via 112 and portion 137a but does not contact conductive via 112 and portion 137a.

[0053] Figure 1L This is a schematic diagram illustrating a cross-sectional view of a substrate according to some embodiments of the present disclosure. Reference Figure 1L The semiconductor package structure includes several dielectric layers, via pads 111, conductive vias 112, conductive vias 152, traces 151, conductive vias 152', traces 151', and electrical connection elements 184. In some embodiments, the via pads 111 are integrally formed with the conductive vias 112. In some embodiments, the via pads 111 are formed before or after the conductive vias 112 are formed. In some embodiments, the traces 151 are at least partially embedded / buried in the conductive vias 152'. In some embodiments, the traces 151' are at least partially embedded / buried in the electrical connection elements 184.

[0054] In some embodiments, in a cross-sectional view, conductive vias 112, 152, and 152' each comprise a trapezoidal shape. In some embodiments, the width of the upper edge of conductive via 152 is greater than the width of the bottom edge of conductive via 152. In some embodiments, the width of the upper edge of conductive via 152' is greater than the width of the bottom edge of conductive via 152'. In some embodiments, the width of the upper edge of conductive via 112 is less than the width of the bottom edge of conductive via 112.

[0055] Figure 2A This is a schematic cross-sectional view illustrating a substrate according to some embodiments of the present disclosure. The substrate includes a dielectric layer 220, a dielectric layer 240, and a conductive via 212. (See reference...) Figure 2A The opening is formed in the dielectric layer 240 before the conductive layer is formed. In some embodiments, the opening is formed using laser drilling technology. In some embodiments, the opening is formed using photolithography technology. Figure 2AIn the illustrated embodiment, the width of the bottom surface 252s of the opening is smaller than the width of the upper surface 212s of the conductive via 212.

[0056] Since the width of the bottom surface 252s of the opening is smaller than the width of the upper surface 212s of the conductive via 212, damage to the dielectric layer 220 that is close to or surrounds the upper surface 212s of the conductive via 212 can be avoided during the formation of the opening.

[0057] Figure 2B This is a schematic diagram illustrating a cross-sectional view of a substrate according to some embodiments of the present disclosure. Figure 2B In the embodiment shown, the width of the bottom surface 252s of the opening is substantially equal to the width of the upper surface 212s of the conductive via 212. During the fabrication of the opening, if the opening is not perfectly aligned with the conductive via 212, the center of the opening will be displaced by a distance d relative to the center of the conductive via 212. In this case, a portion of the dielectric layer 220 shown in dashed circle 2A may be damaged during laser drilling or photolithography processes during the formation of the opening, potentially adversely affecting the performance of the semiconductor substrate. For example, voids or cracks may be seen at or near the interface between the two dielectric layers.

[0058] Figure 2C This is a schematic diagram illustrating a cross-sectional view of a substrate according to some embodiments of the present disclosure. Figure 2C In the embodiment shown, the width of the bottom surface 252s of the opening is greater than the width of the upper surface 212s of the conductive via 212. In this case, a portion of the dielectric layer 220 shown in dashed circle 2B is easily damaged during laser drilling or photolithography processes during opening formation, potentially adversely affecting the performance of the semiconductor substrate. For example, voids or cracks may be seen at or near the interface between the two dielectric layers.

[0059] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H , Figure 3I , Figure 3K , Figure 3L and Figure 3M Methods for manufacturing substrates according to some embodiments of the present disclosure are described.

[0060] refer to Figure 3AA carrier 300 is provided, and a conductive layer 312 is disposed on the surface of the carrier 300. The conductive layer 312 is, for example, a conductive material such as a metal or a metal alloy, or contains a conductive material such as a metal or a metal alloy. Examples include gold (Au), silver (Ag), aluminum (Al), copper (Cu), or alloys thereof.

[0061] refer to Figure 3B A patterned layer 314 is formed on the conductive layer 312. In some embodiments, the patterned layer 314 is formed by an electroplating process. In some embodiments, the patterned layer 314 includes conductive pads and / or conductive traces. The patterned layer 314 is, for example, a conductive material such as a metal or metal alloy, or contains a conductive material such as a metal or metal alloy. Examples include gold (Au), silver (Ag), aluminum (Al), copper (Cu), or alloys thereof.

[0062] refer to Figure 3C A dielectric layer 316 is formed above a patterned layer 314 and encapsulates the patterned layer 314 and the conductive layer 312. A conductive foil layer 318a is formed on the dielectric layer 316. The conductive foil layer 318a may contain conductive materials such as copper (Cu), other conductive metals, alloys, or other suitable materials.

[0063] refer to Figure 3D An opening 320 is formed on dielectric layer 316. (Reference) Figure 3D The trace 330 is exposed through the opening 320. In some embodiments, the opening 320 is formed using laser drilling technology. In some embodiments, the opening 320 is formed using photolithography technology. In some embodiments, forming the opening 320 includes using negative photoresist.

[0064] refer to Figure 3E A seed layer 318b is formed. The seed layer 318b is conformally formed above the conductive foil layer 318a, the dielectric layer 316, the trace 330, and the opening 312. (Reference) Figure 3E Trajectory 330 is surrounded by seed layer 318b.

[0065] refer to Figure 3F A metal deposition process is performed, and a patterned conductive layer 318c is formed above the seed layer 318b. A conductive via 352 is integrally formed with the conductive layer 318c within an opening 320. The conductive foil layer 318a, the seed layer 318b, and the conductive layer 318c will be referred to as the conductive layer 318.

[0066] refer to Figure 3G A portion of the conductive foil layer 318a and the seed layer 318b is removed from the upper surface of the dielectric layer 316. In some embodiments, an etching technique is used to remove a portion of the conductive foil layer 318a and the seed layer 318b.

[0067] refer to Figure 3HBy removing Figure 3G The carrier 300 is used to obtain the package P1. A protective layer 350 is formed on the dielectric layer 316 and encapsulates the conductive layer 318 and the conductive via 352.

[0068] refer to Figure 3I Before removing the protective layer 350 using a stripping process, the conductive layer 312 is removed using an etching technique. The protective layer 350 prevents the conductive layer 318 and the conductive via 352 from being damaged during the etching process.

[0069] Figure 3J This is an explanation Figure 3I A schematic diagram of a portion of the substrate within the dashed box A. This portion of the substrate includes a dielectric layer 316, a trace 314, and a conductive via 352. The conductive via 352 includes an upper surface S1. The dielectric layer 316 includes an upper surface S2. The trace 314 includes an upper surface S3. In some embodiments, surfaces S1, S2, and S3 are substantially coplanar. In some embodiments, surfaces S1, S2, and S3 are not coplanar. In some embodiments, surfaces S1 and S3 are below surface S2.

[0070] See Figure 3K Dielectric layer 360 is formed on dielectric layer 316. Since the upper surface 316s of dielectric layer 316 is substantially flat (i.e., the patterned conductive layer 314 is embedded / buried in dielectric layer 316, rather than disposed on dielectric layer 316), the thickness of dielectric layer 360 can be reduced. Reference Figure 3K Compared to the thickness of dielectric layer 316, the thickness of dielectric layer 360 is smaller.

[0071] refer to Figure 3L An opening 362 is formed on the dielectric layer 316. In some embodiments, the opening 362 is formed using laser drilling technology. In some embodiments, the opening 362 is formed using photolithography technology. In some embodiments, forming the opening 362 involves using a negative photoresist. In some embodiments, the opening 362 exposes the surface of the conductive via 352. In some embodiments, the opening 362 exposes the surface of the trace 330 and a portion of the conductive via 352.

[0072] As mentioned above, because the dielectric layer 360 is thinner, the size of the opening 362 can be reduced, and thus the conductive vias formed in the opening 362 can be reduced.

[0073] refer to Figure 3M A metal deposition process is performed, and a patterned conductive layer 370 is formed above the dielectric layer 360. A conductive via 372 is integrally formed with the conductive layer 370 within the opening 362. Figure 3M The substrate produced in the process corresponds to Figure 1A The substrate shown in the image.

[0074] Figure 3N A cross-sectional view of a substrate according to some embodiments of the present disclosure is shown. Figure 3N The substrate shown in the image is similar to Figure 3M The substrate shown in the image, in addition to Figure 3N In the process, positive photoresist is used to form opening 362, and therefore the shape of conductive via 372 is consistent with... Figure 3M Apart from the different shapes shown in the images.

[0075] Figure 3O A cross-sectional view of a substrate according to some embodiments of the present disclosure is shown. Figure 3O The substrate shown in the image is similar to Figure 3M The substrate shown in the image, in addition to Figure 3O In the process, positive photoresist is used to form openings 320 and 362, and therefore the shapes of conductive vias 352 and 372 are consistent with... Figure 3M Apart from the different shapes shown in the images.

[0076] Figure 3P A cross-sectional view of a substrate according to some embodiments of the present disclosure is shown. Figure 3P The substrate shown in the image is similar to Figure 3M The substrate shown in the image, in addition to Figure 3P In the process, positive photoresist is used to form the opening 320, and therefore the shape of the conductive via 342 is consistent with... Figure 3M Apart from the different shapes shown in the images.

[0077] Figure 4 This is a schematic diagram illustrating a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure. Figure 4 The semiconductor device package shown includes dielectric layers 440, 460, and 480; patterned conductive layers 430, 450, and 470; conductive vias 412, 432, 472, and 474; electrical connection element 484; underfill layer 492; and die 490. (Reference) Figure 4 Conductive via 412 includes via pad 410, and conductive via 432 includes via pad 434. Patterned conductive layer 430 is embedded / buried in dielectric layer 460. Patterned conductive layer 450 is embedded / buried in dielectric layer 440. Patterned conductive layer 470 is embedded / buried in dielectric layer 480.

[0078] Conductive via 432 is integrally formed with patterned conductive layer 430. Conductive via 472 is integrally formed with patterned conductive layer 470. Die 490 is electrically connected to conductive via 472 via electrical connection element 484. Underfill layer 492 is disposed between die 490 and dielectric layer 480. In some embodiments, underfill 492 comprises epoxy resin, molding compound (e.g., epoxy molding compound or other molding compound), polyimide, phenolic compound or material, material comprising silicone dispersed therein, or combinations thereof.

[0079] Figure 4A , Figure 4B , Figure 4C , Figure 4D as well as Figure 4E A method for manufacturing a semiconductor device package according to some embodiments of the present disclosure is described.

[0080] refer to Figure 4A A substrate is provided. The substrate includes dielectric layers 440 and 460, patterned conductive layers 430 and 450, and conductive vias 432. The patterned conductive layer 430 includes a conductive foil layer 430a, a seed layer 430b, and a conductive layer 430c.

[0081] refer to Figure 4B An opening 462 is formed in the dielectric layer 460. In some embodiments, the opening 462 is formed using laser drilling technology. In some embodiments, the opening 462 is formed using photolithography technology. Figure 4B For simplicity, the patterned conductive layer 430 is shown as a single layer.

[0082] refer to Figure 4C A metal deposition process is performed to form a conductive via 412. The conductive via 412 includes a via pad 410. A metal deposition process is then performed to form a patterned conductive layer 470. Conductive vias 472 and 474 are integrally formed within an opening 462 and the conductive layer 470. In some embodiments, the conductive via 472 includes a via pad on its top. In some embodiments, the conductive via 474 includes a trace on its top.

[0083] refer to Figure 4D Dielectric layer 480 is formed on dielectric layer 460. A portion of dielectric layer 480 is removed to expose the surfaces of conductive vias 412 and 472.

[0084] refer to Figure 4E Electrical connection element 484 is disposed on conductive via 472. Electrical connection element 484 will then be used as a connector between conductive via 472 and die 490.

[0085] Figure 5AThis is a schematic cross-sectional view illustrating a substrate according to some embodiments of the present disclosure. The substrate includes dielectric layers 54 and 56, patterned conductive layers 51, 53 and 57, and conductive vias 52 and 55. Conductive via 52 includes portions 52a and 52b. Conductive via 55 includes portions 55a and 55b. (Reference) Figure 5A Part 52b includes a generally flat surface, and conductive vias 55 are stacked on conductive vias 52. In some embodiments, part 52b is a via pad. The presence of part 52b will adversely affect the layout (e.g., width, spacing, etc.) of the patterned conductive layer 57.

[0086] Figure 5B This is a schematic cross-sectional view illustrating a substrate according to some embodiments of the present disclosure. The substrate includes dielectric layers 54 and 56, patterned conductive layers 51 and 53, and conductive vias 52 and 55. In some embodiments, conductive via 52 includes portions 52a, 52b, and 52c. Conductive via 55 includes portions 55a, 55b, and 55c. Portion 52c is a protrusion created during manufacturing, which may adversely affect structures subsequently formed thereon. For example, conductive via 55 subsequently formed on conductive via 52 will necessarily include the protruding portion 55c.

[0087] In some embodiments, the conductive via 52 includes a notch / recess 52d created by manufacturing, which may adversely affect the structure subsequently formed thereon. For example, a conductive via 55 subsequently formed on the conductive via 52 will necessarily include a notch / recess 55d.

[0088] Figure 5C This is a schematic diagram illustrating a cross-sectional view of a substrate according to some embodiments of the present disclosure. Figure 5C In the embodiments shown, the conductive via 52 includes a protrusion 52c or a notch / recess 52d created by manufacturing. To avoid notches / recesses or protrusions formed on the conductive via 55, the position of the conductive via 55 must be moved. In some embodiments, the conductive via 55 is disposed on a portion 52b. In some embodiments, the portion 52b is a via pad. The presence of the portion 52b will adversely affect the layout (e.g., width, spacing, etc.) of the patterned conductive layer formed between dielectric layers 54 and 56.

[0089] As used herein, unless the context clearly indicates otherwise, the singular terms “a” and “the” may include a plural of indicators. In the description of some embodiments, the phrase “above” or “over” one component may cover situations where the preceding component is directly on the following component (e.g., in physical contact with the following component), and situations where one or more intermediate components are located between the preceding and following components.

[0090] As used herein, the terms “generally,” “approximately,” and “about” are used to describe and account for small variations. When used in conjunction with an event or situation, the terms may refer to a situation in which the event or situation has clearly occurred or is very close to occurring. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, the term “about” or “generally” equal to two values ​​may refer to a ratio between 0.9 and 1.1, inclusive.

[0091] Additionally, quantities, ratios, and other values ​​are sometimes presented in range format in this document. It should be understood that such range format is used for convenience and brevity, and should be flexibly interpreted to include not only values ​​explicitly specified as range limits, but also all individual values ​​or subranges covered within the range, as if each value and subrange were explicitly specified.

[0092] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not intended to limit the disclosure. Those skilled in the art will understand that various changes and substitutions for equivalents may be made without departing from the true spirit and scope of the disclosure as defined by the appended claims. The illustrations may not be drawn to scale. Artistic representations in this disclosure may differ from actual devices due to manufacturing processes and tolerances. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not a limitation of this disclosure.

Claims

1. A substrate comprising: A first dielectric layer having a first surface; The second dielectric layer has a first surface configured to be adjacent to the first surface of the first dielectric layer, wherein the second dielectric layer is different from the first dielectric layer, the thickness of the second dielectric layer is less than the thickness of the first dielectric layer, and no through-hole pads are provided at the interface between the first dielectric layer and the second dielectric layer. A first conductive via is disposed in the first dielectric layer and has a first end adjacent to the first surface of the first dielectric layer and a second end opposite to the first end, wherein the width of the first end of the first conductive via is smaller than the width of the second end of the first conductive via and the width of any segment of the first conductive via. as well as A second conductive via is disposed in the second dielectric layer and has a first end adjacent to the first surface of the second dielectric layer, wherein the width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via. A first patterned conductive layer is embedded in the first surface of the first dielectric layer; as well as A second patterned conductive layer is disposed on a second surface of the second dielectric layer, wherein the spacing of the second patterned conductive layer is smaller than the spacing of the first patterned conductive layer.

2. The substrate according to claim 1, wherein the second conductive via further includes a second end opposite to the first end of the second conductive via, and the width of the second end is greater than the width of the first end of the second conductive via.

3. The substrate according to claim 1, wherein the second dielectric layer has an opening penetrating the first surface of the second dielectric layer, the second conductive via is disposed in the opening, and the width of the bottom surface of the opening is less than the width of the upper surface of the first end of the first conductive via.

4. The substrate according to claim 1, wherein the first end of the first conductive via occupies a first region and the first end of the second conductive via occupies a second region, wherein the second region is within the first region, and both the first region and the second region are adjacent to the interface between the first dielectric layer and the second dielectric layer.

5. The substrate of claim 1, further comprising a first trace at least partially embedded in the first conductive via and a second trace located above the second dielectric layer, wherein a portion of the first trace contacts the first end of the second conductive via to be electrically connected to the second trace, and the area of ​​the portion of the first trace is larger than the area of ​​the first end of the second conductive via.

6. The substrate according to claim 1, further comprising a seed layer disposed between the first conductive via and the second conductive via, wherein the seed layer contacts the first end of the second conductive via and the first end of the first conductive via.

7. The substrate according to claim 5, further comprising a seed layer disposed between the first trace and the first conductive via.

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