Encapsulated semiconductor device

Abstract

The present application discloses a packaged semiconductor device. The packaged semiconductor device (300) includes a molded interconnect substrate having a signal layer (221) and a bottom metal layer (223), the signal layer including first and second channels on a dielectric layer (222) having vias, the bottom metal layer for providing a ground return path. The signal layer includes contact pads, the traces of the first and second channels including narrowed trace regions (221s), and the bottom metal layer including a patterned layer having a ground cut region (223a). DC blocking capacitors (C1, C2, C3, C4) are serially connected within the traces of the first and second channels for providing AC coupling, the DC blocking capacitors having one plate above a ground cut. An integrated circuit (IC) (210) includes first and second differential input channels coupled to receive outputs from the DC blocking capacitors, wherein a bump array (218) thereon is flip-chip mounted to the contact pads to provide first and second differential output signals.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of Provisional Application Serial No. 62 / 675,396, filed on May 23, 2018, entitled "MIS Multi - Layer FC - QFN Package Structure for High - Speed (56Gbps +) Applications", the entire content of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to semiconductor devices for high - speed packaging. Background Art

[0004] Some high - speed signal / data devices, such as retimer circuits, repeaters, and clock synthesizers, are high - capacity and medium - to - high pin - count devices that are typically packaged in flip - chip ball grid array (FC BGA) packages, which are relatively high - cost packages. A cost - effective alternative is the wire - bonded BGA package. However, the electrical performance of wire - bonded BGA packages for high - speed (>5 gigabits per second (Gbps)) is relatively poor, such as having poor insertion loss and poor return loss.

[0005] Integrated circuit (IC) packages can be based on an emerging technology called molded interconnect substrate (MIS). MIS starts with a dedicated substrate material for IC package selection. MIS is developed and sold by various vendors, and then the packaging factory typically adopts MIS and assembles the IC package around it, including adding molding. Some people refer to MIS as a lead frame.

[0006] MIS is different from traditional substrates because MIS technology includes a pre - molded structure with one or more metal layers. Each layer is typically pre - configured with at least one top and one bottom copper plating, with a dielectric layer between the copper layers, and the copper layers have vias to provide electrical connections in the package. Summary of the Invention

[0007] The Summary of the Invention is provided to introduce a brief selection of the disclosed concepts in a simplified form, which will be further described in the detailed description (including the provided drawings) below. The Summary of the Invention is not intended to limit the scope of the claimed subject matter.

[0008] By developing a physical structure plus a DC-blocking capacitor in the package to provide a cheaper MIS QFN technology (with MIS tuned to provide performance similar to that of traditional FC BGA packages), the disclosed aspects address the high cost of FC BGA packages for high-speed devices (due to the need to meet high electrical performance, e.g., data rates of 56 Gbps or higher). The disclosed performance tuning includes narrowing corresponding traces on a signal layer (e.g., the negative (N) signal trace and positive (P) signal trace for each channel) and providing a bottom metal layer with ground cuts, where the narrowed signal traces extend beyond the ground cuts and each DC-blocking capacitor has one plate above a ground cut.

[0009] The disclosed aspects include a packaged semiconductor device that includes a plastic-encapsulated interconnect substrate having a signal layer and a bottom metal layer, the signal layer including a first channel and a second channel on a dielectric layer with vias, and the bottom metal layer for providing a ground return path. The signal layer includes contact pads, the traces of the first and second channels include narrowed trace regions, and the bottom metal layer includes a patterned layer with ground cut regions. DC-blocking capacitors are connected in series within the traces of the first and second channels for providing AC coupling, where each DC-blocking capacitor has one plate above one of the ground cuts. An IC includes first and second differential input channels coupled to receive outputs from the DC-blocking capacitors, and a bump array thereon is flip-chip mounted to the contact pads to provide first and second differential output signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Reference will now be made to the drawings, which are not necessarily to scale, in which:

[0011] Figure 1A is a portion of an example packaged MIS QFN-based semiconductor device without its plastic encapsulation, the device having two channels and each channel having two traces, for a total of four traces, each trace having a DC-blocking capacitor connected in series.

[0012] Figure 1B is Figure 1A a schematic diagram of a portion of the packaged MIS QFN-based semiconductor device shown in

[0013] Figure 2 is a cross-sectional view of an example packaged MIS QFN-based semiconductor device according to an example aspect, with its mold compound, showing the signal path in the signal layer for one differential input of a channel through a DC-blocking capacitor shown as C1.

[0014] Figure 3Is a close-up depiction of a portion of an example encapsulated MIS QFN-based semiconductor device without its plastic encapsulation, where a DC-blocking capacitor has been removed to show the disclosed ground cut and the disclosed "slender" trace tuning.

[0015] Figure 4A- Figure 4B Compares the simulated insertion loss between known FC BGA-based semiconductor devices in Figure 4A and Figure 4B the insertion loss in Figure 4B The insertion loss is for an original MIS QFN-based semiconductor device lacking the disclosed performance tuning and for an MIS QFN-based semiconductor device including the disclosed performance tuning. The specification to be met is an insertion loss of < 0.5 dB at 14 GHz; an insertion loss of < 15 dB (pushed to < 20 dB) at 14 GHz, where the device operates at 14 GHz (56 Gbps).

[0016] Figure 4C- Figure 4D Compares the simulated return loss between known FC BGA-based semiconductor devices in Figure 4C and Figure 4D the insertion loss in Figure 4D The return loss is for an original MIS QFN-based semiconductor device lacking the disclosed performance tuning and for an MIS QFN-based semiconductor device including the disclosed performance tuning. DETAILED DESCRIPTION

[0017] Example embodiments are described with reference to the accompanying drawings, where like reference numerals are used to represent like or equivalent elements. The illustrated ordering of acts or events should not be considered limiting, as some acts or events may occur in a different order and / or concurrently with other acts or events. Additionally, some of the illustrated acts or events may not be required to implement the method according to the present disclosure.

[0018] Figure 1A Depicts a quarter (25%) of an example encapsulated MIS QFN-based semiconductor device 100, shown as a dual-channel device having a first channel and a second channel, including MIS 220, having first, second, third, and fourth direct current (DC) blocking capacitors C1, C2, C3, and C4, where each channel has two (one for the P trace and one for the N trace, or 'legs') DC blocking capacitors for providing a DC blocking capacitor for blocking low-frequency components for each input. The IC die 210 is attached to the MIS 220 via a bump array having bumps shown as 218. The bump array may include copper pillars having solder bumps located on the bonding pads of the IC die 210.

[0019] Although molding compounds are generally present for the disclosed packaged devices, Figure 1A the molding compound is not shown in Figure 1A to avoid obscuring features. Also, although not shown, there is also an input signal from the other end of the IC die 210, which is processed by the IC die 210 and then output from the first and second channels. As Figure 1B shown in the simplified schematic diagram of Figure 1B , the IC die as shown in the IC die portion 210’ has receivers (Rx) 2110, 2111 and transmitters (Tx) 2130, 2131, which are coupled together by clock data recovery (CDR) circuits 2120, 2121 for repairing the input signal and then output the repaired signal.

[0020] The packaged semiconductor device 100 can generally include any device that is AC-coupled to a high-speed signal path that travels through the MIS 220 to the IC die 210 and from the IC die 210 through the MIS 220. For example, high-speed signal regulators such as signal retimers, or signal repeaters used in high-performance computing farm applications. The disclosed MIS QFN-based semiconductor device can be tuned for use in any serializer / deserializer (Serdes) or high-speed channel in general.

[0021] The MIS 220 includes a signal layer 221 providing a top surface and a bottom metal layer 223. The signal layer 211 includes contact pads located on a dielectric layer 222 having vias, and the bottom metal layer 223 provides a ground return path, which can also be used for additional signal traces. The traces on the signal layer 221 that reach the bottom metal layer through the vias in the dielectric layer 222 will be the physical bottom of the packaged MIS QFN-based semiconductor device, which the customer will typically solder ( Figure 1A The patterned solder layer is not shown in Figure 1A , but see the patterned solder layer 219 in Figure 2 described below) to its printed circuit board (PCB) 240 as shown in the PCB 240. The patterned solder layer can include solder balls attached to the bottom metal layer 223 of the MIS package 220 or can include a solder paste screen printed onto the PCB 240. Although not shown, the MIS substrate 220 can include more than the 3 layers shown.

[0022] The signal layer 221 and the bottom metal layer 223 generally include copper or copper alloy. The dielectric layer 222 generally includes a molding compound as the dielectric material between the layers 221 and 223. The molding compounds known in the packaging are generally composite materials, which include epoxy resins, phenolic hardeners, silica, catalysts, pigments, and mold release agents.

[0023] MIS 220 provides a coplanar waveguide (CPW) microstrip structure. The thickness of MIS 220 can be about 80 μm, the thickness of the signal layer 221 and the bottom metal layer 223 is about 20 μm, and the thickness of the dielectric layer 222 is about 40 μm. The DC blocking capacitors typically have a capacitance of 0.05 μF to 2 μF. This capacitance range is higher than what is typically possible for capacitors on an IC, so the DC blocking capacitors are typically discrete devices from the IC. In the 0201 size (0.6 x 0.3 mm), the typical capacitance of the DC blocking capacitor is 0.22 μF.

[0024] Figure 1B is shown Figure 1A A simplified equivalent circuit of the differential input channels shown in. For each channel, there is a differential signal, which is shown as the N-trace and P-trace for each channel, shown as RX0P and RX0N for the first channel and RX1P and RX1N for the second channel. The bottom metal layer 223 provides a return path for each signal trace to provide impedance matching. The signal itself is a differential signal, i.e., N and P. The gap / width of the traces in the signal layer 221 is specifically selected to maximize the differential transmission of the signal.

[0025] At the input of the IC (shown as the IC die portion 210’), there are DC blocking capacitors C1, C2, C3, and C4. The traces on the signal layer 221, the vias in the dielectric layer 222, the bumps (see Figure 2 described below) and the interconnects in the paths connecting to the IC die portion 210’ on either side of C1, C2, C3, and C4 are represented by the solid lines shown. On the output side of the IC die portion 210’, there are two DC blocking capacitors for each channel, shown as C5, C6, C7, and C8, and the package traces on the signal layer 221, the vias in the dielectric layer 222, and the bumps (see Figure 2 described below) and the interconnects in the paths from the IC die to the DC blocking capacitors are also represented by the solid lines shown.

[0026] Figure 2FIG. 0 is a cross-sectional view of an example encapsulated MIS QFN-based semiconductor device 200 with a molding compound 260, showing a signal path labeled "signal input" with an arrow for one differential input through a channel of a DC-blocking capacitor shown as C1. The IC die 210 has a bump array (one bump 218 is identified) that is flip-chip attached (FC attached) to contact pads on the signal layer 221 of the MIS. External to the MIS QFN-based semiconductor device 200, there is a patterned solder layer 219 (such as solder balls) on the bottom metal layer 223 that is exposed from the molding compound 260 on the bottom of the MIS 220 for coupling the bottom metal layer 223 to lands on a PCB 240.

[0027] The arrow shown identifies the signal flow from the PCB 240 to the patterned solder layer 219, to the bottom metal layer 223, to a via in the dielectric layer 222, to a node on the signal layer 221, to one plate of C1. After passing through C1, the signal reaches the other plate of C1, then another node on the signal layer 221, reaches the bump 218 (e.g., a Cu pillar bump with solder), and finally reaches the IC die 210.

[0028] Figure 3 FIG. 7 is a close-up depiction of a portion of an example encapsulated MIS QFN-based semiconductor device 300 without its molding, where one DC-blocking capacitor C1 has been removed to show a disclosed ground cut 223a and a disclosed elongated trace 221s included above the ground cut 223a, both the ground cut and the elongated trace being for MIS performance tuning. The ground cut region including the shown ground cut 223a lacks the dielectric layer 222 such that the capacitor plate above the ground cut 223a has no bottom metal layer beneath it. Note that Figure 3 the blank area in FIG. 9 is filled with a dielectric, which is the molding compound (e.g., see the molding compound 260 described above in FIG. Figure 2 9).

[0029] For example, a nominal line width of 50 μm as shown can be used for signal layer 221, while the slender trace 221s can have a width of 30 μm as shown, where this particular example arrangement represents a 40% reduction in trace width for the slender trace 221s. Given device performance requirements are met by tuning that uses narrowing of the traces on signal layer 221 to provide the slender trace regions and ground cuts 223a, both of which are typically used to meet device specifications such as insertion loss and return loss at a given operating frequency. For a particular example specification, the specification is < 0.5 dB of insertion loss at 14 GHz; < 15 dB (pushed to < 20 dB) of insertion loss at 14 GHz, where the device operates at 14 GHz (56 Gbps).

[0030] The percentage range ( % range) of narrowing of the traces on signal layer 221 is from 5% to 50%, such as the slender trace 221s of 25 μm in a standard 50 μm trace width. As Figure 3 shown, the width of the traces in the first signal layer 221 can generally be 50 μm. However, when the traces in the first signal layer 221 are relatively close to the capacitor pads (one of the pads being above the ground cut region), the trace width is significantly reduced, such as 30 μm for the slender trace tuning.

[0031] It can be seen that one plate of the DC blocking capacitors shown as C2 and C3 is located above the ground cut 223a. Figure 3 The metal pads on the signal layer 221 in the shown box are used to attach one plate of C1 thereon, just as C2 and C3 are attached to the corresponding metal pads, the attachment including one of their plates above the ground cut 223a.

[0032] Regarding the tuning of the signal layer traces, the traces can be fine-tuned according to the molding compound material properties. The trace width of the slender traces of the signal layer 221 can be initially predefined by theory and / or experience, then pre-simulated by a 2D field simulator into several trace dimension candidates, and then verified by full-wave 3D simulation on their end performance. During all these steps, the molding compound properties (its dielectric constant and loss tangent) in the dielectric layer 222, as well as the desired characteristic impedance Zo are input as parameters, with the characteristic impedance Zo typically being 50 ohms for single-ended and 100 ohms for differential.

[0033] Regarding the applicable theory, the empirical equation for Zo of the microstrip line transcribed below shows how the dielectric constant is a property of the encapsulant material, as the dielectric in dielectric layer 222 affects the characteristic impedance of the traces in signal layer 221, which is considered important for impedance matching and thus for device performance. The equation for the microstrip line shows the relationship between its characteristic impedance Zo, the dimensions of the trace, and the dielectric constant ∈e of dielectric layer 222, where W is the trace width and d is the via thickness, which is set by the thickness of dielectric layer 222, and the thickness of dielectric layer 222 determines the distance between signal layer 221 and bottom metal layer 223.

[0034]

[0035] For

[0036] As described above, the Zo range is typically controlled to be 50 ohms for single-ended and 100 ohms for differential. Microstrip lines known in the radio frequency (RF) electronics field typically have most of their field lines in the dielectric region, where dielectric layer 222 is concentrated between signal layer 221 and bottom metal layer 223. The disclosed ground cut is placed directly under one of the capacitor pads such that each DC-blocking capacitor has a pad with a ground cut. The same ground cut in bottom metal layer 223 is also implemented under the elongated trace. DC-blocking capacitor pads are typically very capacitive due to their coupling to the ground plane, so the ground cut reduces the overall capacitive performance of the package. There is also a ground cut under the elongated trace on signal layer 221 to further increase the inductance of the elongated trace.

[0037] Figure 4A - Figure 4B The simulated insertion loss between known FC BGA-based semiconductor devices in Figure 4A was compared with the Figure 4B insertion loss in Figure 4B The insertion loss in

[0038] Figure 4C - Figure 4D The simulated return loss between known FC BGA-based semiconductor devices in Figure 4C was compared with theFigure 4D The insertion losses in Figure 4D the return losses were measured for an original MIS QFN-based semiconductor device lacking the disclosed performance tuning, and for an MIS QFN-based semiconductor device including the disclosed performance tuning.

[0039] Figure 4A- Figure 4D The data in proved that, as described herein, by using the significantly less expensive MIS QFN technology (which can be tuned to provide performance similar to that of conventional FC BGA package-based devices) to develop the physical structure plus the DC blocking capacitor in the package, the high cost problem of the conventional FC BGA package technology for high-speed devices (due to the need to meet high electrical performance, data rates of 56 Gbps+) was solved. The disclosed MIS QFN-based packaged device provides the performance of the conventional FC-BGA package technology, where the package cost is reduced by approximately 40% to 60%, and the production cycle is shortened by 1 to 2 weeks because the MIS process flow is faster than the conventional package substrate manufacturing.

[0040] The disclosed embodiments can be integrated into various assembly processes to form various different packaged devices and related products. The assembly can include a single semiconductor die or multiple semiconductor dies, such as a PoP configuration including multiple stacked semiconductor dies. Various package substrates can be used. The semiconductor die can include various elements therein and / or layers thereon, including barrier layers, dielectric layers, device structures, active elements, and passive elements, which include source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Additionally, the semiconductor die can be formed by various processes, including bipolar transistors, insulated gate bipolar transistors (IGBTs), CMOS, BiCMOS, and MEMS.

[0041] Those skilled in the art of the present disclosure will appreciate that many other embodiments and variations of the embodiments are possible within the scope of the claimed invention, and further additions, deletions, substitutions, and modifications can be made to the described embodiments without departing from the scope of the present disclosure.

Claims

1. An encapsulated semiconductor device, comprising: A multi-layer plastic encapsulated interconnect substrate, i.e., MIS, having a signal layer and a bottom metal layer, wherein the signal layer includes first and second traces for a first channel on a dielectric layer having vias and first and second traces for a second channel on the dielectric layer having vias, and the bottom metal layer below the dielectric layer is for providing a ground return path, the signal layer includes contact pads, wherein the first and second traces of the first and second channels include narrowed trace regions, and the bottom metal layer includes a patterned layer containing a plurality of ground cut regions; A first DC blocking capacitor, i.e., a first DC blocking capacitor and a second DC blocking capacitor, connected in series within the first and second traces of the first channel for providing AC coupling, i.e., AC coupling, each of the first DC blocking capacitor and the second DC blocking capacitor having a plate above one of the ground cut regions; A third DC blocking capacitor and a fourth DC blocking capacitor connected in series within the first and second traces of the second channel for providing AC coupling, each of the third DC blocking capacitor and the fourth DC blocking capacitor having a plate above one of the ground cut regions; And An integrated circuit, i.e., IC, comprising: a first differential input channel coupled to receive outputs from the first DC blocking capacitor and the second DC blocking capacitor; And at least a second differential input channel coupled to receive outputs from the third DC blocking capacitor and the fourth DC blocking capacitor, wherein a bump array thereon is flip-chip mounted to the contact pads to provide a first differential output signal and a second differential output signal.

2. The encapsulated semiconductor device according to claim 1, wherein, The narrowed trace region is at least 20% narrower compared to the width of other traces on the signal layer.

3. The encapsulated semiconductor device according to claim 1, wherein, The narrowed trace region is at least 40% narrower compared to the width of other traces on the signal layer.

4. The encapsulated semiconductor device according to claim 1, wherein, The bump array includes copper pillars having solder bumps thereon.

5. The encapsulated semiconductor device according to claim 1, further comprising a printed circuit board, i.e., PCB, and a solder pattern between the bottom metal layer and the PCB, and a plastic encapsulant for encapsulating the encapsulated semiconductor device.

6. The encapsulated semiconductor device according to claim 1, wherein, The IC includes a communication device, and the communication device includes a receiver containing a decoder and a transmitter containing an encoder.

7. The encapsulated semiconductor device according to claim 1, wherein, The capacitance of the first DC blocking capacitor, the second DC blocking capacitor, the third DC blocking capacitor, and the fourth DC blocking capacitor is from 0.05 μF to 2 μF.

8. The encapsulated semiconductor device according to claim 1, wherein, The narrowed trace region is located above a first ground cut region close to the plate of the DC blocking capacitor, and the plate of the DC blocking capacitor is above the first ground cut region.

9. The encapsulated semiconductor device according to claim 1, wherein, The dielectric layer includes a composite material, and the composite material includes epoxy resin.

10. A method of manufacturing an encapsulated semiconductor device, comprising: Provided is a multilayer encapsulated interconnect substrate, i.e., MIS, having a signal layer and a bottom metal layer, the signal layer including first and second traces for a first channel on a dielectric layer having vias and first and second traces for a second channel on the dielectric layer having vias, and the bottom metal layer below the dielectric layer for providing a ground return path, the signal layer including contact pads, wherein the first and second traces of the first and second channels include narrowed trace regions, and the bottom metal layer includes a patterned layer containing a plurality of ground cut regions; A first DC blocking capacitor, i.e., first DC blocker, and a second DC blocking capacitor are serially attached within the first and second traces of the first channel for providing AC coupling, i.e., AC coupling, each of the first DC blocking capacitor and the second DC blocking capacitor having a plate above one of the ground cut regions, and a third DC blocking capacitor and a fourth DC blocking capacitor are serially attached within the first and second traces of the second channel for providing AC coupling, each of the third DC blocking capacitor and the fourth DC blocking capacitor having a plate above one of the ground cut regions, and An integrated circuit, i.e., IC, is attached, the IC including: a first differential input channel coupled to receive outputs from the first DC blocking capacitor and the second DC blocking capacitor; And at least a second differential input channel coupled to receive outputs from the third DC blocking capacitor and the fourth DC blocking capacitor, wherein a bump array thereon is flip-chip mounted to the contact pads to provide a first differential output signal and a second differential output signal.

11. The method according to claim 10, wherein The narrowed trace region is narrowed by at least 20% compared to the width of other traces on the signal layer.

12. The method according to claim 10, wherein, The narrowed trace region is narrowed by at least 40% compared to the width of other traces on the signal layer.

13. The method according to claim 10, further comprising: Designing the narrowed trace region according to the dielectric properties of the dielectric layer; Predefining an initial trace width for the narrowed trace region; Pre-simulating into a number of trace width candidates using a two-dimensional field simulator, Validating using a full-wave three-dimensional simulator to determine performance, wherein the dielectric properties of the dielectric layer and the thickness of the dielectric layer, together with the trace width and the desired characteristic impedance, are input as parameters.

14. The method according to claim 10, wherein, The bump array includes copper pillars having solder bumps thereon.

15. The method according to claim 10, further comprising providing a printed circuit board, i.e., PCB, and providing a solder pattern between the bottom metal layer and the PCB, and providing an encapsulating molding compound for encapsulating the packaged semiconductor device.

16. The method according to claim 10, wherein, The IC includes a communication device, the communication device including a receiver having a decoder and a transmitter having an encoder.

17. The method according to claim 10, wherein the capacitances of the first DC-blocking capacitor, the second DC-blocking capacitor, the third DC-blocking capacitor, and the fourth DC-blocking capacitor are from 0.05 μF to 2 μF.

18. The method according to claim 10, further comprising positioning the narrowed trace region above a first ground cut region proximate to the plate of the DC-blocking capacitor, the plate of the DC-blocking capacitor being above the first ground cut region.

19. An encapsulated semiconductor device, comprising: A multi-layer plastic-packaged interconnect substrate, i.e., MIS, having a signal layer and a bottom metal layer, the signal layer including first traces and second traces for a first channel on a dielectric layer having vias and first traces and second traces for a second channel on the dielectric layer having vias, wherein the first traces and the second traces of the first channel and the second channel include narrowed trace regions, and the bottom metal layer includes a patterned layer containing a plurality of ground cut regions, and at least one of the first traces and the second traces for the first channel and the first traces and the second traces for the second channel is above one of the ground cut regions.

20. The device according to claim 19, further comprising: A first direct current blocking capacitor, i.e., a first DC-blocking capacitor and a second DC-blocking capacitor, connected in series within the first traces and the second traces of the first channel.

21. The device according to claim 20, further comprising: Each of the first DC-blocking capacitor and the second DC-blocking capacitor has a plate above one of the ground cut regions.

22. The device according to claim 19, wherein the bottom metal layer is below the dielectric layer and provides a ground return path.

23. The device according to claim 20, wherein the bottom metal layer is below the dielectric layer and provides a ground return path.

24. The device according to claim 21, wherein the bottom metal layer is below the dielectric layer and provides a ground return path.

25. The device according to claim 20, further comprising: An integrated circuit, i.e., an IC, including: a first differential input channel, which is coupled to receive outputs from the first DC-blocking capacitor and the second DC-blocking capacitor.

26. The device according to claim 21, further comprising: An integrated circuit, i.e., an IC, including: a first differential input channel, which is coupled to receive outputs from the first DC-blocking capacitor and the second DC-blocking capacitor.

27. The device according to claim 23, further comprising: An integrated circuit, i.e., an IC, including: a first differential input channel, which is coupled to receive outputs from the first DC-blocking capacitor and the second DC-blocking capacitor.

28. The device according to claim 24, further comprising: An integrated circuit, i.e., an IC, includes: a first differential input channel coupled to receive outputs from the first DC-blocking capacitor and the second DC-blocking capacitor.

29. The apparatus according to claim 25, further comprising: A bump array flip-chip mounted to the contact pads of the signal layer to provide a first differential output signal and a second differential output signal.

30. The apparatus according to claim 26, further comprising: A bump array flip-chip mounted to the contact pads of the signal layer to provide a first differential output signal and a second differential output signal.

31. The apparatus according to claim 27, further comprising: A bump array flip-chip mounted to the contact pads of the signal layer to provide a first differential output signal and a second differential output signal.

32. The apparatus according to claim 28, further comprising: A bump array flip-chip mounted to the contact pads of the signal layer to provide a first differential output signal and a second differential output signal.

33. The apparatus according to claim 20, wherein the first DC-blocking capacitor and the second DC-blocking capacitor in the first trace and the second trace of the first channel provide AC coupling, i.e., AC coupling.

34. A method of manufacturing a packaged semiconductor device, comprising: Providing a multilayered plastic-encapsulated interconnect substrate, i.e., a MIS, having a signal layer and a bottom metal layer, the signal layer including a first trace and a second trace for a first channel on a dielectric layer having vias and a first trace and a second trace for a second channel on the dielectric layer having vias, wherein the first trace and the second trace of the first channel and the second channel include narrowed trace regions, and the bottom metal layer includes a patterned layer having a plurality of ground cut regions, and at least one of the first trace and the second trace for the first channel and the first trace and the second trace for the second channel is above one of the ground cut regions.

35. The method according to claim 34, further comprising: Attaching a first DC-blocking capacitor, i.e., a first DC-blocking capacitor and a second DC-blocking capacitor, in series within the first trace and the second trace of the first channel.

36. According to the method of claim 35, wherein: One plate of each of the first DC-blocking capacitor and the second DC-blocking capacitor is formed above one of the ground cut regions.

37. According to the method of claim 34, wherein the bottom metal layer is below the dielectric layer and provides a ground return path.

38. According to the method of claim 35, wherein the bottom metal layer is below the dielectric layer and provides a ground return path.

39. According to the method of claim 36, wherein the bottom metal layer is below the dielectric layer and provides a ground return path.

40. The method according to claim 35, further comprising: A coupled integrated circuit, i.e., an IC, the IC including: a first differential input channel to receive outputs from the first DC-blocking capacitor and the second DC-blocking capacitor.

41. The method according to claim 36, further comprising: A coupled integrated circuit, i.e., an IC, the IC including: a first differential input channel to receive outputs from the first DC-blocking capacitor and the second DC-blocking capacitor.

42. The method according to claim 38, further comprising: A coupled integrated circuit, i.e., an IC, the IC including: a first differential input channel to receive outputs from the first DC-blocking capacitor and the second DC-blocking capacitor.

43. The method according to claim 39, further comprising: A coupled integrated circuit, i.e., an IC, the IC including: a first differential input channel to receive outputs from the first DC-blocking capacitor and the second DC-blocking capacitor.

44. The method according to claim 40, further comprising: A flip-chip mounting bump array, the bump array being flip-chip mounted to contact pads on the signal layer to provide a first differential output signal and a second differential output signal.

45. The method according to claim 41, further comprising: A flip-chip mounting bump array, the bump array being flip-chip mounted to contact pads on the signal layer to provide a first differential output signal and a second differential output signal.

46. The method according to claim 42, further comprising: A flip-chip mounting bump array, the bump array being flip-chip mounted to contact pads on the signal layer to provide a first differential output signal and a second differential output signal.

47. The method according to claim 43, further comprising: A flip-chip mounting bump array, the bump array being flip-chip mounted to contact pads on the signal layer to provide a first differential output signal and a second differential output signal.

48. A packaged semiconductor device, comprising: A multi-layer plastic-sealed interconnect substrate, i.e., a MIS, having a signal layer and a bottom metal layer, the signal layer including first traces and second traces for a first channel on a dielectric layer having vias and first traces and second traces for a second channel on the dielectric layer having vias, wherein the first traces and the second traces of the first channel and the second channel include narrowed trace regions, the bottom metal layer including a patterned layer having a plurality of ground cut regions, a first portion of the first traces and the second traces being spaced apart from and covering the bottom metal layer, and a second portion of the first traces and the second traces being spaced apart from but not covering a metal portion of the bottom metal layer.

49. The device according to claim 48, wherein the narrowed trace regions of the first traces and the second traces do not cover a metal portion of the bottom metal layer.

50. The device according to claim 48, wherein the bottom metal layer provides an echo path for each of the first traces and the second traces.

51. The device according to claim 48, wherein the multi-layer plastic-encapsulated interconnect substrate, i.e., MIS, is a coplanar waveguide microstrip structure, i.e., CPW microstrip structure.

52. The device according to claim 48, wherein one of the ground-cutting regions extends below one of the narrowed trace regions, and the other of the ground-cutting regions extends below the other of the narrowed trace regions.

53. A method of manufacturing a packaged semiconductor device, comprising: providing a multi-layer plastic-encapsulated interconnect substrate, i.e., MIS, having a signal layer and a bottom metal layer, the signal layer including first and second traces for a first channel on a dielectric layer having vias and first and second traces for a second channel on the dielectric layer having vias, wherein the first and second traces of the first and second channels include narrowed trace regions, the bottom metal layer including a patterned layer containing a plurality of ground-cutting regions, a first portion of the first and second traces being spaced from and covering the bottom metal layer, and a second portion of the first and second traces being spaced from but not covering the metal portion of the bottom metal layer.

54. The method according to claim 53, wherein the narrowed trace regions of the first and second traces do not cover the metal portion of the bottom metal layer.

55. The method according to claim 53, wherein the bottom metal layer provides an echo path for each of the first and second traces.

56. The method according to claim 53, wherein the multi-layer plastic-encapsulated interconnect substrate, i.e., MIS, is a coplanar waveguide microstrip structure, i.e., CPW microstrip structure.

57. The method according to claim 53, wherein one of the ground-cutting regions extends below one of the narrowed trace regions, and the other of the ground-cutting regions extends below the other of the narrowed trace regions.

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