Nonvolatile memory device having enhanced erase control circuitry therein

Abstract

A nonvolatile memory device having enhanced erase control circuitry therein is provided. A memory device includes a vertical NAND string array of nonvolatile memory cells on an underlying substrate. An erase control circuit is provided that is configured to drive a plurality of bit lines electrically coupled to the vertical NAND string array of nonvolatile memory cells with respective erase voltages having unequal magnitudes during an operation to erase the nonvolatile memory cells in the vertical NAND string array. Such an erase control circuit may also be configured to drive a first bit line of the plurality of bit lines with a first erase voltage for a first duration and drive a second bit line of the plurality of bit lines with a second erase voltage for a second duration that is unequal to the first duration during an operation to erase the nonvolatile memory cells in the vertical NAND string array.

Description

[0001] Citation of priority application

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0069630, filed on Jun. 18, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to nonvolatile memory devices and, more particularly, to nonvolatile memory devices having an erase control circuit therein. Background Art

[0004] Recently, as information communication devices become more multifunctional, there is a need to increase the capacity and integration of memory devices. As the memory cell size is reduced to achieve higher integration, the operating circuits and / or wiring structures within the memory device that control the operation and electrical connections of the circuits therein become more complex. Therefore, there is a need for memory devices with improved electrical characteristics and data reliability and increased integration. Summary of the invention

[0005] Nonvolatile memory devices, including those having a vertical NAND type structure, utilize erase control circuitry to achieve improved operating characteristics. In some embodiments of these memory devices, a nonvolatile memory cell array is provided, wherein the nonvolatile memory cell array has multiple groups of nonvolatile memory cells. In addition, at least one first bit line is provided that is electrically coupled to a first group of the multiple groups of nonvolatile memory cells, and at least one second bit line is provided that is electrically coupled to a second group of the multiple groups of nonvolatile memory cells. An erase control circuit is provided that is configured to drive at least one first bit line and at least one second bit line with unequal first and second erase voltages during operations to respectively erase a first group of the multiple groups of nonvolatile memory cells and a second group of the multiple groups of nonvolatile memory cells.

[0006] In some embodiments of the present invention, the nonvolatile memory cells in the first group of the plurality of groups of nonvolatile memory cells are arranged vertically relative to each other on the underlying substrate. For example, the nonvolatile memory cell array may include a plurality of vertical NAND-type strings of memory cells having corresponding vertical channel structures electrically coupled to corresponding bit lines. In addition, the erase control circuit may be configured to advantageously drive the plurality of bit lines with unequal erase voltages during the operation of erasing the plurality of vertical NAND strings of memory cells, and to cause the memory cells to have more uniform erase characteristics (e.g., threshold voltages). In some of these embodiments of the present invention, the unequal erase voltages include a first erase voltage and a second erase voltage having unequal amplitudes, and the erase control circuit is configured to drive the first bit line of the plurality of bit lines with the first erase voltage for a first duration, and drive the second bit line of the plurality of bit lines with the second erase voltage for a second duration during the operation of erasing the plurality of vertical NAND strings of memory cells. Such a first duration may be shorter than the second duration, and the amplitude of the first erase voltage may be less than the amplitude of the second erase voltage. In some further embodiments of the present invention, a word line cut region may be provided on the semiconductor substrate, and a first group of the plurality of groups of nonvolatile memory cells may extend closer to the word line cut region than a second group of the plurality of groups of nonvolatile memory cells.

[0007] According to further embodiments of the present invention, a memory device is provided that includes an array of vertical NAND strings of nonvolatile memory cells on a lower substrate. Additionally, an erase control circuit is provided that is configured to drive a plurality of bit lines electrically coupled to the vertical NAND string array of nonvolatile memory cells with corresponding erase voltages of unequal magnitudes during an operation to erase the nonvolatile memory cells in the vertical NAND string array. In some of these embodiments of the present invention, the erase control circuit is configured to drive a first bit line of the plurality of bit lines with a first erase voltage for a first duration, and drive a second bit line of the plurality of bit lines with a second erase voltage for a second duration that is unequal to the first duration, during an operation to erase the nonvolatile memory cells in the vertical NAND string array.

[0008] According to another embodiment of the present invention, a non-volatile memory device is provided, which includes a substrate and a memory cell array. The memory cell array includes a plurality of vertical channel structures, which are arranged spaced apart from each other along a first direction and a second direction perpendicular to the first direction, and extend in a direction perpendicular to the substrate. A plurality of bit lines are provided, which extend along the second direction and are electrically connected to corresponding ends of the plurality of vertical channel structures. An erase control circuit is provided, which is configured to form a plurality of groups including at least two bit lines of the plurality of bit lines and apply different erase voltages to two or more of the groups during an erase operation of the memory cell array.

[0009] According to another embodiment, a non-volatile memory device is provided, which includes a plurality of memory blocks arranged along a first direction and a second direction perpendicular to the first direction, and each memory block includes a plurality of pillars extending in a direction perpendicular to a substrate. A plurality of bit lines are provided, which extend along the second direction on the plurality of memory blocks and are electrically connected to the plurality of pillars. One or more word line cutting regions may be formed on the substrate, which extend along the first direction. A control logic is provided for outputting an erase voltage control signal during an erase operation of the plurality of memory blocks. An erase control circuit is also provided, which is configured to form a first group and a second group, each group including at least two bit lines of the plurality of bit lines and configured to apply different erase voltages to the first group and the second group based on the erase voltage control signal.

[0010] In some other embodiments of the present invention, a non-volatile memory device is provided, which includes a plurality of memory blocks, each of which includes a plurality of gate conductive layers stacked on a substrate and a plurality of vertical channel structures extending vertically from the top surface of the substrate through the gate conductive layers. A plurality of bit lines are also provided, which are arranged on the plurality of memory blocks along a first direction and extend along a second direction perpendicular to the first direction. These bit lines are electrically connected to the plurality of vertical channel structures. A voltage generator is provided, which is configured to generate a bit line voltage applied to the plurality of bit lines. A control logic is also provided for outputting an erase voltage control signal during an erase operation of the memory block. An erase control circuit is provided, which is configured to apply different erase voltages to corresponding bit lines (associated with different groups of memory cells) during an erase operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a block diagram of an integrated circuit memory device having an erase control circuit according to an embodiment of the present invention;

[0012] Figure 2 is a perspective view of a three-dimensional implementation of an integrated circuit memory block including a plurality of NAND-type nonvolatile memory cell strings, which can be used as Figure 1A memory block within a memory cell array;

[0013] Figure 3 It is shown Figure 2 A circuit diagram of an equivalent circuit of a memory block;

[0014] Figure 4A is a table showing an erase operation according to an embodiment of the present invention and Figure 4B is a timing diagram showing an erase operation according to an embodiment of the present invention;

[0015] Figure 5A is a circuit diagram of a portion of an erase control circuit according to an embodiment of the present invention;

[0016] Figure 5B yes Figure 1 A plan view of an embodiment of a memory cell array showing the placement of bit lines and memory cell groups according to an embodiment of the present invention;

[0017] Figure 6 is a timing diagram showing voltages applied to bit lines included in each of a plurality of groups of memory cells during an erase operation according to an embodiment of the present invention;

[0018] Fig. 7A is a diagram showing threshold voltage distribution after an erase operation of memory cells included in a group formed according to an exemplary embodiment;

[0019] Figure 7B is a diagram showing threshold voltage distribution after an erase operation of a memory cell connected to a bit line according to a comparative embodiment;

[0020] Figure 8 is a timing diagram showing voltages applied to bit lines included in each group according to another exemplary embodiment of the present invention;

[0021] Fig. 9 is a timing diagram showing voltages applied to bit lines included in each group according to another exemplary embodiment of the present invention;

[0022] Fig. 10A is an operational flow chart illustrating a multi-cycle erase operation according to an embodiment of the present invention;

[0023] Figure 10B-Figure 10C is a timing diagram and a threshold voltage diagram showing a multi-ring erase operation according to an embodiment of the present invention;

[0024] Fig.11 is a circuit diagram showing a memory block according to another exemplary embodiment of the present invention;

[0025] Fig.12is a diagram schematically illustrating orthogonal orientations of word lines (WL) and bit lines (BL) on a memory device according to an embodiment of the present invention; and

[0026] Fig.13 is a block diagram of a solid-state drive (SSD) memory system that may utilize a memory device according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0027] Figure 1 is a block diagram illustrating a memory device according to an exemplary embodiment. Figure 1 , the memory device 100 may include a memory cell array 110, a control logic 120, a voltage generator 130, a row decoder 140, a page buffer 150, and an erase control circuit 160. Figure 1 Although not shown, the memory device 100 may further include a data input / output circuit, an input / output interface, etc. In addition, although not shown, the memory device 100 may further include various sub-circuits such as an error correction circuit for correcting errors of data read from the memory cell array 110.

[0028] The memory cell array 110 includes a plurality of memory cells and may be connected to a string select line SSL (string select line), a word line WL, a ground select line GSL (ground select line), and a bit line BL. In detail, the memory cell array 110 may be connected to a row decoder 140 via the string select line SSL, the word line WL, and the ground select line GSL, and may be connected to a page buffer 150 via a bit line BL.

[0029] For example, the memory cells included in the memory cell array 110 may be nonvolatile memory cells, which can maintain data stored therein even when power is interrupted. In detail, when the memory cells are nonvolatile memory cells, the memory device 100 may be an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), etc. Hereinafter, an exemplary embodiment will be described by taking a case where a plurality of memory cells are NAND flash memory cells as an example, but the inventive concept is not limited thereto.

[0030] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz, and each of the memory blocks BLK1 to BLKz may have a planar structure or a three-dimensional structure. The memory cell array 110 may include a single-level cell block including a single-level cell (SLC), a multi-level cell block including a multi-level cell (MLC), a three-level cell block including a triple-level cell (TLC), and at least one of a quad-level cell block including a quad-level cell (QLC). For example, some of the memory blocks BLK1 to BLKz may be single-level cell blocks, and the other memory blocks may be multi-level cell blocks, three-level cell blocks, or four-level cell blocks.

[0031] The control logic 120 may output various control signals for programming data into the memory cell array 110, reading data from the memory cell array 110, or erasing data stored in the memory cell array 110, such as a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR, based on a command CMD (command), an address ADDR (address), and a control signal CTRL (control signal). For example, the control logic 120 may receive the command CMD, the address ADDR, and the control signal CTRL from a memory controller (not shown) outside the memory device 100. Therefore, the control logic 120 is capable of controlling various operations in the memory device 100.

[0032] According to example embodiments, the control logic 120 may also output the erase voltage control signal CTRL_HV to the erase control circuit 160. For example, the control logic 120 may output the erase voltage control signal CTRL_HV to one or more transistors included in a group including a bit line to which an erase voltage is applied among the bit lines BL.

[0033] The voltage generator 130 may generate various types of voltages for performing programming, reading, and erasing operations on the memory cell array 110 based on the voltage control signal CTRL_vol. In detail, the voltage generator 130 may generate a word line voltage V_WL, for example, a programming voltage, a reading voltage, a pass voltage, an erase verification voltage, or a programming verification voltage. In addition, the voltage generator 130 may generate a string selection line voltage V_SSL and a ground selection line voltage V_GSL based on the voltage control signal CTRL_vol.

[0034] In addition, the voltage generator 130 may generate a bit line voltage V_BL based on the voltage control signal CTRL_vol. For example, the voltage generator 130 may generate a gate induced drain leakage (GIDL) voltage and an erase voltage as the bit line voltage V_BL. According to an exemplary embodiment, the voltage generator 130 may generate a plurality of erase voltages having different levels. According to another exemplary embodiment, the voltage generator 130 may generate a plurality of erase voltages having different application times. A detailed description thereof will be described below.

[0035] The row decoder 140 may select one of the memory blocks BLK1 to BLKz in response to the row address X-ADDR, and may select one of the word lines WL of the selected memory block and one of the string selection lines SSL. The row decoder 140 may also send a voltage for performing a memory operation to the word line of the selected memory block. For example, in an erase operation, the row decoder 140 may send an erase voltage and a verification voltage to the selected word line, and send a pass voltage to an unselected word line.

[0036] The page buffer 150 may transmit and receive data DT (data, DT) with a device outside the memory device 100. The page buffer 150 may select some of the bit lines BL in response to the column address Y-ADDR. The page buffer 150 may operate as a write driver or a sense amplifier.

[0037] The erase control circuit 160 may control an erase voltage applied to the bit line BL. According to an exemplary embodiment, the erase control circuit 160 may generate a plurality of groups, each group including at least two bit lines of the bit lines BL. For example, the same erase voltage may be applied to the bit lines included in one group during an erase operation. The groups may be generated based on, for example, a plurality of transistors electrically connected to the bit lines BL, respectively.

[0038] In addition, according to an exemplary embodiment, the erase control circuit 160 may apply different erase voltages to at least two groups among the plurality of groups during an erase operation of the memory cell array 110. For example, the erase control circuit 160 may apply erase voltages to be applied having different levels to different groups, respectively. In another example, the erase control circuit 160 may apply erase voltages having different application times, respectively, to different groups.

[0039] Figure 2 yes Figure 1 A perspective view of an implementation example of a first memory block among memory blocks of FIG. Figure 2 , the first memory block BLK1 may be formed in a direction (eg, a third direction) perpendicular to the substrate SUB (substrate). Figure 2 The first memory block BLK1 is shown to include a ground selection line GSL, a string selection line SSL, eight word lines WL1 to WL8, and three bit lines BL1 to BL3, but this is only for ease of explanation, and the number of lines may be greater or less than these. In addition, in another example, the first memory block BLK1 may include one or more virtual word lines between the first word line WL1 and the ground selection line GSL and / or between the eighth word line WL8 and the string selection line SSL.

[0040] The substrate SUB may be a polysilicon film doped to a first conductivity type (e.g., p-type). The substrate SUB may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or an epitaxial thin film substrate obtained by performing selective epitaxial growth (SEG). The substrate SUB may include a semiconductor material. For example, the substrate SUB may include at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), and aluminum gallium arsenide (AlGaAs), or a mixture thereof.

[0041] A common source line CSL (common source line) extending along a first direction on the substrate SUB and doped with impurities of a second conductive type (e.g., n-type) may be provided to the substrate SUB. A plurality of insulation layers IL (insulation layer) extending along the first direction may be sequentially provided along a third direction on a region between two common source lines CSL adjacent to each other on the substrate SUB, and the insulation layers IL may be spaced a certain distance from each other along the third direction. For example, the insulation layer IL may include an insulating material such as silicon oxide.

[0042] A plurality of pillars P may be provided which are sequentially arranged along a first direction on a region of a substrate SUB and have a common source line therebetween and penetrate the insulating layer IL along a third direction. For example, the pillars P may contact the substrate SUB by penetrating the insulating layer IL. In detail, a surface layer S of each pillar P may include a silicon material doped to a first conductivity type and used as a channel region. In this specification, the pillars P may also be referred to as a vertical channel structure. On the other hand, an inner layer I of each pillar P may include an insulating material such as silicon oxide or an air gap. For example, the size of the channel hole in each pillar P may decrease toward the substrate SUB.

[0043] A charge storage layer CS (charge storage layer) may be provided on the substrate SUB along the insulating layer IL, the pillars P, and the exposed surface of the substrate SUB via the common source line CSL therebetween. The charge storage layer CS may include a gate insulating layer (or "tunneling insulating layer"), a charge trapping layer, and a blocking insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. In addition, in the region between two common source lines CSL adjacent to each other, gate electrodes GE (gate electrodes) such as a ground selection line GSL, a string selection line SSL, and word lines WL1 to WL8 may be provided on the exposed surface of the charge storage layer CS.

[0044] A drain or drain contact DR (drain contact) may be provided on the pillars P, respectively. For example, the drain or drain contact DR may include a silicon material doped with impurities of the second conductivity type. On the drain contacts DR, bit lines BL1 to BL3 extending in the second direction and spaced apart from each other in the first direction may be provided. The bit lines BL1 to BL3 may be electrically connected to the drain contacts DR through contact plugs (not shown).

[0045] On the common source line CSL, a word line cut region WLC extending along the first direction may be provided. The gate electrode GE may be separated by the word line cut region WLC. For example, the word line cut region WLC may include an insulating material or may be an air gap.

[0046] Figure 3 It is shown Figure 1 A circuit diagram of an equivalent circuit of the first memory block BLK1 among the memory blocks of FIG. Figure 3 , the first memory block BLK1 may be a vertical NAND flash memory, and Figure 1 Each of the memory blocks BLK1 to BLKz shown in FIG. Figure 3 The first memory block BLK1 may include a plurality of NAND cell strings NS11 to NS33, word lines WL1 to WL8, bit lines BL1 to BL3, a plurality of ground selection lines GSL1 to GSL3, a plurality of string selection lines SSL1 to SSL3, and a common source line CSL. Here, the number of NAND cell strings, the number of word lines, the number of bit lines, the number of ground selection lines, and the number of string selection lines may vary according to the embodiment.

[0047] NAND cell strings NS11, NS21, and NS31 are provided between a first bit line BL1 and a common source line CSL, NAND cell strings NS12, NS22, and NS32 are provided between a second bit line BL2 and a common source line CSL, and NAND cell strings NS13, NS23, and NS33 are provided between a third bit line BL3 and a common source line CSL. Each NAND cell string (e.g., NAND cell string NS11) may include a string select transistor SST (string select transistor) connected in series, a plurality of memory cells MC1 to MC8, and a ground select transistor GST (ground select transistor).

[0048] NAND cell strings commonly connected to one bit line may constitute a column. For example, NAND cell strings NS11, NS21, and NS31 commonly connected to a first bit line BL1 may correspond to a first column, NAND cell strings NS12, NS22, and NS32 commonly connected to a second bit line may correspond to a second column, and NAND cell strings NS13, NS23, and NS33 commonly connected to a third bit line BL3 may correspond to a third column.

[0049] The NAND cell strings connected to one cell string selection line may constitute a row. For example, NAND cell strings NS11, NS12, and NS13 connected to a first string selection line SSL1 may correspond to a first row, NAND cell strings NS21, NS22, and NS23 connected to a second string selection line SSL2 may correspond to a second row, and NAND cell strings NS31, NS32, and NS33 connected to a third string selection line SSL3 may correspond to a third row.

[0050] The string selection transistors SST may be connected to the corresponding string selection lines SSL1 to SSL3, respectively. The memory cells MC1 to MC8 may be connected to the corresponding word lines WL1 to WL8, respectively. The ground selection transistors GST may be connected to the corresponding ground selection lines GSL1 to GSL3, and the string selection transistors SST may be connected to the corresponding bit lines BL1 to BL3. The ground selection transistors GST may be connected to the common source line CSL.

[0051] In the present embodiment, word lines (e.g., the first word line WL1) at the same height are connected in common, string selection lines SSL1 to SSL3 are separated from each other, and ground selection lines GSL1 to GSL3 are also separated from each other. For example, in the case of programming memory cells in NAND cell strings NS11, NS12, and NS13 connected to the first word line WL1 and corresponding to the first row, the first word line WL1 and the first string selection line SSL1 are selected. However, the inventive concept is not limited thereto. According to other embodiments, the ground selection lines GSL1 to GSL3 may be connected in common.

[0052] Figure 4A and Figure 4B is a diagram for describing an erase operation according to an exemplary embodiment. In detail, Figure 4A Shows Figure 3 An example of the erase bias condition of the first memory block BLK1 in FIG. 1 and Figure 4B Shows instructions Figure 4A The erase bias condition is shown in Figure 2. Figure 4A and Figure 4B , in order to perform an erase operation on the first memory block BLK1, the bit line voltage V_BL applied to the bit line BL may rise from the first time point t1 to the third time point t3. At the second time point t2, the bit line voltage V_BL reaches the GIDL voltage V_GIDL, and the string selection line voltage V_SSL may also rise. The string selection line voltage V_SSL may rise from the second time point t2 to the third time point t3. The bit line voltage V_BL may reach the erase voltage V_ERS at the third time point t3, and the string selection line voltage V_SSL may reach the bias voltage Vbias at the third time point t3. For example, the bias voltage Vbias may have the same level as a value obtained by subtracting the GIDL voltage V_GIDL from the erase voltage V_ERS.

[0053] The bit line voltage V_BL may then maintain the erase voltage V_ERS from the third time point t3 to the fourth time point t4. For example, the time interval from the third time point t3 to the fourth time point t4 during which the erase voltage V_ERS is maintained may be referred to as the application time of the erase voltage V_ERS. Hereinafter, the application time may refer to a time period during which the target voltage is maintained and applied.

[0054] According to an exemplary embodiment, from the third time point t3 to the fourth time point t4, erase voltages having different levels may be applied to the bit lines of the first group and the bit lines of the second group among the groups generated in the erase control circuit 160. For example, a vertical channel structure electrically connected to the bit lines included in the first group may be placed closer to the word line cutting region WLC than a vertical channel structure electrically connected to the bit lines included in the second group. In this case, the level of the erase voltage applied to the bit lines of the first group may be lower than the level of the erase voltage applied to the bit lines of the second group.

[0055] Subsequently, the bit line voltage V_BL may drop to the initial voltage of the first time point t1 at the fourth time point t4. According to an exemplary embodiment, when the erase voltage applied to the bit line of the second group among the groups generated in the erase control circuit 160 drops at the fourth time point t4, the erase voltage applied to the bit line of the first group may drop before the fourth time point t4. In other words, the application time (or maintenance time) of the erase voltage with respect to the bit line of the first group may be shorter than the application time (or maintenance time) of the erase voltage with respect to the bit line of the second group.

[0056] When a voltage equal to or higher than the GIDL voltage V_GIDL is applied as the bit line voltage V_BL, a hole is generated at the drain edge of the string selection transistor SST, so the channel is charged from the terminal of the bit line BL of the NAND string NS11 to NS33. The channel is continuously charged from the terminal end of the bit line BL until the bit line voltage V_BL rises to the erase voltage V_ERS. On the other hand, the string selection line voltage V_SSL may drop to the initial voltage of the second time point t2 at the fourth time point t4.

[0057] From the second time point t2 to the third time point t3, electron-hole pairs may be generated near the connection portion of the bit line BL. Electrons may be concentrated at the terminal of the bit line BL to which a high voltage is applied, and holes may drift to the channel and charge the channel. Therefore, the channel may be boosted to a voltage close to the GIDL voltage V_GIDL. From the third time point t3 to the fourth time point t4, the bit line voltage V_BL may maintain the erase voltage V_ERS, and the string selection line voltage V_SSL may maintain the bias voltage Vbias (e.g., a value obtained by subtracting the GIDL voltage V_GIDL from the erase voltage V_ERS). At this point, electron-hole pairs are continuously generated, and the channel may be charged to a higher potential.

[0058] In addition, the voltage V_WL applied to the word line WL may be a word line erase voltage Vwe and may be, for example, 0 V. At this time, both the ground selection line GSL and the common source line CSL may be floated. As described above, based on the GIDL phenomenon caused by the voltage applied to the bit line BL, an erase operation may be performed on the first memory block BLK1.

[0059] Figure 5A and Figure 5B is a diagram for describing a group of bit lines formed according to an exemplary embodiment. In detail, Figure 5A shows a specific configuration of the erase control circuit 160 connected to the bit line, and Figure 5B is a memory block (for example, Figure 2 A top view of some components of the first memory block BLK1 in FIG. Figure 5A , the erase control circuit 160 may include a plurality of first transistors 162 and a plurality of second transistors 164. The first transistors 162 are electrically connected between the bit lines BL1 to BLn and the second transistors 164, respectively, and may receive a control signal CTRL_1. For example, the control signal CTRL_1 may be output from the control logic 120, and the first transistors 162 may be turned on or off based on the control signal CTRL_1. Although Figure 5A and Figure 5B It is shown that all transistors in the first transistor 162 receive the same control signal CTRL_1 , but the inventive concept is not limited thereto. That is, different control signals CTRL_1 may be applied to the first transistor 162 .

[0060] Each of the second transistors 164 may include a first terminal to which the erase voltage control signal CTRL_HV is applied and a second terminal electrically connected to the bit lines BL1 to BLn through the first transistor 162. For example, the first terminal may be a gate terminal and the second terminal may be a drain (or source) terminal. Figure 5A and Figure 5B It is shown that the same erase voltage control signal CTRL_HV is applied to the first terminal of the second transistor 164 , but the inventive concept is not limited thereto. That is, different erase voltage control signals CTRL_HV may be applied to the first terminal of the second transistor 164 .

[0061] In an exemplary embodiment, at least two of the third terminals of the second transistors 164 may be electrically connected to each other, and an erase voltage may be applied thereto. For example, the third terminal of each of the second transistors 164 electrically connected to the first bit line BL1 and the n-1th bit line BLn-1 may be electrically connected to each other, and a first erase voltage V_ERS1 may be applied thereto. In addition, the third terminal of each of the second transistors 164 electrically connected to the second bit line BL2 and the n-th bit line BLn may be electrically connected to each other, and an n-th erase voltage V_ERSn may be applied thereto. In other words, in an erase operation, the first bit line BL1 and the n-1th bit line BLn-1 may form a first group GP1, and the second bit line BL2 and the n-th bit line BLn may form a second group GP2.

[0062] In one exemplary embodiment, the first erase voltage V_ERS1 and the nth erase voltage V_ERSn may have different levels. In another exemplary embodiment, the first erase voltage V_ERS1 and the nth erase voltage V_ERSn may have different application times (e.g., different durations relative to each other). In another exemplary embodiment, the first erase voltage V_ERS1 and the nth erase voltage V_ERSn have the same voltage level (e.g., amplitude), but the turn-on time of the second transistor 164 to which the first erase voltage V_ERS1 is applied may be different from the turn-on time of the second transistor 164 to which the nth erase voltage V_ERSn is applied.

[0063] refer to Figure 5B , the first memory block BLK1 may include a word line cut region WLC extending in the first direction and spaced apart from each other in the second direction, and a select line cut region SLC (select line cut region) between the two word line cut regions WLC. For example, the select line cut region SLC is a region on the eighth word line WL8, and the string selection line SSL may be separated by the select line cut region SLC. For example, the select line cut region SLC may include an insulating material or may be an air gap.

[0064] Due to the selection line cutting region SLC, the plurality of string selection line regions SSL0 to SSL3 may be distinguished from each other. For example, the string selection line regions SSL0 to SSL3 may include different string selection lines from each other and may be selected based on the different string selection lines from each other.

[0065] The first memory block BLK1 may include a plurality of pillars P11 to P38 arranged along first and second directions between a word line cutting region WLC and a selection line cutting region SLC. The bit lines BL1 to BL12 may be arranged along the first direction on the first memory block BLK1, and each of the pillars P11 to P38 may be electrically connected to one bit line through a contact plug CP (contact plug).

[0066] For example, the first bit line BL1 may be electrically connected to pillars P11, P14, P15, and P18. The second bit line BL2 may be electrically connected to pillars P12, P13, P16, and P17. The third bit line BL3 may be electrically connected to pillars P21, P24, P25, and P28. The fourth bit line BL4 may be electrically connected to pillars P22, P23, P26, and P27. In the same pattern, electrical connections may be established between the fifth to twelfth bit lines BL5 to BL12 and the pillars.

[0067] In an exemplary embodiment, the first bit line BL1 and the fifth bit line BL5 may constitute a first group GP1. In addition, the second bit line BL2 and the sixth bit line BL6 may constitute a second group GP2. In addition, the third bit line BL3 and the seventh bit line BL7 may constitute a third group GP3. In addition, the fourth bit line BL4 and the eighth bit line BL8 may constitute a fourth group GP4.

[0068] Therefore, the pillars electrically connected to the first bit line BL1 and the fifth bit line BL5 included in the first group GP1 may be positioned closer to the word line cutting region WLC than the pillars electrically connected to the third bit line BL3 and the seventh bit line BL7 included in the third group GP3. In addition, the pillars electrically connected to the third bit line BL3 and the seventh bit line BL7 included in the third group GP3 may be positioned closer to the word line cutting region WLC than the pillars electrically connected to the second bit line BL2 and the sixth bit line BL6 included in the second group GP2. In addition, the pillars electrically connected to the second bit line BL2 and the sixth bit line BL6 included in the second group GP2 may be positioned closer to the word line cutting region WLC than the pillars electrically connected to the fourth bit line BL4 and the eighth bit line BL8 included in the fourth group GP4.

[0069] In the present embodiment, it is described that two bit lines constitute one group. However, this is only an example, and the concept of the present invention is not limited thereto. That is, the first bit line BL1, the fifth bit line BL5, and the ninth bit line BL9 may constitute the first group GP1. In addition, the second bit line BL2, the sixth bit line BL6, and the tenth bit line BL10 may constitute the second group GP2. Alternatively, the first group GP1 and the second group GP2 may each include a greater number of bit lines.

[0070] Due to process characteristics, the vertical channel structure (or pillar P) may be a channel hole with different sizes, which depends on the distance from the word line cutting area WLC. For example, in an erase operation, when the same erase voltage is applied to a vertical channel structure with channel holes of different sizes, the threshold voltage distributions of the memory cells in the corresponding vertical channel structures are different from each other, thereby endangering the reliability of the data. In a memory device according to the present invention, a plurality of groups may be provided to the bit lines, and an erase control circuit for applying different erase voltages to the corresponding groups in an erase operation may be provided. Therefore, for example, different erase voltages may be applied to vertical structures with channel holes of different sizes, so that the difference between the threshold voltage distributions of the memory cells in the corresponding vertical channel structures may be reduced. Therefore, the reliability of the data stored in the memory device may be improved.

[0071] Figure 6 is a graph showing voltages applied to bit lines included in each group according to an exemplary embodiment. Figure 6 It can be shown that the application is, for example, Figure 5B FIG. 2 is a graph showing the voltages of the bit lines BL1 to BL12. Figure 6 , at the second time point t2, the erase voltage control signal CTRL_HV applied to the second transistor 164 may be activated. In other words, the erase voltage control signal CTRL_HV may turn on the second transistor 164. In the graph, the level of the erase voltage control signal CTRL_HV is shown as the sum of the fourth erase voltage V_ERS 4 and the gate voltage (e.g., the gate-source voltage of the second transistor 164), but is not limited thereto. Therefore, the erase voltage may be applied to the bit lines included in the first group GP1, the second group GP2, the third group GP3, and the fourth group GP4 at the second time point t2. In an exemplary embodiment, the first erase voltage V_ERS1 may be applied to the first bit line BL1 and the fifth bit line BL5 included in the first group GP1 until the fourth time point t4. In addition, the second erase voltage V_ERS2 may be applied to the second bit line BL2 and the sixth bit line BL6 included in the second group GP2 until the fourth time point t4. Furthermore, the third erase voltage V_ERS3 may be applied to the third and seventh bit lines BL3 and BL7 included in the third group GP3 until a fourth time point t4. Furthermore, the fourth erase voltage V_ERS4 may be applied to the fourth and eighth bit lines BL4 and BL8 included in the fourth group GP4 until a fourth time point t4.

[0072] In an exemplary embodiment, the third erase voltage V_ERS3 may have a level higher than that of the first erase voltage V_ERS1, and may have a level lower than that of the second erase voltage V_ERS2. In addition, the second erase voltage V_ERS2 may have a level lower than that of the fourth erase voltage V_ERS4. Therefore, in an erase operation, a relatively low erase voltage may be applied to pillars (e.g., P11, P14, etc.) relatively close to the word line cut region WLC and a relatively high erase voltage may be applied to pillars (e.g., P22, P23, etc.) relatively far from the word line cut region WLC.

[0073] Fig. 7A is a diagram showing threshold voltage distributions after an erase operation is performed on memory cells included in a group formed according to an exemplary embodiment, and Figure 7B is a diagram showing a threshold voltage distribution after an erase operation of a memory cell connected to a bit line according to a comparative example. Fig. 7A , electrically connected to the group (eg, Figure 5B The threshold voltage distributions D_GP1 to D_GPm (m is a natural number) of the memory cells of the bit lines in the first group GP1, the second group GP2, the third group GP3, and the fourth group GP4 may be approximately (or substantially) the same as each other. For example, due to the process for forming the gate conductive layer constituting the memory block, the size of the channel hole may vary depending on the distance from the word line cutting area WLC. Figure 7B , when the erase control circuit 160 according to the inventive concept is omitted, after the erase operation of the memory cell, there may be a deviation between the threshold voltage distributions D_BL1 to D_BLm according to the bit lines. In the memory device provided with the erase control circuit 160 according to the inventive concept, since the applied erase voltage varies according to the group formed based on the distance from the word line cutting region WLC, the deviation between the threshold voltage distributions of the memory cells after the erase operation can be enhanced.

[0074] Figure 8 is a graph showing voltages applied to bit lines included in each group according to another exemplary embodiment. Figure 8 It can be shown that the application is, for example, Figure 5B FIG. 2 is a graph showing the voltages of the bit lines BL1 to BL12. Figure 8 At the second time point t2a, the erase voltage V_ERSa may be applied to the bit lines included in the first group GP1, the second group GP2, the third group GP3, and the fourth group GP4. In an exemplary embodiment, the erase voltages V_ERSa having different application times (or retention times) from each other may be applied to the first group GP1, the second group GP2, the third group GP3, and the fourth group GP4, respectively.

[0075] For example, the erase voltage V_ERSa may be applied to the first bit line BL1 and the fifth bit line BL5 included in the first group GP1 until the fourth time point t4a. In addition, the erase voltage V_ERSa may be applied to the third bit line BL3 and the seventh bit line BL7 included in the third group GP3 until the fifth time point t5a. In addition, the erase voltage V_ERSa may be applied to the second bit line BL2 and the sixth bit line BL6 included in the second group GP2 until the sixth time point t6a. In addition, the erase voltage V_ERSa may be applied to the fourth bit line BL4 and the eighth bit line BL8 included in the fourth group GP4 until the seventh time point t7a.

[0076] In an exemplary embodiment, the voltage generator 130 may generate a plurality of erase voltages having different application times from each other (e.g., unequal application durations during an erase operation). In addition, the erase control circuit 160 may control each of the erase voltages having different application times from each other to be applied to a corresponding group.

[0077] Fig. 9 is a graph showing voltages applied to bit lines included in each group according to another exemplary embodiment. Fig. 9 The graph of Figure 8 However, unlike Figure 8 ,exist Fig. 9 In the embodiment of the present invention, the erase voltage control signal CTRL_HVb may be applied to the second transistor 164 at different application times, respectively.

[0078] For example, the erase voltage control signal CTRL_HVb may be applied to the second transistor included in the first group GP1 until the fourth time t4b. In addition, the erase voltage control signal CTRL_HVb may be applied to the second transistor included in the third group GP3 until the fifth time t5b. In addition, the erase voltage control signal CTRL_HVb may be applied to the second transistor included in the second group GP2 until the sixth time t6b. In addition, the erase voltage control signal CTRL_HVb may be applied to the second transistor included in the fourth group GP4 until the seventh time t7b.

[0079] In other words, the erase control circuit 160 may apply erase voltages having application times different from each other to the corresponding groups (e.g., the first group GP1, the second group GP2, the third group GP3, and the fourth group GP4) based on the operation of the second transistors 164. For example, the erase control circuit 160 may control the turn-on time of each of the second transistors 164 that have received the erase voltage V_ERSb generated by the voltage generator 130, thereby applying different erase voltages to the corresponding groups.

[0080] FIG. 10A to FIG. 10C is a diagram for describing an erase operation performed through a plurality of consecutive cycles according to an exemplary embodiment. Specifically, Fig. 10A is a flowchart of the erase operation, and Fig. 10B and Fig. 10C 0 is an example of an erase voltage corresponding to a cycle during an erase operation and a threshold voltage distribution based on the erase voltage. Figure 5B describe FIG. 10A to FIG. 10C .

[0081] refer to Fig. 10A and Fig. 10B , a first erase loop LOOP1 for the memory cell may be first performed (operation S10). In the first erase loop LOOP1, a first cycle erase voltage may be applied to each bit line. In an exemplary embodiment, different first cycle erase voltages may be applied to the first bit line BL1 and the fifth bit line BL5 included in the first group GP1 and the second bit line BL2 and the sixth bit line BL6 included in the second group GP2. The erase voltage applied to the first bit line BL1 and the fifth bit line BL5 included in the first group GP1 is shown in graph B, and the erase voltage applied to the second bit line BL2 and the sixth bit line BL6 included in the second group GP2 is shown in graph A.

[0082] For example, the first loop erase voltage V_ERS_L11 applied to the first bit line BL1 and the fifth bit line BL5 included in the first group GP1 may have a level lower than that of the first loop erase voltage V_ERS_L12 applied to the second bit line BL2 and the sixth bit line BL6 included in the second group GP2. When the first erase loop LOOP1 is completed, a threshold voltage distribution D_B of memory cells connected to the first bit line BL1 and the fifth bit line BL5 included in the first group GP1 and a threshold voltage distribution D_A of memory cells connected to the second bit line BL2 and the sixth bit line BL6 included in the second group GP2 may be formed.

[0083] Next, determination about the erase pass group may be performed (operation S20). For example, a threshold voltage distribution D_B of the memory cells connected to the first bit line BL1 and the fifth bit line BL5 included in the first group GP1 may be formed at a level lower than the verification voltage Vvfy according to the first erase cycle LOOP1, so the first group GP1 may be determined as the erase pass group. On the other hand, a threshold voltage distribution D_A of the memory cells connected to the second bit line BL2 and the sixth bit line BL6 included in the second group GP2 may be at least partially formed at a level higher than the verification voltage Vvfy according to the first erase cycle LOOP1, so the second group GP2 may not be determined as the erase pass group.

[0084] Next, the second erase loop LOOP2 (operation S30) may be performed based on the determination of the erase pass group. In an exemplary embodiment, an erase voltage lower than the level of the erase voltage applied to other groups may be applied to the bit line connected to the group determined as the erase pass group. For example, in the second erase loop LOOP2, the second loop erase voltage V_ERS_L21 applied to the first bit line BL1 and the fifth bit line BL5 connected to the first group GP1 may have a level lower than the level of the second loop erase voltage V_ERS_L22 applied to the second bit line BL2 and the sixth bit line BL6 included in the second group GP2. In addition, in an exemplary embodiment, the second loop erase voltage V_ERS_L21 may have a level lower than or equal to the level of the first loop erase voltage V_ERS_L11. Therefore, deep erasure of the erase pass memory cell connected to the first group GP1 can be prevented. In addition, the deviation between the distributions of the memory cells connected to the first group GP1 and the second group GP2 can be enhanced.

[0085] In this embodiment, although the erase operation is performed by the first erase cycle LOOP1 and the second erase cycle LOOP2, this is only for convenience of explanation, and the erase operation can be performed by more erase cycles. Such an erase operation performed by multiple erase cycles as described above can be called incremental step pulse erase (ISPE).

[0086] refer to Fig. 10C , different from Fig. 10B , the first loop erase voltage V_ERS_L11 of the same level may be applied to the first group GP1 and the second group GP2 in the first erase loop LOOP1. For example, the erase voltage applied to the first group GP1 may be represented as a graph D, and the erase voltage applied to the second group GP2 may be represented as a graph C.

[0087] In other words, in the first erase cycle LOOP1, the same first cycle erase voltage V_ERS_L11 is applied to the first group GP1 and the second group GP2, and it can be determined for each group whether to pass the erase. For example, according to the first erase cycle LOOP1, a threshold voltage distribution D_D of the memory cells connected to the first bit line BL1 and the fifth bit line BL5 included in the first group GP1 can be formed at a level lower than the verification voltage Vvfy, so the first group GP1 can be determined as an erase pass group. On the other hand, according to the first erase cycle LOOP1, a threshold voltage distribution D_C of the memory cells connected to the second bit line BL2 and the sixth bit line BL6 included in the second group GP2 can be at least partially formed at a level higher than the verification voltage Vvfy, so the second group GP2 may not be determined as an erase pass group. Next, the second erase cycle LOOP2 can be performed based on the determination of the erase pass group, and an erase voltage of a level lower than the level of the erase voltage applied to the bit line of the second group GP2 can be applied to the bit line of the first group GP1.

[0088] Fig.11 is a circuit diagram showing a memory block according to another exemplary embodiment. Fig.11 , the first memory block BLKa and the second memory block BLKb may be memory blocks arranged vertically. The first memory block BLKa may include a plurality of lower NAND strings including NAND strings NS1a to NS4a, word lines WL1a to WLna, first to fourth ground selection lines GSL1a to GSL4a, first to fourth lower string selection lines SSL1da to SSL4da, first to fourth upper string selection lines SSL1ua to SSL4ua, and a common source line CSLa. Here, n may be any natural number and may vary according to the embodiment. In an exemplary embodiment, the first to fourth ground selection lines GSL1a to GSL4a may be formed in a linear shape. In an exemplary embodiment, the first to fourth ground selection lines GSL1a to GSL4a may be formed in a plate shape.

[0089] In some embodiments, in the first memory block BLKa, the first to fourth ground selection lines GSL1a to GSL4a arranged at the same level may be electrically connected to each other. In addition, in some embodiments, the first memory block BLKa may include one of the first to fourth upper string selection lines SSL1ua to SSL4ua or the first to fourth lower string selection lines SSL1da to SSL4da. In addition, in some embodiments, the first memory block BLKa may further include at least one virtual word line below the first to fourth lower string selection lines SSL1da to SSL4da.

[0090] The second memory block BLKb may include a plurality of upper NAND strings including NAND strings NS1b to NS4b, word lines WL1b to WLmb, first to fourth ground selection lines GSL1b to GSL4b, first to fourth string selection lines SSL1b to SSL4b, and a common source line CSLb. Here, m may be any natural number and may vary according to the embodiment. In an exemplary embodiment, the first to fourth ground selection lines GSL1b to GSL4b may be formed in a linear shape. In an exemplary embodiment, the first to fourth ground selection lines GSL1b to GSL4b may be formed in a plate shape.

[0091] In an exemplary embodiment, m may be less than n, and therefore, the second memory block BLKb may include a smaller number of word lines than the first memory block BLKa. However, the inventive concept is not limited thereto. In some embodiments, m may be equal to n, and therefore, the first memory block BLKa and the second memory block BLKb may include the same number of word lines. In some embodiments, in the second memory block BLKb, the first to fourth ground selection lines GSL1b to GSL4b arranged at the same level may be electrically connected to each other. In addition, in some embodiments, the second memory block BLKb may further include at least one virtual word line below the first to fourth string selection lines SSL1b to SSL4b.

[0092] The lower NAND string included in the first memory block BLKa may be connected to the first bit line BL1 and the second bit line BL2, and the upper NAND string included in the second memory block BLKb may also be connected to the first bit line BL1 and the second bit line BL2. Therefore, the first memory block BLKa and the second memory block BLKb may share the first bit line BL1 and the second bit line BL2. In detail, both ends of the NAND string NS1a may be connected to the first bit line BL1 and the common source line CSLa, respectively, and both ends of the NAND string NS1b may be connected to the common source line CSLb and the first bit line BL1, respectively.

[0093] In an erase operation, an erase voltage may be applied to both the first memory block BLKa and the second memory block BLKb via the first bit line BL1 and the second bit line BL2. According to an exemplary embodiment, a group may be formed in an erase control circuit (eg, Figure 1 Between the bit lines in the erase control circuit 160) and different erase voltages can be applied to the corresponding groups.

[0094] Fig.12 is a diagram schematically showing a structure of a memory device according to another exemplary embodiment. For example, Fig.12 It can be shown Figure 1 Hereinafter, reference will be made to the structure of the memory device 100. Figure 1 To describe Fig.12 . refer to Fig.12 , the memory device 100 may include a first semiconductor layer L1 and a second semiconductor layer L2. The second semiconductor layer L2 may be stacked on the first semiconductor layer L1 along a third direction. In an exemplary embodiment, at least one of the control logic 120, the voltage generator 130, the row decoder 140, the page buffer 150, and the erase control circuit 160 may be in the first semiconductor layer L1, and the memory cell array 110 may be in the second semiconductor layer L2. For example, the first semiconductor layer L1 may include a lower substrate, and the first semiconductor layer L1 may provide various circuits by forming semiconductor devices such as transistors and patterns for wiring the semiconductor devices on the lower substrate.

[0095] After the circuit is formed in the first semiconductor layer L1, the second semiconductor layer L2 including the memory cell array 110 may be formed. For example, the second semiconductor layer L2 may include a substrate, and the memory cell array 110 may be formed in the second semiconductor layer L2 by forming a plurality of gate conductive layers stacked on the substrate and a plurality of pillars extending through the gate conductive layers in a direction perpendicular to the top surface of the substrate (e.g., a third direction). In addition, a pattern (i.e., a word line WL and a bit line BL) for electrically connecting the memory cell array 110 and the circuit formed in the first semiconductor layer L1 may be formed in the second semiconductor layer L2. For example, the word line WL may extend in the first direction and may be arranged in the second direction. In addition, the bit line BL may extend in the second direction and be arranged in the first direction.

[0096] Therefore, the memory device 100 may have a structure in which the control logic 120, the row decoder 140, the page buffer 150 or various other peripheral circuits and the memory cell array 110 are arranged along the stacking direction (e.g., the third direction), that is, a cell-on-peri (COP) structure, which is also referred to as a cell-over-peri (COP) structure. By arranging circuits other than the memory cell array 110 below the memory cell array 110, the COP structure can effectively reduce the area occupied on the surface perpendicular to the stacking direction, and thus the number of memory cells integrated in the memory device 100 can be increased.

[0097] Despite Fig.12Although not shown in the figure, a plurality of pads may be arranged for electrical connection with devices outside the memory device 100. For example, a plurality of pads for commands CMD, addresses ADDR, and control signals CTRL received from devices outside the memory device 100 may be arranged, and a plurality of pads for input / output data DT may be provided. The pads may be arranged to be close to a peripheral circuit that processes a signal received from or transmitted to a device outside the memory device 100 in a vertical direction (third direction) or a horizontal direction (first direction or second direction).

[0098] Fig.13 is a block diagram showing an example of applying a memory device according to an exemplary embodiment to a solid state drive (SSD) system. Fig.13 , the SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 may exchange signals with the host 1100 through a signal connector and receive power through a power connector. The SSD 1200 may include an SSD controller 1210, an auxiliary power supply 1220, and memory devices 1230, 1240, and 1250. At this time, the SSD 1200 may refer to Figures 1 to 12 According to the exemplary embodiments described above, the memory devices 1230, 1240, and 1250 may each include an erase control circuit 1232. Therefore, during an erase operation, groups may be formed between bit lines, and erase voltages different from each other may be applied to corresponding groups. Therefore, the deviation between the threshold voltage distributions after the erase operation may be enhanced, and thus data reliability may be improved.

[0099] As described above, exemplary embodiments have been disclosed in the drawings and the specification. Although the embodiments have been described herein by using specific terms, it should be understood that they are only used for the purpose of describing the inventive concept, and are not used to limit the scope of the inventive concept defined in the claims. Therefore, it will be understood by those of ordinary skill in the art that various modifications and equivalent embodiments are possible without departing from the scope of the inventive concept. Therefore, the true protection scope of the present disclosure should be determined by the technical ideas of the attached claims.

Claims

1. A memory device, comprising: a nonvolatile memory cell array having a plurality of groups spaced apart from each other in a first direction and extending in a second direction perpendicular to the first direction; at least one first bit line electrically coupled to a first group of the plurality of groups of nonvolatile memory cells and extending in the second direction; at least one second bit line electrically coupled to a second group of the plurality of groups of nonvolatile memory cells and extending in the second direction; and The erase control circuit is configured to drive the at least one first bit line and the at least one second bit line with first and second erase voltages that are unequal and at least partially overlap in time during an operation of respectively erasing a first group of the plurality of groups of non-volatile memory cells and a second group of the plurality of groups of non-volatile memory cells.

2. The memory device of claim 1, wherein the nonvolatile memory cells in a first group of the plurality of groups of nonvolatile memory cells are arranged vertically relative to each other on an underlying substrate.

3. The memory device of claim 2 , wherein the nonvolatile memory cell array comprises a plurality of vertical NAND strings of memory cells having respective vertical channel structures electrically coupled to corresponding bit lines; and wherein the erase control circuit is configured to drive a plurality of bit lines with unequal erase voltages during an operation of erasing the plurality of vertical NAND strings of memory cells.

4. The memory device of claim 3 , wherein the unequal erase voltages include a first erase voltage and a second erase voltage having unequal amplitudes; and wherein the erase control circuit is configured to drive a first bit line of the plurality of bit lines with the first erase voltage for a first duration and drive a second bit line of the plurality of bit lines with the second erase voltage for a second duration during an operation of erasing the plurality of vertical NAND strings of memory cells. The memory device of claim 4 , wherein the first duration is shorter than the second duration. 6 . The memory device of claim 1 , wherein a magnitude of the first erase voltage is smaller than a magnitude of the second erase voltage.

7. The memory device of claim 1 , further comprising a word line cut region on the semiconductor substrate; and wherein a first group of the plurality of groups of nonvolatile memory cells extends closer to the word line cut region relative to a second group of the plurality of groups of nonvolatile memory cells.

8. A non-volatile memory device comprising: substrate; a memory cell array including a plurality of vertical channel structures spaced apart from one another along a first direction and a second direction perpendicular to the first direction and extending in a direction perpendicular to the substrate; a plurality of bit lines extending along the second direction and electrically connected to respective ends of the vertical channel structures; and An erase control circuit is configured to form a plurality of groups each including at least two of the bit lines during an erase operation of the memory cell array, and to apply erase voltages that are different from each other and at least partially overlap in time to two or more of the groups.

9. The nonvolatile memory device according to claim 8, Also included is one or more word line cutting regions formed on the substrate and extending along the first direction, wherein a vertical channel structure electrically connected to a bit line included in a first group among the groups is arranged closer to the word line cut region than a vertical channel structure electrically connected to a bit line included in a second group among the groups, and The erase control circuit applies a first erase voltage to the first group, and applies a second erase voltage different from the first erase voltage to the second group.

10. The nonvolatile memory device according to claim 9, Also included is a voltage generator that outputs the first erase voltage and the second erase voltage having different levels.

11. The nonvolatile memory device according to claim 9, Wherein the first erase voltage has a level lower than a level of the second erase voltage.

12. The nonvolatile memory device according to claim 9, wherein the first erase voltage has a first application time, and The second erase voltage has a second application time different from the first application time.

13. The nonvolatile memory device according to claim 12, The first application time is shorter than the second application time.

14. The nonvolatile memory device according to claim 8, The erase control circuit includes a plurality of transistors, each transistor including first to third terminals, A control signal is applied to the first terminal of the transistor, A second terminal of the transistor is electrically connected to the bit line, and At least two of the third terminals of the transistors are electrically connected to each other, and the erase voltage is applied thereto.

15. The nonvolatile memory device according to claim 14, The erase control circuit controls the application time of the erase voltage applied to the corresponding bit line based on the conduction control of the corresponding transistor.

16. The nonvolatile memory device according to claim 8, wherein the erase operation includes a first erase cycle and a second erase cycle, and The erase control circuit applies different erase voltages to at least two of the groups in the second erase cycle based on a result of the first erase cycle.

17. The nonvolatile memory device according to claim 16, The erase control circuit applies different erase voltages to the at least two groups in the first erase cycle.

18. The nonvolatile memory device according to claim 16, The erase control circuit applies the same erase voltage to the at least two groups in the first erase cycle.

19. A non-volatile memory device comprising: a plurality of memory blocks arranged along a first direction and a second direction perpendicular to the first direction, and each memory block includes a plurality of pillars extending along a direction perpendicular to the substrate; a plurality of bit lines extending along the second direction on the memory block and electrically connected to the pillars, respectively; one or more word line cutting regions formed on the substrate and extending along the first direction; control logic for outputting an erase voltage control signal during an erase operation of the memory block; and An erase control circuit is configured to form a first group and a second group, each group including at least two of the bit lines, and in response to the erase voltage control signal, apply a first erase voltage having a first amplitude to the first group and apply a second erase voltage having a second amplitude that is not equal to the first amplitude and at least partially overlapping with the first erase voltage in time to the second group.

20. The nonvolatile memory device according to claim 19, wherein the erase control circuit comprises a plurality of transistors, one end of each of which is electrically connected to the bit lines, respectively, wherein the on / off state of each of the plurality of transistors is controlled based on the erase voltage control signal, and, During the erase operation, a turn-on time of a transistor electrically connected to the bit line included in the first group is different from a turn-on time of a transistor electrically connected to the bit line included in the second group.

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