Device and method for testing memory

Abstract

A device for testing a memory, the memory comprising a first memory circuit and a second memory circuit. The second memory circuit is configured to store a first response of the first memory circuit. The device comprises a comparison circuit and a calculation circuit. The comparison circuit is configured to compare the first response stored in the second memory circuit with a plurality of responses of the first memory circuit operating under different conditions to generate a plurality of first comparison results. The calculation circuit is configured to output a maximum Hamming distance according to the first comparison result, wherein the maximum Hamming distance is between the first response and two of the plurality of responses of the first memory circuit. A method for testing a memory is also disclosed herein.

Description

Technical Field

[0001] The present disclosure relates to a device for testing a memory, and more particularly to a Hamming distance analyzer and an analysis method thereof. Background Art

[0002] Due to many process factors, even if the integrated circuits are manufactured with the same process and the same materials, each integrated circuit (IC) is unique. Each integrated circuit has the opportunity to operate in different operating environments according to its actual application. Therefore, the robustness of one of the multiple integrated circuits under different operating environments is a key issue in the field of semiconductor technology. Summary of the invention

[0003] One aspect of the present disclosure is to disclose a device for testing a memory, and the memory includes a first memory circuit and a second memory circuit. The second memory circuit is configured to store a first response among a plurality of responses of the first memory circuit, and the first memory circuit is configured to store a second response among a plurality of responses of the second memory circuit. The device includes a comparison circuit and a calculation circuit. The comparison circuit is configured to compare the first response stored in the second memory circuit with a plurality of responses of the first memory circuit operating under a plurality of operating conditions corresponding to different operating environments to generate a plurality of first comparison results, and is configured to compare the second response stored in the first memory circuit with a plurality of responses of the second memory circuit operating under a plurality of operating conditions corresponding to different operating environments to generate a plurality of second comparison results, wherein the comparison circuit is further configured to generate a final result based on the plurality of first comparison results and the plurality of second comparison results. The calculation circuit is configured to output a maximum Hamming distance based on the final result, wherein the maximum Hamming distance is between two of the plurality of responses of the first memory circuit.

[0004] One aspect of the present disclosure is to disclose a method for testing a memory, comprising: maintaining a first response among multiple responses of a first memory circuit of a memory under a first operating condition of a plurality of operating conditions; sequentially comparing the first response stored in a second memory circuit of the memory with multiple responses of the first memory circuit under multiple operating conditions corresponding to different operating environments to generate multiple first comparison results, wherein each comparison result of the multiple first comparison results is generated by adjusting a previous comparison result of the multiple first comparison results; maintaining a first response of a second memory circuit of the memory under a second operating condition of the multiple operating conditions; and comparing the first response stored in a second memory circuit of the memory with multiple responses of the first memory circuit under multiple operating conditions corresponding to different operating environments to generate multiple first comparison results. a second response among responses; the second response stored in the first memory circuit of the memory is sequentially compared with the multiple responses of the first memory circuit under multiple operating conditions corresponding to different operating environments to generate multiple second comparison results, wherein each comparison result of the multiple second comparison results is generated by adjusting the previous comparison result of the multiple second comparison results; a final result is generated based on sequentially comparing the first response with the multiple responses of the first memory circuit and sequentially comparing the second response with the multiple responses of the second memory circuit; based on the final result, a maximum difference between two of the multiple responses of the first memory circuit is obtained.

[0005] One aspect of the present disclosure is to disclose a method for testing a memory, comprising: operating a first memory circuit of a memory under a plurality of operating conditions corresponding to different operating environments to obtain a plurality of responses of the first memory circuit, and storing a first response of the plurality of responses of the first memory circuit in a second memory circuit of the memory; sequentially performing a mutually exclusive OR operation on the first response of the plurality of responses of the first memory circuit stored in the second memory circuit of the memory and other plurality of responses of the plurality of responses of the first memory circuit to generate a plurality of comparison results of the plurality of responses of the first memory circuit; operating the second memory circuit under a plurality of operating conditions corresponding to different operating environments to obtain a first response of the plurality of responses of the first memory circuit; and performing a mutually exclusive OR operation on the first response of the plurality of responses of the first memory circuit stored in the second memory circuit of the memory. Multiple responses of two memory circuits, and a second response storing the multiple responses of the second memory circuit in the first memory circuit; sequentially performing an exclusive OR operation on the second response of the multiple responses of the second memory circuit stored in the first memory circuit of the memory and other multiple responses of the multiple responses of the second memory circuit to generate multiple comparison results of the multiple responses of the second memory circuit; generating a final comparison result based on the exclusive OR operation of the first response of the multiple responses of the first memory circuit and the exclusive OR operation of the second response of the multiple responses of the second memory circuit; and outputting a maximum Hamming distance between two of the multiple responses of the first memory circuit based on the final comparison result.

[0006] One aspect of the present disclosure is to disclose a device for testing a memory, comprising: a memory array configured to store a first response among a plurality of responses of a device under test; a comparison circuit configured to compare the first response with a first response of a plurality of responses of the device under test operated under a plurality of operating conditions to generate a plurality of comparison results, the plurality of operations corresponding to different operating environments, wherein the comparison circuit is configured to perform an exclusive OR operation of the first response and each of the plurality of responses to generate a plurality of comparison results, and further configured to generate a final comparison result according to the plurality of comparison results, wherein an X-th bit of a first comparison result of the plurality of comparison results has a first logic value, the first comparison result is generated before a second comparison result of the plurality of comparison results, and an X-th bit of the second comparison result is configured to have the first logic value; and a calculation circuit configured to generate a value of the final comparison result, the value indicating a number of a plurality of bits having the first logic value, and the calculation circuit is configured to generate a maximum Hamming distance according to the value and a bit number of the final comparison result, the maximum Hamming distance indicating a robustness of the device under test between two of the plurality of responses, wherein the bit number is a number of a plurality of bits of the final comparison result.

[0007] One aspect of the present disclosure is to disclose a method for testing a memory, comprising: retaining a first response among a plurality of responses of a device under test in a first operating condition; changing at least one of the plurality of operating conditions of the device under test in response to a plurality of different operating environments to generate a plurality of responses of the device under test; sequentially comparing the first response with a plurality of responses of the device under test in a plurality of operating environments through a comparison circuit to generate a plurality of comparison results, wherein each comparison result of the plurality of comparison results is generated by adjusting a previous comparison result of the plurality of comparison results; generating a final comparison result according to the plurality of comparison results through the comparison circuit; and generating a numerical value of the final comparison result through a calculation circuit. , the numerical value indicates a number of bits having a first logic value, and a maximum difference is generated according to the numerical value and the number of bits of the final comparison result, the maximum difference indicating a robustness of the device under test between two of the plurality of responses, wherein the number of bits is a number of bits of the final comparison result, wherein comparing the first response with the plurality of responses comprises: performing an exclusive OR operation on the first response and a second response of the plurality of responses to generate a first comparison result of the plurality of comparison results, wherein an X-th bit of a comparison result of the plurality of comparison results has a first logic value, the comparison result is generated before the first comparison result, and an X-th bit of the first comparison result is configured to have the first logic value.

[0008] One aspect of the present disclosure is to disclose a method for testing a memory, characterized by comprising: operating a device under test in a plurality of operating conditions corresponding to different operating environments to obtain a plurality of responses of the device under test; performing a first response of the plurality of responses and an exclusive OR operation of the plurality of responses in sequence through a comparison circuit to generate a plurality of comparison results; generating a final comparison result according to the plurality of comparison results through the comparison circuit; and generating a numerical value indicating a number of a plurality of bits having a first logic value in the final comparison result through a calculation circuit, and generating a maximum Hamming distance according to the numerical value and a bit number of the final comparison result, the maximum Hamming distance indicating a stability of the device under test between two of the plurality of responses, wherein the bit number of the final comparison result is a number of the plurality of bits of the final comparison result, wherein an X-th bit of a first comparison result of the plurality of comparison results has a first logic value, the first comparison result is generated before a second comparison result, and an X-th bit of the second comparison result is configured to have the first logic value.

[0009] One aspect of the present disclosure is to disclose a device for testing a memory, wherein the memory includes a first memory circuit and a second memory circuit, the second memory circuit is configured to store a first response among multiple responses of the first memory circuit, and the first memory circuit is configured to store a second response among multiple responses of the second memory circuit, the device includes: a comparison circuit, configured to compare the first response with multiple responses of the first memory circuit, and configured to compare the second response with multiple responses of the second memory circuit to generate multiple comparison results, wherein the comparison circuit is configured to perform a mutual exclusive OR operation of the first response with each of the multiple responses of the first memory circuit to generate multiple comparison results, and is further configured to generate a final comparison result based on the multiple comparison results; and a maximum Hamming distance generation circuit, configured to generate a maximum Hamming distance based on the final result, and multiple bits of the final result have a first logic value.

[0010] One aspect of the present disclosure is to disclose a method for testing a memory, comprising: performing a first exclusive OR operation to compare a first response of a second memory circuit stored in a first memory circuit with multiple responses of the second memory circuit to generate multiple first comparison results; comparing a second response of a second memory circuit stored in a first memory circuit with multiple responses of the first memory circuit to generate multiple second comparison results; generating a final comparison result based on at least multiple first comparison results; and obtaining a maximum difference between two of the multiple responses of the second memory circuit based on a number of bits having a first logic value in the final comparison result.

[0011] One aspect of the present disclosure is to disclose a method for testing a memory, comprising: performing an exclusive OR operation of a first response of multiple responses of a first memory circuit and multiple responses of the first memory circuit to generate multiple first comparison results, wherein the first response is stored in a second memory circuit; performing an exclusive OR operation of a second response of multiple responses of a second memory circuit and multiple responses of the second memory circuit to generate multiple second comparison results, wherein the second response is stored in the first memory circuit; generating a final comparison result based on at least multiple first comparison results; and outputting a maximum Hamming distance between two of the multiple responses of the first memory circuit based on a number of bits having a first logic value in the final comparison result. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The present disclosure is better understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, as is standard practice in the industry, many features are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of many features may be arbitrarily scaled.

[0013] Figure 1 is a schematic diagram illustrating a device and a device to be tested according to various embodiments of the present disclosure;

[0014] Figure 2 The present invention is a diagram showing various embodiments of the present invention. Figure 1 A flowchart of a method for the device to be tested to operate the device;

[0015] Figure 3 The present invention is directed to various embodiments of the present invention. Figure 1 A schematic diagram of the comparison steps of the device and the device to be tested;

[0016] Figure 4 is a schematic diagram illustrating a device and a memory according to various embodiments of the present disclosure;

[0017] Figure 5 The present invention is a diagram showing various embodiments of the present invention. Figure 4 Flow chart of a method for a device to perform an operation on a memory. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or illustrations to implement different features of the invention. The specific examples of components and arrangements described below are intended to simplify the disclosure. These are of course only examples and are not intended to be limiting. For example, the description of a first feature formed on or above a second feature includes embodiments in which the first feature and the second feature are in direct contact, and also includes embodiments in which other features are formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. The dimensions of many features can be drawn in different proportions to simplify and clarify them. In addition, the disclosure repeats component symbols and / or letters in various examples. The purpose of this repetition is to simplify and clarify, and does not indicate any relationship between the various embodiments and / or configurations discussed.

[0019] The terms used in the specification generally have their original meaning in the art, and each term is used for a specific context. The specific examples used in this specification (including any specific examples of the terms discussed herein) are only used for illustration and are not used to limit the scope and meaning of the present disclosure or any illustrative term. Similarly, the present disclosure is not limited to the various embodiments in this specification.

[0020] Although the terms "first" and "second" may be used herein to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. For example, a first component may be a second component, and similarly, a second component may be a first component without departing from the scope of the embodiments. As used, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0021] The terms “comprise,” “comprising,” “include,” “including,” “has,” “having” and the like used in this specification are open-ended and mean “including, but not limited to,”.

[0022] See also Figure 1 . Figure 1 1 is a schematic diagram of a device 100 and a device under test 105 according to various embodiments of the present disclosure.

[0023] In some embodiments, the device 100 is a test device. The device 100 is configured to test the robustness of the device under test 105. In some embodiments, the device 100 is applied to or implemented as an intra-hamming distance analyzer. The device 100 is configured to generate a maximum Hamming distance (HD) of the device under test 105. The maximum Hamming distance HD represents the robustness of the device under test 105. In some embodiments, the Hamming distance HD indicates the number of different bits between two binary numbers.

[0024] In some embodiments, the device under test 105 is a memory array under test. In some other embodiments, the device under test 105 includes a memory array under test. The memory array under test is, for example, a static random access memory (SRAM), a flash memory, or the like, but is not limited thereto. Various memory arrays or units that are used to build or are built in the device under test 105 are within the scope of protection of the present disclosure.

[0025] In some embodiments, the device under test 105 operates under different operating conditions according to its actual application. The operating conditions correspond to different operating environments. For illustration purposes, different operating conditions correspond to different supply voltages, different operating temperatures, different operating frequencies, or a combination thereof.

[0026] In some embodiments, when the device under test 105 operates under different operating conditions, the response of the device under test 105 is different. In some embodiments, each response is the content of the device under test 105 under a specific operating environment. For illustration, the response of the device under test 105 operating at 10°C is different from the response of the device under test 105 operating at 50°C.

[0027] like Figure 1 As shown, in some embodiments, the device 100 includes a memory array 120, a comparison circuit 140, and a calculation circuit 160. In some embodiments, the device 100 further includes a recorder 180. The memory array 120 is coupled to the device under test 105. The comparison circuit 140 is coupled to the memory array 120 and the device under test 105. The recorder 180 is coupled to the comparison circuit 140. The calculation circuit 160 is coupled to the recorder 180.

[0028] The above discussion is merely an example of a connection method that can be used according to various embodiments. It should be understood that the various embodiments are not limited to the specific connection or Figure 1 As shown.

[0029] In addition, in this specification, the term "coupled" may also be referred to as "electrically coupled", and the term "connected" may also be referred to as "electrically connected". "Coupled" and "connected" may also be used to indicate that two or more elements cooperate or interact with each other.

[0030] like Figure 1 As shown, the memory array 120 is configured to generate at least one response of the device under test 105 and store the at least one response. In some embodiments, the at least one response is copied or replicated from the device under test 105 to the memory array 120. In some embodiments, the memory array 120 is a replica of the device under test 105, and accordingly, the memory array 120 generates at least one response that is the same as the at least one response of the device under test 105.

[0031] In some embodiments, the storage capacity of the memory array 120 corresponds to the number of bits of the at least one interface of the DUT 105. For example, if the at least one interface of the DUT 105 has n bits, the storage capacity of the memory array 120 has at least n bits.

[0032] like Figure 1 As shown, the comparison circuit 140 receives the response from the memory array 120. The comparison circuit 140 also receives the response obtained from the device under test 105 under different operating conditions. The comparison circuit 140 is configured to sequentially compare the response from the memory array 120 with multiple responses from the device under test 105 to generate corresponding comparison results.

[0033] like Figure 1 As shown, in some embodiments, the comparison circuit 140 includes at least one exclusive OR gate 142. The exclusive OR gate 142 has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the memory array 120 to receive the response from the memory array 120. The second input terminal is coupled to the device under test 105 to receive the response obtained from the device under test 105 under different operating conditions. The output terminal of the exclusive OR gate 142 is coupled to the recorder 180.

[0034] The XOR gate 142 is configured to sequentially perform an XOR operation on the response from the memory array 120 and the response from the DUT 105 to generate corresponding comparison results. The comparison results are output to the recorder 180.

[0035] The configuration of the comparison circuit 140 is for illustration purposes only. Various configurations of the comparison circuit 140 are within the scope of the present disclosure. For example, in some other embodiments, the comparison circuit 140 includes more than one exclusive OR gate, and in some other embodiments, the comparison circuit 140 includes a plurality of exclusive OR gates, the number of which corresponds to the same number of responses from the device under test 105. In some other embodiments, the comparison circuit 140 is implemented by other logic elements.

[0036] like Figure 1 As shown, the recorder 180 is configured to temporarily store the comparison result generated by the comparison circuit 140. Then, according to the comparison result, the recorder 180 generates a final comparison result FC. In some embodiments, the final comparison result FC indicates the comparison result generated by comparing the response from the memory array 120 with the final response from the device under test 105.

[0037] The number of recorders 180 is for illustrative purposes only. Various numbers of recorders 180 are within the scope of protection of the present disclosure. In some other embodiments, the device 100 includes more than one recorder. For example, in some other embodiments, the device 100 includes two recorders. A first recorder of the two recorders is coupled to the comparison circuit 140 to temporarily store a comparison of two corresponding bits from the comparison circuit 140. A second recorder of the two recorders is coupled to the first recorder and is configured to generate a final comparison result FC, which is based on multiple comparisons of different two corresponding bits from the first recorder.

[0038] like Figure 1 As shown, the calculation circuit 160 is configured to receive the final comparison result FC from the recorder 180. The calculation circuit 160 is further configured to output the maximum Hamming distance HD according to the final comparison result FC. The maximum Hamming distance HD represents the maximum difference between two responses from the device under test 105.

[0039] like Figure 1 As shown, in some embodiments, the calculation circuit 160 includes a counter 162 and a maximum Hamming distance generation circuit 164. The counter 162 is coupled to the recorder 180. The maximum Hamming distance generation circuit 164 is coupled to the counter 162.

[0040] The counter 162 is configured to receive the aforementioned final comparison result FC from the recorder 180. According to the final comparison result FC, the value counted by the counter 162 indicates the number of bits of the final comparison result FC having the same logic value. In some embodiments, the same logic value is "1". In other words, if the 4 bits of the final comparison result FC have the logic value "1", the counter 162 outputs data indicating 4 to the maximum Hamming distance generation circuit 164. In some embodiments, the counter 162 is implemented by a group counter composed of a plurality of adders (not shown). In other embodiments, the counter 162 is implemented by other logic gates.

[0041] Next, the maximum Hamming distance generating circuit 164 generates the maximum Hamming distance HD according to the aforementioned values ​​and the total number of bits of the final comparison result FC. The maximum Hamming distance HD represents the maximum difference between the two responses from the device under test 105. In some embodiments, the maximum Hamming distance generating circuit 164 is implemented by a subtractor (not shown) or includes a subtractor, but is not limited thereto. In other embodiments, the maximum Hamming distance generating circuit 164 is implemented by other logic gates.

[0042] The configuration of the computing circuit 160 is for illustration purposes only. Various configurations of the computing circuit 160 are within the scope of the present disclosure.

[0043] Furthermore, Figure 1 The configuration of the device 100 is for illustration purposes only. Various configurations of the device 100 are within the scope of protection of the present disclosure.

[0044] See also Figure 2 and Figure 3 . Figure 2 The present invention is a diagram showing various embodiments of the present invention. Figure 1 The device 100 is a flowchart of a method 200 for operating the device under test 105. Figure 3 The present invention is directed to various embodiments of the present invention. Figure 1 Schematic diagram of the comparison steps of the device 100 and the device under test 105.

[0045] Figure 1 The operation between the device 100 and the device under test 105 is performed by the following Figure 2 For a better understanding of the present disclosure, the method 200 is described in detail. Figure 1 and Figure 3 To explain.

[0046] In operation 202, when the device under test 105 is operating under the first operating condition, the response R1 of the device under test 105 can be obtained. In some embodiments, the first operating condition is the initial operating condition of the device under test 105, but is not limited thereto. Therefore, the response R1 is the content of the device under test 105 under the initial operating condition. Figure 3 As shown, the response R1 is 01010101. In other words, when the device under test 105 is operating under the initial condition, the content of the device under test 105 is 01010101. Furthermore, when the device under test 105 is operating under the first operating condition, the initial reference value C0 in the recorder 180 is reset to 0000000.

[0047] The bit numbers of the response R1 and other responses of the device under test 105 are for illustration purposes only. Various bit numbers of the response R1 and other responses of the device under test 105 are within the scope of protection of the present disclosure. For example, in other embodiments, the response R1 or each other response of the device under test 105 has less than 8 bits or more than 8 bits.

[0048] In operation 204, the response R1 is copied to the memory array 120. In some embodiments, the response R1 is copied or copied from the device under test 105 and is retained in the memory array 120. In other words, for the sake of illustration, in the following operations, the response R1 of 01010101 is stored in the memory array 120 and is unchangeable. In various embodiments, the memory array 120 is a copy of the device under test 105, and therefore, the memory array 120 generates at least one response that is the same as the response from the device under test 105.

[0049] In operation 206, the operating condition of the device under test 105 is changed. For example, the operating condition of the device under test 105 is changed from the first operating condition to the second operating condition. In some embodiments, the second operating condition is different from the first operating condition.

[0050] In operation 208, a new response of the device under test 105 is obtained. As described above, when the operating conditions of the device under test 105 change, the content of the device under test 105 changes accordingly. In some embodiments, the new response R2 is considered as the changed content in the device under test 105. For illustration, the response R2 of the device under test 105 is 01000101.

[0051] In operation 210, the comparison circuit 140 compares the response R1 and the response R2 of the device under test 105 to generate a comparison result C1. In some embodiments, the exclusive OR gate 142 performs an exclusive OR operation on each bit of the response R1 and the corresponding bit of the response R2 to adjust the starting reference value C0 so that the starting reference value C0 is adjusted to the comparison result C1.

[0052] See also Figure 3 To illustrate, the exclusive OR gate 142 performs an exclusive OR operation on the first bit corresponding to R1 and the first bit corresponding to R2. In some embodiments, the first bit is considered as, for example Figure 3 The first bit is shown as corresponding to the rightmost bit in the eight bits in R1, and the second bit is treated as corresponding to the bit adjacent to the rightmost bit in the eight bits in R1, and so on. Figure 3 To explain, the first bit corresponding to R1 and the first bit corresponding to R2 have the same logic value "1", so the result of the exclusive OR operation on the two bits is a logic value "0". Therefore, the first bit of the comparison result C1 remains to have a logic value "0", which is the same as the first bit of the starting reference value C0.

[0053] Next, the exclusive OR gate 142 performs an exclusive OR operation on the second bit corresponding to R1 and the second bit corresponding to R2. Since the second bit corresponding to R1 and the second bit corresponding to R2 have the same logic value "0", the result of the exclusive OR operation on the two bits is a logic value "0". Therefore, the second bit of the comparison result C1 remains to have a logic value "0", which is the same as the second bit of the starting reference value C0.

[0054] Accordingly, the third bit of the comparison result C1 , the fourth bit of the comparison result C1 , the sixth bit of the comparison result C1 , the seventh bit of the comparison result C1 , and the eighth bit of the comparison result C1 remain to have a logic value of “0”.

[0055] For illustration, the fifth bit of R1 has a logic value of "1", but the fifth bit of R2 has a logic value of "0", so the result of the exclusive OR operation on the two bits is a logic value of "1". Therefore, the fifth bit of the comparison result C1 crosses from a logic value of "0" to a logic value of "1".

[0056] Therefore, the initial reference value C0 is adjusted to the comparison result C1. The comparison result C1 is 00010000. The comparison result C1 is temporarily stored in the recorder 180.

[0057] In operation 212, it is confirmed whether there are other operating conditions for testing the device under test 105. In some embodiments, the confirmation step is performed by a controller (not shown) or a process circuit (not shown), but is not limited thereto. If there are other operating conditions for testing (e.g., a third operating condition), operation 206 is performed again. In other words, the operating condition of the device under test 105 is changed from the second operating condition to the third operating condition. In some embodiments, the third operating condition is different from the second operating condition and different from the first operating condition.

[0058] When the device under test 105 operates under the third operating condition, a new response of the device under test 105 can be obtained. Figure 3 As shown, the new response of the device under test 105 is 01111001. Next, the XOR gate 142 performs an XOR operation on the response R1 and the response R3 stored in the memory array 120.

[0059] In some embodiments, if the Xth bit of a comparison result has a predetermined logic value (e.g., logic value "1"), the Xth bit of the following comparison result is maintained. For illustration, the fifth bit of the comparison result C1 has a logic value "1". Regardless of the result of the exclusive or operation on the fifth bit of R1 and the fifth bit of R3, the fifth bit of the following comparison result C2 is maintained as having a logic value "1", such as Figure 3 shown.

[0060] In addition, if the Yth bit of the comparison result has a specific logic value (e.g., logic value "0"), the Yth bit of the following comparison results may be changed. In some embodiments, X and Y are positive integers. For illustration purposes, as described above, each pair has n bits. X and Y are less than or equal to n, and Y is different from X.

[0061] For the purpose of explanation, since the first bit corresponding to R1 and the first bit corresponding to R3 have the same logic value (e.g., logic value "0"), the result of the exclusive OR operation on the two bits is logic value "0". Therefore, the first bit of the comparison result C2 is maintained to have logic value "0".

[0062] Accordingly, the second bit of the comparison result C2, the seventh bit of the comparison result C2, and the eighth bit of the comparison result C2 are maintained to have a logic value of “0”.

[0063] For illustration, since the third bit corresponding to R1 and the third bit corresponding to R3 have different logic values, the result of the exclusive OR operation on the two bits is logic value “1”. Therefore, the third bit of the comparison result C2 is changed to logic value “1”.

[0064] Accordingly, the third bit of the comparison result C2, the fourth bit of the comparison result C2, and the sixth bit of the comparison result C2 are maintained to have a logic value of “1”.

[0065] Therefore, the comparison result C1 of 00010000 is adjusted to form a comparison result C2 of 00111100. The comparison result C2 is temporarily stored in the recorder 180. In other words, the comparison result C2 is generated by adjusting the previous comparison result C1.

[0066] After the comparison result C2 is generated, if there are further other operating conditions for testing (e.g., the fourth operating condition), operation 206 is input again. Then, the device under test 105 operates under the fourth operating condition. Therefore, the corresponding response R4 can be obtained. In some embodiments, the fourth operating condition is different from the aforementioned operating condition.

[0067] like Figure 3 As shown, the new response R4 of the device under test 105 is 01000101. Next, the exclusive OR gate 142 performs an exclusive OR operation on the response R1 and the response R4 from the memory array 120 .

[0068] by Figure 3 As an illustration, only the fifth bit corresponding to R4 and the corresponding bit corresponding to R1 have different logic values ​​from each other. The fifth bit of the comparison result C2 has a logic value of "1". Therefore, the fifth bit of the comparison result C3 still has a logic value of "1". Each of the other bits corresponding to R4 has the same logic value as the corresponding bit corresponding to R1. Therefore, the other bits of the comparison result C3 are maintained. Therefore, the comparison result C3 is the same as the comparison result C2. The comparison result C3 is temporarily stored in the recorder 180.

[0069] After the comparison result C3 is generated, if there are other operating conditions for testing (e.g., the fifth operating condition), operation 206 is input again. Then, the operating condition of the device under test 105 is changed from the fourth operating condition to the fifth operating condition. Therefore, a corresponding response R5 can be obtained. In some embodiments, the fifth operating condition is different from the aforementioned operating condition.

[0070] by Figure 3 For illustration, the new response R5 of the device under test 105 is 10000110. Next, the XOR gate 142 performs an XOR operation on the response R1 and the response R5 from the memory array 120 .

[0071] The first bit corresponding to R5 and the first bit corresponding to R1 have different logic values. Therefore, the first bit of the comparison result C4 is adjusted to have a logic value of "1". Accordingly, the second bit of the comparison result C4, the seventh bit of the comparison result C4, and the eighth bit of the comparison result C4 are adjusted to have a logic value of "1". Therefore, the comparison result C3 of 00111100 is adjusted to form a comparison result C4 of 11111111. The comparison result C4 is temporarily stored in the recorder 180.

[0072] by Figure 3 For illustration, after the comparison result C4 is generated, if there is no operating condition to be tested, the operation 214 of the method 200 is performed. The comparison result C4 is regarded as the final comparison result FC mentioned above.

[0073] In some other embodiments, the comparison circuit 140 includes a plurality of exclusive OR gates 142. As an illustration, the comparison circuit 140 includes eight exclusive OR gates 142. Each exclusive OR gate performs an exclusive OR operation on a corresponding bit of R1 and one of the corresponding bits.

[0074] The number of XOR gates 142 in the comparison circuit 140 is for illustration purposes only. Various numbers of XOR gates 142 in the comparison circuit 140 are within the scope of the present disclosure.

[0075] In operation 214, counter 162 generates a value having the same logic value as the bit in comparison result C4. In some embodiments, the logic value of the bit in comparison result C4 is a logic value "1". In other words, counter 162 counts the number of bits having a logic value "1" in comparison result FC. As an illustration, comparison result FC is 11111111. Therefore, the value counted by counter 162 is equal to the value 8. As described above, in some embodiments, counter 162 is implemented as a group counter composed of a plurality of adders (not shown). Therefore, in the aforementioned embodiments, the value 8 is in binary form, such as 1000, but is not limited thereto.

[0076] In operation 216, the maximum Hamming distance generating circuit 164 generates the maximum Hamming distance HD according to the aforementioned value from the counter 162 and the total number of bits of the comparison result FC. As an illustration, the maximum Hamming distance generating circuit 164 calculates the ratio of the value generated by the counter to the total number of bits of the comparison result FC. In other words, if the comparison result C4 has n bits, and the comparison result C4 has m bits with a logic value of "1", the maximum Hamming distance HD is substantially equal to m / n, where m and n are positive integers.

[0077] In some embodiments, the maximum Hamming distance HD is presented in the form of a percentage. Figure 3 As shown, the total number of bits of the comparison result FC is 8. The number of bits having a logic value of "1" in the comparison result FC is also 8. Therefore, the maximum Hamming distance HD is 100%.

[0078] The method 200 described above includes exemplary operations, but the operations of the method 200 are not necessarily performed in the order described. The order of the operations of the method 200 disclosed in the present disclosure may be changed, or the operations may be appropriately performed simultaneously or partially simultaneously, which is in accordance with the spirit and scope of various embodiments of the present disclosure.

[0079] Furthermore, since the aforementioned maximum Hamming distance HD is generated based on the responses of the same device under test 105, in some embodiments, the maximum Hamming distance HD is the internal Hamming distance of the device under test 105. The maximum Hamming distance HD represents Figure 3 The maximum difference between any two of R1-R5 is shown. Figure 3 As an illustration, among the responses R1-R5 of the device under test 105, all bits of the response R3 are different from the corresponding bits of the response R5. In other words, the difference between the response R3 and the response R5 is 100%. Therefore, the maximum Hamming distance HD of the device under test 105 is 100%.

[0080] In some embodiments, when the maximum Hamming distance HD of the device under test is 0%, it means that the device under test is perfectly repeatable and stable under different operating environments.

[0081] In some embodiments, when the maximum Hamming distance HD is higher than a preset value, the device under test 105 needs to be repaired or debugged. The preset value can be dynamically adjusted, but is not limited thereto.

[0082] In some embodiments, the apparatus 100 and the DUT 105 are disposed on the same wafer or the same die. Therefore, the apparatus 100 directly measures the DUT 105 on the wafer or the die. In some embodiments, the apparatus 100 measures the DUT 105 on a wafer acceptance testing (WAT) station.

[0083] In the apparatus 100 discussed in the present disclosure, the apparatus 100 measures the device under test 105 online without downloading any response of the device under test 105. In addition, only the maximum Hamming distance HD is output. Therefore, the time for downloading the response can be saved, and the storage space for storing the downloaded response can also be saved.

[0084] See also Figure 4 . Figure 4 FIG. 1 is a schematic diagram illustrating a device 100A and a memory 105A according to various embodiments of the present disclosure.

[0085] In some embodiments, the device 100A is a test device. The device 100A is configured to test the stability of the memory 105A. In some embodiments, the device 100A is applied to or implemented as an internal Hamming distance analyzer. The device 100A is configured to generate a maximum Hamming distance HD of the memory 105A. The maximum Hamming distance HD represents the stability of the memory 105A. In some embodiments, the Hamming distance HD indicates the number of different bits between two bins.

[0086] In some embodiments, the memory 105A is, for example, a static random access memory, a flash memory, or the like, but is not limited thereto. Various memory arrays or units used to implement the device under test 105 or implemented in the device under test 105 are within the scope of protection of the present disclosure. In other embodiments, the memory 105A includes a memory circuit 101A and a memory circuit 103A. In some embodiments, the memory circuit 101A is the device under test.

[0087] In some embodiments, the memory circuit 101A and the memory circuit 103A are operated under various operating conditions according to actual applications. The various conditions correspond to various operating environments. As an illustration, the various operating conditions include various supply voltages, various operating temperatures, various operating frequencies, or a combination thereof.

[0088] like Figure 4 As shown, in some embodiments, the device 100A includes a comparison circuit 140A and a calculation circuit 160A. In some embodiments, the device 100A further includes a recorder 180A. The comparison circuit 140A is coupled to the memory 105A. The recorder 180A is coupled to the comparison circuit 140A. The calculation circuit 160A is coupled to the recorder 180A. In some embodiments, the comparison circuit 140A includes an exclusive OR gate or is constructed by an exclusive OR gate.

[0089] The above discussion is merely an example of the connection methods used according to various embodiments. It should be understood that the various embodiments are not limited to the above or Figure 4 Specific connection method shown.

[0090] like Figure 4 As shown, the memory circuit 103A is configured to generate at least one response of the memory circuit 101A and store the at least one response. In some embodiments, the at least one response is copied or replicated from the memory circuit 101A to the memory circuit 103A, so the at least one response generated by the memory circuit 103A is the same as the at least one response generated by the memory circuit 101A.

[0091] like Figure 4 As shown, the comparison circuit 140A receives the response from the memory circuit 103A. In some embodiments, the comparison circuit 140A also receives the response from the memory circuit 101A obtained under different operating conditions. The comparison circuit 140A is configured to sequentially compare the response from the memory circuit 103A and the response from the memory circuit 101A to generate a corresponding comparison result.

[0092] In some embodiments, the comparison circuit 140A is configured to sequentially perform an exclusive OR operation of the response from the memory circuit 103A and the response from the memory circuit 101A to generate corresponding comparison results. These comparison results are output to the recorder 180A. In some embodiments, when the comparison results are obtained, the roles of the memory circuit 101A and the memory circuit 103A are reversed and the aforementioned operation is performed again.

[0093] like Figure 4 As shown, the recorder 180A is configured to temporarily store the comparison result generated by the comparison circuit 140A. Then, the recorder 180A generates a final comparison result FC based on the comparison result. In some embodiments, the final comparison result FC indicates the comparison result generated by comparing the response from the memory circuit 103A and the final response from the memory circuit 101A.

[0094] In some embodiments, the recorder 180A includes a record circuit 182A and a record circuit 184A. The record circuit 182A is configured to temporarily store a comparison result generated by comparing the response from the memory circuit 103A with the response from the memory circuit 101A under different operating conditions. The record circuit 184A is configured to temporarily store a comparison result generated by comparing the response from the memory circuit 101A with the response from the memory circuit 103A under different operating conditions.

[0095] like Figure 4 As shown, the calculation circuit 160A is configured to obtain the final comparison result FC from the recording circuit 182A and the recording circuit 184A. The calculation circuit 160A is further configured to output the maximum Hamming distance HD according to the final comparison result FC. The maximum Hamming distance HD represents the maximum difference between the two responses from the memory circuit 101A and the two responses from the memory circuit 103A.

[0096] like Figure 4 As shown, in some embodiments, the calculation circuit 160A includes a counter 162A and a maximum Hamming distance generation circuit 164A. The counter 162A is coupled to the recording circuit 182A and the recording circuit 184A. The maximum Hamming distance generation circuit 164A is coupled to the counter 162A.

[0097] The counter 162A is configured to receive the aforementioned final comparison result FC from the recording circuit 182A and the recording circuit 184A. According to the final comparison result FC, the value counted by the counter 162A indicates the number of bits of the final comparison result FC having the same logic value. In some embodiments, the same logic value is "1". In other words, if the 4 bits of the final comparison result FC have the logic value "1", the counter 162A outputs data indicating 4 to the maximum Hamming distance generating circuit 164A. In some embodiments, the counter 162A is implemented by a group counter composed of a plurality of adders (not shown). In other embodiments, the counter 162A is implemented by other logic gates.

[0098] Next, the maximum Hamming distance generating circuit 164A generates the maximum Hamming distance HD according to the aforementioned values ​​and the total number of bits of the final comparison result FC. The maximum Hamming distance HD represents the maximum difference between the two responses from the memory circuit 101A. In some embodiments, the maximum Hamming distance generating circuit 164A is implemented by a subtractor (not shown) or includes a subtractor, but is not limited thereto. In other embodiments, the maximum Hamming distance generating circuit 164A is implemented by other logic gates.

[0099] See also Figure 5 . Figure 5 The present invention is a diagram showing various embodiments of the present invention. Figure 4 Flow chart of method 200A for operating device 100A and memory 105A.

[0100] The following is Figure 5 The illustrated method 200A describes the operation between the device 100A and the memory 105A. For ease of understanding, the method 200A is combined with Figure 4 Have a discussion.

[0101] In operation 202A, when the memory circuit 101A operates under the first operating condition, the response of the memory circuit 101A is obtained. In some embodiments, the first operating condition is an initial operating condition of the memory circuit 101A, but is not limited thereto.

[0102] In operation 204A, the response is copied or replicated to memory circuit 103A. In some embodiments, the response is copied or replicated from memory circuit 101A and maintained in memory circuit 103A.

[0103] In operation 206A, the operating condition of the memory circuit 101A is changed. For example, the operating condition of the memory circuit 101A is changed from the first operating condition to the second operating condition. In some embodiments, the second operating condition is different from the first operating condition.

[0104] In operation 208A, a new response of the memory circuit 101A is obtained. As described above, when the operating conditions of the memory circuit 101A change, the content of the memory circuit 101A changes accordingly.

[0105] In operation 210A, the comparison circuit 140A compares the new response with the response of the memory circuit 103A to generate a comparison result.

[0106] In operation 212A, it is confirmed whether there are other operating conditions for testing the memory circuit 101A. In some embodiments, the confirmation step is performed by a controller (not shown) or a process circuit (not shown), but is not limited thereto. If there are other operating conditions for testing (e.g., a third operating condition), operation 206A is performed again. In other words, the operating condition of the memory circuit 101A is changed from the second operating condition to the third operating condition. In some embodiments, the third operating condition is different from the second operating condition and different from the first operating condition.

[0107] If there are no other operating conditions to be tested, operation 202B of method 200A is performed. In some embodiments, the roles of memory circuit 101A and memory circuit 103A are reversed, which will be described below.

[0108] In operation 202B, when the memory circuit 103A operates under the first corresponding operating condition, a response of the memory circuit 103A is obtained.

[0109] In operation 204B, the response is copied or replicated into memory circuit 101A. In some embodiments, the response is copied or replicated from memory circuit 103A and maintained in memory circuit 101A.

[0110] In operation 206B, the operating condition of the memory circuit 103A is changed. For example, the operating condition of the memory circuit 103A is changed from the first operating condition to the second operating condition. In some embodiments, the second operating condition is different from the first operating condition.

[0111] In operation 208B, a new response of the memory circuit 103A is obtained. As described above, when the operating conditions of the memory circuit 103A change, the content of the memory circuit 103A changes accordingly.

[0112] In operation 210B, the comparison circuit 140A compares the new response with the response of the memory circuit 101A to generate a comparison result.

[0113] In operation 212B, it is determined whether there are other operating conditions for testing the memory circuit 103A. If there are other operating conditions for testing (eg, the third operating condition), operation 206B is performed again.

[0114] If there are no other operating conditions to test, proceed to operation 214A of method 200A.

[0115] In operation 214A, counter 162A generates a numerical value having the same logical value as the bit in the comparison result. In some embodiments, the logical value of the bit in the comparison result is a logical value "1". In other words, counter 162A counts the number of bits having a logical value "1" in comparison result FC. As an illustration, comparison result FC is 11111111 (binary). Therefore, the value counted by counter 162A is equal to the numerical value 8. As described above, in some embodiments, counter 162A is implemented as a group counter composed of a plurality of adders (not shown). Therefore, in the aforementioned embodiments, the numerical value 8 is in binary form, such as 1000, but is not limited thereto.

[0116] In operation 216A, the maximum Hamming distance generating circuit 164A generates the maximum Hamming distance HD according to the aforementioned value from the counter 162A and the total number of bits of the comparison result FC. As an illustration, the maximum Hamming distance generating circuit 164A calculates the ratio of the value generated by the counter to the total number of bits of the comparison result FC. In other words, if the comparison result has n bits, and the comparison result has m bits with a logic value of "1", the maximum Hamming distance HD is substantially equal to m / n, where m and n are positive integers.

[0117] Compared to Figure 1 In some embodiments, the memory array 120 and the device under test 105 are shown. Figure 4 The embodiment in FIG. 1 only shows a memory 105A including a memory circuit 101A and a memory circuit 103A, which are respectively configured as a memory array and a device under test, or vice versa. Figure 4 In the embodiment of FIG. 1 , the memory 105A may be configured as a device under test for generating PUF bits, and the memory array is used to store responses from the device under test. Figure 4 The overall area of ​​the device can be reduced.

[0118] In some embodiments, a device for testing a memory is disclosed, the memory comprising a first memory circuit and a second memory circuit. The second memory circuit is configured to store a first response of the first memory circuit. The device comprises a comparison circuit and a calculation circuit. The comparison circuit is configured to compare the first response stored in the second memory circuit with a plurality of responses of the first memory circuit operating under different conditions to generate a plurality of first comparison results. The calculation circuit is configured to output a maximum Hamming distance according to the first comparison result, wherein the maximum Hamming distance is between the first response and two of the plurality of responses of the first memory circuit.

[0119] In some embodiments, the first memory circuit is configured to store a second response of the second memory circuit. The comparison circuit is configured to compare the second response stored in the first memory circuit with multiple responses of the second memory circuit operating under different conditions to generate multiple second comparison results.

[0120] In various embodiments, the calculation circuit is configured to output a maximum Hamming distance according to the second comparison result, wherein the maximum Hamming distance is between the second response and two of the plurality of responses of the second memory circuit.

[0121] In some embodiments, the device further includes a recorder, and the recorder includes a first recording circuit and a second recording circuit. The first recording circuit is configured to store a first comparison result for calculating the maximum Hamming distance, and the second recording circuit is configured to store a second comparison result for calculating the maximum Hamming distance.

[0122] In various embodiments, the comparison circuit includes an exclusive OR gate configured to perform an exclusive OR operation on the first pair and each pair of the first memory circuit, and to perform an exclusive OR operation on the second pair and each pair of the second memory circuit.

[0123] In some embodiments, the calculation circuit includes a counter. The counter is configured to generate a first value, wherein the first value indicates the number of bits having the same logic value in the corresponding comparison result of the first comparison result, and the counter is configured to generate a second value, wherein the second value indicates the number of bits having the same logic value in the corresponding comparison result of the second comparison result.

[0124] In various embodiments, the calculation circuit is further configured to generate the maximum Hamming distance according to the first value and the bit number of the corresponding comparison result of the first comparison result, and to generate the maximum Hamming distance according to the second value and the bit number of the corresponding comparison result of the second comparison result.

[0125] A method is also disclosed, which includes the following operations. A first response of a first memory circuit of a memory is maintained under a first operating condition. The first response stored in a second memory circuit of the memory is sequentially compared with a plurality of responses of the first memory circuit under the operating condition to generate a plurality of first comparison results. The aforementioned operating conditions are different from each other. Each comparison result of the plurality of first comparison results is generated by adjusting a previous comparison result of the plurality of first comparison results. Based on the plurality of first comparison results, a maximum difference is obtained, wherein the maximum difference is between the first response and two of the responses of the first memory circuit.

[0126] In some embodiments, the method further comprises the following operations. Maintaining a second response of a second memory circuit of the memory under a second operating condition. The second response stored in the first memory circuit of the memory is sequentially compared with a plurality of responses of the second memory circuit under the operating condition to generate a plurality of second comparison results. The aforementioned operating conditions are different from each other. Each comparison result of the plurality of second comparison results is generated by adjusting a previous comparison result of the plurality of second comparison results.

[0127] In various embodiments, maintaining the first response of the first memory circuit includes the following operations: Copying the first response to a second memory circuit of the memory; and maintaining the copied first response in the second memory circuit.

[0128] In some embodiments, maintaining the first response includes the following operations: generating the first response through a second memory circuit.

[0129] In various embodiments, maintaining the second response of the second memory circuit includes the following operations: Copying the second response to the first memory circuit of the memory; and maintaining the copied second response in the first memory circuit.

[0130] In some embodiments, maintaining the second response includes the following operations: generating the second response through the first memory circuit.

[0131] In some embodiments, the method further comprises the following operations: Temporarily storing the first comparison result and the second comparison result to calculate the maximum Hamming distance.

[0132] In various embodiments, the operation of obtaining the maximum difference value includes the following operations: generating a first value, wherein the first value indicates the number of bits having the same logical value in a corresponding comparison result of the first comparison result; generating a second value, wherein the second value indicates the number of bits having the same logical value in a corresponding comparison result of the second comparison result.

[0133] In some embodiments, outputting the maximum Hamming distance further includes the following operations: generating the maximum Hamming distance according to the first value and the number of bits of the corresponding comparison result of the first comparison result; generating the maximum Hamming distance according to the second value and the number of bits of the corresponding comparison result of the second comparison result.

[0134] In various embodiments, comparing the first response of the second memory circuit stored in the memory with the response of the first memory circuit includes the following operations: performing an exclusive OR operation of the first response stored in the second memory circuit with each response of the first memory circuit.

[0135] In some embodiments, comparing the second response of the first memory circuit stored in the memory with the response of the second memory circuit includes the following operations: performing an exclusive OR operation on the second response stored in the first memory circuit and each response of the second memory circuit.

[0136] A method is further disclosed, which includes the following operations. A first memory circuit of a memory is operated under different conditions to obtain multiple responses of the first memory circuit. The multiple responses of the first memory circuit are stored in a second memory circuit of the memory. A mutual exclusive OR operation is sequentially performed on the multiple responses of the first memory circuit stored in the second memory circuit of the memory and other responses of the response of the first memory circuit to generate a final comparison result. According to the final comparison result, a maximum Hamming distance between the first response and two of the other responses is output.

[0137] In some embodiments, outputting the maximum Hamming distance includes the following operations: generating a value, wherein the value indicates the number of bits having the same logic value in the final comparison result; and generating the maximum Hamming distance according to the value and the number of bits in the final comparison result.

[0138] The above summary summarizes the features of many embodiments, so that those with ordinary knowledge in the art can better understand the aspects of the present disclosure. Those with ordinary knowledge in the art should understand that other processes and structures can be designed or modified based on the present disclosure to achieve the same purpose and / or achieve the same advantages as the embodiments described. Those with ordinary knowledge in the art should also understand that equivalent structures do not deviate from the spirit and scope of the present disclosure, and various changes, exchanges and substitutions can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A device for testing a memory, characterized in that: The memory includes a first memory circuit and a second memory circuit, the second memory circuit is configured to store a first response among a plurality of responses of the first memory circuit, and the first memory circuit is configured to store a second response among a plurality of responses of the second memory circuit, the device includes: a comparison circuit configured to compare the first response stored in the second memory circuit with the responses of the first memory circuit operating under a plurality of operating conditions corresponding to different operating environments to generate a plurality of first comparison results, and configured to compare the second response stored in the first memory circuit with the responses of the second memory circuit operating under a plurality of operating conditions corresponding to the different operating environments to generate a plurality of second comparison results, wherein the comparison circuit is further configured to generate a final result according to the plurality of first comparison results and the plurality of second comparison results; as well as A calculation circuit is configured to output a maximum Hamming distance according to the final result, wherein the maximum Hamming distance is between two of the responses of the first memory circuit.

2. The device according to claim 1, wherein When an X-th bit of a comparison result of a plurality of first comparison results has a first logic value, an X-th bit of a following comparison result of the plurality of first comparison results is adjusted to have the first logic value, wherein the comparison result is generated before the following comparison result, and Each of the plurality of first comparison results has n bits, each of the plurality of responses has n bits, each of X and n is a positive integer, and X is less than or equal to n. 3 . The apparatus according to claim 1 , wherein the calculation circuit is configured to output a maximum Hamming distance between two of the responses of the second memory circuit according to the final result.

4. The device according to claim 3, further comprising: A recorder is configured to store the multiple first comparison results, the multiple second comparison results and the final result, wherein the recorder includes a first recording circuit and a second recording circuit, the first recording circuit is configured to store the multiple first comparison results used to calculate the maximum Hamming distance, and the second recording circuit is configured to store the multiple second comparison results used to calculate the maximum Hamming distance.

5. The device according to claim 3, wherein the comparison circuit comprises: An exclusive OR gate is configured to perform an exclusive OR operation on the first response and each of the plurality of responses of the first memory circuit, and to perform an exclusive OR operation on the second response and each of the plurality of responses of the second memory circuit.

6. The device according to claim 3, wherein the computing circuit comprises: A counter is configured to generate a first value, wherein the first value indicates a number of bits having a same logic value in a corresponding comparison result of the plurality of first comparison results, and the counter is configured to generate a second value, wherein the second value indicates a number of bits having a same logic value in a corresponding comparison result of the plurality of second comparison results.

7. The device according to claim 6, wherein the calculation circuit is further configured to generate the maximum Hamming distance according to the first value and a bit number of the corresponding comparison result of the plurality of first comparison results, and to generate the maximum Hamming distance according to the second value and a bit number of the corresponding comparison result of the plurality of second comparison results.

8. The device according to claim 2, wherein When a Y-th bit of the comparison result of the plurality of first comparison results has a second logic value different from the first logic value, and when a Y-th bit of the first response is different from a Y-th bit of a corresponding response of the plurality of responses of the first memory circuit, a Y-th bit of the following comparison result of the plurality of first comparison results is adjusted to have the second logic value, wherein the comparison result is generated before the following comparison result, Wherein Y is a positive integer less than or equal to n.

9. A method for testing a memory, characterized in that: Include: A first response of a plurality of responses of a first memory circuit of a memory maintained under a first operating condition of a plurality of operating conditions; The first response stored in a second memory circuit of the memory is sequentially compared with the plurality of responses of the first memory circuit under the plurality of operating conditions corresponding to different operating environments to generate a plurality of first comparison results, wherein each comparison result of the plurality of first comparison results is generated by adjusting a previous comparison result of the plurality of first comparison results; maintaining a second response of a plurality of responses of a second memory circuit of the memory under a second operating condition of the plurality of operating conditions; The second response stored in the first memory circuit of the memory is sequentially compared with the plurality of responses of the first memory circuit under the plurality of operating conditions corresponding to the different operating environments to generate a plurality of second comparison results, wherein each comparison result of the plurality of second comparison results is generated by adjusting a previous comparison result of the plurality of second comparison results; Producing a final result based on sequentially comparing the first response with the plurality of responses of the first memory circuit and sequentially comparing the second response with the plurality of responses of the second memory circuit; as well as According to the final result, a maximum difference between two of the responses of the first memory circuit is obtained.

10. The method of claim 9, wherein maintaining the first response of the first memory circuit comprises: Copying the first response to the second memory circuit of the memory; The copied first response is maintained in the second memory circuit.

11. The method of claim 9, wherein maintaining the first response comprises: The first response is generated by the second memory circuit.

12. The method of claim 11 , wherein maintaining the second response of the second memory circuit comprises: Copying the second response to the first memory circuit of the memory; The copied second response is maintained in the first memory circuit.

13. The method of claim 12, wherein maintaining the second response comprises: The second response is generated by the first memory circuit.

14. The method according to claim 13, further comprising: The plurality of first comparison results and the plurality of second comparison results are temporarily stored to output a maximum Hamming distance.

15. The method according to claim 14, wherein obtaining the maximum difference comprises: generating a first value indicating a number of bits having a same logic value in a corresponding comparison result of the plurality of first comparison results; and A second value is generated, the second value indicating a number of bits having a same logic value in a corresponding comparison result of the plurality of second comparison results.

16. The method according to claim 15, wherein outputting the maximum Hamming distance further comprises: generating the maximum Hamming distance according to the first value and a bit number of the corresponding comparison result of the plurality of first comparison results; and The maximum Hamming distance is generated according to the second value and a bit number of the corresponding comparison result of the plurality of second comparison results.

17. The method of claim 16, wherein comparing the first response of the second memory circuit stored in the memory with the plurality of responses of the first memory circuit comprises: An exclusive OR operation is performed on the first response stored in the second memory circuit and each of the plurality of responses in the first memory circuit.

18. The method of claim 17, wherein comparing the second response of the first memory circuit stored in the memory with the plurality of responses of the second memory circuit comprises; An exclusive OR operation is performed on the second response stored in the first memory circuit and each of the plurality of responses in the second memory circuit.

19. A method for testing a memory, characterized in that: Include: A first memory circuit of a memory operated under a plurality of operating conditions corresponding to different operating environments to obtain a plurality of responses of the first memory circuit, and a first response of the plurality of responses of the first memory circuit is stored in a second memory circuit of the memory; sequentially performing an exclusive OR operation of the first response of the plurality of responses of the first memory circuit stored in the second memory circuit of the memory and other plurality of responses of the plurality of responses of the first memory circuit to generate a plurality of comparison results of the plurality of responses of the first memory circuit; operating the second memory circuit under a plurality of operating conditions corresponding to the different operating environments to obtain a plurality of responses of the second memory circuit, and storing a second response of the plurality of responses of the second memory circuit in the first memory circuit; sequentially performing an exclusive OR operation of the second response of the plurality of responses of the second memory circuit of the first memory circuit stored in the memory and other plurality of responses of the plurality of responses of the second memory circuit to generate a plurality of comparison results of the plurality of responses of the second memory circuit; generating a final comparison result according to the exclusive OR operation of the first response of the plurality of responses of the first memory circuit and the exclusive OR operation of the second response of the plurality of responses of the second memory circuit; as well as According to the final comparison result, a maximum Hamming distance between two of the responses of the first memory circuit is output.

20. The method of claim 19, wherein outputting the maximum Hamming distance comprises: generating a value indicating a number of bits having a same logic value in the final comparison result; and The maximum Hamming distance is generated according to the value and a bit number of the final comparison result.

21. A device for testing a memory, characterized in that: Include: a memory array configured to store a first response of a plurality of responses of a device under test; a comparison circuit configured to compare the first response with the first response of the plurality of responses of the device under test operating under a plurality of operating conditions to generate a plurality of comparison results, the plurality of operations corresponding to different operating environments, wherein the comparison circuit is configured to perform a mutual exclusion or operation of the first response and each of the plurality of responses to generate the plurality of comparison results, and is further configured to generate a final comparison result according to the plurality of comparison results, wherein an X-th bit of a first comparison result of the plurality of comparison results has a first logic value, the first comparison result is generated before a second comparison result of the plurality of comparison results, and an X-th bit of the second comparison result is configured to have the first logic value; as well as A calculation circuit is configured to generate a value of the final comparison result, the value indicating a number of the plurality of bits having the first logic value, and the calculation circuit is configured to generate a maximum Hamming distance according to the value and a number of bits of the final comparison result, the maximum Hamming distance indicating a robustness of the device under test between two of the plurality of responses, wherein the number of bits is a number of the plurality of bits of the final comparison result.

22. The apparatus according to claim 21, further comprising: A recorder is configured to store the plurality of comparison results used to calculate the maximum Hamming distance.

23. The device of claim 21, wherein the comparison circuit comprises: An exclusive OR gate is configured to perform the exclusive OR operation on the first response and each of the plurality of responses.

24. The device of claim 21, wherein the comparison circuit comprises: At least one exclusive OR gate is configured to perform the exclusive OR operation on the plurality of bits of the first pair and the plurality of corresponding bits of a pair of the plurality of pairs.

25. The device of claim 21, wherein the memory array is a copy of a memory array under test, the memory array under test being implemented in or by the device under test.

26. The apparatus of claim 21, wherein the computing circuit comprises: A counter is configured to generate a value indicating a number of bits having the first logic value in a corresponding comparison result of the plurality of comparison results.

27. The apparatus of claim 21, wherein the comparison circuit is further configured to compare the first response with the plurality of responses in sequence.

28. A method for testing a memory, characterized in that: Include: retaining a first response of a plurality of responses of a device under test in a first operating condition; corresponding to different operating environments, changing at least one of a plurality of operating conditions of the device under test to generate the plurality of responses of the device under test; sequentially comparing the first response with the plurality of responses of the device under test in the plurality of operating environments through a comparison circuit to generate a plurality of comparison results, wherein each comparison result of the plurality of comparison results is generated by adjusting a previous comparison result of the plurality of comparison results; Generate a final comparison result according to the plurality of comparison results through the comparison circuit; generating, by a calculation circuit, a value of the final comparison result, the value indicating a number of a plurality of bits having a first logic value, and generating a maximum difference according to the value and a number of bits of the final comparison result, the maximum difference indicating a robustness of the device under test between two of the plurality of responses, wherein the number of bits is a number of the plurality of bits of the final comparison result, Wherein comparing the first response with the plurality of responses comprises: performing an exclusive OR operation on the first response and a second response among the plurality of responses to generate a first comparison result of the plurality of comparison results, An X-th bit of a comparison result of the plurality of comparison results has a first logic value, the comparison result is generated before the first comparison result, and an X-th bit of the first comparison result is configured to have the first logic value.

29. The method of claim 28, wherein retaining the first response comprises: copying the first response into a memory array; and The copied first response is maintained in the memory array.

30. The method of claim 28, wherein retaining the first response comprises: The first response is generated by another memory array.

31. The method of claim 28, further comprising: The plurality of comparison results are temporarily stored in order to calculate the maximum difference.

32. The method of claim 28, wherein the first comparison result has n bits, each of X and n is a positive integer, and X is less than or equal to n.

33. The method of claim 32, wherein comparing the first response with the plurality of responses further comprises: An exclusive OR operation is performed on the first response and a third response among the plurality of responses.

34. The method of claim 28, wherein generating the maximum difference further comprises: A maximum Hamming distance is generated according to the value and the bit number of the final comparison result.

35. The method of claim 28, wherein the first operating condition and at least one of the plurality of operating conditions correspond to a supply voltage of the device under test, an operating temperature of the device under test, an operating frequency of the device under test, or a combination thereof.

36. The method of claim 28, wherein when a Yth bit of the first response is different from a Yth bit of the second response, a Yth bit of a second comparison result is set to have the first logic value, The second comparison result has n bits, each of Y and n is a positive integer, Y is less than or equal to n, and Y is different from X.

37. A method for testing a memory, characterized in that: Include: Operating a device under test in a plurality of operating conditions corresponding to different operating environments to obtain a plurality of responses of the device under test; Performing a first response among the plurality of responses and an exclusive OR operation of the plurality of responses in sequence through a comparison circuit to generate a plurality of comparison results; Generate a final comparison result according to the plurality of comparison results through the comparison circuit; as well as A value indicating a number of bits having a first logic value in the final comparison result is generated by a calculation circuit, and a maximum Hamming distance is generated according to the value and a bit number of the final comparison result, the maximum Hamming distance indicating a robustness of the device under test between two of the plurality of responses, wherein the bit number of the final comparison result is a number of bits of the final comparison result, An X-th bit of a first comparison result of the plurality of comparison results has a first logic value, the first comparison result is generated before a second comparison result, and an X-th bit of the second comparison result is configured to have the first logic value.

38. The method of claim 37, further comprising: The first response in a memory array is reserved to perform the exclusive OR operation.

39. The method of claim 37, wherein the maximum Hamming distance is generated by dividing the value by the number of bits of the final comparison result.

40. The method of claim 37, wherein when a Yth bit of one of the plurality of comparison results has the first logic value, a Yth bit of the final comparison result is set to have the first logic value.

41. A device for testing a memory, characterized in that: The memory includes a first memory circuit and a second memory circuit, the second memory circuit is configured to store a first response among a plurality of responses of the first memory circuit, and the first memory circuit is configured to store a second response among a plurality of responses of the second memory circuit, the device includes: a comparison circuit configured to compare the first response with a plurality of responses of the first memory circuit, and configured to compare the second response with a plurality of responses of the second memory circuit to generate a plurality of comparison results, wherein the comparison circuit is configured to perform an exclusive OR operation of the first response and each of the plurality of responses of the first memory circuit to generate the plurality of comparison results, and is further configured to generate a final comparison result according to the plurality of comparison results; as well as A maximum Hamming distance generating circuit is configured to generate a maximum Hamming distance according to the final result, wherein a plurality of bits of the final result have a first logic value.

42. A device according to claim 41, wherein the comparison circuit is configured to compare the first response with the multiple responses of the first memory circuit to generate multiple first comparison results of the multiple comparison results, and is configured to compare the second response with the multiple responses of the second memory circuit to generate multiple second comparison results of the multiple comparison results.

43. The apparatus of claim 42, further comprising: a recorder configured to store the plurality of comparison results used to generate the maximum Hamming distance, wherein the recorder comprises: a first recording circuit configured to store the plurality of first comparison results; and A second recording circuit is configured to store the plurality of second comparison results.

44. The apparatus of claim 41, further comprising: An exclusive OR gate is configured to perform the exclusive OR operation of the first response and each of the plurality of responses of the first memory circuit, and is configured to perform an exclusive OR operation of the second response and each of the plurality of responses of the second memory circuit.

45. The device of claim 44, wherein the comparison circuit is further configured to generate the final comparison result based on the plurality of comparison results, wherein an X-th bit of a first comparison result of the plurality of comparison results has the first logic value, the first comparison result is generated before a second comparison result of the plurality of comparison results, and an X-th bit of the second comparison result is configured to have the first logic value.

46. ​​The apparatus of claim 45, further comprising: A mutual counter is configured to receive the final comparison result and to generate a first value indicating a quantity of the plurality of bits of the final comparison result having the first logic value.

47. The apparatus of claim 46, wherein the maximum Hamming distance generating circuit is configured to generate the maximum Hamming distance further according to the first value and a bit number of the final comparison result.

48. A method for testing a memory, characterized in that: Include: Comparing a first response of a second memory circuit stored in a first memory circuit with a plurality of responses of the second memory circuit by performing a first exclusive OR operation to generate a plurality of first comparison results; Comparing a second response of a second memory circuit stored in a first memory circuit with a plurality of responses of the first memory circuit to generate a plurality of second comparison results; generating a final comparison result according to at least the plurality of first comparison results; as well as A maximum difference between two of the responses of the second memory circuit is obtained according to a number of bits having a first logic value of the final comparison result.

49. The method of claim 48, wherein generating the final comparison result comprises: The final comparison result is generated according to the plurality of second comparison results.

50. The method of claim 49, wherein generating the maximum difference comprises: generating a first value indicating a number of bits of the final comparison result, the bits having the first logic value; and A maximum Hamming distance is generated according to the first value and a bit number of the final comparison result, wherein the maximum Hamming distance represents the maximum difference.

51. The method of claim 48, wherein comparing the second response to a plurality of responses of the first memory circuit comprises: A second exclusive OR operation is performed on a second response stored in a second memory circuit and each of the plurality of responses of the first memory circuit to generate a plurality of second comparison results.

52. The method of claim 51, wherein When an X-th bit of a first comparison result of the plurality of first comparison results has the first logic value, an X-th bit of a second comparison result is used to have the first logic value, wherein the first comparison result is generated before the second comparison result; and When a Yth bit of a third comparison result of the plurality of second comparison results has the first logic value, a Yth bit of a fourth comparison result is used to have the first logic value, wherein the third comparison result is generated before the fourth comparison result.

53. The method of claim 48, further comprising: retaining the first response of the plurality of responses of the second memory circuit in a first operating condition of a plurality of operating conditions; and The second response of the plurality of responses of the first memory circuit is retained in a second operating condition of the plurality of operating conditions.

54. The method of claim 53, wherein the plurality of operating conditions correspond to a plurality of different operating environments.

55. A method for testing a memory, characterized in that: Include: Performing an exclusive OR operation on a first response of a plurality of responses of a first memory circuit and the plurality of responses of the first memory circuit to generate a plurality of first comparison results, wherein the first response is stored in a second memory circuit; performing an exclusive OR operation of a second response of a plurality of responses of a second memory circuit and the plurality of responses of the second memory circuit to generate a plurality of second comparison results, wherein the second response is stored in the first memory circuit; generating a final comparison result according to at least the plurality of first comparison results; as well as A maximum Hamming distance between two of the responses of the first memory circuit is output according to a number of bits of the final comparison result having a first logic value.

56. The method of claim 55, wherein When an X-th bit of a first comparison result of the plurality of first comparison results has the first logic value, an X-th bit of a second comparison result of the plurality of first comparison results is used to have the first logic value, wherein the first comparison result is generated before the second comparison result; and When a Yth bit of a third comparison result of the plurality of second comparison results has the first logic value, a Yth bit of a fourth comparison result of the plurality of second comparison results is used to have the first logic value, wherein the third comparison result is generated before the fourth comparison result.

57. The method of claim 56, wherein the first logic value is one.

58. The method of claim 55, wherein generating the final comparison result comprises: The final comparison result is generated according to the plurality of first comparison results and the plurality of second comparison results.

59. The method of claim 58, further comprising: generating a value indicating a number of bits of the final comparison result having the first logic value, The output of the maximum Hamming distance includes: A ratio between a bit number of the final comparison result and the value is calculated, wherein the ratio represents the maximum Hamming distance.

60. The method of claim 55, further comprising: Operating the first memory circuit of a memory under a plurality of operating conditions corresponding to a plurality of different operating environments to obtain the plurality of responses of the first memory circuit, and storing the first response of the plurality of responses of the first memory circuit in the second memory circuit of the memory; and The second memory circuit is operated in a plurality of operating conditions corresponding to different operating environments to obtain the plurality of responses of the second memory circuit, and the second response of the plurality of responses of the second memory circuit is stored in the first memory circuit of the memory.

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