Handling the dynamic maximum frequency limit of a nuclear group

Abstract

A device system is provided, comprising: a first component and a second component; a first circuit for allocating the first component to a first group of components and the second component to a second group of components; and a second circuit for allocating a first maximum frequency limit to the first group of components and a second maximum frequency limit to the second group of components, wherein the first component and the second component operate according to the first maximum frequency limit and the second maximum frequency limit respectively.

Description

[0001] Priority Claim

[0002] This application claims priority to U.S. Patent Application No. 15 / 632,000, filed on Jun. 23, 2017, entitled “DYNAMIC MAXIMUM FREQUENCY LIMIT FOR PROCESSING CORE GROUPS”, and incorporates the same herein by reference in its entirety. BACKGROUND OF THE INVENTION

[0003] Modern computing devices may include multiple processing cores, such as dozens, hundreds, or even thousands of processing cores. Sharing resources (e.g., current, power, heat contribution, etc.) among multiple processing cores may be a task of great significance. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Embodiments of the present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. However, it should not be used to limit the present disclosure to specific embodiments, but only to explain and understand.

[0005] Figure 1 Schematically illustrates a computing device including multiple processing cores and a maximum frequency limit circuit, where the maximum frequency limit circuit can adaptively and dynamically configure the maximum frequency limits of the respective processing cores of the computing device.

[0006] Figure 2 Schematically illustrates according to some embodiments Figure 1 the functionality of a computing device.

[0007] Figure 3 Illustrates a graph depicting the dynamic maximum frequency limits for multiple processing cores of a computing device according to some embodiments.

[0008] Figure 4 Illustrates a flowchart depicting a method for dynamically setting the maximum frequency limits of various processing cores of a computing device according to some embodiments.

[0009] Figure 5 Illustrates a computing device or SoC (System on Chip) according to some embodiments, where the maximum frequency limits can be dynamically set for various processing cores of the computing device. DETAILED DESCRIPTION

[0010] In a multi-core system, the maximum frequency limits (also referred to as the maximum operating frequency or the turbo frequency) of all processing cores can be the same. Thus, in a multi-core system, each processing core can have the same maximum frequency limit regardless of the workload distribution or the criticality of the workload assignment. Since all processing cores are assigned the same maximum frequency limit, the maximum frequency limit can be relatively low. The maximum frequency limit in such a multi-core system can also be referred to as the baseline maximum frequency limit.

[0011] In some embodiments and as discussed in the present disclosure, in a multi-core system, among other factors, the assignment of the maximum frequency limit or the turbo frequency can also be based on the workload assignment to each core, the frequency requested by each core, etc. For example, a task with a relatively high criticality (or a high computational intensity task, or a computational task that can tolerate low latency) can be assigned to the first processing core, and a relatively high maximum frequency limit can be assigned to the first processing core. On the other hand, a task with a relatively low criticality (or a low computational intensity task, or a computational task that can tolerate high latency) can be assigned to the second processing core, and a relatively low maximum frequency limit can be assigned to the second processing core. In other words, the maximum frequency limit can be dynamically and adaptively assigned to various processing cores. Thus, although some non-critical processing cores can have a maximum frequency limit that can be lower than the baseline maximum frequency limit, some critical processing cores can have a maximum frequency limit that can be higher than the above-mentioned baseline maximum frequency limit. Consequently, the processing cores with a higher maximum frequency limit can complete critical, computationally intensive, and / or time-sensitive workloads at a faster rate. This can lead to an improvement in the performance of the entire system. According to various embodiments and the accompanying drawings, other technical effects will be apparent.

[0012] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present disclosure. However, it will be apparent to those skilled in the art that the embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail, so as not to obscure the embodiments of the present disclosure.

[0013] Note that in the corresponding drawings of the embodiments, signals are represented by lines. Some lines may be thicker to indicate more constituent signal paths, and / or have arrows at one or more ends to indicate the main information flow direction. Such indications are not intended to be limiting. Instead, these lines are used in conjunction with one or more exemplary embodiments to facilitate a better understanding of the circuit or logic unit. Any represented signal, as indicated by design requirements or preferences, can actually include one or more signals that can propagate in either direction and can be implemented with any suitable type of signal scheme.

[0014] Throughout the specification and in the claims, the term "connected" means a direct connection (such as an electrical, mechanical, or magnetic connection) or a magnetic connection between the connected objects. The term "coupled" means a direct connection or an indirect connection through one or more passive or active intermediate devices, such as a direct electrical, mechanical, or magnetic connection or an indirect connection between the connected objects. The term "circuit" or "module" may refer to one or more passive and / or active components arranged to cooperate with each other to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a" and "the" include plural forms. The meaning of "in" includes "in" and "on". The terms "substantially", "close to", "about", "near", and "approximately" generally refer to within + / - 10% of the target value.

[0015] Unless otherwise specified, the use of ordinal adjectives "first", "second", "third", etc. to describe a common object only indicates different instances referring to the same object, and is not intended to imply that the objects so described must be in a given order in terms of time, space, rank, or any other way.

[0016] For the purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The terms "left", "right", "front", "rear", "top", "bottom", "above", "below", etc. (if any) in the specification and claims are for descriptive purposes and not necessarily for describing a permanent relative position.

[0017] Figure 1 Schematically illustrated is a computing device 100 (hereinafter also referred to as device 100) including a plurality of processing cores 104a, 104b,..., 104M, 104N and a maximum frequency limit circuit 108 (hereinafter also referred to as circuit 108) according to certain embodiments, wherein circuit 108 can adaptively and dynamically configure the maximum frequency limits of the respective processing cores 104 of device 100.

[0018] Elements referred to herein by a common reference numeral (followed by a specific number or letter) may be collectively referred to only by the reference numeral. For example, processing cores 104a, 104b, 104M, 104N may be collectively referred to and generally called the processing cores 104 in the plural form, as well as the processing core 104 in the singular form. The processing core 104 may also be referred to as core 104. Although Figure 1Illustrated is a device that includes "N" cores, but such a number is merely exemplary, and device 100 may include several, dozens, hundreds, or even thousands of cores.

[0019] Device 100 can be any suitable computing device that can be used for any suitable operation. By way of example only, device 100 can be used for high-performance computing (HPC) applications, cloud computing applications, applications associated with communications, networking, data centers, laptops, desktops, mobile computing devices, communication infrastructure, smart phones, tablets, and / or the like. For example, device 100 can be any device that can operate as a multi-core processing device.

[0020] In certain embodiments, device 100 may include core prioritization and grouping circuitry 112 (also referred to as circuitry 112) and workload allocation circuitry 116 (also referred to as circuitry 116), which will be discussed in further detail with respect to Figure 2 Further discussion.

[0021] Although Figure 1 Circuitry 108, 112, and 116 are illustrated as being distinct and separate, but in certain embodiments, one or more of these circuits may be at least partially combined. Although device 100 may include a large number of other components (e.g., memory, communication interfaces, input / output interfaces, displays, etc.), such components are not illustrated herein so as not to obscure the teachings of the present disclosure. Figure 1 In

[0022] Figure 2 Schematically illustrated in accordance with certain embodiments of Figure 1Function of computing device 100. In some embodiments, circuit 116 may be configured to allocate workloads to cores 104. For example, circuit 116 may allocate threads to different cores 104. In some embodiments, circuit 116 may operate as a load balancing circuit, for example, to balance the workloads between different cores 104. In some embodiments, circuit 116 may operate to schedule or allocate workloads, such as performing workload distribution or allocation. Workload allocation may be based on the availability of cores 104 for workload allocation, the priority of the workload, the state of each core (e.g., whether it is active or in a low power state), and / or one or more other factors typically associated with workload allocation or load balancing in a multi-core processing environment. In some embodiments, circuit 116 may also determine or estimate the frequency (or frequency range) that will be used to complete the workload, the criticality of the workload, the priority associated with the workload, the latency tolerance associated with the workload (e.g., whether the workload can tolerate high latency or low latency), the time sensitivity of the workload (e.g., whether the workload can be executed with a certain latency or must be executed with minimal or no latency), and / or one or more other parameters associated with the workload. In some embodiments, at least a portion of circuit 116 may be implemented in a processing core (e.g., it may be one of cores 104 or different from cores 104). In some embodiments, the operating system may facilitate workload allocation.

[0023] In some embodiments, based on allocating workloads among one or more of cores 104, circuit 116 may generate workload allocation parameters 124 (hereinafter also referred to as "parameters 124"). Parameters 124 may represent, for example, one or more of the following: the amount of workload allocated to each core 104, the criticality or time sensitivity of the workload allocated to each core 104, the priority associated with the workload, the quality of service (QoS) associated with the workload allocated to each core 104, the time required to complete the workload allocated to each core 104, the latency that the workload can tolerate, the power, current, time, and / or frequency required for each core 104 to complete the workload allocated to it, etc. In other words, parameters 124 may be any suitable parameters that characterize the workloads allocated to each core 104 in some way. In some embodiments, circuit 116 may send parameters 124 to circuit 112.

[0024] In some embodiments, to complete the assigned workload, core 104 may prefer to operate at a specific frequency (or a specific frequency range). For example, core 104a may request frequency fra to complete the workload assigned to core 104a, core 104b may request frequency frb to complete the workload assigned to core 104b, and so on. The requested frequency fra may be only an indication of the frequency requested by the corresponding core 104a. However, the actual operating frequency of core 104a may be different from the requested frequency fra.

[0025] In some embodiments, circuit 112 may receive the requested frequencies fra, …, frN (also referred to as the requested frequency parameters 120, or simply parameters 120) corresponding to cores 104a, …, 104N respectively, and may also receive parameter 124. In some embodiments, circuit 112 may group cores 104 into two or more groups. Figure 2 Illustrated is that circuit 112 groups cores 104 into two groups 204p and 204q (illustrated using dashed lines), but in some other embodiments, circuit 112 may group cores 104 into more than two groups.

[0026] In Figure 2 the example, cores 104a, 104c, 104d, 104M, etc. are assigned to the first group 204p, and cores 104b, 104e, 104N, etc. are assigned to the second group 204q. In some embodiments, the grouping of cores 104 may be based on parameter 124, the requested frequency fr, and / or the like.

[0027] For discussion purposes only, the first group 204p may be referred to as the high-priority group, and the second group 204q may be referred to as the low-priority group. In the example, as the number of groups gets larger, adjectives such as very high priority, high priority, medium priority, low priority, very low priority, etc. may be used. In other examples, numerical labels such as first, second, third, etc. may be used simply to refer to the respective groups.

[0028] In the example, circuit 108 may group cores 104 that may be assigned a relatively high-priority workload into group 204p. Examples of workloads assigned a high priority may include time-sensitive workloads, workloads that may be associated with a higher QoS, workloads that may be key components of a potentially formed pipeline, and / or the like. In some embodiments, parameter 124 may provide an indication of the priority level of the workload assigned to the core.

[0029] In another example, circuit 108 may group cores 104 that may be estimated to take a relatively long time to complete the assigned workload into group 204p.

[0030] In another example, circuit 108 may assign core 104, which may request a higher frequency to complete the assigned workload, to group 204p. For example, circuit 112 may consider the requested frequency parameter 120 when grouping cores 104.

[0031] As an example, if the requested frequency of a core (e.g., the requested frequency fra of core 104a) is higher than the cut-off frequency fc, the core may be assigned to group 204p; and if the requested frequency of the core is lower than the cut-off frequency fc, the core may be assigned to group 204q.

[0032] In another example, circuit 108 may group cores 104 based on the estimated power, current, frequency, and / or voltage requirements to complete the assigned workload. For example, cores 104 that can be estimated to utilize higher power or higher current for the intended assigned workload may be grouped in group 204p.

[0033] In some embodiments, circuit 112 may include grouping information in the priority and grouping parameter 128. For example, parameter 128 may identify the group to which a particular core is assigned. In some embodiments, circuit 112 may send parameter 128 to circuit 108. For example, circuit 112 may store parameter 128 in a table, and circuit 108 may access parameter 128 from the table.

[0034] In some embodiments, circuit 108 may assign the maximum frequency limit of core 104 based on the group to which core 104 is assigned. For example, the maximum frequency limit Fp may be assigned to cores 104a, 104c, 104d, and 104M of group 204p, and the maximum frequency limit Fq may be assigned to cores 104b, 104e, and 104N of group 204q. In some embodiments, the maximum frequency limit Fp may be higher than the maximum frequency limit Fq (e.g., based on group 204p having a higher priority than group 204q).

[0035] In some embodiments, the maximum frequency limit assigned to core 104 (e.g., core 104a) can be the maximum operating frequency or the highest Turbo frequency of core 104a. For example, core 104a can operate in an operating Turbo boost mode for short and intermittent time periods, and core 104a can operate at the maximum operating frequency Fp during such short intermittent time periods. In other words, the operating frequency of core 104a can be limited by the maximum operating frequency Fp, which can form the frequency upper limit of core 104a. Core 104a is capable of operating, for example, at a frequency less than or equal to the maximum operating frequency Fp. In some examples, the maximum operating frequency Fp can also be referred to as the highest Turbo frequency of the first group 204p of cores. In an example, the maximum frequency limit or the highest Turbo frequency can be the maximum frequency (e.g., achievable on the chip), which can be a frequency higher than the guaranteed maximum frequency. As discussed herein, various embodiments of the present disclosure can allow the processor to obtain a frequency higher than the all-core highest Turbo frequency, for example, which can increase the achievable maximum frequency.

[0036] By way of example only, the maximum operating frequency Fp can be assigned to core 104a. Moreover, core 104a can have a requested frequency fra. Thus, in some embodiments, core 104a can operate at the minimum of the maximum operating frequency Fp and the requested frequency fra. The requested frequency fra can change, for example, as the workload of core 104a changes, or can change due to various factors (e.g., thermal considerations, limited power available to core 104a, etc.), but the maximum operating frequency of core 104a can be limited by the frequency Fp.

[0037] In some embodiments, circuit 108 can write the maximum operating frequencies Fp and Fq to corresponding registers. A frequency control circuit or frequency regulator (not shown in the figure) that can control the frequency of core 104a, for example, can access the maximum operating frequency Fp from the corresponding register. In an example, the frequency control circuit or frequency regulator (or core 104a) can control a phase-locked loop (PLL) or another suitable clock generator (not shown in the figure), such that the maximum operating frequency Fp forms the frequency upper limit of core 104a.

[0038] In some embodiments, circuit 112 and / or 108 can include appropriate hardware components. For example, circuit 112 and / or 108 can be implemented as one or more microprocessors, dedicated hardware components, and circuits, etc.

[0039] Figure 3FIG. 300 illustrates a graph depicting the dynamic maximum frequency limits of multiple cores 104 of device 100 in accordance with certain embodiments. In graph 300, the Y-axis represents the maximum frequency limits of the various cores 104, and the X-axis represents the number of cores 104 in the high-priority group 204p. For example, as illustrated by the arrow in the figure, the number of cores in group 204p increases as one traverses from right to left along the X-axis.

[0040] The dashed line 302 represents the maximum frequency limit of device 100, e.g., if device 100 were to operate in a conventional manner. For example, if device 100 were to operate in a conventional manner (e.g., without grouping the cores 104 and having no different maximum frequency limits for different cores), then all cores 104 would have a fixed and identical maximum frequency limit Fcon, as illustrated by line 302. The maximum frequency limit Fcon may also be referred to as the baseline or conventional maximum frequency limit.

[0041] In certain embodiments and as discussed with respect to Figure 2 some of the cores 104 (e.g., cores 104a, 104c, 104d, 104M, etc.) may operate at a maximum frequency limit Fp, while some of the cores 104 (e.g., cores 104b, 104e, 104N, etc.) may operate at a maximum frequency limit Fq. Figure 3 Line 304a in [the figure] illustrates the maximum frequency limit Fp of group 204p, while line 304b illustrates the maximum frequency limit Fq of group 204q.

[0042] In certain embodiments, the maximum frequency limit Fq may be lower than the conventional maximum frequency limit Fcon. However, in certain embodiments, the maximum frequency limit Fp may be higher than the conventional maximum frequency limit Fcon.

[0043] In certain embodiments, the maximum frequency limit Fp may be a function of the number of cores in group 204p. For example, if the number of cores in group 204p is relatively small, then the maximum frequency limit Fp may be relatively high. As the number of cores in group 204p becomes higher and approaches the total number of cores 104 (e.g., if all cores 104 were in group 204p), then the maximum frequency limit Fp may approach the conventional maximum frequency limit Fcon.

[0044] Thus, for example, if certain selected cores 104 (e.g., cores 104a, 104c, 104d, 104M, etc.) are grouped in group 204p, these cores can have a maximum frequency limit Fp, which can be higher than the case where all cores 104 operate at the conventional maximum frequency limit Fcon. By grouping cores 104 into two or more groups and by assigning different maximum frequency limits to different groups, a higher maximum frequency limit Fp can be assigned to critical or high-priority cores, while a relatively lower maximum frequency limit Fq can be assigned to non-critical cores. Additionally, non-critical cores may not even need to exceed the maximum frequency limit Fq (e.g., because these cores can perform relatively light and non-critical workloads), and thus, restricting these cores to the lower maximum frequency limit Fq does not result in a substantial or significant degradation in the performance of non-critical cores. However, the higher maximum frequency limit Fp of critical cores can significantly improve the performance of critical cores. This can lead to an enhancement in the performance of the entire device 100. Although non-critical cores may degrade the performance, critical cores may significantly improve the performance, which may result in a faster overall performance of device 100 and / or an overall reduction in the power consumption of device 100.

[0045] In some embodiments, since an increase in the maximum frequency limit of certain cores is compensated by a corresponding decrease in the maximum frequency limit of certain other cores, the total power limit, current limit, thermal limit, reliability limit, etc. of device 100 can be maintained. Thus, the maximum frequency limit of critical cores (e.g., exceeding the conventional maximum frequency limit Fcon) can be increased without violating any system thermal, current, voltage, reliability, or power boundaries.

[0046] Referring again to Figure 2 , based on various factors (e.g., some of those previously discussed herein), circuits 112 and / or 108 can group cores 104 and assign frequencies Fp and Fq. For example, existing reliability limits, power limits, thermal limits, current limits, etc. can be considered when determining the additional range of frequencies achievable by critical cores.

[0047] In some embodiments, additional factors can also be considered when grouping cores 104 in a group and / or when determining the maximum frequency limits Fp and Fq. For example, circuit 108 can consider allowing exceeding the existing conventional achievable maximum frequency (e.g., Figure 2The number of cores at the maximum frequency limit Fcon) (e.g., the number of cores in group 204p) to calculate the maximum frequency limit Fp. In some embodiments, circuits 108 and / or 112 may also consider, for example, that these critical cores can be set to a maximum frequency limit above the baseline. In some embodiments, circuits 108 and / or 112 may also consider the maximum frequency limits of non-critical cores that may not be allowed to exceed the conventional maximum frequency limit. In some embodiments, when grouping the cores 104 and / or setting the frequencies Fp and Fq, circuits 112 and / or circuit 108 may consider power metrics, maximum current metrics, reliability metrics, heat metrics, etc.

[0048] As discussed hereinabove with respect to Figure 2 the cores 104 can be grouped into more than two groups. A higher number of groups can increase the granularity with which the maximum frequency limit can be distributed among the groups. As an extreme example, the number of groups can be equal to the number of cores 104 (e.g., each group can have one core), such that each core 104 can have a corresponding individual maximum frequency limit.

[0049] In some embodiments, the teachings of the present disclosure can be applied to various application domains. For example, in a system operating multiple virtual machines (VMs), the VMs can be classified into multiple groups. For example, in a simple scenario, the VMs can be grouped into critical and non-critical groups. A higher maximum frequency limit can be assigned to the VMs in the critical group, and a lower maximum frequency limit can be assigned to the VMs in the non-critical group. For example, this can allow a cloud computing provider to offer high-priority VMs with a higher frequency limit, e.g., as an additional VM performance level. In some embodiments, the teachings of the present disclosure can be applied to other application domains, such as HPC, cloud computing, communication networks, etc.

[0050] In some embodiments, the teachings of the present disclosure facilitate, for example, identifying critical components and allowing critical components to achieve a higher Turbo Boost frequency or a guaranteed frequency without reducing the lifespan of the device and without violating power, heat, current, and voltage protection. For example, when the cores are not operating at the same frequency, circuits 116 and / or 112 can learn from the operating frequency the degree to which a core is critical or non-critical. Subsequently, circuits 112 and / or 108 can adjust the frequency ceiling for each core's bin (e.g., critical vs. non-critical). The frequency ceiling can be adjusted such that the device can remain within electrical and thermal limits, but the ceiling for critical cores may be increased compared to the conventional system baseline, while non-critical cores with ceilings below the conventional system baseline are used to compromise for additional headroom. Critical cores can utilize the additional headroom and can enable a computing device to achieve improved performance in various scenarios (e.g., HPC, cloud computing, communication networks, etc.).

[0051] Although various embodiments have been discussed regarding grouping the cores 104 and assigning different maximum frequency limits to different cores, the teachings of the present disclosure may not be limited to processing cores only. For example, as will be readily understood by those skilled in the art based on the teachings of the present disclosure, other components of the device 100 (e.g., memory, graphics processing unit, or any other suitable component) may also be grouped into multiple groups and may be operated at different maximum frequency limits.

[0052] Figure 4 A flowchart of a method 400 for dynamically setting the maximum frequency limits of respective cores of a device (e.g., Figure 1 the device 100) according to certain embodiments is illustrated. Although the blocks in the flowchart are shown in a particular order with reference to Figure 4 the flowchart, the order of the actions can be modified. Thus, the described embodiments can be performed in a different order, and certain actions / blocks can be performed in parallel. According to certain embodiments, Figure 4 certain blocks and / or operations listed in

[0053] may be optional. The numbers of the presented blocks are for clarity and are not intended to prescribe the order of operations in which the various blocks must occur.

[0054] In certain embodiments, at 404 of the method 400, workload allocation parameters 124 and / or requested frequency parameters 120 may be received (e.g., by the circuit 112). At 408, the respective cores may be grouped into corresponding groups among multiple groups (e.g., groups 204p, 204q, etc.). The factors for grouping the cores into different groups have been discussed in detail hereinbefore. As a simple example, a cut-off frequency fc may be determined. If the requested frequency of a core is higher than the cut-off frequency fc, the core may be grouped into a first group (e.g., high-priority group 204p); otherwise, the core may be grouped into a second group (e.g., low-priority group 204q). As discussed in detail herein, other suitable factors may also be considered when grouping the cores.

[0055] At 412, a corresponding maximum frequency limit may be assigned to each group (e.g., by the circuit 108). For example, groups 204p and 204q may be assigned maximum frequency limits Fp and Fq, respectively. The factors for determining the maximum frequency limits of the respective groups have been discussed in detail herein. In certain embodiments, a look-up table may store the group (e.g., group 204p) assigned to a core (e.g., core 104a) and / or the maximum frequency limit (e.g., maximum frequency limit Fp) assigned to the group including the core.

[0056] In some embodiments, method 400 can dynamically update the grouping of cores and / or the maximum frequency limits assigned to each group. Thus, for example, method 400 can loop back from 416 to 404, and method 400 can continue.

[0057] Figure 5 Illustrated is a computing device or SoC (System on Chip) 2100 according to some embodiments, in which maximum frequency limits can be dynamically set for various processing cores of the computing device. It should be noted that Figure 5 Those elements having the same reference numerals (or names) as the elements of any other figure can operate or function in any manner similar to the manner described, and are not limited thereto.

[0058] In some embodiments, computing device 2100 represents a suitable computing device, such as a computing tablet, mobile phone or smartphone, laptop computer, desktop computer, IoT device, server, set-top box, wireless-enabled e-reader, etc. It will be understood that some components are generally illustrated, and not all components of such a device are shown in computing device 2100.

[0059] In some embodiments, computing device 2100 includes a first processor 2110. Various embodiments of the present disclosure may also include a network interface within 2170, such as a wireless interface, such that the system embodiments can be incorporated into a wireless device, such as a cellular phone or a personal digital assistant.

[0060] In one embodiment, processor 2110 can include one or more physical devices, such as, a microprocessor, application processor, microcontroller, programmable logic device, or other processing means. Processing operations performed by processor 2110 include the execution of an operating platform or operating system on which applications and / or device functions are executed. Processing operations include operations related to I / O with a human user or other devices, operations related to power management, and / or operations related to connecting computing device 2100 to another device. Processing operations may also include operations related to audio I / O and / or display I / O.

[0061] In one embodiment, computing device 2100 includes an audio subsystem 2120, which represents the hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functionality to the computing device. Audio functionality can include speaker and / or headphone output, and microphone input. Devices for such functionality can be integrated into computing device 2100, or connected to computing device 2100. In one embodiment, a user interacts with computing device 2100 by providing audio commands that are received and processed by processor 2110.

[0062] The display subsystem 2130 represents the hardware (e.g., a display device) and software (e.g., a driver) components that provide a visual and / or tactile display for a user to interact with the computing device 2100. The display subsystem 2130 includes a display interface 2132, which includes a particular screen or hardware device for providing a display to the user. In one embodiment, the display interface 2132 includes logic separate from the processor 2110 to perform at least some processing related to the display. In one embodiment, the display subsystem 2130 includes a touchscreen (or touchpad) device that provides output and input to the user.

[0063] The I / O controller 2140 represents the hardware devices and software components related to user interaction. The I / O controller 2140 is operable to manage the hardware that is part of the audio subsystem 2120 and / or the display subsystem 2130. Additionally, the I / O controller 2140 illustrates a connection point for attaching additional devices to the computing device 2100 through which a user can interact with the system. For example, devices that can be attached to the computing device 2100 may include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or keypad device, or other I / O devices (such as a card reader or other device) for use with a specific application.

[0064] As mentioned above, the I / O controller 2140 is capable of interacting with the audio subsystem 2120 and / or the display subsystem 2130. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 2100. Additionally, instead of or in addition to a display output, an audio output can be provided. In another example, if the display subsystem 2130 includes a touchscreen, the display device also acts as an input device, which can be at least partially managed by the I / O controller 2140. There may also be additional buttons or switches on the computing device 2100 to provide I / O functions managed by the I / O controller 2140.

[0065] In one embodiment, the I / O controller 2140 manages devices such as an accelerometer, a camera, a light sensor, or other environmental sensors, or other hardware that can be included in the computing device 2100. The input can be part of a direct user interaction or can provide environmental input to the system to affect its operation (such as filtering noise, adjusting the display for brightness detection, firing a flash for a camera application, or other features).

[0066] In one embodiment, computing device 2100 includes power management 2150, which manages battery power usage, charging of the battery, and features related to power saving operations. Storage subsystem 2160 includes storage devices for storing information in computing device 2100. The memory can include non-volatile (state does not change if power to the storage device is interrupted) and / or volatile (state is indeterminate if power to the storage device is interrupted) storage devices. Storage subsystem 2160 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of applications and functions of computing device 2100. In one embodiment, computing device 2100 includes clock generation subsystem 2152 to generate clock signals.

[0067] The elements of the embodiments are also provided as a machine-readable medium (e.g., memory 2160) for storing computer-executable instructions (e.g., instructions for implementing any of the other processes discussed herein). The machine-readable medium (e.g., memory 2160) can include, but is not limited to, flash memory, optical discs, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the present disclosure can be downloaded as a computer program (e.g., BIOS), which can be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) in the form of a data signal via a communication link (e.g., a modem or network connection).

[0068] Connections 2170 include hardware devices (e.g., wireless and / or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable computing device 2100 to communicate with external devices. Computing device 2100 can be a standalone device, such as other computing devices, wireless access points or base stations, and peripheral devices (such as, headsets, printers, or other devices).

[0069] The connection 2170 can include various different types of connections. Generally speaking, a computing device 2100 having a cellular connection 2172 and a wireless connection 2174 is illustrated. The cellular connection 2172 generally refers to a cellular network connection provided by a wireless carrier, such as via GSM (Global System for Mobile Communications) or variants or derivatives, CDMA (Code Division Multiple Access) or variants or derivatives, TDM (Time Division Multiplexing) or variants or derivatives, or other cellular service standards. The wireless connection (or wireless interface) 2174 refers to a non-cellular wireless connection, which can include a personal area network (such as Bluetooth, near field, etc.), a local area network (such as Wi-Fi), and / or a wide area network (such as WiMax), or other wireless communications.

[0070] The peripheral connection 2180 includes hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) for making peripheral connections. It will be understood that the computing device 2100 can be both a peripheral device of other computing devices ("going to" 2182) and can have peripheral devices connected to it ("coming from" 2184). The computing device 2100 typically has a "dock" connector to connect to other computing devices for purposes such as managing (e.g., downloading and / or uploading, changing, synchronizing) the content on the computing device 2100. Additionally, the docking connector can allow the computing device 2100 to connect to some peripheral devices that allow the computing device 2100 to control the output of content to, for example, an audiovisual or other system.

[0071] In addition to proprietary docking connectors or other proprietary connection hardware, the computing device 2100 can also make peripheral connections 2180 via common or standard-based connectors. Common types can include Universal Serial Bus (USB) connectors (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High-Definition Multimedia Interface (HDMI), Firewire, or other types.

[0072] Although a single processor 2110 is illustrated in Figure 5 , in some embodiments, the computing device 2100 can include multiple processing cores (e.g., as discussed with respect to Figure 1 ). In some embodiments, the computing device 2100 can include Figure 1 circuits 116, 112, and / or 108. In some embodiments, the circuits 116, 112, and / or 108 can dynamically group the processing cores of the computing device 2100, and / or can set maximum frequency limits for various processing cores based on such grouping, as discussed with respect to Figure 1-4 .

[0073] References in the specification to "an embodiment", "one embodiment", "some embodiments", or "other embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The appearances of "an embodiment", "one embodiment", or "some embodiments" throughout the specification are not necessarily all referring to the same embodiment. If the specification states that a component, feature, structure, or characteristic "may", "might", or "could" be included, it does not mean that the particular component, feature, structure, or characteristic must be included. If the specification or claims refer to "an" element, it does not mean that there is only one element. If the specification or claims refer to "additional" elements, it does not exclude the presence of more than one additional element.

[0074] In addition, in one or more embodiments, specific features, structures, functions, or characteristics may be combined in any suitable manner. For example, for any situation where the specific features, structures, functions, or characteristics associated with the first and second embodiments are not mutually exclusive, the first embodiment may be combined with the second embodiment.

[0075] Although the present disclosure has been described in connection with specific embodiments of the present disclosure, many alternatives, modifications, and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the present disclosure are intended to cover all such alternatives, modifications, and variations that fall within the broad scope of the appended claims.

[0076] In addition, for the sake of simplicity of exposition and discussion, and to avoid obscuring the present disclosure, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the presented figures. Further, in order to avoid obscuring the present disclosure, and also in view of the fact that the details regarding the implementation of such a block diagram arrangement highly depend on the platform on which the present disclosure is implemented (i.e., such details should be entirely within the purview of those skilled in the art), the arrangement may be shown in block diagram form. In cases where specific details (such as circuits) are set forth to describe example embodiments of the present disclosure, it should be apparent to those skilled in the art that the present disclosure can be practiced without these specific details or with variations of these specific details. Accordingly, the description should be regarded as illustrative rather than restrictive.

[0077] The following example items relate to further embodiments. The details in the example items may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented for a method or process.

[0078] Item 1: A device, comprising: a first component and a second component; a first circuit for allocating the first component to a first group of components and the second component to a second group of components; and a second circuit for allocating a first maximum frequency limit to the first group of components and a second maximum frequency limit to the second group of components, wherein the first component and the second component operate according to the first maximum frequency limit and the second maximum frequency limit, respectively.

[0079] Item 2: The device according to Item 1, wherein the first component is configured to operate according to the first maximum frequency limit such that the operating frequency of the first component does not exceed the first maximum frequency limit.

[0080] Item 3: The device according to Item 1, wherein the first component and the second component are a first processing core and a second processing core, respectively.

[0081] Item 4: The device according to any one of Items 1 - 3, wherein the first circuit is configured to allocate the first component to the first group of components at least partially based on the workload assigned to the first component.

[0082] Item 5: The device according to Item 4, wherein the first circuit is configured to allocate the first component to the first group of components at least partially based on the workload assigned to the first component being classified as relatively critical.

[0083] Item 6: The device according to Item 4, wherein the first circuit is configured to allocate the first component to the first group of components at least partially based on the workload assigned to the first component being classified as relatively compute - intensive.

[0084] Item 7: The device according to any one of Items 1 - 3, wherein the first circuit is configured to allocate the first component to the first group of components at least partially based on comparing a first operating frequency requested by the first component with a threshold frequency.

[0085] Item 8: The device according to any one of Items 1 - 3, further comprising: a first plurality of components, wherein the first plurality of components includes the first component, wherein the first circuit is configured to allocate the first plurality of components to the first group of components, and wherein the first plurality of components operate according to the first maximum frequency limit; and a second plurality of components, wherein the second plurality of components includes the second component, wherein the first circuit allocates the second plurality of components to the second group of components, and wherein the second plurality of components operate according to the second maximum frequency limit.

[0086] Item 9: The device according to any one of Items 1 - 3, wherein the first component operates at the first maximum frequency limit during an accelerated operation mode.

[0087] Item 10: A system, comprising: a memory for storing instructions; and a first processing core coupled to the memory; a second processing core; one or more circuits for: assigning a first maximum frequency to the first processing core and a second maximum frequency to the second processing core, the second maximum frequency being different from the first maximum frequency; and a wireless interface for allowing one or both of the first or second processing cores to communicate with another system.

[0088] Item 11: The system according to item 10, wherein the one or more circuits are for: assigning the first processing core to a first group of processing cores; and assigning the second processing core to a second group of processing cores.

[0089] Item 12: The system according to item 11, wherein the one or more circuits are for: assigning the first maximum frequency to each processing core in the first group of processing cores; and assigning the second maximum frequency to each processing core in the second group of processing cores.

[0090] Item 13: The system according to item 10, wherein the one or more circuits are for: assigning the first maximum frequency to the first processing core and the second maximum frequency to the second processing core at least in part based on the first processing core being assigned a relatively critical workload compared to the workload assigned to the second processing core, wherein the first maximum frequency is higher than the second maximum frequency.

[0091] Item 14: The system according to any one of items 10 - 13, wherein the one or more circuits are for: receiving an identification of a first requested frequency from the first processing core and an identification of a second requested frequency from the second processing core, wherein the first requested frequency is higher than a cut-off frequency and wherein the second requested frequency is lower than the cut-off frequency; and assigning the first maximum frequency to the first processing core and the second maximum frequency to the second processing core at least in part based on the first requested frequency being higher than the cut-off frequency and the second requested frequency being lower than the cut-off frequency, wherein the first maximum frequency is higher than the second maximum frequency.

[0092] Item 15: The system according to any one of items 10 - 13, wherein: the first processing core is for operating at the first maximum frequency such that the operating frequency of the first processing core does not exceed the first maximum frequency; and the second processing core is for operating at the second maximum frequency such that the operating frequency of the second processing core does not exceed the second maximum frequency.

[0093] Item 16: A device, comprising: a plurality of components; one or more first circuits for performing one or both of the following: receiving a plurality of parameters associated with the workload distribution of the plurality of components, or respectively receiving a plurality of request frequencies of the plurality of components; and one or more second circuits for assigning a corresponding maximum frequency limit to each of the plurality of components.

[0094] Item 17: The device according to Item 16, wherein: the one or more first circuits are for grouping the plurality of components into two or more groups; and the one or more second circuits are for assigning a first maximum frequency limit to one or more components of a first group among the two or more groups.

[0095] Item 18: The device according to Item 17, wherein the one or more components of the first group are for operating at the first maximum frequency limit such that the operating frequency of the one or more components of the first group does not exceed the first maximum frequency limit.

[0096] Item 19: The device according to Item 17, wherein the one or more second circuits are for selecting the first maximum frequency limit at least partially based on the number of components in each of the two or more groups.

[0097] Item 20: The device according to Item 17, wherein the one or more first circuits are for grouping the plurality of components into two or more groups at least partially based on the criticality or priority of each of the plurality of components.

[0098] Item 21: One or more non-transitory computer-readable storage media configured to store instructions that, when executed by a processor included in a device, cause the processor to perform the following operations: assigning a first component to a first group of components, assigning a second component to a second group of components; assigning a first maximum frequency limit to the first group of components, assigning a second maximum frequency limit to the second group of components; and causing the first component and the second component to operate at the first maximum frequency limit and the second maximum frequency limit respectively.

[0099] Item 22: The one or more non-transitory computer-readable storage media according to Item 21, wherein the first component is for operating at the first maximum frequency limit such that the operating frequency of the first component does not exceed the first maximum frequency limit.

[0100] Item 23: The one or more non-transitory computer-readable storage media according to Item 21, wherein the first component and the second component are a first processing core and a second processing core respectively.

[0101] Item 24: One or more non-transitory computer-readable storage media according to any one of Items 21-23, wherein the first component is assigned to the first group of components at least partially based on the workload assigned to the first component.

[0102] Item 25: One or more non-transitory computer-readable storage media according to any one of Items 21-23, wherein the first component is assigned to the first group of components at least partially based on the workload assigned to the first component being classified as relatively critical and / or relatively computationally intensive.

[0103] Item 26: A method, comprising: assigning a first component to a first group of components, assigning a second component to a second group of components; assigning a first maximum frequency limit to the first group of components and a second maximum frequency limit to the second group of components; and causing the first component and the second component to operate according to the first maximum frequency limit and the second maximum frequency limit, respectively.

[0104] Item 27: The method according to Item 26, wherein the first component is configured to operate according to the first maximum frequency limit such that the operating frequency of the first component does not exceed the first maximum frequency limit.

[0105] Item 28: The method according to Item 26, wherein the first component and the second component are a first processing core and a second processing core, respectively.

[0106] Item 29: The method according to any one of Items 26-28, wherein the first component is assigned to the first group of components at least partially based on the workload assigned to the first component.

[0107] Item 30: The method according to any one of Items 26-28, wherein the first component is assigned to the first group of components at least partially based on the workload assigned to the first component being classified as relatively critical and / or relatively intensive.

[0108] Item 31: One or more non-transitory computer-readable storage media for storing instructions that, when executed by a processor, cause the processor to perform the method according to any one of Items 26-30.

[0109] Item 32: An apparatus, comprising: a module for performing the method according to any one of Items 26-30.

[0110] Item 33: An apparatus, comprising: a module for allocating a first component to a first group of components and a second component to a second group of components; a module for allocating a first maximum frequency limit to the first group of components and a second maximum frequency limit to the second group of components; and a module for causing the first component and the second component to operate according to the first maximum frequency limit and the second maximum frequency limit respectively.

[0111] Item 34: The apparatus according to item 33, wherein the first component is configured to operate according to the first maximum frequency limit such that the operating frequency of the first component does not exceed the first maximum frequency limit.

[0112] Item 35: The apparatus according to item 33, wherein the first component and the second component are a first processing core and a second processing core respectively.

[0113] Item 36: The apparatus according to any one of items 33 - 35, wherein the first component is allocated to the first group of components at least partially based on the workload assigned to the first component.

[0114] Item 37: The apparatus according to any one of items 33 - 35, wherein the first component is allocated to the first group of components at least partially based on the workload assigned to the first component being classified as relatively critical and / or relatively computationally intensive.

[0115] A summary is provided to allow the reader to determine the nature and gist of the technical disclosure. The summary is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The appended claims are hereby incorporated into the detailed description, where each claim stands on its own as a separate embodiment.

Claims

1. An apparatus, comprising: A first component and a second component; A first circuit for allocating the first component to a first group of components and the second component to a second group of components; And A second circuit for allocating a first maximum frequency limit to the first group of components and a second maximum frequency limit to the second group of components, Wherein the first component and the second component operate according to the first maximum frequency limit and the second maximum frequency limit respectively; Wherein the first maximum frequency limit is higher than the reference maximum frequency limit of the first component and the second component; And Wherein the second maximum frequency limit is lower than the reference maximum frequency limit of the first component and the second component; and Wherein the number of components in the first group and the second group is dynamically set; Wherein the first circuit is configured to: allocate the first component to the first group of components at least partially based on the workload assigned to the first component, and the workload of the first component has a higher QoS compared to the second workload with a lower QoS assigned to the second component.

2. The device according to claim 1, wherein The first component is configured to operate according to the first maximum frequency limit such that the operating frequency of the first component does not exceed the first maximum frequency limit.

3. The device according to claim 1, wherein, The first component and the second component are a first processor core and a second processor core respectively.

4. The device according to claim 1, wherein The first circuit is configured to allocate the first component to the first group of components at least partially based on the workload assigned to the first component.

5. The apparatus according to claim 4, wherein The first circuit is configured to allocate the first component to the first group of components at least partially based on the workload assigned to the first component being classified as relatively critical.

6. The device according to claim 4, wherein The first circuit is configured to allocate the first component to the first group of components at least partially based on the workload assigned to the first component being classified as relatively compute-intensive.

7. The apparatus according to claim 1, wherein The first circuit is configured to allocate the first component to the first group of components at least partially based on comparing a first operating frequency requested by the first component with a threshold frequency.

8. The apparatus according to claim 1, further comprising: A first plurality of components, wherein the first plurality of components includes the first component, wherein the first circuit is configured to allocate the first plurality of components to the first group of components, and wherein the first plurality of components operate according to the first maximum frequency limit; And A second plurality of components, wherein the second plurality of components includes the second component, wherein the first circuit allocates the second plurality of components to the second group of components, and wherein the second plurality of components operate according to the second maximum frequency limit.

9. The device according to claim 1, wherein The first component operates at the first maximum frequency limit during an accelerated operation mode.

10. A system, comprising: A memory for storing instructions; A first processor core coupled to the memory; A second processor core; One or more circuits for: Allocating a first maximum frequency limit to the first processor core, and Allocating a second maximum frequency limit to the second processor core, the second maximum frequency being different from the first maximum frequency; And Wherein, the first maximum frequency limit is higher than the reference maximum frequency limits of the first and second processor cores; and wherein, the second maximum frequency limit is lower than the reference maximum frequency limits of the first and second processor cores; Wherein, the reference maximum frequency limit is a function of the number of processor cores in a group, wherein the first processor core is in a first group of processor cores, wherein the second processor core is in a second group of processor cores, and wherein the number of processor cores in the first group and the second group is dynamically set, Wherein, the one or more circuits are configured to: allocate the first processor core to the first group of processor cores at least in part based on the workload assigned to the first processor core, wherein the workload of the first processor core has a higher QoS compared to a second workload with a lower QoS assigned to the second processor core, A wireless interface for allowing one or both of the first and second processor cores to communicate with another system.

11. The system according to claim 10, wherein, The one or more circuits are configured to: Allocate the first processor core to the first group of processor cores; and Allocate the second processor core to the second group of processor cores.

12. The system according to claim 11, wherein, The one or more circuits are configured to: Allocate the first maximum frequency to each processor core in the first group of processor cores; and Allocate the second maximum frequency to each processor core in the second group of processor cores.

13. The system according to claim 10, wherein the one or more circuits are configured to: Allocate the first maximum frequency to the first processor core and the second maximum frequency to the second processor core at least in part based on the first processor core being assigned a relatively critical workload compared to the workload assigned to the second processor core, Wherein the first maximum frequency is higher than the second maximum frequency.

14. The system according to claim 10, wherein, The one or more circuits are configured to: Receive an identification of a first requested frequency from the first processor core and an identification of a second requested frequency from the second processor core, wherein the first requested frequency is higher than a cut-off frequency, and wherein the second requested frequency is lower than the cut-off frequency; And Allocate the first maximum frequency to the first processor core and the second maximum frequency to the second processor core at least in part based on the first requested frequency being higher than the cut-off frequency and the second requested frequency being lower than the cut-off frequency, Wherein the first maximum frequency is higher than the second maximum frequency.

15. The system according to claim 11, wherein: The first processor core is configured to operate at the first maximum frequency such that the clock frequency of the first processor core does not exceed the first maximum frequency; and The second processor core is configured to operate at the second maximum frequency such that the clock frequency of the second processor core does not exceed the second maximum frequency.

16. An apparatus, comprising: A plurality of components including a first component and a second component; First one or more circuits for performing one or both of the following: Receiving a plurality of parameters associated with the workload allocation of the plurality of components, or Receive a plurality of request frequencies of the plurality of components respectively; And A second one or more circuits for assigning a corresponding maximum frequency limit to each of the plurality of components; Wherein, the first one or more circuits are used to group the plurality of components into two or more groups; and the second one or more circuits are used to assign a first maximum frequency limit to one or more components of the first group among the two or more groups, and assign a second maximum frequency limit to one or more components of the second group among the two or more groups; the first maximum frequency limit is higher than the reference maximum frequency limits of the first component and the second component; and, The second maximum frequency limit is lower than the reference maximum frequency limits of the first component and the second component; Wherein, the number of components in the first group and the second group is dynamically set; Wherein, the second one or more circuits are configured to: assign the first component to the first group of components at least partially based on the workload assigned to the first component, and the workload of the first component has a higher QoS compared with the second workload with a lower QoS assigned to the second component.

17. The apparatus according to claim 16, wherein, One or more components of the first group are used to operate at the first maximum frequency limit, so that the clock frequency of one or more components of the first group does not exceed the first maximum frequency limit.

18. The apparatus according to claim 16, wherein the second one or more circuits are used to select the first maximum frequency limit at least partially based on the number of components in each of the two or more groups.

19. The apparatus according to claim 16, wherein The first one or more circuits are used to group the plurality of components into two or more groups at least partially based on the criticality or priority of each of the plurality of components.

20. One or more non-transitory computer-readable storage media configured to store instructions that, when executed by a processor included in a device, cause the processor to perform the following operations: Assign the first component to the first group of components and assign the second component to the second group of components; Assign a first maximum frequency limit to the first set of components and a second maximum frequency limit to the second set of components; And Cause the first component and the second component to operate at the first maximum frequency limit and the second maximum frequency limit respectively; Wherein the first maximum frequency limit is higher than the reference maximum frequency limits of the first component and the second component; And Wherein, the second maximum frequency limit is lower than the reference maximum frequency limits of the first component and the second component; and Wherein, the number of components in the first group and the second group is dynamically set; Wherein, the first component is assigned to the first group of components at least partially based on the workload assigned to the first component.

21. The one or more non-transitory computer-readable storage media according to claim 20, wherein, The first component is used to operate at the first maximum frequency limit, so that the operating frequency of the first component does not exceed the first maximum frequency limit.

22. The one or more non-transitory computer-readable storage media according to claim 20, wherein, Assign the first component to the first group of components at least partially based on the workload assigned to the first component.

23. A multi-processor system-on-chip (SoC) with a reference frequency limit, the multi-processor SoC comprising: A first processor core that operates at a first maximum frequency limit higher than the reference frequency limit; A second processor core that operates at a second maximum frequency limit lower than the reference frequency limit; Wherein, compared to the workload of the second processor core, the first processor core has a higher workload, A circuit that dynamically and adaptively assigns the first maximum frequency limit to the first processor core and the second maximum frequency limit to the second processor core; Wherein, the reference frequency limit is a function of the number of processor cores in a group, wherein the first processor core is located in a first group of processor cores, and wherein the second processor core is located in a second group of processor cores, and Wherein, the number of processor cores in the group is dynamically set, Wherein, the circuit is configured to: at least in part, assign the first processor core to the first group based on the first workload assigned to the first processor core, and the workload of the first processor core has a higher quality of service (QoS) compared to the second workload with a lower QoS assigned to the second processor core.

24. The SoC according to claim 23, wherein The first processor core is assigned to the first group, and the second processor core is assigned to the second group based on a thermal limit.

25. The SoC as claimed in claim 23, wherein The number of groups including the first group and the second group is equal to the number of processor cores including the first processor core and the second processor core.

26. The SoC as claimed in claim 23, wherein The first group is associated with a first virtual machine (VM), and wherein the second group is associated with a second virtual machine (VM).

Images