A Static Current Elimination Circuit and Method for a Nuclear Magnetic Resonance Gradient Power Amplifier

Abstract

The present invention provides a static current elimination circuit for a nuclear magnetic resonance gradient power amplifier, which includes an FPGA controller, a first digital-to-analog converter (DAC), a proportional resistor, a gradient power amplifier, a measuring resistor, and a gradient coil connected in series in sequence. The output end of the gradient coil is grounded through a Blank switch. The FPGA controller is also connected to a second DAC, and the output end of the second DAC is connected to the input end of the gradient power amplifier through a bias proportional resistor. By iteratively detecting the static current and calculating the feedback voltage, the present invention makes the static current tend to zero. At the same time, the Blank switch is used to isolate the gradient power amplifier and the gradient coil circuit, blocking the output of the static current, thus becoming an ideal gradient power amplifier without static current that is not affected by external signals.

Description

Technical Field

[0001] The present invention relates to a static current elimination circuit and method for a nuclear magnetic resonance gradient power amplifier. Background Art

[0002] A nuclear magnetic resonance spectrometer is developed and produced based on the principle of nuclear magnetic resonance. It emits high-power radio frequency pulses to the object to be measured placed in a uniform strong magnetic field to excite the resonance phenomenon of the atomic nuclei of the object to be measured, and obtains the nuclear magnetic resonance signals of the target sample area or spectral area through methods such as accumulation, phase encoding, and gradient selection. The phase encoding and gradient selection methods often output pulsed currents of specified power through a gradient power amplifier. This current forms a linearly varying gradient magnetic field in the gradient coil, so that the resonance characteristics of the magnetic fields where each area of the measured sample is located in the Z, X, and Y directions are accurately encoded, thereby accurately selecting the nuclear magnetic resonance signals of the target sample area or spectral area. In order to achieve the accuracy of selection, objectively, it is required that the pulsed current output by the gradient power amplifier of the nuclear magnetic resonance spectrometer has good linearity, high precision, accurate shape, and good symmetry of positive and negative pulses.

[0003] In a nuclear magnetic resonance spectrometer, as an analog power amplification component, the gradient power amplifier is directly connected to the gradient coil installed at the center of the magnet. The radio frequency coil is installed closely inside the gradient coil. In actual operation, the nuclear magnetic resonance spectrometer has the following requirements for the gradient system:

[0004] 1) The output of the gradient power amplifier is in the form of a pulse. When no pulse is output, the ideal output current of the gradient power amplifier should be 0. As an analog power component, the gradient power amplifier is composed of a large number of operational amplifiers, power transistors, etc. And analog devices such as operational amplifiers and power transistors have the inherent characteristic of output bias. In the gradient power amplifier, it is manifested that when the input voltage of the gradient power amplifier is 0, the gradient power amplifier still outputs a non-zero static current. According to the different characteristics of these analog devices, the static current varies from microamperes to milliamperes. When the static current of the gradient power amplifier flows through the gradient coil, the gradient coil will generate a magnetic field in the Z, X, or Y direction, which will damage the magnetic field uniformity of the superconducting magnet.

[0005] 2) When there is a weak static current in the gradient power amplifier, it can be compensated by room temperature shimming, but the compensation is constant and cannot be changed during the nuclear magnetic test. When the gradient static current changes, the compensation will fail. As an analog circuit, when the power supply voltage of the gradient power amplifier drifts or changes in other states, its static current will change, causing the compensation to fail. Especially when the nuclear magnetic resonance spectrometer performs long-term tests, the accumulated drift of the static current will cause the test results to deteriorate seriously.

[0006] 3) The output of the gradient power amplifier should not be affected by other components in the nuclear magnetic resonance spectrometer. In a nuclear magnetic resonance spectrometer, the gradient coil is both the transmitting coil for the gradient field and the audio receiving coil at the same time. The gradient coil will receive the radio frequency pulses from the radio frequency coil installed in the middle of the gradient coil and the interference signals from the external space. These signals are input into the gradient power amplifier through the cable, which will cause fluctuations in the output current of the gradient power amplifier and generate interference pulses at the same time, and then output to the gradient coil, seriously deteriorating the magnetic field, reducing the test signal quality, and even causing errors in the test results.

[0007] 4) The gradient power amplifier has good linearity, and the output shape must be accurate. In nuclear magnetic resonance, multiple gradient pulses with accurately proportional output sizes are often used to perform gradient encoding on the sample to be measured. In fact, there is a static current in the gradient power amplifier itself, which causes the gradient pulses that theoretically require a strict proportional relationship to deviate from the theoretical proportional relationship, and also causes the shaped pulses to deviate from the ideal function shape. Objectively, the static current of the gradient power amplifier should reach the microampere level.

[0008] To meet the above requirements, the methods of the existing technology are as follows:

[0009] 1) Since the static current always exists and changes, it can only be reduced by optimizing the device and cannot be eliminated. Generally, two methods are adopted to eliminate it:

[0010] a. Measure the magnitude of the static current at regular intervals, and set the bias current in the digital control value of the gradient current through software methods to eliminate the bias current;

[0011] b. Generate additional currents in the X, Y, and Z directions of the room temperature shimming between each nuclear magnetic resonance detection to offset the magnetic field generated by the gradient static current in the corresponding direction.

[0012] 2) In order to avoid the gradient coil from receiving external interference signals, a low-pass filter is often connected in series in the cable connecting the gradient power amplifier to the gradient coil to filter the high-frequency signal interference emitted by the radio frequency coil.

[0013] The disadvantages of the existing technology are as follows:

[0014] 1) The method of measuring the static current at regular intervals is often manually measured, and the measured value is recorded in the control software. Due to the uncertainty of the implementation time and the difficulty of fixing the time point, professional maintenance personnel are required to measure, which is difficult for ordinary users to operate. Moreover, during the long-term nuclear magnetic resonance test, the static current cannot be measured.

[0015] 2) By means of shimming at room temperature, the magnetic fields generated by the static currents in the X, Y, and Z directions are cancelled out. The influence of the static currents can be eliminated in a short time. However, when the static currents change, shimming cannot be carried out in time, and the influence of the static currents cannot be completely eliminated. Since shimming cannot be performed during the nuclear magnetic resonance (NMR) detection process, the longer the NMR detection time, the more serious the influence of the static currents will be, resulting in a deterioration of the NMR detection quality or even invalid data.

[0016] 3) Since the gradient power amplifier operates in the audio frequency range, the method of eliminating external interference by a series-connected filter makes the volume of the filter very large, the overall structure of the system becomes complex, and the filter cannot eliminate the external interference signals within the audio frequency range. It only has a certain inhibitory effect on the out-of-band signals, and still a part of the interference signals will enter the gradient power amplifier, causing changes in the static current of the gradient power amplifier. Summary of the Invention

[0017] The present invention provides a static current elimination circuit and method for a nuclear magnetic resonance gradient power amplifier without static current. A Blank switch is used to isolate the gradient power amplifier and the gradient coil loop, blocking the output of the static current and avoiding the influence of external signals on the gradient power amplifier. At the same time, by iteratively detecting the static current and calculating the feedback voltage, the static current tends to zero, making the gradient power amplifier an ideal gradient power amplifier without static current that is not affected by external signals.

[0018] The technical solution of the present invention is implemented as follows:

[0019] A static current elimination circuit for a nuclear magnetic resonance gradient power amplifier includes an FPGA controller 1, a first digital-to-analog converter DAC2, a proportional resistor 4, a gradient power amplifier 7, a measuring resistor 8, and a gradient coil 15 connected in series in sequence. A feedback proportional resistor 6 is connected in parallel between the input terminal and the output terminal of the gradient power amplifier 7. The gradient coil 15 is grounded through a Blank switch 16. It is characterized in that the FPGA controller 1 is further connected to the input terminal of a second digital-to-analog converter DAC3, the output terminal of the second digital-to-analog converter DAC3 is connected to a bias proportional resistor 5, and the bias proportional resistor 5 is also connected to the input terminal of the gradient power amplifier 7.

[0020] Preferably, a measuring resistor 8 is further connected between the output terminal of the gradient power amplifier 7 and the gradient coil 15, and the two input terminals of a differential amplifier 9 are respectively connected to both ends of the measuring resistor 8.

[0021] Preferably, the output terminal of the differential amplifier 9 is connected to the fixed terminal of the first single-pole double-throw switch 10. The first moving terminal of the first single-pole double-throw switch 10 is connected to the input terminal of the first feedback amplifier 11. The output terminal of the first feedback amplifier 11 is connected to the first moving terminal of the second single-pole double-throw switch 13. The fixed terminal of the second single-pole double-throw switch 13 is connected to the input terminal of the analog-to-digital converter ADC 14. The output terminal of the analog-to-digital converter ADC 14 is connected to the FPGA controller 1.

[0022] Preferably, the second moving terminal of the first single-pole double-throw switch 10 is connected to the input terminal of the second feedback amplifier 12. The output terminal of the second feedback amplifier 12 is connected to the second moving terminal of the second single-pole double-throw switch 13.

[0023] Preferably, the amplification factor of the first feedback amplifier 11 is greater than that of the second feedback amplifier 12. The first feedback amplifier 11 is used to detect a static current less than 1 mA, and the second feedback amplifier 12 is used to detect a gradient current greater than 1 A.

[0024] A method for eliminating the static current of a nuclear magnetic resonance gradient power amplifier. The FPGA controller 1 receives external gradient control data and drives the first digital-to-analog converter DAC2 to generate a voltage waveform. The voltage is amplified by a proportional power amplifier composed of a proportional resistor 4, a feedback proportional resistor 6, and a gradient power amplifier 7 and then outputs a gradient current I. The gradient current I is output to the gradient coil 15 and forms a gradient magnetic field in the gradient coil 15. It is characterized in that the FPGA controller (1) also simultaneously drives the second digital-to-analog converter DAC3 to generate a reverse feedback voltage -ΔD according to the error current ΔD. The feedback voltage -ΔD is input to the gradient power amplifier 7 after passing through the bias proportional resistor 5 to eliminate the static current of the gradient power amplifier 7.

[0025] Preferably, it specifically includes the following steps:

[0026] S1. During the t0 period, the gradient power amplifier 7 operates in the gradient output mode to output the gradient current I. The Blank switch 16 is controlled by an external signal. The FPGA controller 1 receives external gradient control data and drives the first digital-to-analog converter DAC2 to generate a voltage waveform. When the gradient power amplifier 7 is powered on or triggered by an external signal, the FPGA controller 1 switches to the static current adjustment mode and enters the t1 period.

[0027] S2. During the t1 period, the FPGA controller 1 turns off the externally input gradient control signal and the Blank switch 16 signal, sets the Blank switch 16 to 0 to disconnect, makes the current output of the gradient power amplifier 0, and clears the outputs of the first digital-to-analog converter DAC2 and the second digital-to-analog converter DAC3.

[0028] S3, during time period t2, the FPGA controller 1 switches the first single-pole double-throw switch 10 and the second single-pole double-throw switch 13 to the first feedback amplifier 11, so that the voltage on the measuring resistor 8 is input to the analog-to-digital converter ADC 14; the FPGA controller (1) continuously acquires the voltage value when the current output is 0 through the analog-to-digital converter ADC 14, and records this value as the static current adjustment target value D Zero ;

[0029] t2 lasts for a specified time to ensure the target value D Zero is stable and accurate, and then enters time period t3.

[0030] S4, during time period t3, set the Blank switch 16 to 1 to conduct, so that the static current of the gradient power amplifier flows out, and continuously detect the magnitude D of the output static current through the first feedback amplifier 11 and the analog-to-digital converter ADC 14 Current ;

[0031] The FPGA controller (1) calculates the error current ΔD: error current ΔD = static current D Current - static current adjustment target value D Zero ;

[0032] The FPGA controller (1) controls the second digital-to-analog converter DAC (3) to generate a reverse error feedback voltage -ΔD according to the error current ΔD. The error feedback voltage -ΔD is input to the gradient power amplifier (7) through the bias ratio resistor (5) to cancel the static current D Current , to eliminate the static current;

[0033] S5, during time period t4, keep the output of the second digital-to-analog converter DAC3, set the Blank switch 16 to 0 to disconnect, the analog-to-digital converter ADC 14 stops collecting, switch the first single-pole double-throw switch 10 and the second single-pole double-throw switch 13 to the second feedback amplifier 12, and exit the static current adjustment mode after a specified time, and enter time period t5;

[0034] S6, during time period t5, the gradient power amplifier 7 works in the gradient output mode, the error feedback voltage -ΔD calculated in time period t3 is maintained, the FPGA controller 1 accesses the externally input gradient control signal and Blank switch signal, and the external controller controls the operation of the gradient power amplifier. At the same time, the analog-to-digital converter ADC 14 continuously collects and monitors the output gradient waveform.

[0035] Preferably, in step S3, the FPGA controller (1) continuously performs an average calculation on the collected static current adjustment target value D Zero and sets the average value as the adjustment target value D Zero , the static current adjustment target value D ZeroDetect the bias voltage of the detection circuit when the corresponding output current is 0.

[0036] Preferably, in step S4, if the error current ΔD is greater than the set threshold, the error feedback value is iteratively calculated to reduce the static current, and the feedback process is as follows:

[0037] a. Send the error current ΔD to the PID calculation module of the FPGA controller (1) to calculate the control value of the second digital-to-analog converter DAC (3);

[0038] b. Write the calculated control value into the second digital-to-analog converter DAC (3);

[0039] c. The voltage generated by the second digital-to-analog converter DAC (3) forms a current in the gradient power amplifier (7) that is opposite to the direction of the actual static current, so that the static current is cancelled out;

[0040] d. Repeat the steps of collecting the static current, calculating the error current ΔD, and writing the new feedback value until the magnitude D of the static current Current is less than the threshold.

[0041] Preferably, in step S4, if the error current ΔD is less than the threshold, stop calculating the new feedback value, continuously monitor the static current for t seconds. If the magnitude D of the static current Current continuously remains less than the threshold, then enter t4; otherwise, repeat step S4 until the error current ΔD meets the threshold requirement within t seconds.

[0042] The beneficial effects of the present invention are as follows: The Blank switch is used to isolate the gradient power amplifier and the output from the gradient coil, so that the static current cannot be output, thereby avoiding the influence of the static current on the magnetic field and preventing the gradient output from being abnormal or the static current from changing due to external factors such as the RF coil. At the same time, a differential measurement resistor, a high-gain amplifier, a high-precision analog-to-digital converter ADC, and a digital-to-analog converter DAC are used to form a static current acquisition and feedback loop, and the PID algorithm is used to automatically iterate and eliminate the static current, so that the output static current of the gradient power amplifier is reduced to the microampere level, thereby ensuring that the output of the gradient power amplifier maintains an accurate shape and symmetry; the static current monitoring and elimination system operates fully automatically, is easy to use, and realizes an ideal gradient power amplifier with high linearity, high symmetry, and no static current. Description of the Drawings

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0044] Figure 1 This is the circuit principle block diagram of the present invention.

[0045] Figure 2 This is the static current adjustment timing diagram.

[0046] Figure 3 This is the static current adjustment flowchart. Detailed implementation manners

[0047] Next, the technical solution of the present invention will be clearly and completely described in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present invention.

[0048] As Figure 1 shown, a static current elimination circuit of a nuclear magnetic resonance gradient power amplifier includes an FPGA controller 1, a first digital-to-analog converter DAC 2, a proportional resistor 4, a gradient power amplifier 7, a measuring resistor 8, and a gradient coil 15 connected in series in sequence. A feedback proportional resistor 6 is connected in parallel to the input end and the output end of the gradient power amplifier 7. The gradient coil 15 is grounded through a Blank switch 16.

[0049] The FPGA controller 1 is further connected to the input end of a second digital-to-analog converter DAC 3. The output end of the second digital-to-analog converter DAC 3 is connected to a bias proportional resistor 5, and the bias proportional resistor 5 is also connected to the input end of the gradient power amplifier 7. A measuring resistor 8 is also connected between the output end of the gradient power amplifier 7 and the gradient coil 15. Two input ends of a differential amplifier 9 are respectively connected to both ends of the measuring resistor 8.

[0050] Wherein, the output end of the differential amplifier 9 is connected to the fixed end of a first single-pole double-throw switch 10. The first moving end of the first single-pole double-throw switch 10 is connected to the input end of a first feedback amplifier 11. The output end of the first feedback amplifier 11 is connected to the first moving end of a second single-pole double-throw switch 13. The fixed end of the second single-pole double-throw switch 13 is connected to the input end of an analog-to-digital converter ADC 14. The output end of the analog-to-digital converter ADC 14 is connected to the FPGA controller 1. The second moving end of the first single-pole double-throw switch 10 is connected to the input end of a second feedback amplifier 12. The output end of the second feedback amplifier 12 is connected to the second moving end of the second single-pole double-throw switch 13.

[0051] Among them, the amplification factor of the first feedback amplifier 11 is greater than that of the second feedback amplifier 12. The first feedback amplifier 11 is used to detect the static current below 1 mA, and the second feedback amplifier 12 is used to detect the gradient current above 1 A. Moreover, the maximum outputs of the first feedback amplifier 11 and the second feedback amplifier 12 are close to the maximum allowable input of the analog-to-digital converter ADC 14 to ensure the maximum detection current resolution.

[0052] The FPGA controller 1 receives external gradient control data and drives the first digital-to-analog converter DAC2 to generate a voltage waveform. The voltage is amplified by a proportional power amplifier composed of a proportional resistor 4, a feedback proportional resistor 6, and a gradient power amplifier 7 and then outputs a gradient current I. The gradient current I is output to the gradient coil 15 through a measuring resistor 8 and forms a gradient magnetic field in the gradient coil 15.

[0053] The FPGA controller 1 also simultaneously drives the second digital-to-analog converter DAC3 to generate a reverse constant feedback voltage according to the error current ΔD. The constant feedback voltage is input to the gradient power amplifier 7 after passing through a bias proportional resistor 5 to eliminate the static current of the gradient power amplifier 7.

[0054] In this embodiment, the switching timing of the Blank switch 16 is synchronized with the output of the gradient current I. That is, when the gradient current I is output, the Blank switch 16 is turned on to enable the normal output of the gradient current I. When the gradient current I is not output, the Blank switch 16 is turned off. When the Blank switch 16 is turned off, the static current of the gradient power amplifier is blocked to prevent the static current from flowing to the gradient coil 15. When the Blank switch 16 is turned on, the output of the gradient power amplifier is superimposed with the static current and output to the gradient coil to generate a magnetic field.

[0055] In the embodiment, the gradient power amplifier 7 is composed of multiple operational amplifiers, power amplifier tubes, etc. The operational amplifiers and power amplifier tubes have inherent static biases. When the input of the gradient power amplifier 7 is 0, its output also has a certain magnitude of static current, which ranges from a few microamperes to dozens of milliamperes. The static current causes the following problems: 1) The static current finally forms a gradient magnetic field in the Z, X, or Y direction with a certain intensity in the gradient coil 15, destroying the uniformity of the magnetic field. 2) The static current will be superimposed on the normally output gradient current I, causing a bias in the finally output gradient current I and deviating the shape and proportional relationship of the gradient waveform from the theoretical values.

[0056] When the gradient current I flows through the measuring resistor 8, a voltage V = I × R will be formed on both sides of the measuring resistor 8 sThe voltage V is detected and amplified by the differential amplifier 9 and selectively output to the first feedback amplifier 11 or the second feedback amplifier 12 through the first single-pole double-throw switch 10. Among them, the first feedback amplifier 11 has a large amplification factor and is used to detect a weak static current less than 1 mA; the first feedback amplifier 11 has a small amplification factor and is used to detect a gradient current above 1 A of the normal output. The output of the first feedback amplifier 11 or the second feedback amplifier 12 is sent to the analog-to-digital converter ADC14, and the analog-to-digital converter ADC14 converts the output voltage into a digital signal under the control of the FPGA controller 1.

[0057] The gradient power amplifier 7 operates in two modes: static current adjustment mode and gradient output mode.

[0058] When the gradient power amplifier operates in the static current adjustment mode, the first single-pole double-throw switch 10 and the second single-pole double-throw switch 13 are switched to the first feedback amplifier 11. The weak voltage formed by the static current on the measuring resistor 8 is amplified by the differential amplifier 9 and the first feedback amplifier 11. Within the allowable static current range, the voltage of the output signal of the first feedback amplifier 11 is close to the maximum allowable input of the analog-to-digital converter ADC14.

[0059] When the gradient power amplifier 7 operates in the gradient output mode, the first single-pole double-throw switch 10 and the second single-pole double-throw switch 13 are switched to the second feedback amplifier 12. The strong voltage formed by the gradient current above 1 A on the measuring resistor 8 is amplified by the differential amplifier 9 and the second feedback amplifier 12, and the output maximum voltage is close to the maximum allowable input voltage of the analog-to-digital converter ADC14.

[0060] A method for eliminating the static current of a nuclear magnetic resonance gradient power amplifier specifically includes the following steps:

[0061] S1, in the time period t0, the gradient power amplifier 7 operates in the gradient output mode. The Blank switch 16 is controlled by an external signal. The FPGA controller 1 receives external gradient control data and drives the first digital-to-analog converter DAC2 to generate a voltage waveform. The gradient power amplifier 7 is powered on or triggered by an external signal, and the FPGA controller 1 switches to the static current adjustment mode and enters the time period t1.

[0062] S2, in the time period t1, the FPGA controller 1 turns off the externally input gradient control signal and the Blank switch 16 signal, sets the Blank switch (16) to 0 to disconnect, makes the current output of the gradient power amplifier 0, and clears the outputs of the first digital-to-analog converter DAC(2) and the second digital-to-analog converter DAC(3).

[0063] S3, during time period t2, the FPGA controller 1 switches the first single-pole double-throw switch 10 and the second single-pole double-throw switch 13 to the first feedback amplifier 11, so that the voltage on the measuring resistor 8 is input to the analog-to-digital converter ADC 14; the analog-to-digital converter ADC 14 continuously acquires the voltage value when the current output is 0, and records this value as the static current adjustment target value D Zero ;

[0064] The FPGA controller (1) continuously averages the acquired static current adjustment target value D Zero and sets the average value as the adjustment target value D Zero , the static current adjustment target value D Zero corresponds to the bias voltage of the detection circuit when the output current is 0. This method eliminates the error introduced by the sampling circuit in the finally adjusted static current.

[0065] t2 lasts for a specified time to ensure that the acquired value is stable, and then enters the t3 time period.

[0066] S4, during time period t3, set the Blank switch 16 to 1 to conduct, so that the static current of the gradient power amplifier flows out, and continuously detect the magnitude D of the output static current through the first feedback amplifier 11 and the analog-to-digital converter ADC 14 Current , the FPGA controller (1) calculates the error current ΔD:

[0067] Error current ΔD = static current D Current - static current adjustment target value D Zero

[0068] where D Current detects the sum of the voltage formed by the static current of the gradient power amplifier on the detection resistor 8 and the bias voltage of the feedback detection circuit part, and D Zero is the bias voltage of the feedback detection circuit. The difference between the two is the error current ΔD, that is, there is actually a static current in the gradient power amplifier circuit itself. The FPGA controller 1 calculates the feedback value using the PID algorithm according to the error current ΔD, and drives the second digital-to-analog converter DAC3 to generate a reverse error current -ΔD. After passing through the bias proportional resistor 5, it is input to the gradient power amplifier 7. After repeated iteration, the static current is finally reduced to the uA level.

[0069] During the process of detecting the static current and calculating the feedback voltage, if the error current ΔD is greater than the set threshold, the error feedback value is iteratively calculated to reduce the static current. The calculation process is as follows:

[0070] a. Send the error current ΔD to the PID calculation module of the FPGA controller (1) to calculate the control value of the second digital-to-analog converter DAC (3);

[0071] b. Write the calculated control value to the second digital-to-analog converter DAC(3);

[0072] c. The voltage generated by the second digital-to-analog converter DAC(3) forms a current in the gradient power amplifier (7) that is opposite to the direction of the actual static current, canceling out the static current;

[0073] d. Repeat the acquisition of the static current, calculation of the error current ΔD, and writing of the new feedback value until the magnitude D of the static current Current is less than the threshold.

[0074] During the process of detecting the static current and calculating the feedback voltage, if the error current ΔD is less than the threshold, stop calculating the new feedback value, continuously monitor the static current for t seconds, and if the magnitude D of the static current Current continues to remain less than the threshold, then enter t4, otherwise repeat the iterative calculation steps until the error current ΔD meets the threshold requirement within t seconds.

[0075] S5. During the t4 period, maintain the output of the second digital-to-analog converter DAC3, set the Blank switch 16 to 0 to disconnect, stop the analog-to-digital converter ADC 14 from collecting, switch the first single-pole double-throw switch 10 and the second single-pole double-throw switch 13 to the second feedback amplifier 12, and exit the static current adjustment mode after a specified time, entering the t5 period;

[0076] S6. During the t5 period, the gradient power amplifier 7 operates in the gradient output mode, the error current ΔD calculated during the t3 period is maintained, the FPGA controller 1 accesses the externally input gradient control signal and the Blank switch signal, and the gradient power amplifier is controlled by the external controller to operate. At the same time, the analog-to-digital converter ADC 14 continuously collects and monitors the output gradient waveform to judge the correctness of the output waveform, and the received gradient waveform is transmitted through the communication interface for monitoring the working state of the gradient system.

[0077] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A static current elimination circuit for a nuclear magnetic resonance gradient power amplifier, comprising an FPGA controller (1), a first digital-to-analog converter DAC (2), a proportional resistor (4), a gradient power amplifier (7), a measuring resistor (8) and a gradient coil (15) connected in series in sequence. A feedback proportional resistor (6) is connected in parallel to the input end and the output end of the gradient power amplifier (7). The gradient coil (15) is grounded through a Blank switch (16), and is characterized in that, The FPGA controller (1) is also connected to the input end of the second digital-to-analog converter DAC (3). The output end of the second digital-to-analog converter DAC (3) is connected to the bias proportional resistor (5), and the bias proportional resistor (5) is also connected to the input end of the gradient power amplifier (7). A measuring resistor (8) is also connected between the output end of the gradient power amplifier (7) and the gradient coil (15). Two input ends of the differential amplifier (9) are respectively connected to both ends of the measuring resistor (8). The output end of the differential amplifier (9) is connected to the fixed end of the first single-pole double-throw switch (10). The first moving end of the first single-pole double-throw switch (10) is connected to the input end of the first feedback amplifier (11). The output end of the first feedback amplifier (11) is connected to the first moving end of the second single-pole double-throw switch (13). The fixed end of the second single-pole double-throw switch (13) is connected to the input end of the analog-to-digital converter ADC (14). The output end of the analog-to-digital converter ADC (14) is connected to the FPGA controller (1). The second moving end of the first single-pole double-throw switch (10) is connected to the input end of the second feedback amplifier (12). The output end of the second feedback amplifier (12) is connected to the second moving end of the second single-pole double-throw switch (13). The amplification factor of the first feedback amplifier (11) is greater than that of the second feedback amplifier (12). The first feedback amplifier (11) is used to detect the static current below 1 mA, and the second feedback amplifier (12) is used to detect the gradient current above 1 A.

2. A method for eliminating the static current of a nuclear magnetic resonance gradient power amplifier, wherein an FPGA controller (1) receives external gradient control data and drives a first digital-to-analog converter DAC (2) to generate a voltage waveform, and the voltage is amplified by a proportional power amplifier composed of a proportional resistor (4), a feedback proportional resistor (6) and a gradient power amplifier (7) to output a gradient current I, and the gradient current I is output to a gradient coil (15) and forms a gradient magnetic field in the gradient coil (15), characterized in that, The FPGA controller (1) also simultaneously calculates the feedback value using the PID algorithm according to the error current ΔD, and drives the second digital-to-analog converter DAC (3) to generate a reverse feedback voltage -ΔD. The feedback voltage -ΔD is input to the gradient power amplifier (7) after passing through the bias proportional resistor (5), and through repeated iteration, the static current is finally reduced to the μA level.

3. The static current elimination method of a nuclear magnetic resonance gradient power amplifier according to claim 2, characterized in that Specifically, it includes the following steps: S1. In the t0 period, the gradient power amplifier (7) operates in the gradient output mode to output the gradient current I. The Blank switch (16) is controlled by an external signal. The FPGA controller (1) receives the external gradient control data and drives the first digital-to-analog converter DAC (2) to generate a voltage waveform. The gradient power amplifier (7) is powered on or triggered by an external signal, and the FPGA controller (1) switches to the static current adjustment mode and enters the t1 period. S2. In the t1 period, the FPGA controller (1) turns off the external input gradient control signal and the Blank switch (16) signal, sets the Blank switch (16) to 0 to disconnect, makes the current output of the gradient power amplifier be 0, and clears the outputs of the first digital-to-analog converter DAC (2) and the second digital-to-analog converter DAC (3). S3. During time period t2, the FPGA controller (1) switches the first single-pole double-throw switch (10) and the second single-pole double-throw switch (13) to the first feedback amplifier (11), so that the voltage on the measuring resistor (8) is input to the analog-to-digital converter ADC (14); the FPGA controller (1) continuously collects the voltage value when the current output is 0 through the analog-to-digital converter ADC (14), and records this value as the static current adjustment target value D Zero ; t2 lasts for the specified time to ensure that the target value D Zero is stable and accurate, and then enters the t3 period; At time period t3 of S4, the FPGA controller (1) sets the Blank switch (16) to 1 to turn it on, allowing the static current of the gradient power amplifier to flow out, and continuously detecting the magnitude D of the output static current through the first feedback amplifier (11) and the analog-to-digital converter ADC (14). Current ; The FPGA controller (1) calculates the error current ΔD: Error current ΔD = Static current D Current - Static current adjustment target value D Zero ; The FPGA controller (1) calculates the feedback value using the PID algorithm based on the error current ΔD, and controls the second digital-to-analog converter DAC (3) to generate a reverse error feedback voltage -ΔD. The error feedback voltage -ΔD is input to the gradient power amplifier (7) after passing through the bias proportional resistor (5), and through repeated iteration, the static current D Current is reduced to the threshold value; During the time periods S5 and t4, maintain the output of the second digital-to-analog converter DAC (3), set the Blank switch (16) to 0 to disconnect, stop the analog-to-digital converter ADC (14) from sampling, switch the first single-pole double-throw switch (10) and the second single-pole double-throw switch (13) to the second feedback amplifier (12), and exit the static current adjustment mode after a specified time to enter the t5 time period; S6. During the t5 time period, the gradient power amplifier (7) operates in the gradient output mode, the error feedback voltage -ΔD calculated in the t3 time period is maintained, the FPGA controller (1) accesses the externally input gradient control signal and the Blank switch signal, and the gradient power amplifier is controlled by the external controller to operate. At the same time, the analog-to-digital converter ADC (14) continuously samples to monitor the output gradient waveform.

4. The static current elimination method of a nuclear magnetic resonance gradient power amplifier according to claim 3, wherein In step S3, the FPGA controller (1) continuously performs an average calculation on the collected static current adjustment target value D Zero and sets the average value as the adjustment target value D Zero , and the static current adjustment target value D Zero corresponds to the bias voltage of the detection circuit when the output current is 0.

5. The static current elimination method of a nuclear magnetic resonance gradient power amplifier according to claim 3, characterized in that, In step S4, if the error current ΔD is greater than the set threshold, the error feedback value is iteratively calculated to reduce the static current, and the calculation process is as follows: a. Send the error current ΔD to the PID calculation module of the FPGA controller (1) to calculate the control value of the second digital-to-analog converter DAC (3); b. Write the calculated control value into the second digital-to-analog converter DAC (3); c. The voltage generated by the second digital-to-analog converter DAC (3) forms a current in the gradient power amplifier (7) that is opposite to the direction of the actual static current, so that the static current is cancelled out; d. Repeatedly collect the static current, calculate the error current ΔD, and write the new feedback value until the magnitude D of the static current Current is less than the threshold value.

6. The static current elimination method of a nuclear magnetic resonance gradient power amplifier according to claim 3, characterized in that, In step S4, if the error current ΔD is less than the threshold, stop calculating the new feedback value, continuously monitor the static current for t seconds, and if the magnitude D of the static current Current continuously remains less than the threshold, then enter t4; otherwise, repeat step S4 until the error current ΔD meets the threshold requirement within t seconds.

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