Inrush current suppression circuit and method for suppressing inrush current

Abstract

A surge current suppression circuit includes a first switch, a pre-charging branch, a third switch, and a control device. The first switch is connected between the input voltage and the bus capacitor; the pre-charging branch is connected in parallel with the first switch, and the pre-charging branch includes a second switch and a resistor connected in series; the third switch is connected between the bus capacitor and the load, and the load is connected in parallel with the bus capacitor. The output end of the control device is respectively connected to the control ends of the first switch, the second switch, and the third switch. The present invention also discloses a method for suppressing surge current using a surge current suppression circuit. The present invention can effectively suppress surge current generated when the switch is turned on, has good versatility, and is low in cost.

Description

Technical Field

[0001] The present invention relates to a surge current suppression technology. Background Art

[0002] A car uses numerous controllers, some of which include power modules. These modules, for example, are power converters capable of providing a certain amount of power, directly driving motors or solenoid valves. Power modules require large bus capacitors to maintain normal operation. The controller's internal bus and input power are typically connected via an input power switch, typically a semiconductor switch such as a MOS transistor or triode. During controller power-up, the input power switch turns on, charging the bus capacitors. If left uncontrolled, this can generate significant inrush current, impacting the power supply network and placing undesirable stress on semiconductor components.

[0003] Currently, there are two common methods to reduce the inrush current when the input power switch is closed:

[0004] Method 1: Slowly drive the input power switch to operate in the linear region to limit inrush current, or continuously turn on the input power switch briefly to limit average power, so that the generated stress does not exceed the safe operating range of the input power switch. The limitation of Method 1 is that the volt-ampere characteristics of the input power switch during the on- and off-time are nonlinear, making the peak inrush current very difficult to control and varying significantly with ambient temperature. A large amount of energy is lost within the input power switch during charging of the bus capacitor, forcing the input power switch to use semiconductor switching devices with higher current and power specifications, resulting in a significant cost increase.

[0005] Method 2: Figure 1 As shown, a resistor R1 is connected in parallel across the first switch S1, forming a series connection with a second switch S2 to precharge the rear-end bus capacitor C1. When the second switch S2 is turned on for precharging, the presence of resistor R1 keeps the current in the circuit less than or equal to the input voltage / R1, thereby suppressing inrush current. After precharging is complete, when the first switch S1 is turned on, the voltage drop across the first switch S1 is smaller than in the absence of precharging. Therefore, during the on-state of the first switch S1, the inrush current and stress on the first switch S1 are reduced. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide an inrush current suppression circuit which can effectively suppress the inrush current generated when a switch is turned on, has good versatility and low cost.

[0007] Another technical problem to be solved by the present invention is to provide a method for suppressing inrush current.

[0008] An embodiment of the present invention provides an inrush current suppression circuit, comprising: a first switch connected between an input voltage and a bus capacitor; a pre-charging branch connected in parallel with the first switch, the pre-charging branch comprising a second switch and a resistor connected in series; a third switch connected between the bus capacitor and a load, the load being connected in parallel with the bus capacitor; a control device, wherein the output end of the control device is respectively connected to the control end of the first switch, the control end of the second switch, and the control end of the third switch; the control device is used to control the second switch to be turned on and the first switch and the third switch to be turned off, so that the input voltage is charged to the bus capacitor through the pre-charging branch, and when the voltage difference between the input voltage and the bus capacitor voltage is less than or equal to a preset first voltage difference threshold, the first switch is first controlled to be turned on, and after the first switch is normally turned on, the second switch is controlled to be turned off and the third switch is controlled to be turned on in sequence.

[0009] An embodiment of the present invention further provides a method for suppressing an inrush current using the inrush current suppression circuit, comprising the following steps:

[0010] The control device controls the second switch to be turned on and controls the first switch and the third switch to be turned off, so that the input voltage charges the bus capacitor through the pre-charging branch;

[0011] The control device determines whether the voltage difference between the input voltage and the bus capacitor voltage is less than or equal to a preset first voltage difference threshold. When the voltage difference between the input voltage and the bus capacitor voltage is less than or equal to the preset first voltage difference threshold, the control device first controls the first switch to be turned on. After the first switch is normally turned on, the control device sequentially controls the second switch to be turned off and the third switch to be turned on.

[0012] Another embodiment of the present invention provides an inrush current suppression circuit, comprising: a first switch connected between an input voltage and a bus capacitor, the bus capacitor being connected in parallel with a load; a pre-charging branch connected in parallel with the first switch, the pre-charging branch comprising a second switch and a resistor connected in series; a control device, wherein the output end of the control device is respectively connected to the control end of the first switch, the control end of the second switch and the enable end of the load; the control device is used to control the second switch to be turned on and to control the first switch to be turned off and the load to be disabled, so that the input voltage is charged to the bus capacitor through the pre-charging branch, and when the voltage difference between the input voltage and the bus capacitor voltage is less than or equal to a preset first voltage difference threshold, the first switch is first controlled to be turned on, and after the first switch is normally turned on, the second switch is controlled to be turned off and the load is enabled in sequence.

[0013] Another embodiment of the present invention further provides a method for suppressing an inrush current using the inrush current suppression circuit, comprising the following steps:

[0014] The control device controls the second switch to be turned on and the first switch to be turned off and the load to be disabled, so that the input voltage is charged to the bus capacitor through the pre-charging branch;

[0015] The control device determines whether the voltage difference between the input voltage and the bus capacitor voltage is less than or equal to a preset first voltage difference threshold. When the voltage difference between the input voltage and the bus capacitor voltage is less than or equal to the preset voltage difference threshold, the control device first controls the first switch to be turned on. After the first switch is normally turned on, the control device sequentially controls the second switch to be turned off to enable the load.

[0016] After adopting the above technical solution, the present invention has at least the following advantages and characteristics:

[0017] 1. In the present invention, the load can be disconnected by controlling the third switch to open or disable it. After the second switch is turned on and the bus capacitor is charged, the voltage difference across the first switch is closer to 0V when it is turned on. Therefore, the inrush current and stress when the first switch is turned on are reduced, meeting more stringent inrush current requirements. Accordingly, low-cost, low-current, low-power semiconductor switching devices can be selected as the first switch, thereby reducing costs.

[0018] 2. Compared to existing technologies, the embodiments of the present invention allow the selection of resistors with higher resistance values ​​and lower power ratings under the same conditions. This will not significantly affect the surge current during the conduction of the first switch, while also reducing the impact current during the conduction of the second switch. Resistors with higher resistance values ​​and lower power ratings also require smaller packages, thereby reducing costs and reducing the current consumption of the bus circuit during the pre-charging phase. Accordingly, in the embodiments of the present invention, lower-cost, low-current, low-power semiconductor switching devices can also be selected as the second switch, thereby achieving a cost-reduction effect.

[0019] 3. With the embodiments of the present invention, load adjustments do not result in significant changes in the inrush current during the conduction of the first switch. This means that the embodiments of the present invention are more versatile. For example, the design solution can remain unchanged only when the load changes, thereby reducing costs in the design, testing, and production stages.

[0020] 4. During the conduction of the second switch, since the load is in an inoperative state, even if the load undergoes unexpected changes, it will not cause an increase in surge current and damage the switching device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A circuit schematic diagram of an existing inrush current suppression circuit is shown.

[0022] Figure 2 FIG. 4 shows a circuit principle diagram of an inrush current suppression circuit according to a first embodiment of the present invention.

[0023] Figure 3 A schematic diagram showing control signals sent by a control device to a first switch, a second switch, and a third switch according to a first embodiment of the present invention is shown.

[0024] Figure 4 FIG. 4 shows a circuit principle diagram of an inrush current suppression circuit according to a second embodiment of the present invention.

[0025] Figure 5 The figure shows the simulation waveforms of the bus capacitor voltage in the pre-charging stage, the inrush current when the first switch S1 is turned on, and the instantaneous power consumption when the first switch S1 is turned on of a traditional automobile chassis controller product without the third switch S3.

[0026] Figure 6 The diagram shows the simulation waveforms of the bus capacitor voltage, the inrush current when the first switch S1 is turned on, and the instantaneous power consumption when the first switch S1 is turned on of the improved automobile chassis controller product equipped with the third switch S3 in the pre-charging stage. DETAILED DESCRIPTION

[0027] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] The inventors have found in practice that the method 2 described in the "Background Technology" section of this specification has the following deficiencies:

[0029] 1. After the second switch S2 is turned on, the load 9 is also energized, generating an operating current. This causes a constant voltage drop across the resistor R1. Consequently, a certain inrush current will still exist while the first switch S1 is turned on, necessitating the use of costly, high-current, high-power semiconductor switching devices. Furthermore, with the increasing sophistication of automotive electronics design, the requirements for inrush current control will become increasingly stringent. Therefore, method 2 will eventually fail to meet the more stringent inrush current requirements in the future.

[0030] 2. In the prior art, a resistor R1 with a lower resistance and higher power rating is generally selected as much as possible. This can reduce the voltage drop across the resistor R1 to a certain extent, thereby reducing the inrush current when the first switch S1 is closed. However, a lower resistance R1 also means that the inrush current suppression effect when the second switch S2 is turned on is weakened. In addition, a smaller resistance and higher power resistor R1 means higher power consumption and a larger package, and requires the use of a high-cost, high-current, high-power semiconductor switch device as the second switch S2, which increases cost and power consumption.

[0031] 3. In different design solutions, the size of resistor R1 needs to be adjusted according to the input voltage, load 9, and inrush current design requirements. This means that more time, equipment, and manpower are required to reselect and test resistor R1 to meet the design requirements. In addition, more types of resistors R1 need to be stored and managed in the factory, resulting in a significant increase in costs.

[0032] 4. If an unexpected change occurs in the load 9 during the conduction of the second switch S2, for example, the current flowing through the load 9 is greater than the normal range due to a fault in the load 9 or a deterioration in the operating environment, the voltage on the load 9 may increase unexpectedly. That is, the surge current during the conduction of the first switch S1 may also increase unexpectedly, which may further lead to undesirable consequences, such as damage or failure of the switching device, or failure of other circuits other than the load 9.

[0033] The existing technology cannot solve the above technical problems.

[0034] Figure 2 The schematic diagram of the inrush current suppression circuit according to the first embodiment of the present invention is shown. The inrush current suppression circuit according to the first embodiment of the present invention includes a first switch S1, a pre-charging branch, a third switch S3, a first voltage detection circuit 11, a second voltage detection circuit 12 and a control device 3.

[0035] The first switch S1 is connected between the input voltage and bus capacitor C1. A pre-charge branch is connected in parallel with the first switch S1 and includes a second switch S2 and a resistor R1 connected in series. The third switch S3 is connected between bus capacitor C1 and load 9, which is connected in parallel with bus capacitor C1. The input voltage can be provided by a power supply or a voltage conversion circuit. The first switch S1 is the product's input safety switch and is typically a semiconductor power switch, such as a MOS transistor. In this embodiment, the second switch S2 and the third switch S3 also utilize semiconductor switches.

[0036] The first voltage detection circuit 11 is used to detect the magnitude of the input voltage; the second voltage detection circuit 12 is used to detect the magnitude of the voltage of the bus capacitor C1.

[0037] The input end of the control device 3 is connected to the output end of the first voltage detection circuit 11 and the output end of the second voltage detection circuit 12, respectively. The output end of the control device 3 is connected to the control end of the first switch S1, the control end of the second switch S2, and the control end of the third switch S3, respectively. The control device 3 is used to control the second switch S2 to be turned on and the first switch S1 and the third switch S3 to be turned off, so that the input voltage charges the bus capacitor C1 through the pre-charge branch, and to determine in real time whether the voltage difference between the input voltage and the voltage of the bus capacitor C1 is less than or equal to a preset voltage difference threshold. When the voltage difference between the input voltage and the voltage of the bus capacitor C1 is less than or equal to the preset voltage difference threshold, the first switch S1 is first controlled to be turned on. After the first switch S1 is normally turned on, the second switch S2 is sequentially controlled to be turned off and the third switch S3 is controlled to be turned on.

[0038] Optionally, the control device is an MCU inside the product.

[0039] The method for suppressing an inrush current by an inrush current suppression circuit according to the first embodiment of the present invention comprises the following steps:

[0040] Step a1: The control device 3 controls the second switch S2 to be turned on and controls the first switch S1 and the third switch S3 to be turned off, so that the input voltage charges the bus capacitor C1 through the pre-charging branch;

[0041] During the product's power-on phase, the first switch S1, the second switch S2, and the third switch S3 are all disconnected. When the control device 3 detects that the product meets the power-on conditions (for example, the power button is pressed, or the input voltage enters the predetermined power-on range, or the product is awakened by the network), it controls the second switch S2 to conduct. At this time, the input voltage charges the bus capacitor C1 through the pre-charging branch formed by resistor R1 and the second switch S2. The peak charging current does not exceed the input voltage / R1, so the peak current is controllable and easy to adjust. The value of resistor R1 can be pre-set based on the peak charging current to be controlled and the required charging time. During this process, the function of the third switch S3 is to disconnect the bus load 9 from the bus, making the actual load on the bus very small. After the charging process is completed, the voltage of the bus capacitor C1 is very close to the input voltage.

[0042] In step a2, the control device 3 determines whether the voltage difference between the input voltage and the voltage of the bus capacitor C1 is less than or equal to a preset first voltage difference threshold (the first voltage difference threshold is, for example, 1V). If the voltage difference between the input voltage and the bus capacitor voltage is less than or equal to the preset first voltage difference threshold, the control device 3 first controls the first switch S1 to conduct. After the first switch S1 is normally conducted, the control device 3 sequentially controls the second switch S2 to be turned off and the third switch S3 to be conducted. When the first switch S1 is controlled to conduct, since the bus capacitor voltage has already been precharged to a level very close to the input voltage, the first switch S1 does not generate a large inrush current or high stress during the conduction process. Figure 3 FIG. 1 is a schematic diagram showing control signals sent by the control device 3 to the first switch S1 , the second switch S2 and the third switch S3 according to the first embodiment of the present invention.

[0043] Furthermore, after a first preset time has passed since the control device 3 controlled the second switch S2 to be turned on and the first and third switches S1 and S3 to be turned off, if the voltage difference between the input voltage and the bus capacitor voltage is still greater than a preset first voltage difference threshold, this indicates a product defect or unsatisfactory external conditions. The control device 3 then controls the first and third switches S1 and S3 to be turned off to protect the circuit. The first preset time can be selected as 300ms. The first preset time can also be adjusted based on actual circuit parameters.

[0044] Furthermore, the control device 3 determines in real time whether the voltage difference between the input voltage and the voltage of the bus capacitor C1 is less than or equal to a preset second voltage difference threshold from the time the first switch S1 is controlled to be turned on. When the voltage difference between the input voltage and the voltage of the bus capacitor C1 is less than or equal to the preset second voltage difference threshold, the control device 3 determines that the first switch S1 is normally turned on. When the first switch S1 is normally turned on, the voltage difference between the input voltage and the voltage of the bus capacitor C1 is close to 0V. The second voltage difference threshold is less than the aforementioned first voltage difference threshold. In this embodiment, the preset second voltage difference threshold is selected to be 0.1V, and this threshold can also be adjusted based on actual circuit parameters. Alternatively, after the control device 3 controls the first switch S1 to be turned on, the control device 3 can directly determine that the first switch S1 has been normally turned on after a second preset time, for example, 100 μs, has passed. The second preset time can also be adjusted based on actual circuit parameters.

[0045] As a variation of the first embodiment, the first voltage detection circuit 11 and the second voltage detection circuit 12 may also be omitted. Accordingly, after the control device 3 controls the second switch S2 to be turned on and the first switch S1 and the third switch S3 to be turned off, and a first preset time (which can be 300 ms in this embodiment) has passed, the control device 3 directly determines that the voltage difference between the input voltage and the bus capacitor voltage is less than or equal to a preset first voltage difference threshold. The control device first controls the first switch S1 to be turned on. After the first switch S1 is normally turned on, the control device sequentially controls the second switch S2 to be turned off and the third switch S3 to be turned on. Specifically, after the control device 3 controls the first switch S1 to be turned on and a second preset time (e.g., 100 μs) has passed, the control device 3 determines that the first switch S1 is normally turned on.

[0046] Figure 4 The schematic diagram of the inrush current suppression circuit according to the second embodiment of the present invention is shown. The inrush current suppression circuit according to the second embodiment of the present invention includes a first switch S1, a pre-charging branch, a first voltage detection circuit 11, a second voltage detection circuit 12 and a control device 3.

[0047] The first switch S1 is connected between the input voltage and the bus capacitor C1, which is connected in parallel with the load 9. The pre-charging branch is connected in parallel with the first switch S1 and includes a second switch S2 and a resistor R1 connected in series.

[0048] The first voltage detection circuit 11 is used to detect the magnitude of the input voltage; the second voltage detection circuit 12 is used to detect the magnitude of the voltage of the bus capacitor C1.

[0049] The input end of the control device 3 is respectively connected to the output end of the first voltage detection circuit 11 and the output end of the second voltage detection circuit 12, and the output end of the control device 3 is respectively connected to the control end of the first switch S1, the control end of the second switch S2, and the enable end of the load 9. The control device 3 is used to control the second switch S2 to be turned on and the first switch S1 to be turned off and the load 9 to be disabled, so that the input voltage is charged to the bus capacitor C1 through the pre-charge branch, and to determine in real time whether the voltage difference between the input voltage and the voltage of the bus capacitor C1 is less than or equal to a preset voltage difference threshold. When the voltage difference between the input voltage and the voltage of the bus capacitor C1 is less than or equal to the preset voltage difference threshold, the first switch S1 is first controlled to be turned on. After the first switch S1 is normally turned on, the second switch S2 is sequentially controlled to be turned off, enabling the load 9.

[0050] The main difference between the second embodiment and the first embodiment is that the third switch S3 is eliminated, and the function of the third switch S3 is performed by the enable and disable signals sent by the control device 3. For example, some loads 9 are IC chips. They can receive the disable signal and enter a disabled state (disabled here also includes a dormant state), thereby eliminating or reducing the current consumption of the IC chip.

[0051] A method for suppressing an inrush current by an inrush current suppression circuit according to a second embodiment of the present invention includes the following steps:

[0052] Step b1: The control device 3 controls the second switch S2 to be turned on and the first switch S1 to be turned off and the load 9 to be disabled, so that the input voltage is charged to the bus capacitor C1 through the pre-charging branch;

[0053] In step b2, the control device 3 determines whether the voltage difference between the input voltage and the voltage of the bus capacitor C1 is less than or equal to a preset first voltage difference threshold. When the voltage difference between the input voltage and the voltage of the bus capacitor C1 is less than or equal to the preset first voltage difference threshold, the control device 3 first controls the first switch S1 to be turned on. After the first switch S1 is normally turned on, the control device 3 controls the second switch S2 to be turned off in turn to enable the load 9.

[0054] Furthermore, after a first preset time has passed since the control device 3 controlled the second switch S2 to be turned on, the first switch S1 to be turned off, and the load 9 to be disabled, if the voltage difference between the input voltage and the bus capacitor voltage is determined to be greater than a preset first voltage difference threshold, indicating a product defect or unsatisfactory external conditions, the control device 3 controls the first switch S1 to be turned off and the load to be disabled to protect the circuit. The first preset time can be selected as 300ms.

[0055] Furthermore, the control device 3 determines in real time whether the voltage difference between the input voltage and the voltage of the bus capacitor C1 is less than or equal to a preset second voltage difference threshold from the time the first switch S1 is controlled to be turned on. When the voltage difference between the input voltage and the voltage of the bus capacitor C1 is less than or equal to the preset second voltage difference threshold, the control device 3 determines that the first switch S1 is normally turned on. When the first switch S1 is normally turned on, the voltage difference between the input voltage and the voltage of the bus capacitor C1 is close to 0V. The second voltage difference threshold is lower than the aforementioned first voltage difference threshold. In this embodiment, the preset second voltage difference threshold is 0.1V, but this threshold can also be adjusted based on the actual circuit. Alternatively, the control device 3 can directly determine that the first switch S1 is normally turned on after a second preset time (e.g., 100 μs) has elapsed since the first switch S1 was controlled to be turned on.

[0056] As a variation of the second embodiment, the first voltage detection circuit 11 and the second voltage detection circuit 12 may also be omitted. Accordingly, after the control device 3 controls the second switch S2 to be turned on, the first switch S1 to be turned off, and the load 9 to be disabled, and a first preset time (which can be 300 ms in this embodiment) has elapsed, the control device 3 directly determines that the voltage difference between the input voltage and the bus capacitor voltage is less than or equal to a preset first voltage difference threshold. The control device first controls the first switch S1 to be turned on. After the first switch S1 is normally turned on, the control device 3 sequentially controls the second switch S2 to be turned off and the load 9 to be enabled. Specifically, after the control device 3 controls the first switch S1 to be turned on, and a second preset time (e.g., 100 μs) has elapsed, the control device 3 determines that the first switch S1 is normally turned on. The operating principle of the present invention is described below with reference to a specific application embodiment.

[0057] The chassis controller's input voltage (supply voltage) is 13.5V, the busbar capacitance is 710uF, and a 100ohm resistor is used for precharging. The current provided by the input power supply through the 100ohm resistor is sufficient to operate the sensor interface chip (i.e., load 9) on the busbar normally. Without the third switch S3, the busbar load current during the precharging phase is 30mA. After the third switch S3 is set and opened, allowing the sensor interface chip to enter standby mode, the busbar load current drops to below 4mA.

[0058] Figure 5 Simulated waveforms show the bus capacitor voltage, inrush current, and instantaneous power consumption during the pre-charge phase of a conventional chassis controller without the third switch S3. Without the third switch S3, the bus capacitor voltage can only pre-charge to 10V 300ms after the second switch S2 is turned on. During the on-state of the first switch S1, the bus capacitor voltage charges to a final value of 13.5V. During this process, the maximum inrush current is 21A, and the energy loss in the first switch S1 is 1.8mJ.

[0059] Figure 6 The simulation waveforms show the bus capacitor voltage, inrush current when the first switch S1 is turned on, and instantaneous power consumption during the pre-charge phase of an improved chassis controller equipped with a third switch S3. With the third switch S3 installed, the bus capacitor voltage can be pre-charged to 12.6V 300ms after the second switch S2 is turned on. During the on-state of the first switch S1, the bus capacitor voltage charges to a final value of 13.5V. During this process, the maximum inrush current is only 7A, and the energy loss in the first switch S1 is 0.1mJ.

[0060] The inrush current suppression circuit of the embodiment of the present invention can effectively control the charging current and time. In addition, most of the energy loss during the charging process is concentrated inside the resistor, which reduces the pressure on the semiconductor switch. Therefore, low-cost, low-current, low-power semiconductor switches can be used as the first switch and the second switch, reducing costs.

[0061] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A surge current suppression circuit, characterized in that: include; A first switch is connected between the input voltage and the bus capacitor; a pre-charging branch connected in parallel with the first switch, the pre-charging branch comprising a second switch and a resistor connected in series; a third switch connected between the bus capacitor and a load, wherein the load is connected in parallel with the bus capacitor; a control device, wherein the output end of the control device is respectively connected to the control end of the first switch, the control end of the second switch, and the control end of the third switch; the control device is used to control the second switch to be turned on and the first switch and the third switch to be turned off, so that the input voltage charges the bus capacitor through the pre-charging branch, and when the voltage difference between the input voltage and the bus capacitor voltage is less than or equal to a preset first voltage difference threshold, the first switch is first controlled to be turned on, and after the first switch is normally turned on, the second switch is sequentially controlled to be turned off and the third switch is controlled to be turned on.

2. The inrush current suppression circuit according to claim 1, wherein: The control device is used to determine that the voltage difference between the input voltage and the bus capacitor voltage is less than or equal to a preset first voltage difference threshold after a first preset time has passed since the second switch is controlled to be turned on and the first switch and the third switch are controlled to be turned off.

3. The inrush current suppression circuit according to claim 1, wherein: Also includes: A first voltage detection circuit, configured to detect the magnitude of the input voltage; A second voltage detection circuit is used to detect the voltage of the bus capacitor; The input end of the control device is connected to the output end of the first voltage detection circuit and the output end of the second voltage detection circuit respectively; the control device is used to determine in real time whether the voltage difference between the input voltage and the bus capacitor voltage is less than or equal to a preset first voltage difference threshold.

4. The inrush current suppression circuit according to claim 3, wherein: The control device is used to control the first switch and the third switch to be disconnected, and if it is determined that the voltage difference between the input voltage and the bus capacitor voltage is greater than a preset first voltage difference threshold after a first preset time has passed since the second switch is controlled to be turned on and the first switch and the third switch are controlled to be disconnected, then the first switch and the third switch are controlled to be disconnected.

5. The inrush current suppression circuit according to claim 3, wherein: The control device is used to determine in real time whether the voltage difference between the input voltage and the voltage of the bus capacitor is less than or equal to a preset second voltage difference threshold from the time the first switch is controlled to be turned on. When the voltage difference between the input voltage and the bus capacitor voltage is less than or equal to the preset second voltage difference threshold, it is determined that the first switch has been normally turned on and the second voltage difference threshold is less than the first voltage difference threshold.

6. The inrush current suppression circuit according to claim 2 or 3, characterized in that: The control device is used to determine that the first switch has been normally turned on after a second preset time has passed since the first switch is controlled to be turned on.

7. A method for suppressing an inrush current using an inrush current suppression circuit as claimed in claim 1, characterized in that: The following steps are involved: The control device controls the second switch to be turned on and controls the first switch and the third switch to be turned off, so that the input voltage charges the bus capacitor through the pre-charging branch; The control device determines whether the voltage difference between the input voltage and the bus capacitor voltage is less than or equal to a preset first voltage difference threshold. When the voltage difference between the input voltage and the bus capacitor voltage is less than or equal to the preset first voltage difference threshold, the control device first controls the first switch to be turned on. After the first switch is normally turned on, the control device sequentially controls the second switch to be turned off and the third switch to be turned on.

8. A surge current suppression circuit, characterized in that: include: A first switch is connected between the input voltage and a bus capacitor, wherein the bus capacitor is connected in parallel with the load; a pre-charging branch connected in parallel with the first switch, the pre-charging branch comprising a second switch and a resistor connected in series; A control device, wherein the output end of the control device is respectively connected to the control end of the first switch, the control end of the second switch, and the enable end of the load; the control device is used to control the second switch to be turned on and the first switch to be turned off and the load to be disabled, so that the input voltage charges the bus capacitor through the pre-charging branch, and when the voltage difference between the input voltage and the bus capacitor voltage is less than or equal to a preset first voltage difference threshold, the first switch is first controlled to be turned on, and after the first switch is normally turned on, the second switch is sequentially controlled to be turned off and the load is enabled.

9. The inrush current suppression circuit according to claim 8, wherein: The control device is used to determine that the voltage difference between the input voltage and the bus capacitor voltage is less than or equal to a preset first voltage difference threshold after a first preset time has passed since the second switch is controlled to be turned on and the first switch is controlled to be turned off and the load is disabled.

10. The inrush current suppression circuit according to claim 8, wherein: Also includes: A first voltage detection circuit, configured to detect the magnitude of the input voltage; A second voltage detection circuit is used to detect the voltage of the bus capacitor; The input end of the control device is connected to the output end of the first voltage detection circuit and the output end of the second voltage detection circuit respectively; the control device is used to determine in real time whether the voltage difference between the input voltage and the bus capacitor voltage is less than or equal to a preset first voltage difference threshold.

11. The inrush current suppression circuit according to claim 10, wherein: The control device is used to control the first switch to be disconnected and the load to be disabled, if it is determined that the voltage difference between the input voltage and the bus capacitor voltage is greater than a preset first voltage difference threshold after a first preset time has passed since the second switch is controlled to be turned on and the first switch is controlled to be disconnected and the load is disabled.

12. The inrush current suppression circuit according to claim 10, wherein: The control device is used to determine in real time whether the voltage difference between the input voltage and the voltage of the bus capacitor is less than or equal to a preset second voltage difference threshold from the time the first switch is controlled to be turned on. When the voltage difference between the input voltage and the bus capacitor voltage is less than or equal to the preset second voltage difference threshold, it is determined that the first switch has been normally turned on and the second voltage difference threshold is less than the first voltage difference threshold.

13. The inrush current suppression circuit according to claim 9 or 10, characterized in that: The control device is used to determine that the first switch has been normally turned on after a second preset time has passed since the first switch is controlled to be turned on.

14. The method for suppressing an inrush current by an inrush current suppression circuit according to claim 8, wherein: The following steps are involved: The control device controls the second switch to be turned on and the first switch to be turned off and the load to be disabled, so that the input voltage is charged to the bus capacitor through the pre-charging branch; The control device determines whether the voltage difference between the input voltage and the bus capacitor voltage is less than or equal to a preset first voltage difference threshold. When the voltage difference between the input voltage and the bus capacitor voltage is less than or equal to the preset first voltage difference threshold, the control device first controls the first switch to be turned on. After the first switch is normally turned on, the control device sequentially controls the second switch to be turned off to enable the load.

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