Docking contact structure

Abstract

An abutment contact structure is provided. In one embodiment, the structure includes a first transistor on a substrate, the first transistor including a first source or drain region, a first gate, and a first gate spacer disposed between the first gate and the first source or drain region. The structure includes a second transistor on the substrate, the second transistor including a second source or drain region, a second gate, and a second gate spacer disposed between the second gate and the second source or drain region. The structure includes an abutment contact disposed over the first source or drain region and extending from the first source or drain region to at least one of the first gate or the second gate, a portion of the first gate spacer extending a distance into the abutment contact to separate a first bottom surface of the abutment contact from a second bottom surface of the abutment contact.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to semiconductor structures and methods of manufacturing the same, and particularly to abutment contact structures and methods of manufacturing the same. BACKGROUND

[0002] Contacts are generally vertical metal interconnect structures formed in integrated circuits that connect various elements of semiconductor devices, such as active regions and gate electrodes, with interconnect metal layers. Various semiconductor devices formed in a semiconductor substrate are electrically coupled to one another through contacts to form a functional integrated circuit. As the semiconductor industry has progressed to nanotechnology process nodes, such as a 5 nanometer node, new challenges have arisen in pursuit of higher device densities. Accordingly, improved contact structures and methods are needed. SUMMARY

[0003] According to an embodiment of the present disclosure, an abutment contact structure is provided, comprising: a first transistor on a substrate, the first transistor comprising a first source or drain region, a first gate, and a first gate spacer disposed between the first gate and the first source or drain region; a second transistor on the substrate, the second transistor comprising a second source or drain region, a second gate, and a second gate spacer disposed between the second gate and the second source or drain region; and an abutment contact disposed over the first source or drain region and extending from the first source or drain region to at least one of the first gate or the second gate, a portion of the first gate spacer extending a distance into the abutment contact to separate a first bottom surface of the abutment contact from a second bottom surface of the abutment contact.

[0004] According to another embodiment of the present disclosure, an abutment contact structure is provided, comprising: a first transistor on a substrate, the first transistor comprising a source or drain region; a conductive feature contacting the source or drain region; a gate electrode of a gate structure of a second transistor on the substrate; an abutment contact comprising (i) a first surface contacting the gate electrode, (ii) a second surface contacting the conductive feature, (iii) a third surface extending from the first surface at a first angle, and (iv) a fourth surface extending from the second surface at a second angle, the third surface intersecting the fourth surface at a third angle; and a gate spacer disposed between the source or drain region and the gate structure, a portion of the gate spacer disposed laterally between the third surface and the fourth surface.

[0005] According to another embodiment of the present application, a method for fabricating a semiconductor device is provided. The method includes forming a source or drain region on a substrate, the source or drain region having a conductive feature formed thereon; forming a gate on the substrate, the gate having a first dielectric layer formed thereon; forming a gate spacer on a side of the gate; depositing a second dielectric layer on the conductive feature, the first dielectric layer, and the gate spacer, the second dielectric layer being different from the first dielectric layer; depositing a first masking layer on the second dielectric layer; depositing a second masking layer on the first masking layer; etching a first contact opening through the second masking layer, the first masking layer, the second dielectric layer, and the first dielectric layer to expose the gate, the etching of the first contact opening including etching the second masking layer using a first etch recipe, etching the first masking layer using a second etch recipe, etching the second dielectric layer using a third etch recipe, and etching the first dielectric layer using a fourth etch recipe, the first, second, third, and fourth etch recipes being different from one another; etching a second contact opening through the second masking layer, the first masking layer, and the second dielectric layer to expose the conductive feature, the etching of the second contact opening including etching the second masking layer using the first etch recipe, etching the first masking layer using the second etch recipe, and etching the second dielectric layer using the third etch recipe, the first contact opening and the second contact opening being connected at the gate spacer, and the first etch recipe and the second etch recipe shaping a portion of the gate spacer into a tapered profile; and filling the first contact opening and the second contact opening with a conductive material. BRIEF DESCRIPTION OF DRAWINGS

[0006] The details of one or more embodiments of the application are set forth in the accompanying detailed description below, and in part will be apparent to those skilled in the art from the description, or can be learned by practice of the application. It is to be understood that both the foregoing general description and the following detailed description are examples and provided for the purpose of assisting in understanding the application but are not intended to limit the application.

[0007] Figure 1A A portion of the circuitry shown is depicted as a top-down schematic view of an integrated circuit layout.

[0008] Figure 1B Corresponding Figure 1A A portion of the circuitry shown depicts a top-down schematic view of an integrated circuit layout.

[0009] Figure 2 A portion of the circuitry shown is depicted as a top-down schematic view of an integrated circuit layout. Figure 1A A portion of the circuitry shown depicts a top-down schematic view of an integrated circuit layout.

[0010] Figures 3 to 16 、 Figure 17A and Figure 17B are cross-sectional schematic views of a portion of a semiconductor device corresponding to various stages of fabrication, according to some embodiments.

[0011] Figure 18 A portion of the cross-sectional schematic view according to some embodiments is depicted Figure 17A to further illustrate additional details.

[0012] Wherein the reference numerals are explained as follows:

[0013] 100 - Static random access memory cell

[0014] 101, 106, 121, 152, 153 - Gate

[0015] 104, 115, 292 - Source / Drain region

[0016] 110, 120 - Pass gate transistor

[0017] 112, 116, 114, 118 - Transistor

[0018] 140 - First inverter

[0019] 142 - Second inverter

[0020] 150 - Integrated circuit layout

[0021] 154, 155 - Active region

[0022] 156, 157 - Drain region

[0023] 158, 159 - Docking contact

[0024] 158A, 158B, 159A, 159B, 277, 291 - Pattern

[0025] 160, 162 - Contact

[0026] 160A, 162A - Contact pattern

[0027] 201 - First transistor region

[0028] 203 - Second transistor region

[0029] 214 - Silicide region

[0030] 215, 223, 1702, 1704 - Bottom

[0031] 220 - Interfacial dielectric

[0032] 222 - Gate dielectric layer

[0033] 224 - Conformal layer

[0034] 225, 1814, 1816 - Sidewall

[0035] 226 ~ gate conductive fill material

[0036] 227 ~ conductive fill

[0037] 228a, 228b ~ replacement gate structure

[0038] 229, 234, 236, 1801 ~ top surface

[0039] 231 ~ first self-aligned contact

[0040] 233 ~ second self-aligned contact

[0041] 235, 237 ~ hardmask layer

[0042] 238 ~ landing contact opening

[0043] 239, 261 ~ three-layer (hardmask) structure

[0044] 240 ~ semiconductor device

[0045] 241, 263 ~ bottom layer

[0046] 243, 265 ~ middle layer

[0047] 245, 267 ~ top layer

[0048] 246 ~ conductive material

[0049] 247 ~ first opening

[0050] 248 ~ recess

[0051] 249 ~ first mask

[0052] 250 ~ protective liner

[0053] 251 ~ gate structure

[0054] 253 ~ trench

[0055] 255 ~ first pattern

[0056] 257 ~ radiation beam

[0057] 259 ~ first contact opening

[0058] 269 ~ second mask

[0059] 270 ~ substrate

[0060] 271 ~ second pattern

[0061] 273 ~ second opening

[0062] 274 ~ fin

[0063] 275, 289 - inset

[0064] 278 - isolation region

[0065] 279a, 279b, 279c, 279d, 293a, 293b, 293c, 293d - component

[0066] 280 - interfacial dielectric

[0067] 281 - second contact opening

[0068] 282 - dummy gate

[0069] 284 - mask

[0070] 286 - gate spacer

[0071] 286' - tapered top

[0072] 297 - first interlayer dielectric

[0073] 1800 - butt contact structure

[0074] 1802 - left V-shaped portion

[0075] 1804 - right V-shaped portion

[0076] 1818 - first sidewall

[0077] 1820 - second sidewall

[0078] A, B, E, F, G - angle

[0079] A-A - cross-section

[0080] BL - bit line

[0081] BLB - complementary bit line

[0082] D1, D2, D3, D4, D5, D6 - dimension

[0083] WL - word line DETAILED DESCRIPTION

[0084] The following detailed description is provided to provide a better understanding of the present embodiments, and should not be taken as a sole basis for interpreting the scope of the present embodiments. Embodiments merely typify examples of the present embodiments. Unless otherwise specified, definitions herein will be applied regardless of whether a method, system or architecture is in question. The detailed description includes specific details for the purpose of providing a thorough understanding of the present embodiments. However, it will be apparent to those skilled in the art that the present embodiments can be practiced without these specific details. In some instances, well-known structures and functions have not been described in detail in order to avoid obscuring the concepts of the present embodiments. In the description of the present embodiments, same reference numerals can be used throughout the different figures to denote the same or similar components.

[0085] In addition, where spatially relative terms are used, such as "beneath", "below", "lower", "above", "upper", and the like, they are used for ease of describing the conceptual merits of the present embodiments to the figures. It will be further understood that the spatially relative terms are intended to encompass different orientations of the device in use or step in addition to the orientations depicted in the figures. The devices depicted in the figures are intended only as examples and are not intended to limit the scope of the present embodiments. As will be understood by those of ordinary skill in the art, the spatially relative terms are intended to encompass different orientations of the device in use or step in addition to the orientations depicted in the figures.

[0086] The various embodiments described below provide methods for forming a shared contact structure that enables a source or drain region of a transistor to be connected to a gate of the same or another transistor on a substrate without the use of a horizontal metal interconnect layer. A tapered gate spacer is disposed laterally between the source or drain region and the gate. The tapered gate spacer extends between angled sidewalls inside the shared contact structure to a bottom of the shared contact structure. The tapered gate spacer and the angled sidewalls can ensure good metal fill capability so that a subsequently deposited metal fill has no voids or seams. The shared contact structure can be formed by a double patterning process using two separate photomasks, each having a portion of a pattern corresponding to the shared contact structure.

[0087] Some aspects of embodiments of the application are broadly summarized above. Concepts consistent with embodiments of the application can be employed in planar transistor devices or in three-dimensional transistor devices, such as the semiconductor device 240 described in embodiments of the application. Some example devices that can implement aspects described herein include fin field effect transistors (FinFETs), horizontal gate all around (HGAA) field effect transistors, vertical gate all around (VGAA) field effect transistors, nanowire channel field effect transistors, strained semiconductor devices, silicon-on-insulator (SOI) devices, or other devices that can benefit from aspects of embodiments of the application.

[0088] Figure 1A An example of an illustrative circuit diagram of a 6T (6 transistor) static random access memory (SRAM) cell 100 is shown in accordance with some embodiments. The 6T static random access memory cell 100 includes a first inverter 140 cross-coupled with a second inverter 142. The first inverter 140 includes a pull-up transistor 112 and a pull-down transistor 114. The second inverter 142 includes a pull-up transistor 116 and a pull-down transistor 118. The static random access memory cell 100 also includes pass gate transistors 110, 120. Gates (e.g., gate 101) of the pass gate transistors 110, 120 are coupled with and controlled by a word line WL, and sources / drain of the pass gate transistors 110, 120 are coupled with bit line BL and complementary bit line BLB, respectively.

[0089] Shared contacts or so-called butted contacts can be used for various connections in the circuit diagram shown. For example, the connection between the source / drain region 104 of the pull-up transistor 112 and the gate 106 of the pull-up and pull-down transistors 116 and 118, and the connection between the source / drain region 115 of the pull-up transistor 116 and the gate 121 of the pull-up and pull-down transistors 112 and 114. Other connections can be formed by butted contacts. Figure 1A

[0090] Figure 1B Corresponding Figure 1A ​A portion of the static random access memory cell 100 is shown to illustrate a top view schematic of an integrated circuit (IC) layout 150. The integrated circuit layout 150 includes two pull-up transistors 112 and 116. For clarity, the pull-up transistor 112 is represented by a component having a dashed line, while the pull-up transistor 116 is represented by a component having a solid line. The pull-up transistor 112 includes a gate 152 formed over a portion of an active region 154, while the pull-up transistor 116 includes a gate 153 formed over a portion of an active region 155. The gates 152 and 153 can include a metal-containing substance, as described below. Each pull-up transistor (112, 116) includes a drain region 156, 157, respectively, within the active regions 154 and 155. A landing contact 158, 159 can extend along a length from a first end to a second end. For example, a first end of the landing contact 158 can contact the gate 152, which corresponds to the pull-up transistor 112 within a first inverter (e.g., the first inverter 140 of Figure 1A Figure 1A The second end of the landing contact 158 contacts the drain region 157, which corresponds to the pull-up transistor 116 within a second inverter (e.g., the second inverter 142 of Figure 1A Thus, the landing contact connects the gate of a transistor within one inverter to the source / drain of a transistor within a cross-coupled inverter, as shown by the static random access memory cell 100. The integrated circuit layout 150 also includes contacts 160 and 162. The contacts 160 and 162 can be any suitable internal connections or contact components desired in the semiconductor device 240. For example, the contacts 160 and 162 can be disposed on the active regions 154, 155, respectively, and can be configured to provide a voltage Vcc to the source terminals of the pull-up transistors 112 and 116, respectively.

[0091] It is contemplated that Figure 1B The depicted transistors and contact components are for illustrative purposes and should not be considered limiting. The configuration and / or number of transistors and contact components can vary depending on the application. Other applications of common or landing contacts include other memory applications, power devices, and any other semiconductor in which adjacent elements can be electrically connected at the transistor level. For example, while embodiments of the present invention discuss gate-to-drain landing contacts, other landing contacts are contemplated, such as source-to-drain of adjacent transistors, gate-to-source of adjacent transistors, source-to-body, drain-to-body, and other landing contacts.

[0092] Some embodiments employ multiple patterning techniques to form mating contacts, such as dual patterning processes. For example, a rectangular pattern corresponding to the mating contact (e.g., Figure 1B The mating contact 158 ​​can be split or divided into two square patterns 158A and 158B. Then, the two square patterns 158A and 158B are recombinated using two separate photomasks in successive lithography and etching steps to form a rectangular mating contact 158, which will be transferred to the film layer of the device. Because the square patterns 158A and 158B are transferred to the film layer of the device through two separate lithography processes, appropriate critical dimensional uniformity can be obtained. By dividing the layout into two different photomasks, the minimum line spacing in the combined pattern can be reduced while maintaining good resolution. In some embodiments, each photomask may also contain a pattern of the nominal contact to be transferred to the substrate to ensure a minimum number of photomasks are involved. For example, a first photomask may include a square pattern 158A for mating contacts 158, a square pattern 159A for mating contacts 159, and a contact pattern 162A to be formed on the active region 155, while a second photomask may include a square pattern 158B for mating contacts 158, a square pattern 159B for mating contacts 159, and a contact pattern 160A to be formed on the active region 154. Various embodiments for forming mating contacts will be discussed in more detail below.

[0093] Figure 2 It shows that it can be used to form Figure 1Asemiconductor device 240 has a fin 274 formed on a semiconductor base 270. Semiconductor base 270 can be or include a bulk semiconductor base, a semiconductor-on-insulator (SOI) base, or a similar base, which can be doped (e.g., with p-type or n-type dopants) or undoped. In some embodiments, the semiconductor material of semiconductor base 270 can include an elemental semiconductor including silicon (Si) or germanium (Ge); a compound semiconductor; an alloy semiconductor; or combinations of the foregoing. Fin 274 provides an active region for one or more transistors of static random access memory cell 100. Fabrication of fin 274 can be by suitable processes performed on semiconductor base 270, including masking, lithography, and / or etching processes, to form a trench 253 in base 270, leaving fin 274 extending upward from base 270. Trench 253 can then be filled with an insulating material, such as an oxide (e.g., silicon oxide), nitride, similar material, or combinations of the foregoing. The insulating material can be recessed to form isolation regions 278, such as by using a suitable etching process. Recessing the insulating material leaves fin 274 protruding between and above adjacent isolation regions 278.

[0094] Semiconductor device 240 has gate structures 251 formed over a top surface of fin 274. As described herein, gate structures 251 are in place of dummy gate stacks in a replacement gate process, although other examples contemplate implementing a gate-first process. Gate structures 251 are positioned over and extend perpendicular to fin 274. Each gate structure 251 includes an interface dielectric 280, a dummy gate 282 over interface dielectric 280, and a capping layer 284 over dummy gate 282, as described herein. Figure 2The various film layers for the interface dielectric 280, dummy gate 282, and mask 284 of the gate structure 251 can be formed in sequence, and then patterned to form the gate structure 251. For example, the interface dielectric 280 can include or be silicon oxide, silicon nitride, similar materials, or multilayer structures of the foregoing. The dummy gate 282 can include or be silicon (e.g., polysilicon) or other materials. The mask 284 can include or be silicon nitride, silicon oxynitride, silicon carbonitride, similar materials, or combinations of the foregoing. The film layers can be formed or deposited by any suitable deposition technique. The film layers for the interface dielectric 280, dummy gate 282, and mask 284 can then be patterned using, for example, lithography and one or more etch processes to form the interface dielectric 280, dummy gate 282, and mask 284 for each gate structure 251.

[0095] The semiconductor device 240 also includes source / drain regions 292 disposed in opposing regions of the fin 274 relative to the gate structure 251. The source / drain regions 292 and one of the gate structures 251 (or a corresponding replacement gate structure formed subsequently) define at least a first transistor in the first transistor region 201. The expression "source / drain" as used in the context of embodiments of the present application is used to refer to either a source or a drain region of a transistor (e.g., the first transistor in the first transistor region 201). The first transistor in the first transistor region 201 can be, for example, a pull-up transistor, such as the pull-up transistor 112 of Figure 1B The other gate structures 251 (or corresponding replacement gate structures formed subsequently) are part of a second transistor in the second transistor region 203, and the second transistor can be, for example, a pull-up transistor, such as the pull-up transistor 116 of Figure 1B Figure 2 The reference cross-sections used in the subsequent figures are shown. The cross-section A-A is in a plane along, for example, a channel in the fin 274 between opposing source / drain regions 292. For clarity, the subsequent figures refer to this reference cross-section.

[0096] Figure 3 ​Gate spacers 286 are shown formed over the sidewalls of the gate structures 251 (e.g., sidewalls of the interface dielectric 280, dummy gates 282, and the mask 284) and the fins 274. For example, the gate spacers 286 can be formed by conformally depositing one or more film layers for the gate spacers 286 and etching the one or more film layers anisotropically. The material(s) of the one or more film layers for the gate spacers 286 can be different than the material(s) used for the gate structures 251. In some embodiments, the gate spacers 286 can include or be a dielectric material, such as silicon oxycarbide, silicon nitride, silicon oxynitride, silicon carbonitride, similar materials, a multilayer structure of the foregoing, or a combination of the foregoing, and can be deposited by any suitable deposition technique. An anisotropic etch process is then performed to remove portions of the spacer layer to form the gate spacers 286.

[0097] Figure 4 Epitaxial source / drain regions 292 are shown formed in recesses in the fins 274. The recesses are formed in the fins 274 on opposite sides of the gate structures 251. The recessing can be performed by an etch process. The etch process can be isotropic or anisotropic, or further, can be selective to one or more crystalline planes of the substrate 270. Thus, the recesses can have various profile shapes depending on the etch process performed.

[0098] The epitaxial source / drain regions 292 are epitaxially grown in the recesses. The material of the epitaxial source / drain regions 292 can be selected to include or be silicon germanium, silicon carbide, silicon phosphorous, silicon carbon phosphorous, germanium, a Group III-V compound semiconductor, a Group II-VI compound semiconductor, or similar materials depending on the conductivity type of the transistors. The epitaxial source / drain regions 292 can be raised relative to the fins 274 and can have facets that can correspond to the crystalline planes of the semiconductor substrate 270 and the orientation of the crystalline planes of the fins 274 relative to the substrate. In some examples, the epitaxial source / drain regions 292 can also be doped, such as by in situ doping during epitaxial growth and / or implanting dopants into the epitaxial source / drain regions 292 after epitaxial growth.

[0099] Figure 5Formation of a first interlayer dielectric (ILD) 297 is shown, as well as subsequent planarization thereof. The first interlayer dielectric 297 is formed over the surfaces of the source / drain regions 292 exposed by the removal of the gate stack, the sidewalls and top surfaces of the gate spacers 286, the top surface of the mask 284, and the top surface of the isolation regions 278, using any suitable deposition technique. An optional contact etch stop layer (CESL) (not shown) can be deposited between the first interlayer dielectric 297 and the surfaces of the source / drain regions 292 and the sidewalls of the gate spacers 286. The first interlayer dielectric 297 can comprise or be tetraethylorthosilicate (TEOS) oxide, silicon dioxide, a low-k dielectric material (e.g., a material having a dielectric constant lower than that of silicon dioxide), or the like. The contact etch stop layer can comprise or be silicon nitride, silicon carbon nitride, carbon nitride, the like, or combinations of the foregoing. Subsequently, a planarization process, such as chemical mechanical planarization (CMP), can remove the first interlayer dielectric 297 until the top surface of the dummy gate 282 is exposed, which process can also remove the mask 284.

[0100] Figure 6 Removal of the remaining gate structures 251 and formation of replacement gate structures 228a, 228b is shown. One or more etch processes are used to remove the gate structures 251. After removal of the gate structures 251, recesses are formed between the gate spacers 286 where the gate stacks were removed, and the channel regions of the fins 274 are exposed through the recesses. Subsequently, replacement gate structures 228a, 228b are formed in the recesses where the gate structures 251 were removed. Each replacement gate structure 228a, 228b can comprise an interface dielectric 220, a gate dielectric layer 222, one or more optional conformal layers 224, and a gate conductive fill material 226. The thickness of the replacement gate structures 228a, 228b can be between about 8 nm and about 25 nm, such as between about 12 nm and about 20 nm.

[0101] The interface dielectric 220 is formed on the top surfaces of the fins 274 along the channel regions. The interface dielectric 220 can be an oxide (e.g., silicon oxide) formed by thermal or chemical oxidation of the fins 274.

[0102] The gate dielectric layer 222 can be conformally deposited in the recesses created by removal of the gate stack (e.g., on the interface dielectric 220 and on the sidewalls of the gate spacers 286) as well as on the top surfaces of the first ILD 297 and the gate spacers 286. The gate dielectric layer 222 can be or include silicon oxide, silicon nitride, a high-k dielectric material, a multilayer structure of the foregoing, or other dielectric material. The high-k dielectric material can have a dielectric constant value greater than about 7.0 and can include a metal oxide or metal silicate of hafnium (Hf), aluminum (Al), zirconium (Zr), lanthanum (La), magnesium (Mg), barium (Ba), titanium (Ti), lead (Pb), a multilayer structure of the foregoing, or a combination of the foregoing.

[0103] One or more optional conformal layers 224 can be conformally deposited on the gate dielectric layer 222. The one or more optional conformal layers 224 can include one or more barrier and / or capping layers as well as one or more work-function tuning layers. The one or more barrier and / or capping layers can include tantalum nitride, titanium nitride, similar materials, or combinations of the foregoing. The one or more work-function tuning layers can include or be titanium aluminum carbide, aluminum titanium oxide, aluminum titanium nitride, similar materials, or combinations of the foregoing. The materials used for the one or more work-function tuning layers, barrier layers, and / or capping layers can be selected to achieve a desired threshold voltage (Vt) for a transistor, which can be a p-type field effect transistor (pFET) or an n-type field effect transistor (nFET). A gate conductive fill material 226 is formed on the one or more conformal layers 224 (if implemented) and / or the gate dielectric layer 222. The gate conductive fill material 226 can fill the recesses left by removal of the gate stack. The gate conductive fill material 226 can be or include a metal-containing material such as tungsten, cobalt, aluminum, ruthenium, copper, a multilayer structure of the foregoing, a combination of the foregoing, or similar materials.

[0104] A planarization process such as chemical mechanical planarization can remove portions of the film layer for the gate conductive fill material 226, the one or more conformal layers 224, and the gate dielectric layer 222 that are above the top surfaces of the first ILD 297 and the gate spacers 286. Thus, a replacement gate structure 228a, 228b including the gate conductive fill material 226, the one or more conformal layers 224, the gate dielectric layer 222, and the interface dielectric 220 can be formed as shown. Figure 6

[0105] Figure 7 ​First self-aligned contacts (SACs) 231 are shown formed on each replacement gate structure 228a, 228b, and conductive features are formed to the epitaxial source / drain regions 292. After forming the replacement gate structures 228a, 228b, portions of the replacement gate structures 228a, 228b, such as the gate dielectric layer 222, one or more conformal layers 224, and a top portion of the gate conductive fill material 226, are removed using one or more etch processes. After removing the top portions of the replacement gate structures 228a, 228b, recesses are formed between the gate spacers 286. Then, individual first self-aligned contacts 231 are formed in the recesses where the top portions of the gate dielectric layer 222, one or more conformal layers 224, and gate conductive fill material 226 were removed. The first self-aligned contacts 231 protect the replacement gate structures 228a, 228b during subsequent opening formation configured to accommodate subsequent contact formation for electrically connecting the source / drain regions 292, respectively. The first self-aligned contacts 231 can include or be an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, any suitable dielectric material, or any combination of the foregoing. In some embodiments, the first self-aligned contacts 231 are silicon oxycarbonitride. The first self-aligned contacts 231 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), any suitable deposition technique, or a combination of the foregoing, and subsequent planarization, such as chemical mechanical planarization.

[0106] After forming the first self-aligned contact 231, a source / drain contact opening is formed through the first interlayer dielectric 297 to the source / drain region 292 to expose at least a portion of the source / drain region 292. Next, a conductive feature is formed in the source / drain contact opening. The conductive feature can include a silicide region 214 formed on the source / drain region 292 and a conductive material 246 formed on the silicide region 214. The first interlayer dielectric 297 can be patterned using an opening, for example, using lithography and one or more etching processes, such as dry etching or any suitable anisotropic etching process. Although not shown, each conductive material 246 can include, for example, an adhesion layer conformally deposited in the source / drain contact opening and on the top surface of the first interlayer dielectric 297, a barrier layer conformally deposited on the adhesion layer, and a conductive fill material deposited on the barrier layer. The silicide region 214 can be formed by thermally reacting an upper portion of the source / drain region 292 with the adhesion layer, which can be titanium, tantalum, or similar material. The barrier layer can be or include titanium nitride, titanium oxide, tantalum nitride, tantalum oxide, any suitable transition metal nitride or oxide, similar material, or any combination of the foregoing. The conductive fill material can be or include cobalt, tungsten, copper, ruthenium, aluminum, gold, silver, alloys of the foregoing, similar material, or combinations of the foregoing. After depositing the conductive fill material, excess conductive fill material, barrier layer, and adhesion layer can be removed by using a planarization process, such as chemical mechanical planarization. Thus, the conductive material 246 and the top surface of the first interlayer dielectric 297 can be coplanar.

[0107] Figure 8 An etch back of the conductive material 246 is shown, thereby forming a recess 248. The etch back can include using one or more etching processes that are selective to the conductive material 246. The formation of the recess 248 causes the top surface of the conductive material 246 to be lower than the top surfaces of the first interlayer dielectric 297, the first self-aligned contact 231, and the gate spacers 286.

[0108] Figure 9 Formation of a protective liner 250 is shown. After forming the recess 248, the protective liner 250 is conformally deposited in the recess 248 (e.g., on the exposed surfaces of the first interlayer dielectric 297 and the conductive material 246) and on the top surfaces of the first interlayer dielectric 297, the first self-aligned contact 231, and the gate spacers 286. The protective liner 250 can prevent the underlying device features from being damaged during etching of the contact opening. In some embodiments, the protective liner 250 can be formed of a material that has a relatively high etch selectivity (compared to the gate spacers 286). For example, the protective liner 250 can be a dielectric, which can include or be aluminum oxide (AI2O3), aluminum oxynitride (AION), aluminum nitride (AIN), titanium oxide (TiO2), titanium oxynitride (T1ON), tantalum oxide (Ta2O5), tantalum oxynitride (TaON), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), zirconium oxynitride (ZrON), silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (Si3N4), silicon carbide (SiC), silicon carbonitride (SiCN), silicon carbonoxynitride (SiCON), silicon carbonoxycarbonitride (SiCONN), silicon carbonoxycarbonoxynitride (SiCONN), silicon carbonoxycarbonoxycarbonitride (SiCONN), silicon carbonoxycarbonoxycarbonoxynitride (SiCONN), silicon carbonoxycarbonoxycarbonoxycarbonitride (SiCONN), silicon carbonoxycarbonoxycarbonoxycarbonoxynitride (SiCONN), silicon carbonoxycarbonoxycarbonoxycarbonoxycarbonitride (SiCONN), silicon carbonoxycarbonoxycarbonoxycarbonoxycarbonoxynitride (SiCONN), silicon carbonoxycarbonoxycarbonoxycarbonoxycarbonoxycarbonitride (SiCONN), or any combination of the foregoing. x x ​), titanium oxynitride (TiON), titanium nitride (TiN), and similar materials. In one example, the protective liner 250 is aluminum oxynitride (AlON). The protective liner 250 can be deposited by atomic layer deposition, physical vapor deposition, chemical vapor deposition, or any suitable deposition technique.

[0109] Figure 10 Formation of the second self-aligned contact 233 is shown. After the protective liner 250 is formed, the second self-aligned contact 233 is formed over the protective liner 250. The second self-aligned contact 233 can be formed of a different material than the first self-aligned contact 231. The second self-aligned contact 233 can be made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, any suitable dielectric material, or any combination of the foregoing. In some embodiments, the second self-aligned contact 233 is silicon nitride. The second self-aligned contact 233 can be formed by chemical vapor deposition, physical vapor deposition, any suitable deposition technique, or a combination of the foregoing. If desired, a planarization process such as chemical mechanical planarization can be used to planarize the top surface of the second self-aligned contact 233.

[0110] Figure 10A first hard mask layer 235, a second hard mask layer 237, and a three-layer mask structure 239 are sequentially formed over the second self-aligned contact 233. The first hard mask layer 235 and the second hard mask layer 237 are configured to provide etch selectivity with respect to the second self-aligned contact 233 and the first hard mask layer 235, respectively, during one or more etch processes. The first hard mask layer 235 can be made of a metal compound, such as titanium nitride (TiN), tungsten carbide (WC), tantalum nitride (TaN), tungsten nitride (WN), or other materials. The second hard mask layer 237 can include or be a silicon oxide layer or any suitable oxide material. The first hard mask layer 235 and the second hard mask layer 237 can be deposited by any suitable deposition technique, such as physical vapor deposition, chemical vapor deposition, or similar techniques. The three-layer structure (also referred to as the three-layer mask structure) 239 includes a bottom layer 241, a middle layer 243, and a top layer 245. The three-layer structure 239 can be selected for deep ultraviolet (DUV) or extreme ultraviolet (EUV) lithography. The bottom layer 241 can be a bottom anti-reflective coating (BARC) layer, such as a silicon rich oxide or silicon oxycarbide (SiOC). The middle layer 243 can be a silicon-containing or metal-containing polymer. The top layer 245 can be a radiation-sensitive layer, such as a photoresist. The bottom layer 241, the middle layer 243, and the top layer 245 can be deposited by any suitable deposition technique, such as physical vapor deposition, chemical vapor deposition, spin-on coating, or similar techniques.

[0111] Figure 11 A first opening 247 is formed through the top layer 245 and the middle layer 243 of the three-layer mask structure 239 during a first lithography and etch process. The first opening 247 formed in the top layer 245 is generally aligned with the replacement gate 228b. The first lithography process is performed by positioning a first mask 249 over the structure of Figure 10 The first mask 249 can be suitable for exposure with deep ultraviolet radiation, such as an ArF excimer laser (193 nanometers) or a KrF excimer laser (248 nanometers). The first mask 249 has a first pattern 255, which can be various features, such as squares, lines, holes, a mesh, or any desired shape (e.g., polygons), depending on the features to be formed in the target layer. In some embodiments, the first pattern 255 includes a square pattern.

[0112] Figure 11Illustration 289 is an enlarged top view schematic diagram illustrating a portion of a pattern 291 for patterning a first photomask 249 for patterning a top layer 245 according to some embodiments. Pattern 291 includes a plurality of components 293a, 293b, 293c, 293d, which can be linear, square, grid-like, or any desired shape (e.g., polygonal), depending on the components to be formed in the top layer 245. In some embodiments, components 293a, 293b, 293c, 293d are square patterns. It is contemplated that the four components and their configuration are shown for illustrative purposes. Depending on the application and components to be formed in the semiconductor device 240, components 293a, 293b, 293c, 293d may be repeated on the first photomask 249. Components 293a, 293b, 293c, 293d may provide openings for contacts, providing electrical connections to the source / drain regions and / or gate of the semiconductor device 240. For example, component 293a may be a square pattern corresponding to a portion of the first mating contact (e.g., pattern 158A of mating contact 158, such as...). Figure 1B (As shown). Component 293b may be a square pattern corresponding to a portion of the second mating contact (e.g., pattern 159A of mating contact 159, as shown). Figure 1B (As shown). Components 293c and 293d can be square patterns corresponding to the contact components (e.g., as shown). Figure 1B The contact pattern shown is 162A. Components 293a and 293b of the first photomask 249 and components 279a and 279b from the second photomask 269 (to be described below) Figure 14 (Discussion) Recombination to produce rectangular mating contacts (e.g., as...) Figure 1B The mating contacts 158 and 159 shown will be transferred to the target layer (e.g., the second self-aligning contact 233). Depending on the application, the dimensions of the components 293a, 293b, 293c, and 293d can range from about 10 nanometers to about 80 nanometers, for example, from about 20 nanometers to about 55 nanometers.

[0113] The first pattern 255 is transferred to the top layer 245 by exposing the top layer 245 to a radiation beam 257 using a first photomask 249. The radiation beam 257 can be extreme ultraviolet radiation (e.g., 13.5 nm) or deep ultraviolet radiation such as an ArF excimer laser (193 nm) or a KrF excimer laser (248 nm). Other suitable radiation, such as an electron beam, X-ray, or ion beam, can also be used depending on the masking material. Then, depending on whether a positive or negative photoresist is used, the exposed or unexposed portions of the top layer 245 can be removed.

[0114] Next, the middle layer 243 is patterned using the patterned top layer 245 as a mask. As a result, the first openings 247 of the top layer 245 are transferred to the middle layer 243. The patterning of the middle layer 243 can use any suitable process, such as a dry etch process. An exemplary dry etch process can be performed in a dual RF power source plasma reactor using a chemistry containing an inert gas, such as argon, and a fluorocarbon gas, such as tetrafluoromethane (CF4), trifluoromethane (CHF3), hexafluorobutadiene (C4F6), difluoromethane (CH2F2), octofluoropropane (C3F8), octofluorocyclobutane (C4F8), or any combination of the foregoing. In some embodiments, the chemistry contains CF4and CHF3. The chamber pressure of the plasma reactor can be maintained at about 5 mTorr to about 20 mTorr, such as about 10 mTorr. During the dry etch process, the source power is provided at a first power level and the bias power is provided at a second power level, and the ratio of the first power level to the second power level can be controlled in a range of about 30: 1 to about 10: 1, such as about 20: 1. In some embodiments, the first power is about 300 W and the second power is about 15 W, for example.

[0115] Figure 12The first openings 247 are shown formed through the bottom layer 241 and the underlying hardmask layers 235 and 237. The bottom layer 241 is patterned using the patterned top layer 245 and the middle layer 243 as a mask. The patterning of the bottom layer 241 can use any suitable process, such as a dry etch process. The dry etch process can be performed in a dual radio frequency powered plasma reactor. An exemplary dry etch process for etching the bottom layer 241 can include a first etch process and a second etch process after the first etch process. In advanced technology, as device components are scaled down, the margin for a misalignment between the contact openings and the gate electrodes is significantly reduced. The reduced margin for misalignment can result in a significant device yield loss or create serious device reliability problems, particularly in the area of the landing contacts, where a misalignment can easily cause a complete break in the connection to the source / drain regions or the gate electrode. Therefore, to facilitate the lithography process, it can be advantageous to form the first openings 247 with a wider diameter, which is then tailored / reduced in diameter when transferred in the three-layer structure 239. The two-stage etch process allows for a gradual reduction in the critical dimensions of the pattern in the bottom layer 241. The reduced pattern critical dimensions can avoid the chance of misalignment between the contact openings and the gate electrodes.

[0116] In some embodiments, the first etch process uses a first chemistry including nitrogen (N2) and hydrogen (H2). The nitrogen gas flows into the plasma reactor at a first volumetric flow rate and the hydrogen gas flows into the plasma reactor at a second volumetric flow rate, and the ratio of the first volumetric flow rate to the second volumetric flow rate can be controlled in a range from about 2: 1 to about 5: 1, such as about 3: 1. The chamber pressure of the plasma reactor can be maintained at about 1 mTorr to about 30 mTorr, such as about 10 mTorr. During the first etch process, the power supply power is provided at a first power level and the bias power is provided at a second power level, and the ratio of the first power level to the second power level can be controlled in a range from about 3: 1 to about 7: 1, such as about 5: 1. In some embodiments, for example, the first power is about 500 W and the second power is about 100 W.

[0117] After the first etch process, a second etch process is performed in the same plasma reactor using a second chemistry comprising carbon dioxide (C02) and oxygen (02). The carbon dioxide flows into the plasma reactor at a first volumetric flow rate and the oxygen flows into the plasma reactor at a second volumetric flow rate, and the ratio of the first volumetric flow rate to the second volumetric flow rate can be controlled in a range from about 2: 1 to about 6: 1, such as about 3: 1. The chamber pressure of the plasma reactor can be maintained at about 1 mTorr to about 30 mTorr, such as about 10 mTorr. During the second etch process, the power supply power is provided at a first power level and the bias power is provided at a second power level, and the ratio of the first power level to the second power level can be controlled in a range from about 2: 1 to about 6: 1, such as about 4: 1. In some embodiments, for example, the first power is about 200 W and the second power is about 50 W. Upon completion of the second etch process, the openings of the top layer 245 can have a first diameter, and the openings of the bottom layer 241 can have a second diameter that is less than the first diameter.

[0118] Next, the patterned three-layer structure 239 is used as a mask to pattern the second hard mask layer 237. The patterning of the second hard mask layer 237 can use any suitable process, such as a dry etch process. The dry etch process can be performed in a dual radio frequency power plasma reactor. An exemplary dry etch process for etching the second hard mask layer 237 can include using a chemistry comprising an inert gas, such as argon, and a fluorocarbon gas, such as tetrafluoromethane (CF4), trifluoromethane (CHF3), hexafluorobutadiene (C4F6), hexafluoroethane (C2F6), difluoromethane (CH2F2), octafluoropropane (C3F8), octafluorocyclobutane (C4F8), or any combination of the foregoing. In some embodiments, the chemistry comprises CF4and argon. The chamber pressure of the plasma reactor can be maintained at about 5 mTorr to about 20 mTorr, such as about 10 mTorr. During the dry etch process, the power supply power is provided at a first power level and the bias power is provided at a second power level, and the ratio of the first power level to the second power level can be controlled in a range from about 2: 1 to about 6: 1, such as about 3.5: 1. In some embodiments, for example, the first power is about 500 W and the second power is about 150 W.

[0119] Then, a dry etch process and / or a strip process, such as an ashing process, can be performed to sequentially remove the patterned top layer 245, the patterned middle layer 243, and the patterned bottom layer 241. A wet clean can be performed after the strip process.

[0120] Next, an etch process is performed to transfer the first openings 247 from the second hardmask (also referred to as the second hardmask layer) 237 to the first hardmask layer 235. The etch process can be a dry etch process performed in a dual radio frequency power plasma reactor. An exemplary dry etch process for etching the first hardmask layer 235 can include the use of a chemistry containing an inert gas (e.g., argon) and a fluorocarbon gas, such as tetrafluoromethane (CF4), trifluoromethane (CHF3), hexafluorobutadiene (C4F6), hexafluoroethane (C2F6), difluoromethane (CH2F2), octafluoropropane (C3F8), octafluorocyclobutane (C4F8), or any combination of the foregoing. In some embodiments, the chemistry includes C4F8and argon. The chamber pressure of the plasma reactor can be maintained at about 5 mTorr to about 20 mTorr, such as about 10 mTorr. During the dry etch process, power supply power is provided at a first power level and bias power is provided at a second power level, and the ratio of the first power level to the second power level can be controlled in a range of about 2: 1 to about 6: 1, such as about 4: 1. In some embodiments, the first power is about 200 W and the second power is about 50 W, for example. A wet clean process can be performed after the dry etch process to remove residue.

[0121] Figure 13A first contact opening 259 is formed through a portion of the second self-aligned contact 233, the protective liner 250, the first self-aligned contact 231, and the gate spacer 286 using the patterned second hardmask 237 and the patterned first hardmask layer 235 as a mask. The first contact opening 259 can be formed by using one or more etching processes. An exemplary etching process can include a first dry etching process performed in a dual radio frequency powered plasma reactor using the patterned second hardmask 237 and the patterned first hardmask layer 235 as a mask to remove a portion of the second self-aligned contact 233. The first dry etching process can use chemistry including a fluorine-containing gas and an inert gas, such as argon. Suitable fluorine-containing gases can include, but are not limited to, CF4, CHF3, CH3F, C4F6, C2F6, CH2F2, C4F8, or any combination of the foregoing. In some embodiments, the chemistry includes C4F8and CH3F. The fluorine-containing gas flows into the plasma reactor at a first volumetric flow rate, the argon gas flows into the plasma reactor at a second volumetric flow rate, and the ratio of the first volumetric flow rate to the second volumetric flow rate can be controlled in a range from about 1 : 1 to about 3 : 1, such as about 2: 1. The chamber pressure of the plasma reactor can be maintained at about 5 mTorr to about 200 mTorr, such as about 10 to 50 mTorr. During the dry etching process, power supply power is provided at a first power level and bias power is provided at a second power level, and the ratio of the first power level to the second power level can be controlled in a range from about 1 : 1 to about 2: 1. In some embodiments, the first power is about 300 to 500 W and the second power is about 100 W, for example.

[0122] After the second self-aligned contact 233 is removed, a portion of the protective liner 250 is exposed. Next, a second dry etching process can be performed in a dual radio frequency powered plasma reactor using the patterned second hardmask 237 and the patterned first hardmask layer 235 as a mask to remove the exposed protective liner 250. The second dry etching process can use chemistry including a chlorine-containing gas and an inert gas, such as helium or argon. Suitable chlorine-containing gases can include, but are not limited to, chlorine (Cl2) and boron trichloride (BC13), methyl fluoride (CH3F), and similar gases. The chamber pressure of the plasma reactor can be maintained at about 10 mTorr to about 300 mTorr, such as about 100 mTorr. During the second dry etching process, power supply power is provided at a first power level and bias power is provided at a second power level, and the ratio of the first power level to the second power level can be controlled in a range from about 3 : 1 to about 6: 1, such as about 5: 1. In some embodiments, the first power is about 800 W and the second power is about 150 W, for example.

[0123] After the protective liner 250 is removed, a portion of the first self-aligned contact 231 and a portion of the gate spacer 286 are exposed. A third dry etch process can be performed in a dual frequency power plasma reactor that uses the patterned second hard mask 237 and the patterned first hard mask layer 235 as a mask to remove the exposed first self-aligned contact 231. In some cases, the gate spacer 286 can be used as a mask to remove the exposed first self-aligned contact 231. In any case, the result of the third dry etch process exposes the top surface of the gate spacer 286, the gate dielectric layer 222, the one or more optional conformal layers 224, and the gate conductive fill material 226. The third dry etch process can use chemistry that includes a fluorine-containing gas and a hydrogen-containing gas. Suitable fluorine-containing gases can include, but are not limited to, F2, CF4, CHF3, C4F6, C2F6, CH2F2, C4F8, SF6, or any combination of the foregoing. Suitable hydrogen-containing gases can include, but are not limited to, CH4, H2, NH3, a hydrocarbon, or any molecule with abstractable hydrogen atoms, or any combination of the foregoing. The chemistry can further include an oxygen-containing gas, such as O2, NO, N2O, etc. In some embodiments, the chemistry includes CF4and CH4. The chamber pressure of the plasma reactor can be maintained at about 5 mTorr to about 200 mTorr, such as about 50 mTorr. During the dry etch process, power source power is provided at a first power level and bias power is provided at a second power level, and the ratio of the first power level to the second power level can be controlled to be in a range of about 2: 1 to about 6: 1, such as about 4: 1. In some embodiments, the first power is about 1600 W and the second power is about 350 W, for example.

[0124] The first contact opening 259 has a bottom 215 and sidewalls 217 extending upwardly from the bottom 215. The bottom 215 can be substantially coplanar with the top surface of the gate conductive fill material 226, the gate dielectric layer 222, and the one or more optional conformal layers 224. In some embodiments, the bottom 215 can further extend into a portion of the gate spacer 286. The sidewalls 217 can be angled relative to the bottom 215 by an angle "A". In some embodiments, the angle "A" is in a range of about 91° to about 100°, such as about 92° to about 95° (e.g., about 93° to about 94°). The angle "A" can vary depending on the application and / or the parameters used during the etching process to form the first contact opening 259.

[0125] Figure 14 The first contact opening 259 is shown in Figure 13A three-layer structure 261 is formed over the structure of semiconductor device 240. Three-layer structure 261, which can be implemented using the same or similar processes as three-layer structure 239 and the same or similar materials as three-layer structure 239, includes a bottom layer 263, an intermediate layer 265, and a top layer 267. First contact openings 259 are filled by bottom layer 263 and overburdened to a predetermined thickness. In one example, the top surface of bottom layer 263 is higher than the top surface of second hardmask layer 237. Intermediate layer 265 and top layer 267 are then sequentially deposited over bottom layer 263.

[0126] After three-layer structure 261 is formed, a second lithography process is used to pattern top layer 267. The second lithography process is performed by positioning a second photomask 269 over semiconductor device 240. Second photomask 269 has a second pattern 271. Second pattern 271 can have similar features as first pattern 255 described above. In some embodiments, second pattern 271 includes a square pattern. Similarly, second pattern 271 can be transferred to top layer 267 by exposing top layer 267 to a beam of radiation 257, removing exposed portions of top layer 267. As a result, second openings 273 are formed in top layer 267. Second openings 273 formed in top layer 267 are generally aligned with source / drain regions 292, as shown in Figure 14 According to the application, the width of second openings 273 can be similar to, greater than, or less than the width of first openings 247.

[0127] Figure 14 FIG. 275 is an enlarged top view schematic diagram illustrating a portion of a pattern 277 of second photomask 269 used to pattern top layer 267, according to some embodiments. Second photomask 269 can be suitable for exposure to deep ultraviolet light radiation, such as an ArF excimer laser (193 nanometers) or a KrF excimer laser (248 nanometers). Pattern 277 includes a plurality of features 279a, 279b, 279c, 279d, which can be linear, square, grid, or any desired shape (e.g., polygonal), depending on the features to be formed in top layer 267. In some embodiments, features 279a, 279b, 279c, 279d are a square pattern. It is contemplated that the four features and their configuration are shown for illustrative purposes. According to the application and the features to be formed in semiconductor device 240, features 279a, 279b, 279c, 279d can be repeated on second photomask 269. Features 279a, 279b, 279c, 279d can provide openings for contacts that provide electrical connections to source / drain regions and / or gates of semiconductor device 240. For example, feature 279a can be a square pattern corresponding to a portion of a first landing contact (e.g., pattern 158B of landing contact 158, as shown in Figure 1B(As shown). Part 279b may be a square pattern corresponding to a portion of the second mating contact (e.g., pattern 159B of mating contact 159, as shown). Figure 1B (As shown). Parts 279c and 279d can be square patterns corresponding to the contact parts (e.g., as shown). Figure 1B The contact pattern 160A shown is an example. Components 279a and 279b of the second photomask 269 and components 293a and 293b from the first photomask 249 are recombined to produce rectangular mating contacts (e.g., as shown in the diagram). Figure 1B The mating contacts 158 and 159 shown will be transferred to the target layer (e.g., the second self-aligned contact 233). By dividing the layout into multiple different masks (e.g., the first mask 249 and the second mask 269), components can be formed separately on a single layer using multiple masks consecutively. Therefore, the minimum line spacing in the combined pattern can be reduced while maintaining good resolution.

[0128] It should be understood that the components 293a, 293b, 293c, 293d and components 279a, 279b, 279c, 279d discussed in the embodiments of the present invention can be of any shape and / or configured in any desired pattern shape, as long as the combination of components 293a, 293b, 293c, 293d and components 279a, 279b, 279c, 279d produces the predetermined complete shape of the mating contacts and / or other contact components required for the semiconductor device 240.

[0129] After patterning the top layer 267, the patterned top layer 267 can be used as a mask to match the above reference. Figure 11 and Figure 12 The discussed method patternifies the intermediate layer 265 and the bottom layer 263, thereby transferring the second opening 273 to the bottom layer 263. The patterned structure (also known as a three-layer structure) 261 can then be used as a mask to correspond with the aforementioned reference. Figure 11 and Figure 12 The second hard mask layer 237 is patterned in a similar manner to that discussed. At this stage, the underlying layer 263 in the first contact opening 259 is preserved. Next, an etching process can be performed to transfer the modified second opening 273 from the second hard mask layer 237 to the first hard mask layer 235, in a manner similar to that described above. Figure 12 The methods discussed.

[0130] Figure 15A second contact opening 281 is formed through the second self-aligned contact 233 and the protective liner 250. Next, using the patterned second hardmask 237, the patterned first hardmask layer 235 (and, in some cases, the remaining portion of the bottom layer 263 in the first contact opening 259) as a mask, one or more etch processes are performed to remove portions of the second self-aligned contact 233 and the protective liner 250, thereby forming the second contact opening 281 having an angled profile. The second contact opening 281 exposes at least the top surface of the conductive material 246. The second self-aligned contact 233 can be removed using a first etch process, such as the first dry etch process discussed above with reference to the second self-aligned contact 233. The protective liner 250 can be removed using a second etch process, such as the second dry etch process discussed above with reference to the protective liner 250. After the etch processes, the bottom layer 263 remaining in the first contact opening 259 can be removed using a suitable stripping process, such as an ashing process. Figure 13 Figure 13

[0131] The second contact opening 281 has a bottom portion 223 and sidewalls 225 extending upwardly from the bottom portion 223. The sidewalls 225 can be angled with respect to the bottom portion 223 by an angle "B". In some embodiments, the angle "B" is in a range from 91° to about 100°, such as from about 92° to about 95° (e.g., from about 93° to about 94°). The angle "B" can vary depending on the application and / or the parameters used during the etch process to form the second contact opening 281.

[0132] Figure 15 The first contact opening 259 and the second contact opening 281 are shown. Together, the first contact opening 259 and the second contact opening 281 expose portions of the conductive material 246, the first ILD 297, the gate conductive fill material 226, the gate dielectric layer 222, the one or more optional conformal layers 224, and the gate spacer 286. The combination of the first contact opening 259 and the second contact opening 281 provides a contact opening for the abutting contacts, such as the abutting contacts 158 and 159 shown. Figure 1B

[0133] Figure 16 ​​​The first and second contact openings 259, 281 (collectively, the mating contact openings 238) are shown filled with a conductive fill 227, such as a contact metal. The conductive fill 227 can be or include tungsten, cobalt, copper, ruthenium, aluminum, gold, silver, alloys of the foregoing, similar materials, or combinations of the foregoing, and deposition of the conductive fill 227 can be by physical vapor deposition, electrochemical plating (ECP), atomic layer deposition, chemical vapor deposition, or any suitable deposition technique. In some cases, a barrier / adhesion layer (not shown) can be conformally deposited on the exposed surfaces of the mating contact openings 238. The barrier / adhesion layer can include or be titanium nitride, titanium-silicon nitride, titanium-carbon nitride, titanium-aluminum nitride, tantalum nitride, tantalum-silicon nitride, tantalum-carbon nitride, tungsten nitride, tungsten carbide, tungsten-carbon nitride, similar materials, or combinations of the foregoing, and deposition of the barrier / adhesion layer can be by atomic layer deposition, plasma-enhanced CVD (PECVD), molecular beam deposition (MBD), or any suitable deposition technique. After deposition of the conductive fill 227, excess conductive fill 227 can be removed by using a planarization process, such as chemical mechanical planarization. The planarization process can remove excess conductive fill 227, the second hard mask layer 237, the first hard mask layer 235, and the second self-aligned contact 233, down to the top surface 229 of the protective liner 250. Figure 17A The top surface 229 of the protective liner 250, the top surface 234 of the conductive fill 227, and the top surface 236 of the second self-aligned contact 233 are shown substantially coplanar after the planarization process. The mating contact openings 238 generally have a first bottom 1702 above and extending across the source / drain region 292, and a second bottom 1704 above and extending across the replacement gate structure 228b. A tapered component, such as a tapered top portion 286’ of the gate spacer 286, is disposed between the first bottom 1702 and the second bottom 1704, and extends upwardly between the source / drain region 292 and the replacement gate structure 228b. While the first bottom 1702 is shown as being higher than the second bottom 1704, the first bottom 1702 can be at the same height as the second bottom 1704, or even lower than the second bottom 1704, depending on the receipts and / or application of the process. Figure 17BAn embodiment showing the first bottom 1702 and the second bottom 1704 at the same height. The conductive fill 227 in the abutment contact opening 238 enables the conductive material 246 of the contact source / drain region 292 to electrically connect between the gate conductive fill material 226 of the replacement gate structure 228b without the use of a horizontal metal interconnect layer. As a result, a shared or abutment contact is obtained, e.g. Figure 1B the abutment contacts 158 and 159 shown.

[0134] After the conductive fill 227 is formed in the abutment contact opening 238, the structure can undergo further processing to form various components and regions needed to complete a static random access memory memory cell. For example, subsequent processing can form additional contacts / vias / wires and multilayer interconnect components (e.g., metal layers and inter- or intra-metal dielectrics) on the substrate 270 configured to connect various components to form functional circuitry that can include one or more devices.

[0135] Figure 18 An embodiment showing Figure 17A a portion of a cross-sectional schematic diagram to further show additional details in accordance with some embodiments. It is to be understood that, for ease of illustration purposes, Figure 18 are not drawn to scale. The abutment contact structure 1800 can be viewed as a W-shaped structure having a left V-shaped portion 1802 and a right V-shaped portion 1804. The abutment contact structure 1800 has a first dimension Dl along a top surface 1801 of the abutment contact structure 1800. The left V-shaped portion 1802 has a second dimension D2 along a bottom 1702 of the left V-shaped portion 1802. The right V-shaped portion 1804 has a third dimension D3 along a bottom 1704 of the right V-shaped portion 1804. The ratio of the second dimension D2 to the first dimension Dl can be in a range of about 1 : 1.5 to about 1 :3, and the ratio of the third dimension D3 to the first dimension Dl can be in a range of about 1 : 1.5 to about 1 :3. The bottom 1702 of the left V-shaped portion 1802 and the bottom 1704 of the right V-shaped portion 1804 can be non-coplanar. In Figure 18 In the embodiment shown, the bottom 1702 of the left V-shaped portion 1802 is higher than the bottom 1704 of the right V-shaped portion 1804 by a fourth dimension D4. The fourth dimension D4 can be in a range of about -5 nanometers to about 5 nanometers. In other words, the bottom 1702 of the left V-shaped portion 1802 can also be lower than the bottom 1704 of the right V-shaped portion 1804. The left V-shaped portion 1802 has a fifth dimension D5 measured from the top surface 1801 to the bottom 1702 of the left V-shaped portion 1802. The right V-shaped portion 1804 has a sixth dimension D6 measured from the top surface 1801 to the bottom 1704 of the right V-shaped portion 1804. The ratio of the fifth dimension D5 to the sixth dimension D6 can be in a range of about 0.9: 1 to about 1.2: 1, e.g., about 1 : 1.

[0136] The left V-shaped portion 1802 has a sidewall 1814 extending between the top surface 1801 of the butt contact structure 1800 and the bottom 1702 of the left V-shaped portion 1802. The right V-shaped portion 1804 has a sidewall 1816 extending between the top surface 1801 of the butt contact structure 1800 and the bottom 1704 of the right V-shaped portion 1804. A gate spacer 286 is disposed between the source / drain region 292 and the replacement gate structure 228b. The gate spacer 286 has a tapered portion (also referred to as a tapered top portion) 286' separating the left V-shaped portion 1802 and the right V-shaped portion 1804. In other words, the bottom 1702 of the left V-shaped portion 1802 and the bottom 1704 of the right V-shaped portion 1804 are not continuous. The tapered portion 286' has a first sidewall 1818 and a second sidewall 1820 intersecting the first sidewall 1818 at an angle "E" greater than 0°, for example, about 2° to about 20°. The first sidewall 1818 is angled at an angle "F" relative to the bottom 1704 of the right V-shaped portion 1804. The second sidewall 1820 is angled at an angle "G" relative to the bottom 1702 of the left V-shaped portion 1802. The angle "F" can be in a range of about 91° to about 100°, for example, about 92° to about 95°. The angle "G" can be in a range of about 91° to about 100°, for example, about 92° to about 95°.

[0137] The various embodiments described herein can provide many advantages. It should be understood that not all advantages are necessarily described herein, and that many embodiments can provide one or more of the advantages described herein, or other advantages not similarly described. By way of example, the embodiments described herein provide improved butt contact structures that enable one or more gates to be connected to one or more active regions without using a horizontal metal interconnect layer. The butt contact structures between the gate contacts and the source or drain contacts can be formed by a double patterning process using two separate photo-masks, each having a pattern corresponding to one-half of the common or butt contact structure. By reducing the total number of photo-masks to two, the number of photo-mask alignments is reduced, and yield loss due to misalignment of another photo-mask is mitigated. As a result, manufacturing costs can be reduced and throughput can be increased. In addition, the improved butt contact structures have tapered gate spacers that protrude into the bottom of the butt contact structure. The tapered gate spacers and the angled sidewalls of the butt contact structure can ensure good metal fill capability for a subsequently deposited metal fill. Thus, the metal fill can be deposited completely in the butt contact structure without voids or seams.

[0138] In one embodiment, a structure is provided. The structure includes a first transistor on a substrate, the first transistor including a first source or drain region, a first gate, and a first gate spacer disposed between the first gate and the first source or drain region. The structure also includes a second transistor on the substrate, the second transistor including a second source or drain region, a second gate, and a second gate spacer disposed between the second gate and the second source or drain region. The structure further includes a docking contact disposed over the first source or drain region and extending from the first source or drain region to at least one of the first gate or the second gate, a portion of the first gate spacer extending a distance into the docking contact to separate a first bottom surface of the docking contact from a second bottom surface of the docking contact.

[0139] In some embodiments, the portion of the first gate spacer has a tapered profile. In some embodiments, the portion of the first gate spacer has a first sidewall and a second sidewall that intersects the first sidewall. In some embodiments, the first sidewall contacts the first bottom surface of the docking contact at an angle in a range of 91° to 100°. In some embodiments, the first bottom surface and the second bottom surface are at the same height. In some embodiments, the first bottom surface and the second bottom surface are at different heights.

[0140] In another embodiment, a structure includes a first transistor on a substrate, the first transistor including a source or drain region; a conductive feature contacting the source or drain region; and a gate electrode of a gate structure of a second transistor on the substrate. The structure also includes a docking contact including (i) a first surface contacting the gate electrode, (ii) a second surface contacting the conductive feature, (iii) a third surface extending from the first surface at a first angle, and (iv) a fourth surface extending from the second surface at a second angle, the third surface intersecting the fourth surface at a third angle. The structure further includes a gate spacer disposed between the source or drain region and the gate structure, a portion of the gate spacer disposed laterally between the third surface and the fourth surface.

[0141] In some embodiments, the first surface and the second surface are coplanar. In some embodiments, the first surface and the second surface are at different heights. In some embodiments, the first angle is in a range of 91° to 100°, the second angle is in a range of 91° to 100°, and the third angle is greater than 0°. In some embodiments, the portion of the gate spacer has a tapered profile. In some embodiments, the docking contact includes tungsten, cobalt, copper, ruthenium, aluminum, gold, silver, alloys thereof, or combinations thereof.

[0142] In another embodiment, a method of fabricating a semiconductor is provided. The method includes forming a source or drain region of a first transistor on a substrate, the source or drain region having a conductive feature formed thereon; forming a gate of a second transistor on the substrate, the gate having a first dielectric layer formed thereon; forming a gate spacer on a side of the gate, the gate spacer laterally disposed between the gate and the source or drain region; depositing a second dielectric layer over the conductive feature, the first dielectric layer, and the gate spacer, the second dielectric layer being different from the first dielectric layer; depositing a first masking layer over the second dielectric layer; depositing a second masking layer over the first masking layer; etching a first contact opening through the second masking layer, the first masking layer, the second dielectric layer, and the first dielectric layer to expose the gate, the etching of the first contact opening including etching the second masking layer using a first etch recipe and etching the first dielectric layer using a fourth etch recipe, the first, second, third, and fourth etch recipes being different from one another; etching a second contact opening through the second masking layer, the first masking layer, and the second dielectric layer to expose the conductive feature, the etching of the second contact opening including etching the second masking layer using the first etch recipe, etching the first masking layer using a second etch recipe, and etching the second dielectric layer using a third etch recipe, the first contact opening and the second contact opening being connected at the gate spacer, and the first etch recipe and the second etch recipe shaping a portion of the gate spacer into a tapered profile; and filling the first contact opening and the second contact opening with a conductive material.

[0143] In some embodiments, a method of fabricating a semiconductor includes forming a source or drain region on a substrate, forming a gate on the substrate, and forming a gate spacer on a side of the gate, wherein the source or drain region has a conductive feature formed thereon, the gate has a first dielectric layer formed thereon, and the gate spacer is laterally disposed between the gate and the source or drain region; depositing a second dielectric layer over the conductive feature, the first dielectric layer, and the gate spacer, wherein the second dielectric layer is different from the first dielectric layer; depositing a first masking layer over the second dielectric layer; depositing a second masking layer over the first masking layer; etching a first contact opening through the second masking layer, the first masking layer, the second dielectric layer, and the first dielectric layer to expose the gate, etching the first contact opening includes using a first etch recipe to etch the second masking layer, using a second etch recipe to etch the first masking layer, using a third etch recipe to etch the second dielectric layer, and using a fourth etch recipe to etch the first dielectric layer, wherein the first, second, third, and fourth etch recipes are different from one another; etching a second contact opening through the second masking layer, the first masking layer, and the second dielectric layer to expose the conductive feature, etching the second contact opening includes using the first etch recipe to etch the second masking layer, using the second etch recipe to etch the first masking layer, using the third etch recipe to etch the second dielectric layer, the first contact opening and the second contact opening are connected at the gate spacer, and the first etch recipe and the second etch recipe shape a portion of the gate spacer into a tapered profile; and filling the first contact opening and the second contact opening with a conductive material.

[0144] In some embodiments, the first contact openings are defined by a first pattern transferred from a first mask using a first lithography process, and the second contact openings are defined by a second pattern transferred from a second mask using a second lithography process. In some embodiments, the first mask further includes a third pattern, and the second mask further includes a fourth pattern, after the first and second lithography processes, the third pattern and the fourth pattern are combined to create the contact features in the substrate. In some embodiments, the first lithography process is performed by: depositing a first mask layer stack on a second mask layer; and forming first openings corresponding to the first pattern in the first top layer, the first middle layer, and the first bottom layer, and the size of the first openings in the first top layer is larger than the size of the first openings in the first bottom layer. In some embodiments, depositing the first mask layer stack on the second mask layer includes: depositing the first bottom layer on the second mask layer; depositing the first middle layer on the first bottom layer, the first middle layer having a different material than the first bottom layer; and depositing the first top layer on the first middle layer, the first top layer having a different material than the first middle layer. In some embodiments, the method further includes: after etching the first contact openings, performing the second lithography process by: depositing a second mask layer stack on the first contact openings; and forming second openings corresponding to the second pattern in the second top layer, the second middle layer, and the second bottom layer, and the size of the second openings in the second top layer is larger than the size of the second openings in the second bottom layer. In some embodiments, depositing the second mask layer stack on the first contact openings includes: depositing the second bottom layer on the first contact openings and the second mask layer; depositing the second middle layer on the second bottom layer, the second middle layer having a different material than the second bottom layer; and depositing the second top layer on the second middle layer, the second top layer having a different material than the second middle layer. In some embodiments, the materials of the first top layer, the first middle layer, and the first bottom layer are the same as the materials of the second top layer, the second middle layer, and the second bottom layer, respectively. In some embodiments, the first dielectric layer and the second dielectric layer are selected from the group consisting of silicon carbon oxynitride, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, and silicon carbon nitride. In some embodiments, the first etch recipe is a dry etch process using chemicals including CF4and argon, the second etch recipe is a dry etch process using chemicals including C4F8and argon, the third etch recipe is a dry etch process using chemicals including C4F8and CH3F, and the fourth etch recipe is a dry etch process using chemicals including CF4and CH4.

[0145] The components of the above-described embodiments can be implemented as computer-readable code on a computer readable medium. The computer-readable medium can be a non-transitory computer-readable medium. A computer-readable medium refers to any medium that participates in providing data to a computer processor for execution. Such a medium can take many forms, including but not limited to storage media, and transmission media. Storage media can be non-transitory computer-readable media such as volatile and non-volatile computer memory, such as RAM and ROM, magnetic media such as a hard disk or floppy disk, or optical or solid state media such as a CD ROM and a DVD ROM. Transmission media can include coaxial cables, copper wire and fiber optics, among others. Some forms of computer-readable media can be tangible, while other forms can be transitory.

Claims

1. A docked contact structure, comprising: a first transistor on a substrate, the first transistor including a first source or drain region, a first gate, and a first gate spacer disposed between the first gate and the first source or drain region; a second transistor on the substrate, the second transistor including a second source or drain region, a second gate, and a second gate spacer disposed between the second gate and the second source or drain region; and a docked contact disposed over the first source or drain region and extending from the first source or drain region to at least one of the first gate or the second gate, a portion of the first gate spacer extending a distance into the docked contact to separate a first bottom surface of the docked contact from a second bottom surface of the docked contact.

2. The docking contact structure of claim 1, wherein, The portion of the first gate spacer has a tapered profile.

3. The docking contact structure of claim 1, wherein, The portion of the first gate spacer has a first sidewall and a second sidewall that intersects the first sidewall.

4. The docking contact structure of claim 3, wherein, The first sidewall contacts the first bottom surface of the docked contact at an angle of 91° to 100°.

5. The docking contact structure of claim 3, wherein, The first bottom surface and the second bottom surface are at the same height.

6. The docking contact structure of claim 3, wherein, The first bottom surface and the second bottom surface are at different heights.

7. The docking contact structure of claim 1, wherein, A ratio of a width of the docked contact at the first source or drain region to a width of the docked contact along an upper surface of the docked contact is in a range of 1 : 1.5 to 1 :

3.

8. A docked contact structure, comprising: a first transistor on a substrate, the first transistor including a source or drain region; a conductive feature contacting the source or drain region; a gate electrode of a gate structure of a second transistor on the substrate; a docked contact including (i) a first surface contacting the gate electrode, (ii) a second surface contacting the conductive feature, (iii) a third surface extending from the first surface at a first angle, and (iv) a fourth surface extending from the second surface at a second angle, the third surface intersecting the fourth surface at a third angle; and a gate spacer disposed between the source or drain region and the gate structure, a portion of the gate spacer disposed laterally between the third surface and the fourth surface.

9. The docking contact structure of claim 8, wherein, The first surface and the second surface are coplanar.

10. The docking contact structure of claim 8, wherein, The first surface and the second surface are at different heights.

11. The docking contact structure of claim 8, wherein, The first angle is in a range of 91° to 100°, the second angle is in a range of 91° to 100°, and the third angle is greater than 0°.

12. The docking contact structure of claim 8, wherein, The portion of the gate spacer has a tapered profile.

13. The docking contact structure of claim 8, wherein, The docked contact includes tungsten, cobalt, copper, ruthenium, aluminum, gold, silver, alloys thereof, or combinations thereof.

14. The docking contact structure of claim 8, wherein, A perpendicular distance between the first surface and the second surface is less than 5 nm.

15. A docked contact structure, comprising: an active region in a substrate; a conductive feature over the active region; a gate structure on the substrate, the gate structure including a gate spacer and a gate electrode, wherein the gate spacer is interposed between the gate electrode and the conductive feature; and A pair of landing contacts contacts the conductive feature and the gate electrode, wherein an upper surface of the gate spacer is higher than a first interface between the gate electrode and the pair of landing contacts, wherein the upper surface of the gate spacer is higher than a second interface between the conductive feature and the pair of landing contacts.

16. The docking contact structure of claim 15, wherein, The gate spacer has sloped sidewalls that intersect at an angle of 2° to 20°.

17. The landing contact structure of claim 15, further comprising a silicide region interposed between the conductive feature and the active region.

18. The landing contact structure of claim 15, further comprising an interlayer dielectric layer over the substrate, wherein a first portion of the interlayer dielectric layer is interposed between the gate spacer and the conductive feature.

19. The docking contact structure of claim 18, wherein, The gate spacer protrudes above the first portion of the interlayer dielectric layer.

20. The docking contact structure of claim 15, wherein, The first interface is lower than the second interface.

21. A method of fabricating a semiconductor, comprising: forming a source or drain region on a substrate, forming a gate on the substrate, and forming a gate spacer on a side of the gate, wherein the source or drain region has a conductive feature formed thereon, the gate has a first dielectric layer formed thereon, and the gate spacer is laterally disposed between the gate and the source or drain region; depositing a second dielectric layer over the conductive feature, the first dielectric layer, and the gate spacer, wherein the second dielectric layer is different from the first dielectric layer; depositing a first mask layer over the second dielectric layer; depositing a second mask layer over the first mask layer; etching a first contact opening through the second mask layer, the first mask layer, the second dielectric layer, and the first dielectric layer to expose the gate, etching the first contact opening includes using a first etch recipe to etch the second mask layer, a second etch recipe to etch the first mask layer, a third etch recipe to etch the second dielectric layer, and a fourth etch recipe to etch the first dielectric layer, wherein the first etch recipe, the second etch recipe, the third etch recipe, and the fourth etch recipe are different from each other; etching a second contact opening through the second mask layer, the first mask layer, and the second dielectric layer to expose the conductive feature, etching the second contact opening includes using the first etch recipe to etch the second mask layer, the second etch recipe to etch the first mask layer, the third etch recipe to etch the second dielectric layer, the first contact opening and the second contact opening are connected at the gate spacer, and the first etch recipe and the second etch recipe shape a portion of the gate spacer into a tapered profile; and filling the first contact opening and the second contact opening with a conductive material.

22. The method of manufacturing a semiconductor according to claim 21, wherein The first contact opening is defined by a first pattern transferred from a first mask using a first lithography process, and the second contact opening is defined by a second pattern transferred from a second mask using a second lithography process.

23. The method of manufacturing a semiconductor according to claim 22, wherein The first mask further includes a third pattern and the second mask further includes a fourth pattern, and after the first lithography process and the second lithography process, the third pattern and the fourth pattern are combined to create a contact feature in the substrate.

24. The method of manufacturing a semiconductor according to Claim 22, wherein The first lithography process is performed as follows: depositing a first mask layer stack over the second mask layer, including: depositing a first bottom layer over the second mask layer; depositing a first middle layer over the first bottom layer, the first middle layer having a different material than the first bottom layer; and depositing a first top layer over the first middle layer, the first top layer having a different material than the first middle layer; and forming a first opening corresponding to the first pattern in the first top layer, the first middle layer, and the first bottom layer, and the first opening in the first top layer having a larger size than the first opening in the first bottom layer.

25. The method of claim 24, further comprising: after etching the first contact opening, performing the second lithography process as follows: depositing a second mask layer stack over the first contact opening, including: depositing a second bottom layer in the first contact opening and over the second mask layer; depositing a second middle layer over the second bottom layer, the second middle layer having a different material than the second bottom layer; and depositing a second top layer over the second middle layer, the second top layer having a different material than the second middle layer; and forming a second opening corresponding to the second pattern in the second top layer, the second middle layer, and the second bottom layer, and the second opening in the second top layer having a larger size than the second opening in the second bottom layer.

26. The method of manufacturing a semiconductor according to claim 25, wherein The materials of the first top layer, the first middle layer, and the first bottom layer are the same as the materials of the second top layer, the second middle layer, and the second bottom layer, respectively.

27. The method of producing a semiconductor according to claim 21, wherein The first dielectric layer and the second dielectric layer are selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, and silicon carbonitride.

28. The method of producing a semiconductor according to claim 21, wherein The first etch recipe is a dry etch process using chemicals including CF4 and argon, the second etch recipe is a dry etch process using chemicals including C4F8 and argon, the third etch recipe is a dry etch process using chemicals including C4F8 and CH3F, and the fourth etch recipe is a dry etch process using chemicals including CF4 and CH4.

29. A method of fabricating a semiconductor, comprising: forming a first dielectric layer over a gate structure and a conductive feature connected to a source / drain region; forming a first mask layer over the first dielectric layer, the first mask layer having a first opening; patterning the first dielectric layer using the first mask layer to form a first contact opening exposing the gate structure; filling the first contact opening with a bottom anti-reflective coating layer; forming a second opening through the first mask layer; patterning the first dielectric layer using the first mask layer to form a second contact opening exposing the conductive feature, the second contact opening merging with the first contact opening to form a merged contact opening; and filling the merged contact opening with a conductive material to form a landing contact.

30. The method of manufacturing a semiconductor according to Claim 29, wherein A spacer is inserted between the gate structure and the source / drain region, wherein an uppermost surface of the spacer is higher than an interface between the landing contact and the gate structure and higher than an interface between the landing contact and the conductive feature.

31. The method of producing a semiconductor according to claim 30, wherein The interface between the landing contact and the gate structure is lower than the interface between the landing contact and the conductive feature.

32. The method of producing a semiconductor according to claim 30, wherein The spacer has sloped sidewalls that intersect at an angle of 2° to 20°.

33. The method of producing a semiconductor according to claim 29, wherein Forming the first dielectric layer includes forming the first dielectric layer over a protective dielectric layer inserted between the gate structure and the first dielectric layer, and wherein forming the first contact opening or forming a second contact opening includes patterning the protective dielectric layer.

34. A method of fabricating a semiconductor, comprising: forming a first transistor on a substrate, the first transistor including a source / drain region, a gate structure, and a spacer along a sidewall of the gate structure; forming a first dielectric layer over the substrate, wherein a surface of a conductive feature and a surface of a protective layer are exposed, the conductive feature contacting the source / drain region and the protective layer contacting the gate structure; forming a second dielectric layer over the first dielectric layer; forming a landing contact opening, forming the landing contact opening includes: forming a first contact opening through the second dielectric layer; filling the first contact opening with a sacrificial material; forming a second contact opening through the second dielectric layer, wherein the second contact opening overlaps the first contact opening; and removing the sacrificial material, thereby forming the landing contact opening, the landing contact opening exposing a surface of the conductive feature and a surface of the gate structure; and forming a conductive material in the landing contact opening.

35. The method of producing a semiconductor according to claim 34, wherein A bottom surface of the landing contact opening forms a W shape.

36. The method of producing a semiconductor according to claim 34, wherein Forming the landing contact opening further includes: forming a first mask layer over the second dielectric layer, wherein forming the first contact opening and forming the second contact opening includes forming the first contact opening and the second contact opening through the first mask layer.

37. The method for manufacturing a semiconductor according to Claim 34, further comprising: The conductive feature is recessed prior to forming the second dielectric layer.

38. The method of producing a semiconductor according to claim 34, wherein The first contact opening exposes the gate structure and the second contact opening exposes the conductive feature.

39. A method of fabricating a semiconductor, comprising: forming a first transistor on a substrate, the first transistor including a source / drain region, a gate structure, and a spacer along a sidewall of the gate structure; forming a contact to the source / drain region; forming one or more dielectric layers over the first transistor and the contact; after forming the one or more dielectric layers, forming a landing contact opening through the one or more dielectric layers, forming the landing contact opening includes: forming a first contact opening to the gate structure in the one or more dielectric layers using a first process and forming a second contact opening to the contact in the one or more dielectric layers using a second process, wherein the first process and the second process are performed sequentially, wherein a sidewall of the first contact opening includes the spacer, wherein a sidewall of the second contact opening includes the spacer; and forming a conductive material in the landing contact opening.

40. The method of producing a semiconductor according to claim 39, wherein forming the first contact opening and the second contact opening includes: forming one of the first contact opening and the second contact opening; filling the one of the first contact opening and the second contact opening with a sacrificial material; forming the other of the first contact opening and the second contact opening; and removing the sacrificial material, thereby forming the abutment contact opening.

41. The method of producing a semiconductor according to claim 40, wherein filling the one of the first contact opening and the second contact opening with the sacrificial material is a full fill of the one of the first contact opening and the second contact opening.

42. The method for manufacturing a semiconductor according to Claim 39, further comprising: recessing the contact.

43. The method of producing a semiconductor according to claim 42, wherein, recessing the contact prior to forming the one or more dielectric layers, wherein the recessing forms a recess.

44. The method of producing a semiconductor according to claim 43, wherein forming the one or more dielectric layers includes: forming a first dielectric layer in the recess and over the gate structure; and forming a second dielectric layer over the first dielectric layer, the second dielectric layer extending into the recess.

45. The method of producing a semiconductor according to claim 44, wherein forming the conductive material includes: forming a conductive layer in the first contact opening and the second contact opening, wherein the conductive layer extends over the one or more dielectric layers; and planarizing the conductive layer and the one or more dielectric layers.

46. The method of producing a semiconductor according to claim 45, wherein after planarizing, a portion of the first dielectric layer remains along a sidewall of the conductive material.

47. The method of producing a semiconductor according to claim 39, wherein the first contact opening overlaps the second contact opening.

48. A method of fabricating a semiconductor, comprising: forming a first dielectric layer over a first conductive feature and a second conductive feature; patterning the first dielectric layer to form a first contact opening, the first contact opening exposing the first conductive feature; filling the first contact opening with a bottom anti-reflective coating; patterning the first dielectric layer to form a second contact opening, the second contact opening exposing the second conductive feature, the second contact opening merging with the first contact opening; removing the bottom anti-reflective coating to form a merged contact opening; filling the merged contact opening with a conductive material to form an abutment contact. one of the first conductive feature and the second conductive feature includes a contact to a source / drain region, wherein the other of the first conductive feature and the second conductive feature includes a gate electrode.

49. The method of producing a semiconductor according to claim 48, wherein the first conductive feature or the second conductive feature includes a gate structure, wherein the gate structure includes a gate electrode and a spacer adjacent to the gate electrode, wherein the abutment contact extends along both sidewalls of the spacer.

50. The method of producing a semiconductor according to claim 48, wherein patterning to form the first contact opening includes recessing a portion of an upper surface of the spacer.

51. The method of producing a semiconductor according to claim 50, wherein patterning to form the second contact opening includes recessing a portion of an upper surface of the spacer.

52. The method of producing a semiconductor according to claim 50, wherein removing at least a portion of the first dielectric layer after filling the merged contact opening with the conductive material.

53. The method of manufacturing a semiconductor according to Claim 48, further comprising:

54. A method of fabricating a semiconductor, comprising: forming a first conductive region and a second conductive region on a substrate, wherein the first conductive region and the second conductive region are separated by a first dielectric layer; forming one or more second dielectric layers over the first conductive region, the second conductive region, and the first dielectric layer; after forming the one or more second dielectric layers, forming an abutment contact opening, forming the abutment contact opening includes: ​ a first contact opening through the one or more second dielectric layers to the first conductive region is formed using a first process and a second contact opening through the one or more second dielectric layers to the second conductive region is formed using a second process, wherein the first process and the second process are performed sequentially, wherein the first dielectric layer protrudes above a bottom of the mating contact opening; and filling the mating contact opening with a conductive material to form a mating contact.

55. The method of producing a semiconductor according to claim 54, wherein a first interface between the mating contact and the first conductive region is lower than a second interface between the mating contact and the second conductive region.

56. The method of producing a semiconductor according to claim 55, wherein a vertical distance between the first interface and the second interface is less than 5 nm.

57. The method of producing a semiconductor according to claim 54, wherein the first dielectric layer has a slanted sidewall intersecting at an angle of 2° to 20°.

58. The method of producing a semiconductor according to claim 54, wherein the first dielectric layer is a spacer inserted between a gate structure and a source / drain region. the first dielectric layer is a spacer inserted between a gate structure and a source / drain region.

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