Semiconductor package including stress-balanced chip

Abstract

The present application provides a semiconductor package. The semiconductor package includes a chip stack having a plurality of semiconductor chips stacked vertically on a package substrate. A stress balancing chip is arranged on the chip stack, and the stress balancing chip is configured to provide a reduction in the variation of electrical characteristics between the plurality of semiconductor chips. A sealant is arranged on the package substrate and is configured to cover at least a portion of the chip stack. Each of the plurality of semiconductor chips is electrically connected to the package substrate. The stress balancing chip is not electrically connected to the substrate or the plurality of semiconductor chips.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0081546 filed on July 13, 2018 in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] A package according to example embodiments relates to a multi-chip semiconductor package including a stress-balanced chip on a chip stack. Background Art

[0004] Multi-chip semiconductor packages have advantages in reducing the weight, thickness and size of electronic devices, thereby miniaturizing semiconductor devices. Multi-chip semiconductor packages have a structure in which multiple semiconductor chips are stacked. The structure in which the multiple semiconductor chips are stacked is subjected to different amounts of stress depending on the stacking position of the semiconductor chips. Due to the occurrence of stress singularities, the distribution of electrical characteristics of multiple semiconductor chips increases. Certain stresses may cause piezoelectric effects, in which the electrical characteristics of a circuit change due to physical stress on the semiconductor chip. Summary of the invention

[0005] Example embodiments are directed to providing a semiconductor package capable of reducing distribution of specific electrical characteristics caused by specific stress and a method of forming the same.

[0006] According to an example embodiment, a semiconductor package includes a chip stack having a plurality of semiconductor chips stacked vertically on a package substrate. A stress equalization chip is arranged on the chip stack, and the stress equalization chip is configured to reduce the variation of electrical characteristics between the plurality of semiconductor chips. A sealant is arranged on the package substrate and is configured to cover at least a portion of the chip stack. Each of the plurality of semiconductor chips is electrically connected to the package substrate. The stress equalization chip is not electrically connected to the package substrate or the plurality of semiconductor chips.

[0007] According to an example embodiment that may include the above-described embodiment, a semiconductor package includes a chip stack having a plurality of semiconductor chips on a package substrate. A stress balancing chip as a dummy chip is arranged on the chip stack. A sealant is arranged on the package substrate and is configured to cover at least a portion of the chip stack. The plurality of semiconductor chips include an uppermost semiconductor chip arranged at an uppermost layer of the chip stack and a plurality of lower semiconductor chips below the uppermost semiconductor chip. Each of the plurality of semiconductor chips is separated from an adjacent semiconductor chip by a first vertical distance. The stress balancing chip is separated from the uppermost semiconductor chip by a first vertical distance.

[0008] According to an example embodiment, a semiconductor package includes a chip stack having a plurality of semiconductor chips stacked offset on a package substrate. A dummy chip is stacked on the chip stack and is arranged offset relative to the topmost semiconductor chip of the plurality of semiconductor chips, and has the same width and length as each of the plurality of semiconductor chips. A sealant is arranged on the package substrate and is configured to cover at least a portion of the chip stack. Each of the plurality of semiconductor chips includes a non-volatile memory. The dummy chip includes a semiconductor substrate, one or more metal layers, and one or more insulating layers, configured to reduce electrical characteristic variations between the plurality of semiconductor chips, and the dummy chip is not electrically connected to a circuit of the package substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1 to 3 is a cross-sectional view for describing a semiconductor package according to example embodiments.

[0010] Figure 4 and Figure 5 is a top view for describing a semiconductor package according to example embodiments.

[0011] Figures 6 to 17 is a cross-sectional view for describing a semiconductor package according to example embodiments. DETAILED DESCRIPTION

[0012] Figures 1 to 3 is a cross-sectional view for describing a semiconductor package according to example embodiments.

[0013] Reference Figure 1, a semiconductor package according to an example embodiment of the inventive concept may include a substrate 21, a plurality of protruding electrodes 23, a chip stack 30, a plurality of adhesives 41, a plurality of interconnections 45, a sealant 56, and a stress equalization chip 139. The substrate 21 may include a plurality of external terminals 24, an internal interconnection 25, and at least one internal terminal 27. The chip stack 30 may include a plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38. The plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 may include a first semiconductor chip 31, a second semiconductor chip 32, a third semiconductor chip 33, a fourth semiconductor chip 34, a fifth semiconductor chip 35, a sixth semiconductor chip 36, a seventh semiconductor chip 37, and an eighth semiconductor chip 38, which may be vertically stacked on the substrate 21. Each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 may include at least one stress sensitive region 149 and at least one chip pad 43.

[0014] The substrate 21 may include a package substrate such as a rigid printed circuit board, a flexible printed circuit board, a rigid-flexible printed circuit board, or a combination thereof. The substrate 21 may be a multilayer circuit board. The plurality of external terminals 24 may be arranged on the lower surface of the substrate 21, and the at least one internal terminal 27 may be arranged on the upper surface of the substrate 21. The at least one internal terminal 27 may be electrically connected to one selected from the plurality of external terminals 24 via an internal interconnection portion 25 within the substrate 21. Each of the plurality of protruding electrodes 23 may be formed on each of the plurality of external terminals 24.

[0015] The plurality of protruding electrodes 23 may include solder balls, conductive bumps, conductive sheets, conductive wires, or combinations thereof. The plurality of external terminals 24, the internal interconnection 25, and the at least one internal terminal 27 may include conductive materials such as metals, metal nitrides, conductive carbon, or combinations thereof. For example, the plurality of external terminals 24, the internal interconnection 25, and the at least one internal terminal 27 may include copper (Cu). The at least one internal terminal 27 may correspond to a bond finger. In example embodiments, the plurality of external terminals 24 and the plurality of protruding electrodes 23 may be selectively omitted. The substrate 21 may correspond to a mainboard or an interposer.

[0016] Each of the plurality of external terminals 24 and the at least one internal terminal 27 may be a conductive pad formed on the surface of the substrate 21 and having a flat surface, which may be coplanar with the surface of the substrate 21. In addition, the protruding electrode 23 may be referred to as an external terminal or an external package terminal by itself or in combination with the corresponding external terminal 24. The internal interconnection portion 25 may be referred to as an internal conductive interconnection portion or an internal wiring.

[0017] As used herein, a component described as being "electrically connected" is configured so that an electrical signal can be electrically transferred through the component from one component to another. Thus, a component such as a wire, pad, internal wire, transistor, capacitor, etc. that is physically connected to an electrically insulating component (e.g., a prepreg layer of a printed circuit board, an electrically insulating adhesive connecting two devices, an electrically insulating underfill or mold layer, etc.) and does not electrically transfer a signal through the electrically insulating component is not electrically connected to the component.

[0018] The plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37 and 38 may include a non-volatile memory, a volatile memory, a microprocessor, an application processor, a controller, an image sensor, or a combination thereof. In example embodiments, some of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37 and 38 may have different sizes. The semiconductor chips 31, 32, 33, 34, 35, 36, 37 and 38 may each be formed on a die from a wafer, and may include a semiconductor substrate, one or more integrated circuits formed on the semiconductor substrate, one or more conductive layers, and one or more insulating layers. Each semiconductor chip 31, 32, 33, 34, 35, 36, 37 and 38 includes external terminals described as external chip terminals that are electrically connected to other components outside the semiconductor chip and within the semiconductor package, and each semiconductor chip 31, 32, 33, 34, 35, 36, 37 and 38 is electrically connected to the circuit of the package substrate 21, and can be electrically connected to a device outside the semiconductor package through the circuit of the package substrate 21.

[0019] For example, the plurality of adhesives 41 (e.g., adhesive layers) may include a die attach film (DAF). The plurality of adhesives 41 may be attached to lower surfaces of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 and the stress equalization chip 139, respectively. The plurality of adhesives 41 may be attached between the first semiconductor chip 31 and the substrate 21, between the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38, and between the eighth semiconductor chip 38 and the stress equalization chip 139. The plurality of adhesives 41 may each have the same thickness (e.g., in the z-direction), and the chips 31, 32, 33, 34, 35, 36, 37, 38, and 139 may be vertically spaced equidistantly from each other (e.g., in the z-direction). In this manner, each of the plurality of semiconductor chips 31 , 32 , 33 , 34 , 35 , 36 , 37 and 38 is separated from adjacent semiconductor chips by a first vertical distance, and the stress equalization chip 139 may be separated from the uppermost semiconductor chip 38 by the same first vertical distance.

[0020] The at least one chip pad 43 may include a conductive material such as a metal, a metal nitride, a conductive carbon, or a combination thereof. For example, the at least one chip pad 43 may include Cu, Co, Al, Sn, Ni, Au, Ag, W, WN, Ti, TiN, Ta, TaN, Ru, Pt, or a combination thereof. The at least one chip pad 43 may be electrically connected to active or passive components included in the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38.

[0021] Each of the plurality of interconnects 45 may include a bonding wire, a beam lead (BL), a tape automated bonding (TAB), or a combination thereof. For example, each of the plurality of interconnects 45 may include Au, Al, Cu, Ag, or a combination thereof. The plurality of interconnects 45 may contact the at least one internal terminal 27 and the at least one chip pad 43. The term "contact" as used herein refers to a direct physical connection, for example, a touch. The plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 may be electrically connected to the substrate 21 via the plurality of interconnects 45. In an example embodiment, the plurality of interconnects 45 are not electrically connected to the stress balancing chip 139. The plurality of interconnects 45 may be insulated from the stress balancing chip 139. In a specific embodiment, the stress balancing chip 139 is not electrically connected to the substrate 21 or the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38. The stress-balance chip 139 may be electrically insulated from the substrate 21 and the plurality of semiconductor chips 31 , 32 , 33 , 34 , 35 , 36 , 37 , and 38 , and thus, in some embodiments, not communicate with other components in or outside the semiconductor package.

[0022] The sealant 56 may include an epoxy molding compound (EMC). The sealant 56 may cover at least a portion of the chip stack 30. In example embodiments, the sealant 56 may be formed on the substrate 21 to cover the side surfaces and upper portions of the chip stack 30, the stress equalization chip 139, and the plurality of interconnection portions 45. The side surfaces of the sealant 56 and the side surfaces of the substrate 21 may be substantially coplanar and exposed outside the semiconductor package.

[0023] As used herein, terms such as "same," "equal," "flat," or "coplanar" when referring to an orientation, layout, position, shape, size, amount, or other measurement do not necessarily mean exactly the same orientation, layout, position, shape, size, amount, or other measurement, but are intended to cover approximately the same orientation, layout, position, shape, size, amount, or other measurement within an acceptable range of variation that may be caused, for example, by manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning. For example, a term described as "substantially the same," "substantially equal," or "substantially flat" may be exactly the same, equal, or flat, or may be the same, equal, or flat within an acceptable range of variation that may be caused, for example, by manufacturing processes.

[0024] In example embodiments, the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 may be of the same type. The plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 may include the same type of memory. For example, each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 may include a non-volatile memory such as a flash memory having substantially the same size and substantially the same storage capacity. Each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 may have substantially the same size. Each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 may have substantially the same lateral width, substantially the same lateral length, and substantially the same thickness. Each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 may include the at least one stress sensitive region 149 at substantially the same position. The at least one stress sensitive region 149 may be adjacent to the at least one chip pad 43 .

[0025] The plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37 and 38 may be stacked on the substrate 21 in an offset order. The first semiconductor chip 31 may be arranged on the substrate 21. The second semiconductor chip 32 may be arranged offset on the first semiconductor chip 31. For example, the second semiconductor chip 32 may be arranged offset on the first semiconductor chip 31 by a predetermined distance in a lateral direction (e.g., y direction) along the length of the first semiconductor chip 31. From a top view, the second semiconductor chip 32 may overlap the at least one stress-sensitive region 149 in the first semiconductor chip 31. The second semiconductor chip 32 may be arranged to completely cover the at least one stress-sensitive region 149 in the first semiconductor chip 31. The third semiconductor chip 33 to the eighth semiconductor chip 38 may be arranged offset on the second semiconductor chip 32 in the same lateral direction as the second semiconductor chip 32, respectively, along the length of the lower semiconductor chip. The chip stack 30 may be described as a cascade stack, or as having a staircase structure.

[0026] The eighth semiconductor chip 38 may be arranged offset on the seventh semiconductor chip 37. From a top view, the eighth semiconductor chip 38 may overlap with the at least one stress-sensitive region 149 in the seventh semiconductor chip 37. Figure 1 As shown, in one embodiment, each semiconductor chip 31 to 38 in the chip stack 30 may overlap the at least one stress sensitive region 149 of the semiconductor chip immediately therebelow and may entirely overlap the at least one stress sensitive region 149 .

[0027] The stress balancing chip 139 may be arranged on the chip stack 30. The stress balancing chip 139 may be offset and arranged on the eighth semiconductor chip 38 in the same lateral direction as the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38. The offset distance d1 between the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 and the stress balancing chip 139 may be substantially the same. For example, the offset distance d1 between the stress balancing chip 139 and the eighth semiconductor chip 38 may be substantially the same as the offset distance d1 between the eighth semiconductor chip 38 and the seventh semiconductor chip 37. The stress balancing chip 139 may overlap the at least one stress sensitive region 149 in the eighth semiconductor chip 38. The horizontal widths (e.g., in the x-direction) of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 may be substantially the same as the horizontal width of the stress balancing chip 139. The lengths of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 (e.g., in the y direction) and the length of the stress equalization chip 139 may be substantially the same. The thickness or height (e.g., in the z direction) of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 and the stress equalization chip 139 may be substantially the same. The stress equalization chip 139 may be a dummy chip having substantially the same size (e.g., length and width) as each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38. The stress equalization chip 139 may have substantially the same thickness as each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38.

[0028] The electrical characteristics of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 may be changed by stress applied to the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 due to various mechanisms such as a piezoresistive effect. When the variation of the stress applied to each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 is large, the plurality of corresponding semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 may have different electrical characteristics. When the variation between the electrical characteristics of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 is large, it is difficult to design and operate a correction circuit for the chip stack 30.

[0029] The piezoresistive effect may include a phenomenon in which the spacing between silicon atoms and the electron mobility change due to stress applied to the channel region of the transistor. In example embodiments, the at least one stress sensitive region 149 may include a portion that is sensitive to the piezoresistive effect. When the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 are of the same type, the at least one stress sensitive region 149 may be generated at substantially the same position of each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38.

[0030] The stress equalization chip 139 may be used to reduce the variation of stress applied to each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38. The stress equalization chip 139 may be used to similarly control the position and size of stress singularities occurring in each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38. The stress equalization chip 139 may be used to equalize the stress applied to the eighth semiconductor chip 38 to be similar to the stress applied to each of the first semiconductor chip 31 to the seventh semiconductor chip 37. For example, the stress equalization chip 139 may be used as and configured to reduce the variation of electrical characteristics between the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 according to its composition, size, and position. The reduction of the variation of electrical characteristics between the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 may be beneficial to the design and operation of the correction circuit for the chip stack 30.

[0031] The first semiconductor chip 31 may correspond to the lowermost semiconductor chip arranged on the lowermost layer of the chip stack 30, and the eighth semiconductor chip 38 may correspond to the uppermost semiconductor chip arranged on the uppermost layer of the chip stack 30. In example embodiments, the seventh semiconductor chip 37 may correspond to the lower semiconductor chip, and the eighth semiconductor chip 38 may correspond to the upper semiconductor chip arranged on the lower semiconductor chip. In example embodiments, the sixth semiconductor chip 36 may correspond to the lower semiconductor chip, the seventh semiconductor chip 37 may correspond to the middle semiconductor chip arranged on the lower semiconductor chip, and the eighth semiconductor chip 38 may correspond to the uppermost semiconductor chip arranged on the middle semiconductor chip.

[0032] In example embodiments, the stress equalization chip 139 may include a semiconductor substrate, a metal plate, a metal nitride plate, a metal oxide plate, an insulating substrate, or a combination thereof or one or more thereof. The stress equalization chip 139 may include a semiconductor substrate, one or more metal layers, and one or more insulating layers. The substrate and / or one or more of these layers may be patterned.

[0033] In an example embodiment, stress equalization chip 139 is, for example, a dummy chip that is not electrically connected to substrate 21 (e.g., circuits of substrate 21) or any other chip of the semiconductor package. The stress equalization chip may or may not have circuits (e.g., internal wiring or integrated circuits) formed thereon.

[0034] In some embodiments, to ensure that each subsequent higher semiconductor chip in the chip stack 30 covers the stress-sensitive region 149 of the lower semiconductor chip, before each semiconductor chip is stacked on the lower chip, the lower semiconductor chip is tested to determine the stress-sensitive region 149. Then, based on the test results, the next semiconductor chip is arranged to cover the stress-sensitive region 149 of the lower chip. For the eighth semiconductor chip 38, the same test may be performed to determine the stress-sensitive region 149 of the eighth semiconductor chip 38, and then the stress-equalizing chip may be arranged to cover the determined stress-sensitive region 149.

[0035] In an exemplary embodiment of the inventive concept, the stress condition can effectively improve carrier mobility. Compressive strain in a PMOS transistor significantly improves hole mobility. Tensile strain in an NMOS transistor significantly improves electron mobility. The location of the stress sensitive region 149 can be determined by the location of the design and the density of sub-devices such as PMOS transistors.

[0036] Reference Figure 2 The stress equalization chip 139 may have a lateral width (e.g., a length in the y direction) smaller than a lateral width of each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38. One side surface of the stress equalization chip 139 may be substantially coplanar (e.g., along the x / z direction) with one side surface of the eighth semiconductor chip 38.

[0037] Reference Figure 3 , the lateral width (e.g., length in the y direction) of the stress equalization chip 139 may be different from the lateral width of each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38. The lateral width of the stress equalization chip 139 may be smaller than the lateral width of each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38. The stress equalization chip 139 may overlap with at least one stress sensitive region 149 in the eighth semiconductor chip 38.

[0038] In one embodiment, a plurality of interconnections 45 may be arranged between the stress balancing chip 139, the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38, and the substrate 21. The plurality of interconnections 45 may contact at least one chip pad 43 in the stress balancing chip 139. The stress balancing chip 139 may be electrically connected to the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 and the substrate 21 via the plurality of interconnections 45. The stress balancing chip 139 may include chips of a different type from the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38. For example, the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 may include a nonvolatile memory such as a flash memory or a magnetoresistive random access memory (MRAM), or a volatile memory such as a dynamic random access memory (DRAM). The stress-balancing chip 139 may include a logic chip such as a controller, a microprocessor, or an application processor.

[0039] Figure 4 and Figure 5 is a top view for describing a semiconductor package according to example embodiments.

[0040] Reference Figure 4 , a semiconductor package according to an example embodiment of the inventive concept may include a substrate 21, a chip stack 30, a plurality of interconnection portions 45, and a stress equalization chip 139. The substrate 21 may include a plurality of internal terminals 27. The chip stack 30 may include a plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38. Each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 may include at least one stress sensitive region 149 and a plurality of chip pads 43. The stress equalization chip 139 may include a plurality of chip pads 43.

[0041] The first semiconductor chip 31 may be arranged on the substrate 21. The second semiconductor chip 32 may be arranged offset on the first semiconductor chip 31. Similar to the second semiconductor chip 32, the third to eighth semiconductor chips 33 to 38 may be arranged offset in sequence on the second semiconductor chip 32. The stress equalization chip 139 may be arranged offset on the eighth semiconductor chip 38 in the same direction as the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38.

[0042] The size of the stress equalization chip 139 may be smaller than the size of each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38. The lateral width (e.g., length in the y direction) of the stress equalization chip 139 may be smaller than the lateral width of each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38. The horizontal width (e.g., in the x direction) of the stress equalization chip 139 may be smaller than the horizontal width of each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38. The stress equalization chip 139 may overlap the at least one stress sensitive region 149 in the eighth semiconductor chip 38.

[0043] The plurality of interconnection portions 45 may contact the plurality of internal terminals 27 and the plurality of chip pads 43. The plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 and the stress equalization chip 139 may be electrically connected to the substrate 21 via the plurality of interconnection portions 45. The stress equalization chip 139 may be electrically connected to the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 and the substrate 21 via the plurality of interconnection portions 45.

[0044] Reference Figure 5 , a semiconductor package according to example embodiments of the inventive concepts may include a substrate 21 , a chip stack 30 , a plurality of interconnection portions 45 , a ninth semiconductor chip 139A, and a stress equalization chip 139 . The ninth semiconductor chip 139A may include a plurality of chip pads 43 .

[0045] The ninth semiconductor chip 139A may be arranged on the eighth semiconductor chip 38 with an offset in the same direction as the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38. The size of the ninth semiconductor chip 139A may be smaller than the size of each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38. The lateral width of the ninth semiconductor chip 139A may be smaller than the lateral width of each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38. The horizontal width of the ninth semiconductor chip 139A may be smaller than the horizontal width of each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38. The plurality of interconnection portions 45 may contact the plurality of internal terminals 27 and the plurality of chip pads 43. The ninth semiconductor chip 139A may be electrically connected to the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37 and 38 and the substrate 21 via the plurality of interconnections 45. The ninth semiconductor chip 139A may alternatively be disposed on at least one stress sensitive region 149 in the eighth semiconductor chip 38.

[0046] The ninth semiconductor chip 139A may include chips of different types from the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38. For example, the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 may include a nonvolatile memory such as a flash memory or an MRAM, or a volatile memory such as a DRAM, etc. The ninth semiconductor chip 139A may include a logic chip such as a controller, a microprocessor, or an application processor.

[0047] The stress balancing chip 139 may be arranged on the eighth semiconductor chip 38 offset in the same direction as the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37 and 38. The stress balancing chip 139 may be arranged adjacent to the ninth semiconductor chip 139A (e.g., in the x direction). The size of the stress balancing chip 139 may be smaller than the size of each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37 and 38. The lateral width of the stress balancing chip 139 may be smaller than the lateral width of each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37 and 38. The horizontal width of the stress balancing chip 139 may be smaller than the horizontal width of each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37 and 38. The stress balancing chip 139 may overlap the at least one stress sensitive region 149 in the eighth semiconductor chip 38. The plurality of interconnection portions 45 are not electrically connected to the stress balancing chip 139. The stress-balancing chip 139 may be a dummy chip having a size different from that of each of the plurality of semiconductor chips 31 , 32 , 33 , 34 , 35 , 36 , 37 and 38 , and may be electrically insulated from (and therefore not electrically connected to) the plurality of semiconductor chips 31 , 32 , 33 , 34 , 35 , 36 , 37 and 38 or the substrate 21 .

[0048] Figures 6 to 17 is a cross-sectional view for describing a semiconductor package according to example embodiments.

[0049] Reference Figure 6 , the upper surface of the stress balancing chip 139 may be exposed to the outside of the semiconductor package. The upper surface of the sealant 56 and the upper surface of the stress balancing chip 139 are substantially coplanar. The stress balancing chip 139 may be a dummy chip having substantially the same size as each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38.

[0050] Reference Figure 7, the upper surface of the stress equalization chip 139 may be exposed outside the semiconductor package. The upper surface of the sealant 56 and the upper surface of the stress equalization chip 139 are substantially coplanar. The stress equalization chip 139 may be a dummy chip having a lateral width greater than a lateral width of each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38. In example embodiments, at least one side surface of the stress equalization chip 139 and at least one side surface of the sealant 56 are substantially coplanar.

[0051] Reference Figure 8 , a semiconductor package according to an example embodiment of the inventive concept may include a substrate 21, a plurality of protruding electrodes 23, a chip stack 30, a plurality of adhesives 41, a plurality of interconnections 45 and 46, a sealant 56, and a stress equalization chip 139. The substrate 21 may include a plurality of external terminals 24, an internal interconnection 25, and a plurality of internal terminals 27 and 28.

[0052] The first semiconductor chip 31 may be arranged on the substrate 21. The second semiconductor chip 32 may be arranged offset on the first semiconductor chip 31. For example, the second semiconductor chip 32 may be arranged offset on the first semiconductor chip 31 by a predetermined distance in the first lateral direction. The second semiconductor chip 32 may overlap with at least one stress sensitive region 149 in the first semiconductor chip 31. Similar to the second semiconductor chip 32, the third semiconductor chip 33 and the fourth semiconductor chip 34 may be arranged offset on the second semiconductor chip 32 in sequence. At least one chip pad 43 of each of the first semiconductor chip 31 to the fourth semiconductor chip 34 may contact the first interconnection portion 45. One end of the first interconnection portion 45 may contact the first internal terminal 27.

[0053] The fifth semiconductor chip 35 may be arranged offset on the fourth semiconductor chip 34. For example, the fifth semiconductor chip 35 may be arranged offset on the fourth semiconductor chip 34 by a predetermined distance in the first lateral direction. The fifth semiconductor chip 35 may overlap with at least one stress sensitive region 149 in the fourth semiconductor chip 34. At least one chip pad 43 in the fifth semiconductor chip 35 may be arranged at a position relatively far from the first interconnection portion 45.

[0054] The sixth semiconductor chip 36 may be arranged offset on the fifth semiconductor chip 35. For example, the sixth semiconductor chip 36 may be arranged offset on the fifth semiconductor chip 35 by a predetermined distance in a second lateral direction different from the first lateral direction. The second lateral direction may be opposite to the first lateral direction. The sixth semiconductor chip 36 may overlap the at least one stress sensitive region 149 in the fifth semiconductor chip 35. Similar to the sixth semiconductor chip 36, the seventh semiconductor chip 37 and the eighth semiconductor chip 38 may be arranged offset on the sixth semiconductor chip 36 in sequence. The at least one chip pad 43 of each of the fifth semiconductor chip 35 to the eighth semiconductor chip 38 may contact the second interconnection portion 46. One end of the second interconnection portion 46 may contact the second internal terminal 28.

[0055] The stress equalization chip 139 may be arranged on the eighth semiconductor chip 38 in an offset manner in the same direction as the sixth to eighth semiconductor chips 36 to 38. The stress equalization chip 139 may overlap the at least one stress sensitive region 149 in the eighth semiconductor chip 38.

[0056] Reference Fig. 9 , the second semiconductor chip 32 may be arranged offset on the first semiconductor chip 31. For example, the second semiconductor chip 32 may be arranged offset on the first semiconductor chip 31 by a predetermined distance in the first lateral direction. At least one chip pad 43 in the first semiconductor chip 31 may be arranged relatively close to the first internal terminal 27. At least one chip pad 43 in the second semiconductor chip 32 may be arranged relatively close to the second internal terminal 28.

[0057] The third semiconductor chip 33 may be arranged offset on the second semiconductor chip 32. For example, the third semiconductor chip 33 may be arranged offset by a predetermined distance in a second lateral direction different from the first lateral direction on the second semiconductor chip 32. At least one chip pad 43 in the third semiconductor chip 33 may be arranged relatively close to the first internal terminal 27.

[0058] The fourth semiconductor chip 34 may be offset on the third semiconductor chip 33. For example, the fourth semiconductor chip 34 may be offset on the third semiconductor chip 33 by a predetermined distance in the first lateral direction. At least one chip pad 43 in the fourth semiconductor chip 34 may be arranged relatively close to the second internal terminal 28.

[0059] The fifth semiconductor chip 35 may be offset on the fourth semiconductor chip 34. For example, the fifth semiconductor chip 35 may be offset on the fourth semiconductor chip 34 by a predetermined distance in the second lateral direction. At least one chip pad 43 in the fifth semiconductor chip 35 may be arranged relatively close to the first internal terminal 27.

[0060] The sixth semiconductor chip 36 may be offset on the fifth semiconductor chip 35. For example, the sixth semiconductor chip 36 may be offset on the fifth semiconductor chip 35 by a predetermined distance in the first lateral direction. At least one chip pad 43 in the sixth semiconductor chip 36 may be arranged relatively close to the second internal terminal 28.

[0061] The seventh semiconductor chip 37 may be offset on the sixth semiconductor chip 36. For example, the seventh semiconductor chip 37 may be offset on the sixth semiconductor chip 36 by a predetermined distance in the second lateral direction. At least one chip pad 43 in the seventh semiconductor chip 37 may be arranged relatively close to the first internal terminal 27.

[0062] The eighth semiconductor chip 38 may be offset on the seventh semiconductor chip 37. For example, the eighth semiconductor chip 38 may be offset on the seventh semiconductor chip 37 by a predetermined distance in the first lateral direction. At least one chip pad 43 in the eighth semiconductor chip 38 may be arranged relatively close to the second internal terminal 28.

[0063] The first semiconductor chip 31, the third semiconductor chip 33, the fifth semiconductor chip 35, and the seventh semiconductor chip 37 may be vertically aligned. The side surfaces of the first semiconductor chip 31, the side surfaces of the third semiconductor chip 33, the side surfaces of the fifth semiconductor chip 35, and the side surfaces of the seventh semiconductor chip 37 may be substantially coplanar. The first interconnection portion 45 may contact the at least one chip pad 43 of each of the first semiconductor chip 31, the third semiconductor chip 33, the fifth semiconductor chip 35, and the seventh semiconductor chip 37. The first semiconductor chip 31, the third semiconductor chip 33, the fifth semiconductor chip 35, and the seventh semiconductor chip 37 may be electrically connected to the first internal terminal 27 in the substrate 21 via the first interconnection portion 45.

[0064] The second semiconductor chip 32, the fourth semiconductor chip 34, the sixth semiconductor chip 36, and the eighth semiconductor chip 38 may be vertically aligned. The side surfaces of the second semiconductor chip 32, the side surfaces of the fourth semiconductor chip 34, the side surfaces of the sixth semiconductor chip 36, and the side surfaces of the eighth semiconductor chip 38 may be substantially coplanar. The second interconnection portion 46 may contact the at least one chip pad 43 of each of the second semiconductor chip 32, the fourth semiconductor chip 34, the sixth semiconductor chip 36, and the eighth semiconductor chip 38. The second semiconductor chip 32, the fourth semiconductor chip 34, the sixth semiconductor chip 36, and the eighth semiconductor chip 38 may be electrically connected to the second internal terminal 28 in the substrate 21 via the second interconnection portion 46. The chip stack 30 may be understood as a zigzag stack.

[0065] The stress equalization chip 139 may be arranged offset on the eighth semiconductor chip 38 in the second lateral direction. The stress equalization chip 139 may overlap the at least one stress sensitive region 149 in the eighth semiconductor chip 38. The stress equalization chip 139 may be vertically aligned with the first semiconductor chip 31, the third semiconductor chip 33, the fifth semiconductor chip 35, and the seventh semiconductor chip 37. The side surfaces of the stress equalization chip 139, the side surfaces of the first semiconductor chip 31, the side surfaces of the third semiconductor chip 33, the side surfaces of the fifth semiconductor chip 35, and the side surfaces of the seventh semiconductor chip 37 may be substantially coplanar. The respective adhesives 41 may have the same thickness (e.g., in the vertical direction).

[0066] Reference Fig.10 , the first semiconductor chip 31 to the eighth semiconductor chip 38 may be sequentially and vertically stacked on the substrate 21. A plurality of adhesives 41 may be attached between the substrate 21 and the first semiconductor chip 31 and between the first semiconductor chip 31 to the eighth semiconductor chip 38. The side surfaces of the first semiconductor chip 31 to the eighth semiconductor chip 38 may be substantially coplanar. A plurality of interconnection portions 45 and 46 may pass through the plurality of adhesives 41 to contact at least one chip pad 43 of each of the first semiconductor chip 31 to the eighth semiconductor chip 38.

[0067] The stress equalization chip 139 may be arranged on the eighth semiconductor chip 38. The stress equalization chip 139 may overlap with at least one stress sensitive region 149 in the eighth semiconductor chip 38. In example embodiments, the stress equalization chip 139 may be vertically aligned with the first to eighth semiconductor chips 31 to 38. Side surfaces of the stress equalization chip 139 and side surfaces of the first to eighth semiconductor chips 31 to 38 may be substantially coplanar. The sealant 56 may be formed to cover the side surfaces and upper portions of the chip stack 30, the stress equalization chip 139, and the plurality of interconnection portions 45 and 46.

[0068] Reference Fig.11 The lateral width of the stress equalization chip 139 may be smaller than the lateral width of the eighth semiconductor chip 38 . The stress equalization chip 139 may overlap with at least one stress sensitive region 149 in the eighth semiconductor chip 38 .

[0069] Reference Fig.12 The upper surface of the stress balancing chip 139 may be exposed outside the semiconductor package. The upper surface of the stress balancing chip 139 and the upper surface of the sealant 56 may be substantially coplanar.

[0070] Reference Fig.13The lateral width of the stress balancing chip 139 may be greater than the lateral width of the eighth semiconductor chip 38. The upper surface and side surfaces of the stress balancing chip 139 may be exposed outside the semiconductor package. The side surfaces of the stress balancing chip 139 and the side surfaces of the sealant 56 may be substantially coplanar.

[0071] Reference Fig.14 , a semiconductor package according to an example embodiment of the inventive concept may include a substrate 21, a plurality of protruding electrodes 23, a chip stack 30, a plurality of adhesives 41, a plurality of interconnections 47 and 48, a sealant 56, and a stress equalization chip 139. The substrate 21 may include a plurality of external terminals 24, an internal interconnection 25, and a plurality of internal terminals 29. The plurality of interconnections 47 and 48 may include a plurality of conductive bumps 47 and a plurality of through silicon vias (TSVs) 48. The chip stack 30 may include a plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38. Each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38 may include at least one stress sensitive region 149.

[0072] The first semiconductor chip 31 to the eighth semiconductor chip 38 may be stacked sequentially and vertically on the substrate 21. The side surfaces of the first semiconductor chip 31 to the eighth semiconductor chip 38 may be substantially coplanar. The plurality of adhesives 41 may be attached between the substrate 21 and the first semiconductor chip 31, between the first semiconductor chip 31 to the eighth semiconductor chip 38, and between the eighth semiconductor chip 38 and the stress equalization chip 139. The plurality of adhesives 41 may include an underfill such as a non-conductive resin. Each of the plurality of TSVs 48 may pass through each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38. The plurality of conductive bumps 47 may be arranged between the substrate 21 and the first semiconductor chip 31, between the first semiconductor chip 31 to the eighth semiconductor chip 38, and between the eighth semiconductor chip 38 and the stress equalization chip 139. The plurality of conductive bumps 47 may pass through the plurality of adhesives 41 to contact the plurality of internal terminals 29 and the plurality of TSVs 48. The plurality of semiconductor chips 31 , 32 , 33 , 34 , 35 , 36 , 37 , and 38 may be electrically connected to the substrate 21 via the plurality of interconnections 47 and 48 .

[0073] The stress equalization chip 139 may be arranged on the eighth semiconductor chip 38. The stress equalization chip 139 may overlap the at least one stress sensitive region 149 in the eighth semiconductor chip 38. In example embodiments, the stress equalization chip 139 may be vertically aligned with the first to eighth semiconductor chips 31 to 38. The stress equalization chip 139 may have substantially the same lateral width as each of the plurality of semiconductor chips 31, 32, 33, 34, 35, 36, 37, and 38. The side surface of the stress equalization chip 139 and the side surface of the first to eighth semiconductor chips 31 to 38 may be substantially coplanar. The sealant 56 may be formed to cover the side surfaces and upper portion of the chip stack 30 and the stress equalization chip 139.

[0074] Reference Fig.15 The upper surface of the stress equalization chip 139 may be exposed outside the semiconductor package. The upper surface of the stress equalization chip 139 and the upper surface of the sealant 56 may be substantially coplanar.

[0075] Reference Fig.16 The lateral width of the stress balancing chip 139 may be greater than the lateral width of the eighth semiconductor chip 38. The upper surface and side surfaces of the stress balancing chip 139 may be exposed outside the semiconductor package. The side surfaces of the stress balancing chip 139 and the side surfaces of the sealant 56 may be substantially coplanar.

[0076] Reference Fig.17 The lateral width of the stress equalization chip 139 may be smaller than the lateral width of the eighth semiconductor chip 38 . The stress equalization chip 139 may overlap with at least one stress sensitive region 149 in the eighth semiconductor chip 38 .

[0077] According to an example embodiment of the inventive concept, a stress balancing chip is arranged on a chip stack having a plurality of semiconductor chips. The uppermost semiconductor chip of the plurality of semiconductor chips may include at least one stress sensitive region. The stress balancing chip may overlap the at least one stress sensitive region. The stress balancing chip may be used to reduce the variation of stress applied to each of the plurality of semiconductor chips. Due to the role of the stress balancing chip, the distribution of electrical characteristics of the plurality of semiconductor chips may be significantly reduced. Therefore, a semiconductor package with high electrical characteristics may be realized.

[0078] Although the embodiments of the present invention have been described with reference to the accompanying drawings, it should be understood by those skilled in the art that various modifications may be made without departing from the scope of the present invention and without changing its basic features. Therefore, the above embodiments should be viewed only in a descriptive sense and not for a limiting purpose.

Claims

1. A semiconductor package, comprising: a chip stack having a plurality of semiconductor chips vertically stacked on a package substrate; a stress balancing chip disposed on the chip stack, the stress balancing chip being configured to reduce variations in electrical characteristics between the plurality of semiconductor chips; as well as an encapsulant disposed on the package substrate and configured to cover at least a portion of the chip stack, wherein each of the plurality of semiconductor chips is electrically connected to the package substrate, and the stress equalization chip is not electrically connected to the package substrate or the plurality of semiconductor chips, wherein each of the plurality of semiconductor chips comprises at least one stress-sensitive region; The plurality of semiconductor chips include a lower semiconductor chip and an upper semiconductor chip arranged on the lower semiconductor chip, and The upper semiconductor chip overlaps the at least one stress-sensitive region of the lower semiconductor chip, wherein the plurality of semiconductor chips include an uppermost semiconductor chip arranged at an uppermost layer of the chip stack; and The stress equalization chip overlaps with the at least one stress sensitive region of the uppermost semiconductor chip and is disposed on the uppermost semiconductor chip without any other semiconductor chip formed therebetween, and The center of the stress equalization chip is not aligned with the center of the uppermost semiconductor chip.

2. The semiconductor package according to claim 1, wherein: The stress equalization chip and each of the plurality of semiconductor chips have the same width in a first direction.

3. The semiconductor package according to claim 1, wherein: The lower semiconductor chip is arranged on the package substrate; The upper semiconductor chip is arranged on the lower semiconductor chip in an offset manner along the length of the lower semiconductor chip; The uppermost semiconductor chip is arranged on the upper semiconductor chip offset along the length of the upper semiconductor chip, and The stress equalization chips are arranged on the uppermost semiconductor chip in an offset manner along the length of the uppermost semiconductor chip.

4. The semiconductor package according to claim 3, wherein: The uppermost semiconductor chip is arranged offset in the same direction as the direction in which the upper semiconductor chip is arranged offset with respect to the lower semiconductor chip; and The stress equalization chip is arranged offset in the same direction as the direction in which the uppermost semiconductor chip is arranged offset with respect to the upper semiconductor chip.

5. The semiconductor package according to claim 3, wherein: The uppermost semiconductor chip is arranged offset relative to the upper semiconductor chip in a direction different from the direction in which the upper semiconductor chip is arranged offset relative to the lower semiconductor chip; and The stress equalization chip is arranged offset relative to the uppermost semiconductor chip in a direction different from a direction in which the uppermost semiconductor chip is arranged offset relative to the upper semiconductor chip.

6. The semiconductor package according to claim 3, wherein: The offset distance between the stress equalization chip and the uppermost semiconductor chip is the same as the offset distance between the uppermost semiconductor chip and the upper semiconductor chip.

7. The semiconductor package according to claim 3, wherein: The stress equalization chip has a width in the first direction that is smaller than a width of each of the lower semiconductor chip, the upper semiconductor chip, and the uppermost semiconductor chip in the first direction.

8. The semiconductor package according to claim 1, wherein: A first adhesive is formed under the stress equalization chip, and a second adhesive is formed under each of the plurality of semiconductor chips, and wherein the first adhesive and the second adhesive have the same thickness.

9. The semiconductor package according to claim 1, wherein: The sealant covers the upper surface and the side surfaces of the stress equalization chip.

10. The semiconductor package according to claim 1, wherein An upper surface of the encapsulant and an upper surface of the stress balance chip are coplanar, and the stress balance chip is exposed outside the semiconductor package.

11. The semiconductor package according to claim 1, wherein: The plurality of semiconductor chips and the stress equalization chip are arranged in a staircase structure.

12. The semiconductor package according to claim 11, wherein: The stress-balancing chip is a dummy chip that does not communicate with the plurality of semiconductor chips or the package substrate, and The stress equalization chip has the same width and length as each of the plurality of semiconductor chips.

13. A semiconductor package, comprising: a chip stack having a plurality of semiconductor chips on a package substrate; A stress balancing chip, which is arranged on the chip stack, and the stress balancing chip is a dummy chip; as well as an encapsulant disposed on the package substrate and configured to cover at least a portion of the chip stack, wherein the plurality of semiconductor chips include an uppermost semiconductor chip arranged at an uppermost layer of the chip stack and a plurality of lower semiconductor chips below the uppermost semiconductor chip, Each semiconductor chip in the plurality of semiconductor chips is separated from an adjacent semiconductor chip by a first vertical distance, wherein the stress balancing chip is separated from the uppermost semiconductor chip by the first vertical distance, wherein the stress balancing chip is not electrically connected to the package substrate, The stress equalization chip covers the stress sensitive area of ​​the uppermost semiconductor chip, and The center of the stress equalization chip is not aligned with the center of the uppermost semiconductor chip.

14. The semiconductor package according to claim 13, wherein: Each of the plurality of semiconductor chips has the same lateral width and horizontal width; and The stress equalization chip has the same lateral width and horizontal width as each of the plurality of semiconductor chips.

15. The semiconductor package according to claim 13, wherein: The plurality of semiconductor chips and the stress equalization chip are arranged in a staircase structure.

16. The semiconductor package according to claim 13, wherein: The stress-balancing chip is arranged offset relative to the uppermost semiconductor chip of the plurality of semiconductor chips; and The dummy chip includes a semiconductor substrate, one or more metal layers, and one or more insulating layers, is configured to reduce electrical characteristic variations among the plurality of semiconductor chips, and is not electrically connected to a circuit of the package substrate.

17. The semiconductor package according to claim 16, wherein: The plurality of semiconductor chips and the dummy chip are arranged in a staircase structure.

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