Semiconductor packaging

Abstract

A semiconductor package is disclosed, comprising: a packaging substrate; a first semiconductor chip on the packaging substrate, the first semiconductor chip comprising a first region and a second region; a second semiconductor chip on the first region; a heat radiation spacer on the second region; a third semiconductor chip supported by the second semiconductor chip and the heat radiation spacer; and a molding layer covering the first semiconductor chip to the third semiconductor chip and the heat radiation spacer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0084510 filed in the Korean Intellectual Property Office on Jul. 20, 2018, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The inventive concept relates to a semiconductor package, and more particularly, to a semiconductor package including a heat radiation spacer. Background Art

[0004] With the rapid development of the electronics industry and in response to customer needs, electronic devices have been manufactured to be reduced in size and / or lightweight and have higher capacity. Semiconductor packages including many semiconductor chips have been developed. Semiconductor packages including multiple semiconductor chips of various types and sizes have been developed. Summary of the invention

[0005] Some example embodiments of the inventive concepts provide a semiconductor package capable of effectively releasing heat generated from a semiconductor chip.

[0006] According to some example embodiments conceived in the present invention, a semiconductor package may include: a packaging substrate; a first semiconductor chip on the packaging substrate, including a first region and a second region; a second semiconductor chip in the first region; a thermal radiation spacer in the second region; a third semiconductor chip supported by the second semiconductor chip and the thermal radiation spacer; and a molding layer covering the first semiconductor chip to the third semiconductor chip and the thermal radiation spacer.

[0007] According to some example embodiments conceived in the present invention, a semiconductor package may include: a packaging substrate; a first semiconductor chip on the packaging substrate, including a first region and a second region; a thermal radiation spacer on the first semiconductor chip, the thermal radiation spacer including: a base, the base including a first segment in the first region and a second segment in the second region, and a protrusion on the second segment; a second semiconductor chip on the first segment; a third semiconductor chip supported by the second semiconductor chip and the protrusion; and a molding layer covering the first semiconductor chip to the third semiconductor chip and the thermal radiation spacer.

[0008] According to some example embodiments of the present inventive concept, a semiconductor package may include: a package substrate; a first semiconductor chip on the package substrate, including a first region and a second region; a pair of second semiconductor chips spaced apart from each other in the first region; a heat radiation spacer in the second region; a pair of third semiconductor chips on corresponding ones of the pair of second semiconductor chips; and a molding layer covering the first to third semiconductor chips and the heat radiation spacer. Each third semiconductor chip may include: a first section on the second semiconductor chip; and a second section on the heat radiation spacer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A Plan views illustrating semiconductor packages according to some example embodiments of the inventive concepts are illustrated.

[0010] Figure 1B Shown along Figure 1A A cross-sectional view taken along line AA′.

[0011] Figure 1C Shown along Figure 1A A cross-sectional view taken along line BB′.

[0012] Figure 2A and Figure 3A A plan view illustrating a method of manufacturing a semiconductor package according to some example embodiments of the inventive concepts is shown.

[0013] Figure 2B and 3B Shown are Figure 2A and 3A A cross-sectional view taken along line AA′.

[0014] Figure 2C and 3C Shown are Figure 2A and 3A A cross-sectional view taken along line BB′.

[0015] Figure 4A Plan views illustrating semiconductor packages according to some example embodiments of the inventive concepts are illustrated.

[0016] Figure 4B Shown along Figure 4A A cross-sectional view taken along line AA′.

[0017] Figure 5 Plan views illustrating semiconductor packages according to some example embodiments of the inventive concepts are illustrated.

[0018] Fig. 6A Shown along Figure 1A A cross-sectional view taken along line AA′.

[0019] Figure 6B Shown along Figure 1A A cross-sectional view taken along line BB'. DETAILED DESCRIPTION

[0020] Figure 1A Plan views illustrating semiconductor packages according to some example embodiments of the inventive concepts are illustrated. Figure 1B Shown along Figure 1A A cross-sectional view taken along line AA′. Figure 1C Shown along Figure 1A A cross-sectional view taken along line BB′.

[0021] refer to Figures 1A to 1C , a substrate 100 may be provided. The package substrate 100 may be a printed circuit board (PCB) having a circuit pattern.

[0022] The external terminals 105 may be disposed on the bottom surface of the package substrate 100. The external terminals 105 may be, but are not limited to, solder balls, conductive bumps, conductive spacers, pin grid arrays, etc. The external terminals 105 may electrically connect the package substrate 100 to an external electrical device (not shown).

[0023] The first semiconductor chip SC1 may be disposed on the package substrate 100. The first semiconductor chip SC1 may include a memory circuit, a logic circuit, or a combination thereof. The first semiconductor chip SC1 may include a first region RG1 and a second region RG2. A heat source 111 may be embedded in the second region RG2 of the first semiconductor chip SC1. The heat source 111 may be a central processing unit (CPU), a memory interface, a universal serial bus (USB), or other intellectual property (IP) block. The term "IP block" may mean a block that configures the functions required to constitute a semiconductor integrated circuit in a hardware or software manner. The heat sources 111 may be spaced apart from each other in the first semiconductor chip SC1, which may result in minimization or reduction of electrical and / or thermal interference between the heat sources 111. When the first semiconductor chip SC1 is operated, the heat generated from the second region RG2 may be greater than the heat generated from the first region RG1.

[0024] The first semiconductor chip SC1 and the package substrate 100 can be electrically connected to each other through the connection terminal 112 provided therebetween. When viewed in a plane, the connection terminals 112 can be spaced apart from each other. The connection terminals 112 can have a solder or bump shape. The connection terminals 112 can include a conductive material. For example, the connection terminals 112 can include one or more of tin (Sn), lead (Pb), nickel (Ni), gold (Au), silver (Ag), copper (Cu) and bismuth (Bi).

[0025] An underfill layer 114 may be provided to fill the gap between the first semiconductor chip SC1 and the package substrate 100. The underfill layer 114 may be formed by an underfill process, in which an underfill paste is applied and then cured. The underfill paste may be, for example, an epoxy-based material that does not contain conductive particles. The underfill layer 114 may surround the surface of the connection terminal 112.

[0026] In some example embodiments different from the illustrated example embodiment, the first semiconductor chip SC1 may be electrically connected to the package substrate 100 using wire bonding.

[0027] A pair of second semiconductor chips SC2 may be disposed on the first region RG1 of the first semiconductor chip SC1. The second semiconductor chip SC2 may have a first length along the first direction D1 and a second length along the second direction D2. The first length may be greater than the second length. The first direction D1 and the second direction D2 may intersect each other and may be parallel to the top surface of the package substrate 100. The pair of second semiconductor chips SC2 may be spaced apart from each other along the second direction D2.

[0028] The first adhesive layer AL1 may be disposed between the second semiconductor chip SC2 and the first semiconductor chip SC1. The second semiconductor chip SC2 may be adhered to the top surface of the first semiconductor chip SC1 through the first adhesive layer AL1. The first adhesive layer AL1 may be, for example, a direct adhesive film (DAF) or a film on wire (FOW). For example, the first adhesive layer AL1 may include a dielectric material. The first adhesive layer AL1 may electrically insulate the first semiconductor chip SC1 and the second semiconductor chip SC2 from each other.

[0029] The heat radiation spacer 140 may be disposed on the second region RG2 of the first semiconductor chip SC1. The heat radiation spacer 140 may extend along the second direction D2. The heat radiation spacer 140 may vertically overlap with the heat source 111 embedded in the second region RG2 of the first semiconductor chip SC1. The heat radiation spacer 140 may guide the release of heat generated from the first semiconductor chip SC1. In some example embodiments, the heat radiation spacer 140 may receive heat generated from the first semiconductor chip SC1. For example, the heat generated from the heat source 111 may be transferred to the heat radiation spacer 140. The heat radiation spacer 140 may include a material with high thermal conductivity. For example, the heat radiation spacer 140 may include copper (Cu) or silver (Ag). The heat radiation spacer 140 may include a material with strong adhesion. For example, the heat radiation spacer 140 may include an adhesive polymer. For another example, the heat radiation spacer 140 may include an adhesive polymer in which copper (Cu) or silver (Ag) particles are distributed.

[0030] A third semiconductor chip SC3 may be disposed on each second semiconductor chip SC2. The third semiconductor chip SC3 may be offset stacked on the second semiconductor chip SC2. For example, a third semiconductor chip SC3 partially exposing the top surface of the second semiconductor chip SC2 may be stacked on the second semiconductor chip SC2. A pair of third semiconductor chips SC3 may be spaced apart from each other along the second direction D2. The third semiconductor chip SC3 may have a top surface at a height substantially the same as that of the top surface of the heat radiation spacer 140.

[0031] The second adhesive layer AL2 may be disposed between the third semiconductor chip SC3 and the second semiconductor chip SC2. The second adhesive layer AL2 may include a material substantially the same as that of the first adhesive layer AL1.

[0032] The fourth semiconductor chip SC4 may be disposed on the heat radiation spacer 140 and each of the third semiconductor chips SC3. For example, a portion of the fourth semiconductor chip SC4 may be disposed on the third semiconductor chip SC3, and the other portion of the fourth semiconductor chip SC4 may be disposed on the heat radiation spacer 140. In this configuration, the fourth semiconductor chip SC4 may be supported by the third semiconductor chip SC3 and the heat radiation spacer 140. The fourth semiconductor chip SC4 may be offset and stacked on the third semiconductor chip SC3. The fourth semiconductor chip SC4 may span the heat radiation spacer 140. A pair of fourth semiconductor chips SC4 may be spaced apart from each other along the second direction D2.

[0033] The third adhesive layer AL3 may be disposed between the fourth semiconductor chip SC4 and the third semiconductor chip SC3 and between the fourth semiconductor chip SC4 and the heat radiation spacer 140. The third adhesive layer AL3 may include a material substantially the same as that of the first adhesive layer AL1. The fourth semiconductor chip SC4 may be adhered to the top surfaces of the third semiconductor chip SC3 and the heat radiation spacer 140 through the third adhesive layer AL3.

[0034] A fifth semiconductor chip SC5 may be disposed on each fourth semiconductor chip SC4. The fifth semiconductor chip SC5 may be offset-stacked on the fourth semiconductor chip SC4. A pair of fifth semiconductor chips SC5 may be spaced apart from each other in the second direction D2.

[0035] Each of the second to fifth semiconductor chips SC2 to SC5 may include a memory circuit, a logic circuit, or a combination thereof. Each of the second to fifth semiconductor chips SC2 to SC5 may be a semiconductor chip of a different type from the first semiconductor chip SC1. For example, the first semiconductor chip SC1 may be a logic chip including a logic circuit, and each of the second to fifth semiconductor chips SC2 to SC5 may be a memory chip including a plurality of memory cells. In some example embodiments, the first semiconductor chip SC1 may manage and control the operation of the second to fifth semiconductor chips SC2 to SC5, and the heat generated from the first semiconductor chip SC1 may be greater than the heat generated from each or all of the second to fifth semiconductor chips SC2 to SC5.

[0036] The fourth adhesive layer AL4 may be disposed between the fifth semiconductor chip SC5 and the fourth semiconductor chip SC4. The fourth adhesive layer AL4 may include a material substantially the same as that of the first adhesive layer AL1.

[0037] The connection pad 181 may be provided on each semiconductor chip in the first semiconductor chip SC1 to the fifth semiconductor chip SC5. The connection pad 181 may be a terminal for inputting or outputting an electrical signal to or from each semiconductor chip in the first semiconductor chip SC1 to the fifth semiconductor chip SC5. The connection pad 181 may include a conductive material. For example, the connection pad 181 may include one or more of gold (Au), silver (Ag), copper (Cu), nickel (Ni), aluminum (Al), tin (Sn), lead (Pb), platinum (Pt), bismuth (Bi), indium (In) and alloys thereof.

[0038] A bonding wire 182 may be provided to connect the connection pads 181 to each other. The bonding wire 182 may electrically connect the first semiconductor chip SC1 to the fifth semiconductor chip SC5 to each other. The bonding wire 182 may include a conductive material. For example, the bonding wire 182 may include one or more of gold (Au), silver (Ag), copper (Cu), aluminum (Al) and alloys thereof.

[0039] In some example embodiments different from the illustrated embodiment, flip chip bonding may be used to electrically connect the first to fifth semiconductor chips SC1 to SC5 to each other. In some example embodiments, instead of the first to fourth adhesive layers AL1 to AL4, connection terminals and an underfill layer may be provided between the first to fifth semiconductor chips SC1 to SC5.

[0040] The mold layer 190 may be disposed on the package substrate 100. The mold layer 190 may cover the lateral surfaces and top surfaces of the first to fifth semiconductor chips SC1 to SC5. The mold layer 190 may also cover the lateral surfaces and top surfaces of the heat radiation spacer 140. For example, the mold layer 190 may include epoxy molding compound (EMC).

[0041] A thermal path pattern 191 may be provided to penetrate the mold layer 190. The thermal path pattern 191 may be provided on the heat radiation spacer 140. When viewed in a plane, the thermal path patterns 191 may be spaced apart from each other. Each thermal path pattern 191 may be provided on an edge of the heat radiation spacer 140 or between a pair of third semiconductor chips SC3. The thermal path pattern 191 may extend in a vertical direction, for example, along a third direction D3. Each thermal path pattern 191 may have a thermal conductivity greater than that of the mold layer 190. The thermal path pattern 191 may include a conductive material and / or an adhesive polymer. For example, the conductive material may include aluminum (Al), tin (Sn), copper (Cu), silver (Ag), aluminum oxide (Al2O3), or the like. 2 O 3 ), zinc oxide (ZnO), silicon carbide (SiC), aluminum nitride (AlN), boron nitride (BN), diamond, and combinations thereof. Heat generated from the first semiconductor chip SC1 may be transferred to the heat path pattern 191 through the heat radiation spacer 140 .

[0042] The heat radiation member 192 may be disposed on the mold layer 190. The heat radiation member 192 may include a material with high thermal conductivity. For example, the heat radiation member 192 may include one of a thermal slag, a heat sink, and a graphite sheet. The heat radiation member 192 may receive and externally release heat generated from the first semiconductor chip SC1.

[0043] The heat transfer layer 193 may be inserted between the mold layer 190 and the heat radiation member 192. The heat transfer layer 193 may be connected to the heat path pattern 191. The heat transfer layer 193 may extend between the mold layer 190 and the heat radiation member 192. The heat transfer layer 193 may include the same material as that of the heat path pattern 191. For example, the heat transfer layer 193 may include a conductive material and / or an adhesive polymer. The heat radiation member 192 may be adhered to the mold layer 190 through the heat transfer layer 193. The heat generated from the first semiconductor chip SC1 may be transferred to the heat radiation member 192 through the heat transfer layer 193. Compared with a case where neither the heat transfer layer 193 nor the heat radiation member 192 is provided, the semiconductor package according to the present invention can improve the operational reliability of the first semiconductor chip SC1.

[0044] Figure 2A and Figure 3AA plan view illustrating a method of manufacturing a semiconductor package according to some example embodiments of the inventive concepts is shown. Figure 2B and 3B Shown are Figure 2A and 3A A cross-sectional view taken along line AA′. Figure 2C and 3C Shown are Figure 2A and 3A A cross-sectional view taken along line BB′.

[0045] To simplify the description, refer to Figures 1A to 1C Components that are substantially the same as those discussed are assigned the same reference numerals, and duplicate descriptions thereof are omitted.

[0046] refer to FIG. 2A to FIG. 2C , a package substrate 100 may be prepared. External terminals 105 may be formed on the bottom surface of the package substrate 100. A first semiconductor chip SC1 may be provided on the package substrate 100. A connection terminal 112 may be formed to electrically connect the first semiconductor chip SC1 and the package substrate 100 to each other. An underfill layer 114 may be formed to fill a gap between the first semiconductor chip SC1 and the package substrate 100. The underfill layer 114 may be formed by an underfill process, in which an underfill slurry is applied and then cured. In some example embodiments different from the illustrated example embodiment, the first semiconductor chip SC1 may be electrically connected to the package substrate 100 using wire bonding.

[0047] The second semiconductor chips SC2 may be disposed on the first region RG1 of the first semiconductor chip SC1. Each of the second semiconductor chips SC2 may be adhered to a top surface of the first semiconductor chip SC1 through a first adhesive layer AL1.

[0048] The third semiconductor chip SC3 may be disposed on each of the second semiconductor chips SC2. The third semiconductor chips SC3 may be offset-stacked on the second semiconductor chips SC2. Each of the third semiconductor chips SC3 may be adhered to the top surface of the second semiconductor chip SC2 through the second adhesive layer AL2.

[0049] The heat radiation spacer 140 may be formed on the second region RG2 of the first semiconductor chip SC1. For example, the heat radiation spacer 140 may be formed by coating and curing a paste including a material with high thermal conductivity on the second region RG2 of the first semiconductor chip SC1. For another example, the heat radiation spacer 140 may be formed by providing a film including a material with high thermal conductivity on the second region RG2 of the first semiconductor chip SC1. The heat radiation spacer 140 may be formed before or after providing the second semiconductor chip SC2 and the third semiconductor chip SC3. The heat source 111 may be embedded in the second region RG2 of the first semiconductor chip SC1. The heat radiation spacer 140 may vertically overlap with the heat source 111.

[0050] refer to FIG. 3A to FIG. 3C , a fourth semiconductor chip SC4 may be disposed on each of the heat radiation spacer 140 and the third semiconductor chip SC3. For example, the fourth semiconductor chip SC4 may be supported by the third semiconductor chip SC3 and the heat radiation spacer 140. The fourth semiconductor chip SC4 may be offset and stacked on the third semiconductor chip SC3. The fourth semiconductor chip SC4 may be adhered to the top surface of the third semiconductor chip SC3 and the heat radiation spacer 140 by a third adhesive layer AL3.

[0051] A fifth semiconductor chip SC5 may be disposed on each fourth semiconductor chip SC4. The fifth semiconductor chip SC5 may be offset-stacked on the fourth semiconductor chip SC4. Each fifth semiconductor chip SC5 may be adhered to a top surface of the fourth semiconductor chip SC4 through a fourth adhesive layer AL4.

[0052] The bonding wires 182 may be formed to electrically connect the connection pads 181 provided on each of the first to fifth semiconductor chips SC1 to SC5 to one another. The bonding wires 182 may electrically connect the first to fifth semiconductor chips SC1 to SC5 to one another.

[0053] In some example embodiments different from the illustrated embodiment, flip chip bonding may be used to electrically connect the first to fifth semiconductor chips SC1 to SC5 to each other. In some example embodiments, instead of the first to fourth adhesive layers AL1 to AL4, connection terminals and an underfill layer may be formed between the first to fifth semiconductor chips SC1 to SC5.

[0054] A mold layer 190 may be formed on the package substrate 100 . The mold layer 190 may cover lateral surfaces and top surfaces of the first to fifth semiconductor chips SC1 to SC5 . The mold layer 190 may also cover lateral surfaces and top surfaces of the heat radiation spacers 140 .

[0055] Return to reference Figures 1A to 1C , a thermal path pattern 191 may be formed to penetrate the mold layer 190. The formation of the thermal path pattern 191 may include removing a portion of the mold layer 190 to form an opening to expose the heat radiation spacer 140, and filling the opening with a conductive material and / or an adhesive polymer. The formation of the opening may include performing laser drilling to remove a portion of the mold layer 190. Because the opening is formed on the heat radiation spacer 140, the first semiconductor chip SC1 may be reduced or prevented from being damaged by the laser drilling.

[0056] The heat transfer layer 193 may be formed on the mold layer 190. The formation of the heat transfer layer 193 may include coating a conductive material and / or an adhesive polymer on the mold layer 190. The heat transfer layer 193 may be connected to each of the thermal path patterns 191.

[0057] The heat radiation member 192 may be formed on the heat transfer layer 193. The heat transfer layer 193 may attach the heat radiation member 192 to the mold layer 190. When the heat radiation member 192 includes a graphite sheet, the heat transfer layer 193 and the heat radiation member 192 may be attached to the mold layer 190 at the same time.

[0058] Figure 4A Plan views illustrating semiconductor packages according to some example embodiments of the inventive concepts are illustrated. Figure 4B Shown along Figure 4A A cross-sectional view taken along line AA′.

[0059] To simplify the description, refer to Figures 1A to 1C Components that are substantially the same as those discussed are assigned the same reference numerals, and duplicate descriptions thereof are omitted.

[0060] refer to Figure 4A and Figure 4B , the heat radiation spacer 140 may include a substrate 141 and a protrusion 142. The substrate 141 may include a first section 141a and a second section 141b. The first section 141a may be disposed on the first region RG1 of the first semiconductor chip SC1. The second section 141b may be disposed on the second region RG2 of the first semiconductor chip SC1. The protrusion 142 may be disposed on the second section 141b. The protrusion 142 may protrude along a third direction D3 on the second section 141b of the substrate 141. For example, the protrusion 142 may have a top surface at a height higher than that of the top surface of the substrate 141. The protrusion 142 may extend along the second direction D2. The protrusion 142 may vertically overlap with the heat source 111 embedded in the second region RG2 of the first semiconductor chip SC1.

[0061] The second semiconductor chip SC2 may be disposed on the first section 141 a of the base 141 of the heat radiation spacer 140 . The second semiconductor chip SC2 may be attached to the first section 141 a by adhesion of the heat radiation spacer 140 .

[0062] The third semiconductor chip SC3 may be disposed on each of the second semiconductor chips SC2 . The third semiconductor chip SC3 may have a top surface at substantially the same height as that of the top surface of the protrusion 142 of the heat radiation spacer 140 .

[0063] The fourth semiconductor chip SC4 may be disposed on the protrusion 142 of the heat radiation spacer 140 and each of the third semiconductor chips SC3. For example, a portion of the fourth semiconductor chip SC4 may be disposed on the third semiconductor chip SC3, and the other portion of the fourth semiconductor chip SC4 may be disposed on the protrusion 142 of the heat radiation spacer 140. The fourth semiconductor chip SC4 may be adhered to the top surfaces of the third semiconductor chips SC3 and the top surfaces of the protrusions 142 of the heat radiation spacer 140 by the second adhesive layer AL2.

[0064] Figure 5 Plan views illustrating semiconductor packages according to some example embodiments of the inventive concepts are illustrated.

[0065] To simplify the description, refer to Figures 1A to 1C Components that are substantially the same as those discussed are assigned the same reference numerals, and duplicate descriptions thereof are omitted.

[0066] refer to Figure 5 , a pair of heat radiation spacers 140 may be disposed on the second region RG2 of the first semiconductor chip SC1. The heat radiation spacers 140 may be spaced apart from each other along the second direction D2. The heat radiation spacers 140 may individually support the fourth semiconductor chip SC4. For example, one heat radiation spacer 140 may support one fourth semiconductor chip SC4. Each heat radiation spacer 140 may vertically overlap with the heat source 111 embedded in the second region RG2 of the first semiconductor chip SC1.

[0067] Fig. 6A Shown along Figure 1A A cross-sectional view taken along line AA′. Figure 6B Shown along Figure 1A A cross-sectional view taken along line BB'.

[0068] To simplify the description, refer to Figures 1A to 1C Components that are substantially the same as those discussed are assigned the same reference numerals, and duplicate descriptions thereof are omitted.

[0069] refer to Figure 1A , Fig. 6A and Figure 6B , the third adhesive layer AL3 may be selectively disposed between the fourth semiconductor chip SC4 and the third semiconductor chip SC3, but not between the fourth semiconductor chip SC4 and the heat radiation spacer 140. In some example embodiments, the heat radiation spacer 140 may have a top surface at substantially the same height as that of the top surface of the third adhesive layer AL3, and the fourth semiconductor chip SC4 may directly contact the heat radiation spacer 140. Attachment of the fourth semiconductor chip SC4 may be achieved by adhesion of the heat radiation spacer 140.

[0070] According to example embodiments of the inventive concepts, a semiconductor package may include a heat radiation spacer between semiconductor chips, and thus may effectively release heat generated from the semiconductor chips.

[0071] Although the exemplary embodiments of the inventive concept have been described in conjunction with the exemplary embodiments of the inventive concept in the accompanying drawings, it should be understood by those skilled in the art that various changes and modifications may be made without departing from the technical spirit and basic features of the inventive concept. It is obvious to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the inventive concept.

Claims

1. A semiconductor package, comprising: Package substrate; The first semiconductor chip on the packaging substrate includes a first region and a second region; a second semiconductor chip on the first region; a heat radiating spacer on the second region; a third semiconductor chip supported by the second semiconductor chip and the heat radiation spacer; a fourth semiconductor chip, on the third semiconductor chip; a molding layer covering the first semiconductor chip to the fourth semiconductor chip and the heat radiation spacer; a heat radiation member on the molding layer; as well as a heat transfer layer interposed between the mold layer and the heat radiation member, Wherein, the fourth semiconductor chip covers the top surface of the heat radiation spacer.

2. The semiconductor package according to claim 1, wherein The first semiconductor chip includes a heat source in the second region.

3. The semiconductor package according to claim 2, wherein: The heat source vertically overlaps the heat radiating spacer.

4. The semiconductor package according to claim 1, further comprising: A heat path pattern penetrates the mold layer and is connected to the heat radiation spacer.

5. The semiconductor package according to claim 4, in, The heat transfer layer connects the heat path pattern to the heat radiation member.

6. The semiconductor package according to claim 1, further comprising: An adhesive layer is between the third semiconductor chip and the second semiconductor chip and between the third semiconductor chip and the heat radiation spacer.

7. The semiconductor package according to claim 1, further comprising: an adhesive layer between the third semiconductor chip and the second semiconductor chip, Wherein, the third semiconductor chip directly contacts the heat radiation spacer.

8. A semiconductor package, comprising: Package substrate; The first semiconductor chip on the packaging substrate includes a first region and a second region; The heat radiation spacer on the first semiconductor chip comprises: a substrate comprising a first section in the first region and a second section in the second region, and a protrusion on the second section; a second semiconductor chip on the first section; a third semiconductor chip supported by the second semiconductor chip and the protrusions; and A molding layer covers the first to third semiconductor chips and the heat radiation spacer.

9. The semiconductor package according to claim 8, wherein: The first semiconductor chip includes a heat source in the second region.

10. The semiconductor package according to claim 9, wherein The heat source vertically overlaps the protrusion.

11. The semiconductor package according to claim 8, wherein: A height of a top surface of the protrusion is substantially the same as a height of a top surface of the second semiconductor chip.

12. The semiconductor package according to claim 8, wherein The bump and the third semiconductor chip are in direct contact with each other.

13. The semiconductor package according to claim 8, further comprising: a thermal path pattern penetrating the mold layer and connected to the protrusion; as well as a heat radiation member, on the mold layer, Wherein, the thermal conductivity of the thermal path pattern is greater than the thermal conductivity of the molding layer.

14. The semiconductor package according to claim 13, further comprising: a heat transfer layer between the mold layer and the heat radiation member, Wherein, the heat transfer layer comprises the same material as that of the thermal path pattern.

15. A semiconductor package, comprising: Package substrate; The first semiconductor chip on the packaging substrate includes a first region and a second region; a pair of second semiconductor chips spaced apart from each other in the first region; a heat radiating spacer in the second region; a pair of third semiconductor chips on the pair of second semiconductor chips; as well as a molding layer covering the first semiconductor chip to the third semiconductor chip and the heat radiation spacer, Wherein, each of the third semiconductor chips comprises: a first section, on the corresponding second semiconductor chip; and The second section is on the heat radiation spacer.

16. The semiconductor package according to claim 15, wherein: The heat radiation spacer includes a pair of heat radiation spacers, Each heat radiation spacer supports the second section of the corresponding third semiconductor chip.

17. The semiconductor package according to claim 16, wherein: The first semiconductor chip includes a plurality of heat sources, the plurality of heat sources being in the second region, Wherein, each of the heat sources vertically overlaps with the heat radiation spacer.

18. The semiconductor package according to claim 15, further comprising: a heat path pattern penetrating the mold layer and connected to the heat radiating spacer; as well as A heat radiation member is on the molding layer.

19. The semiconductor package according to claim 18, wherein: The thermal path pattern comprises a plurality of thermal path patterns, At least one of the thermal path patterns is between the pair of third semiconductor chips.

20. The semiconductor package according to claim 18, wherein The thermal path pattern comprises a plurality of thermal path patterns, Wherein, at least one of the heat path patterns is on an edge of the heat radiation spacer.

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