Device and method for self-testing a phase-locked loop using pseudo-random noise

Abstract

A device includes a signal control circuit system, a phase locked loop (PLL), and a correlation circuit. The signal control circuit system provides a reference clock signal carrying pseudo-random phase noise and as derived from an application clock signal and the pseudo-random noise. The PLL provides an output signal correlated with the phase of the reference clock signal in response to the reference clock signal carrying the pseudo-random phase noise. The correlation circuit self-tests the PLL by cross-correlating a signal corresponding to the output signal from the phase detector with the pseudo-random noise and in response by evaluating the result of the cross-correlation relative to a known threshold indicating a performance level of the PLL.

Description

Technical Field

[0001] Aspects of various embodiments relate to devices and methods thereof related to self-testing a phase-locked loop (PLL) of the device using pseudo-random noise. Background Art

[0002] PLLs provide control to various applications by generating an output signal that is related to the phase of one or more input signals. PLL parameters may affect the overall performance of an integrated circuit (IC) and are used in various applications. Some applications may involve compliance with standards that require PLL parameters to be within various limits and in many cases require that the PLL parameters remain within various limits over the life of the circuit.

[0003] These and other issues present challenges for self-testing PLL implementations for various applications. Summary of the invention

[0004] Various example embodiments are directed to problems such as those mentioned above and / or other problems that may become apparent from the following disclosure, which is directed to self-testing one or more phase-locked loop (PLL) parameters of a PLL by adding pseudo-random noise to the input signal of a phase detector of the PLL.

[0005] In certain example embodiments, aspects of the present disclosure relate to self-testing a PLL of a device after production testing and / or when the device is in the field. The self-test may occur each time the device is powered on, at periodic intervals, and / or continuously (e.g., simultaneously with an application mode of the device).

[0006] In a more specific example embodiment, a device includes a signal control circuit system, a PLL, and a correlation circuit. The signal control circuit system provides a reference clock signal carrying pseudo-random phase noise. For example, the input application clock signal can be phase modulated to generate the reference clock signal carrying the pseudo-random phase noise as the input of the PLL. As described further herein, the pseudo-random noise can be generated or can be noise present in the system and can be used to modulate the application clock signal to generate the reference clock signal having or including the pseudo-random phase noise. The PLL includes a phase detector that responds to the reference clock signal carrying the pseudo-random phase noise (e.g., generates an output signal related to the phase difference between the input signal and the feedback signal of the PLL) by providing an output signal related to the phase of the transmitted one of the at least two output signals derived from the application clock signal. The correlation circuit performs self-testing on the PLL by cross-correlating a signal corresponding to the output signal from the phase detector with the pseudo-random noise and by evaluating the result of the cross-correlation relative to a known threshold indicating the performance level of the PLL.

[0007] In some specific embodiments, the signal control circuit system includes a signal delay control circuit, which responds to the control signal carrying the pseudo-random noise and the application clock signal by transmitting one of at least two output signals as the reference clock signal, the at least two output signals being derived from the application clock signal and including at least one output signal delayed relative to another of the at least two output signals. The transmitted signal is the reference clock signal input to the PLL and includes or carries the pseudo-random phase noise (e.g., the phase is modulated by the pseudo-random noise to result in a reference clock signal including the pseudo-random phase noise). The delayed signal can be provided by the signal delay circuit. The PLL includes a phase detector, which responds to the reference clock signal (e.g., one of the at least two output signals from the signal delay control circuit) by providing an output signal related to the phase of the transmitted one of the at least two output signals derived from the application clock signal (e.g., generating an output signal related to the phase difference between the input signal and the feedback signal of the PLL).

[0008] In various embodiments, the signal delay circuit is integrated with the signal delay control circuit system. For example, the device may include a variable delay line circuit that integrates the signal delay circuit and the signal delay control circuit. In other embodiments, the signal delay circuit and the signal delay control circuit are separate, but still cooperate as described below. The signal delay circuit can provide a delayed clock signal relative to the application clock signal to the signal delay control circuit, and the signal delay control circuit (e.g., a multiplexer) transmits one of the output signals derived from the application clock signal and the delayed clock signal as the reference clock signal phase-modulated by the pseudo-random noise and inputs it to the PLL (the reference clock signal carries or includes the pseudo-random phase noise).

[0009] The PLL may include the phase detector, a loop filter, an oscillator, and a feedback loop. The loop filter filters a phase error signal as output by the phase detector. The phase error signal is proportional to a phase difference between the one of the reference clock signal (e.g., the at least two output signals from the signal delay control circuit) and a feedback signal from the PLL. The oscillator provides an output in response to the filtered phase error signal, and the feedback loop including a feedback divider circuit provides the feedback signal to the phase detector in response to the output of the oscillator.

[0010] The correlation circuit may derive a PLL pulse response from the cross-correlation, the cross-correlation being used to derive one or more PLL parameters. The PLL pulse response may include an pulse response of the phase error or may be derived directly from the cross-correlation. In a specific embodiment, the correlation circuit includes at least one adding circuit and a filter circuit, the filter circuit being used to derive the PLL pulse response from the cross-correlation obtained using the folded product of the phase error (e.g., the output of the phase detector) of the PLL and the pseudo-random noise. In other embodiments, the correlation circuit includes at least one adding circuit and a filter circuit, the filter circuit being used to derive an impulse response from the difference between the cross-correlation of the phase error of the PLL and the pseudo-random noise and the autocorrelation of the pseudo-random noise. For example, the correlation circuit may derive an impulse response of the phase error from the difference between the input phase and the output phase and the cross-correlation of the pseudo-random noise and derive the PLL pulse response from the cross-correlation according to the difference between the autocorrelation of the pseudo-random noise and the impulse response of the phase error. The PLL impulse response may be estimated by inverting a difference between the impulse response of the phase error and the autocorrelation of the pseudorandom noise, although embodiments are not limited thereto.

[0011] According to a number of embodiments, a self-test of the PLL is performed after production testing (e.g., when the device is in the field). The self-test of the PLL may occur simultaneously with the processing of the application signal, each time the device is powered on, periodically (simultaneously or not simultaneously with the processing of the application signal), and / or continuously. In some embodiments, such as when the processing of the application signal is performed simultaneously with the self-test of the PLL, at least a portion of the pseudo-random phase noise is removed from the output signal provided as an output from the PLL using a previously generated pseudo-random phase noise. The amount of the previously generated pseudo-random phase noise may be determined (e.g., using the pseudo-random noise) and used to remove at least a portion of the (next) pseudo-random phase noise. In such an example embodiment, the device may include a noise reduction circuit system for removing at least a portion of the pseudo-random phase noise from the output of the PLL using a cross-correlation of a previous signal corresponding to another output signal from the phase detector and another control signal carrying pseudo-random noise.

[0012] In various specific embodiments, one or more actions may be performed based on the self-test. For example, the evaluation of the cross-correlation may indicate a circuit failure. In response to the indication of a circuit failure, the device performs an action based on the failure, such as re-running the self-test, providing an error message, restarting the device, powering down the device, and various combinations thereof.

[0013] In addition, various specific embodiments may include multiple changes relative to what is described above. For example, as further described herein, the pseudo-random phase noise may have a spectrum and amplitude that (is intended to) jitter the input clock and / or the PLL includes an all-digital PLL (ADPLL) with a digital loop filter and the phase detector provides a digital signal. In some specific embodiments, it is determined whether the PLL is locked before evaluating the PLL. For example, the output signal and input signal from the PLL are used to determine whether the PLL is locked, and the PLL is self-tested in response to determining that the PLL is locked.

[0014] In other embodiments, the present disclosure relates to methods using specific embodiments of the circuits disclosed herein and including providing a reference clock signal carrying pseudo-random phase noise. For example, the reference clock signal and the noise can be combined by providing a control signal carrying the pseudo-random noise and using the control signal to transmit one of at least two output signals derived from an application clock signal as the reference clock signal carrying the pseudo-random phase noise (e.g., modulating the application clock signal with the noise so as to cause the reference clock signal to include or otherwise carry the pseudo-random phase noise). The method may further include self-testing the PLL by cross-correlating a signal corresponding to the output signal from the phase detector with the pseudo-random noise and evaluating the result of the cross-correlation relative to a known threshold indicating the performance level of the PLL in response.

[0015] The cross-correlation can be used to determine one or more PLL parameters. For example, the method may include self-testing the PLL by calculating a phase margin using the cross-correlation. For example, the phase margin is calculated using the impulse response as derived from the cross-correlation and the phase margin is compared to the known threshold, the known threshold indicating at least one of a phase margin limit and a previously calculated phase margin. In response to the comparison or evaluation indicating a circuit failure, the method may include performing an action based on the failure, the action selected from the group consisting of: providing an error message, restarting the device, powering off the device, and a combination thereof. In various specific embodiments, the method includes processing an application signal while the PLL simultaneously provides the output signal, the output signal having a phase related to the phase of the transmitted one of the at least two output signals derived from the application clock signal.

[0016] As another specific embodiment, the phase transfer function may be determined from the cross-correlation and at least one component of the PLL may be fine-tuned in response to the determined phase transfer function. One or more PLL parameters or a phase error transfer function may be derived from the phase transfer function.

[0017] The above discussion / summary is not intended to describe each embodiment or every implementation of the present disclosure. The following figures and detailed description also illustrate various embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Various example embodiments may be more fully understood upon consideration of the following detailed description in conjunction with the accompanying drawings, in which:

[0019] Figure 1 An example device according to the present disclosure is shown;

[0020] Figure 2A-2B An example device according to the present disclosure is shown;

[0021] Figure 3 An example PLL according to the present disclosure is shown;

[0022] Figure 4 An example of a process for self-testing a PLL of a device according to the present disclosure is shown;

[0023] Figure 5 An example device according to the present disclosure is shown;

[0024] Figure 6 shows a graph illustrating the use of noise correlation to estimate a phase transfer function in accordance with the present disclosure;

[0025] Figure 7 shows a graph showing a simulated PLL impulse response after subtracting the autocorrelation of pseudorandom noise, a sliding average, and an impulse response calculated from PLL closed loop parameters in accordance with the present disclosure;

[0026] Figure 8 shows a graph showing derived PLL parameters according to the present disclosure;

[0027] Fig. 9 An example correlation circuit for processing phase error as a PLL impulse response according to the present disclosure is shown;

[0028] Figures 10A-10B An example correlation circuit using phase error to derive a PLL pulse response according to the present disclosure is shown; and

[0029] Fig.11 Examples of low pass filters according to various embodiments are shown.

[0030] Although the various embodiments discussed herein are suitable for modification and alternative forms, various aspects of the embodiments have been shown by way of example in the accompanying drawings and will be described in detail. However, it should be understood that the intent is not to limit the present disclosure to the specific embodiments described. On the contrary, the intent is to cover all modifications, equivalents, and alternatives that fall within the scope of the present disclosure, including those defined in the claims. In addition, as used throughout this application, the term "example" is illustrative only and not restrictive. DETAILED DESCRIPTION

[0031] Aspects of the present disclosure are considered to be applicable to various different types of devices, systems and methods involving self-testing a phase-locked loop (PLL) by combining pseudo-random noise with an input signal of the PLL. In certain embodiments, when pseudo-random noise is added to the context of a control signal for switching the PLL input between an application clock signal and one or more delayed clock signals, aspects of the present disclosure have been shown to be beneficial. Although not necessarily so limited, aspects can be understood by the following discussion of non-limiting examples using exemplary contexts.

[0032] Therefore, in the following description, various specific details are set forth to describe the specific examples presented herein. However, it should be apparent to those skilled in the art that one or more other examples and / or variations of these examples may be practiced without all the specific details given below. In other examples, in order not to obscure the description of the examples herein, well-known features are not described in detail. For ease of illustration, the same reference numerals may be used in different figures to refer to the same element or other examples of the same element. And, although aspects and features may be described in a single figure in some cases, it should be understood that features from one figure or embodiment may be combined with features of another figure or embodiment, even if the combination is not explicitly shown or explicitly described as a combination.

[0033] A PLL is a circuit that generates an output signal with a phase related to the phase of an input signal, such as a reference clock signal. A PLL can be used to maintain a well-defined phase, and therefore frequency, relationship between two input sources. A PLL can have an oscillator that is constantly adjusted to match the frequency of an input reference clock signal. An example PLL can be used to generate, stabilize, modulate, demodulate, filter and / or recover a signal from a noisy communication channel where data may have been damaged. PLL parameters may affect the overall performance of an integrated circuit. For example, a glitch or undervoltage of a reference clock signal may cause a PLL or system lock failure, which may be beneficial to detect. For safety-sensitive integrated circuits and other applications, such as in automobiles, because performance parameters may change over time due to circuit system defects and / or aging, it may be beneficial to measure one or more PLL parameters during the service life of the device.

[0034] Embodiments according to the present disclosure relate to devices and methods for self-testing a PLL using a built-in self-test (BIST). As further described herein, a BIST can be used to measure one or more PLL parameters by adding pseudo-random noise to an input signal of the PLL, such as a reference clock signal (e.g., a reference phase input or a reference frequency input) that is phase modulated by the pseudo-random noise. The PLL is self-tested by cross-correlating the pseudo-random noise with the output signal of the phase detector of the PLL. The result of the correlation allows the calculation of an impulse response of a phase error, which can be interchangeably referred to as an impulse response at the output of the phase detector relative to the input phase and can be used to calculate a phase margin and other PLL parameters. The impulse response of the phase error can be related to the output response of the PLL (e.g., the impulse response of the system or the PLL impulse response). For example, the impulse response of the phase error is the sum of the negative impulse response of the system and a Dirac pulse, and thus the impulse response of the phase error and the frequency spectrum of the PLL impulse response are similar and can be used to characterize the system. The PLL can be self-tested each time the device is powered on, periodically / or continuously (e.g., simultaneously with the application mode). Self-testing performed concurrently with the application mode can allow detection of false faults, which are sometimes referred to as single event upsets (SEUs). Some standards may mandate detection of SEUs and / or mandate proof of adequate diagnostic coverage of SEUs. As described further herein, self-testing of the PLL may specify a straightforward way to provide diagnostic coverage.

[0035] The device according to various embodiments includes a signal control circuit system, a PLL and a correlation circuit. The signal control circuit is used to provide a reference clock signal carrying pseudo-random phase noise, such as by modulating the clock signal with pseudo-random noise. For example, pseudo-random noise is used to modulate the clock signal, which produces a reference clock signal including pseudo-random phase noise. The PLL including a phase detector responds to the reference clock signal carrying pseudo-random phase noise by providing an output signal (e.g., a phase error signal) related to the phase of the reference clock signal (and the feedback signal provided to the PLL). As described in addition herein, the correlation circuit is self-tested by cross-correlating a signal corresponding to an output signal (e.g., a phase error signal or a phase difference signal) from the phase detector with the pseudo-random noise and in response by evaluating the result of the cross-correlation relative to a known threshold indicating the performance level of the PLL.

[0036] In a specific embodiment, the signal control circuit system may include a signal delay circuit and a signal delay control circuit. In various embodiments, the signal delay circuit may be integrated with the signal delay control circuit or include different circuits. The signal delay circuit provides a delayed signal relative to the application clock signal to the signal delay control circuit. As further shown herein, the signal delay control circuit may include a multiplexer and / or a variable delay line (the variable delay line integrates the signal delay circuit). The signal delay control circuit transmits one of at least two output signals derived from the application clock signal as a reference clock signal, and the reference clock signal is the input of the PLL. The transmitted reference clock signal includes the application clock signal or at least one output signal delayed based on a control signal carrying pseudo-random noise relative to another output signal of the at least two output signals of the PLL. In some embodiments, the multiplexer is used to transmit the application clock signal or an output signal delayed based on a control signal carrying pseudo-random noise relative to the application clock signal. In other embodiments, the variable delay line is used to output the application clock signal or one of a plurality of signals delayed based on a control signal carrying pseudo-random noise (and the variable delay line is used to select a delay path). The pseudo-random noise is thereby used to modulate the application clock signal by the signal control circuit system, which outputs a reference clock signal carrying the pseudo-random phase noise. More specifically, the signal control circuit system modulates the application clock signal with the pseudo-random noise, which results in modulating the phase of the application clock signal (e.g., the zero crossings of the modulated signal) to generate a reference clock signal carrying or including the pseudo-random phase noise. The control signal selects the reference clock signal from one of the application clock signal or the delayed signal, and the resulting reference clock signal carries the pseudo-random phase noise.

[0037] In a specific embodiment, the PLL may include a phase detector, a loop filter, an oscillator, and a feedback loop. The phase detector generates an output signal (e.g., an output voltage, an output current, or an output digital signal such as a digital word as described elsewhere herein) that is proportional to the phase difference between its inputs (or otherwise indicates the phase difference), which may be referred to as a phase error signal or a phase difference signal. The first input is a reference clock signal that depends on a control signal (e.g., the control signal is used to switch between an application clock signal and one or more delayed clock signals). As described above, the reference clock signal carries pseudo-random phase noise. The second input is related to the output of the oscillator. The loop filter filters the phase error signal as output by the phase detector. As described above, the phase error signal may be proportional to the phase difference between the reference clock signal and a feedback signal from the PLL. The oscillator provides an output signal in response to the filtered phase error signal, for example, by generating an oscillating electronic signal. The feedback loop provides a feedback signal to the phase detector in response to the output signal of the oscillator. The feedback loop may include a feedback divider circuit that divides the output signal of the oscillator.

[0038] As described above, in a specific embodiment, the self-test of the PLL can include phase modulating the application clock signal using pseudo-random noise to generate a reference clock signal including or carrying pseudo-random phase noise. For example, the reference clock signal can be generated by providing a control signal that combines the pseudo-random noise with the control signal of the device. The pseudo-random noise can be generated by the noise generation circuit of the device and mixed with the input signal of the PLL (for example, for phase modulation) by switching between the application clock signal and the delayed phase-shifted version of the application clock signal (depending on the noise signal). The control signal is used to transmit one of the at least two output signals as a reference clock signal including pseudo-random phase noise, the at least two output signals being derived from the application clock signal and including at least one output signal delayed relative to another output signal of the at least two output signals. For example, the control signal is provided to the signal delay control circuit and is used to selectively transmit one of the at least two output signals, for example, as a reference clock signal carrying pseudo-random phase noise of the PLL to the PLL phase modulated by pseudo-random noise. The PLL responds to the transmitted output signal (for example, the reference clock signal) from the signal delay control circuit by providing an output signal related to the phase of the reference clock signal derived from the application clock signal. The PLL can provide an output signal indicative of a phase difference between a feedback signal from the PLL and a transmitted one of the at least two output signals. The method further includes cross-correlating a signal corresponding to the output signal from the phase detector with pseudo-random noise and in response evaluating a result of the cross-correlation relative to a known threshold value indicative of a performance level of the PLL.

[0039] In a specific embodiment, the cross-correlation circuit can derive the PLL pulse response from the cross-correlation. The PLL pulse response can be related to the pulse response of the phase error (e.g., the pulse response at the output of the phase detector). For example, the pulse response of the phase error can be directly used as the PLL pulse response (e.g., the pulse response of the system) or can be used to derive the PLL pulse response. In some embodiments, the correlation circuit may include at least one adding circuit and a filter circuit, and the filter circuit derives the PLL pulse response from the cross-correlation obtained by using the phase error of the PLL (e.g., the output from the phase detector) and the folded product of the pseudo-random noise. In other embodiments, the correlation circuit includes at least one adding circuit and a filter circuit, and the PLL pulse response is derived from the difference between the cross-correlation of the phase error of the PLL and the pseudo-random noise and the autocorrelation of the pseudo-random noise. In various embodiments, the cross-correlation result can be optionally inverted (e.g., the autocorrelation is subtracted from the cross-correlation result and inverted), however, the embodiment is not limited to this.

[0040] According to a number of embodiments, the self-test of the PLL is performed after the production test (such as when the device is in the field). The self-test of the PLL can occur simultaneously with the processing of the application signal. The self-test can occur periodically and / or continuously each time the device is powered on. In some embodiments, such as when the processing of the application signal is performed simultaneously with the self-test of the PLL, the previously generated pseudo-random phase noise can be used to remove at least a portion of the pseudo-random phase noise from the output signal (e.g., the output application clock signal) of the PLL as provided as an output from the device. The amount of the previously generated pseudo-random phase noise can be determined and used to remove at least a portion of the pseudo-random phase noise at the output.

[0041] In various embodiments, cross-correlation can be used to determine one or more PLL parameters. Example PLL parameters include phase transfer function, phase error transfer function, phase margin of PLL, identification of whether PLL is locked, damping, natural frequency and other parameters. For example, cross-correlation is used to determine PLL pulse. Using the pulse response, the phase margin can be determined. As described in addition herein, as for a PLL with a high-pass characteristic, the phase error can be directly processed as a PLL pulse response (e.g., a system pulse response), or as for a PLL with a low-pass characteristic, the PLL pulse response can be derived from the pulse response of the phase error. As a specific example, cross-correlation is used to derive a PLL pulse response (directly from the pulse response of the phase error or derived therefrom), and the PLL pulse response is then used to calculate the phase margin of the PLL. The phase margin is compared with a known threshold indicating at least one of the phase margin limit and the previously calculated phase margin. As described in addition below, in response to a comparison indicating a circuit failure, the device can perform one or more actions.

[0042] In various specific embodiments, in response to an evaluation indicating a circuit failure, one or more actions may be performed based on a self-test of the PLL. In response to an indication of a circuit failure, the device may perform actions such as rerunning a self-test, providing an error message, restarting the device, powering down the device, and various combinations thereof.

[0043] Now turning to the attached figure, Figure 1 An example device according to the present disclosure is shown. The device 100 may self-test a PLL 104 forming part of the device 100 using pseudo-random noise 103 to determine a PLL pulse response and / or phase margin for evaluating a performance level of the PLL 104 .

[0044] As shown, the device 100 includes a signal control circuit system 102, a PLL 104, and a correlation circuit 106. The signal control circuit system 102 may include one or more circuits for providing a reference clock signal (as an input to the PLL 104) carrying pseudo-random phase noise. The reference clock signal may carry and / or include pseudo-random phase noise by using a delay line, a phase modulator, and / or adding noise to a digital reference clock signal. In the embodiments described above, the application clock signal is phase modulated by the pseudo-random noise 103 to generate a reference clock signal carrying pseudo-random phase noise. The noise may be generated, for example, by a pseudo-random noise generator circuit, or may be real noise present in the device 100, such as noise obtained from a resistor and / or a diode by means of an amplifier.

[0045] In some specific embodiments, the signal control circuit system 102 includes a signal delay circuit system that combines the control signal with the pseudo-random noise 103 and transmits one of the at least two output signals as a reference clock signal carrying pseudo-random phase noise, and is responsive to the control signal and the application clock signal 101 carrying the pseudo-random noise 103. In this context, the control signal is used to select between the output signals and transmit the selected signal to the PLL 104 as a reference clock signal. The reference clock signal, such as a reference frequency signal or a reference phase signal, carries the pseudo-random phase noise. The pseudo-random noise 103 is used to modulate the application clock signal 101 by the signal control circuit system 102. More specifically, the signal control circuit system 102 modulates the application clock signal 101 with the pseudo-random noise 103, which results in modulating the phase of the application clock signal (e.g., the zero crossing of the modulated signal) and generating a reference clock signal carrying or including the pseudo-random phase noise.

[0046] In various embodiments, the signal control circuit system 102 may include a signal delay circuit and a signal delay control circuit (e.g., a multiplexer (MUX)). The signal delay control circuit may transmit one of the two output signals as a reference clock signal of the input of the PLL 104 in response to a control signal. The first output signal is derived from or includes the application clock signal 101, and the second output signal is delayed relative to the application clock signal 101. In other embodiments, the signal delay circuit system is a variable delay line integrating both the signal delay circuit and the signal delay control circuit. The variable delay line may transmit one of the multiple output signals in response to a control signal carrying a pseudo-random noise 103. The first output signal is derived from or includes the application clock signal 101, and the remaining multiple output signals have different delays relative to the application clock signal 101. For ease of reference, signals with different delays relative to the application clock signal 101 are sometimes referred to herein as delayed clock signals. The pseudo-random noise 103 may be used to phase modulate an input signal of the PLL 104, such as a reference clock signal of the input of the PLL 104. As can be appreciated, the output from the signal delay circuitry is provided to a linear system including PLL 104 in response to a control signal that may carry pseudo-random noise.

[0047] The phase detector of the PLL 104 responds to the phase of the input reference clock signal by outputting a phase error signal, which may be modulated by the pseudo-random noise 103, for example. Both the output of the phase detector of the PLL and the pseudo-random noise 103 are input to the correlation circuit 106. In some specific embodiments, the control signal carrying the pseudo-random noise 103 is used to switch between the application clock signal 101 and one or more delayed clock signals, which are provided to the phase detector of the PLL 104 as a reference clock signal (sometimes referred to as the application clock input and including a modulated signal, for example, including pseudo-random phase noise). As further described herein, the output of the phase detector of the PLL 104 may be cross-correlated with the pseudo-random noise to derive a PLL pulse response relative to the phase of the input of the PLL 104. The PLL pulse response may be derived directly by cross-correlation, which may include or indicate a pulse response of a phase error or may be used to derive other PLL parameters such as the PLL pulse response.

[0048] More specifically, PLL 104 responds to a reference clock signal (e.g., a transmitted output signal) from signal control circuit system 102 by providing an output signal related to the phase of the reference clock signal (e.g., a transmitted output signal derived from the application clock signal and as modulated by pseudo-random noise 103). As previously described, PLL 104 may include a phase detector, a loop filter, an oscillator, and a feedback loop. The phase detector outputs a phase error signal or a phase difference signal. The phase error signal includes or is based on the phase difference of the inputs of the phase detector (e.g., the transmitted output signal / reference clock signal and the feedback signal) and is proportional to the phase error of the PLL (e.g., the phase difference between one of the at least two output signals from the signal delay control circuit and the feedback signal from the PLL). The loop filter filters the phase error signal as output by the phase detector. The oscillator provides an output in response to the filtered phase error signal. For example, the oscillator generates an output phase provided to the phase detector as an application clock output and feedback. The oscillator may include other types of oscillators such as a voltage controlled oscillator (VCO), a current controlled oscillator (CCO), a digitally controlled oscillator (DCO), etc. The feedback loop provides a feedback signal to the phase detector in response to the output of the oscillator. The feedback loop may include a feedback divider circuit that divides the output of the oscillator and provides a feedback signal (e.g., a divided version of the oscillator output signal) as negative feedback to the phase detector.

[0049] Pseudo-random noise 103 and the output from the phase detector are provided as inputs to correlation circuit 106. Correlation circuit 106 cross-correlates the two inputs provided (e.g., pseudo-random noise 103 and a phase error signal or phase difference signal). In response, correlation circuit 106 evaluates the result of the cross-correlation relative to a known threshold value indicating the performance level of PLL 104. In a specific embodiment, correlation circuit 106 self-tests PLL 104 by cross-correlating a signal corresponding to the output signal from the phase detector with pseudo-random noise 103 and, in response, evaluating the result of the cross-correlation relative to a known threshold value indicating the performance level of PLL 104.

[0050] The cross correlation can be defined as:

[0051]

[0052] x(t) and y(t) are the two signals to be correlated, and τ is the delay between the two signals. For time-discrete signals, the cross-correlation can be expressed as follows:

[0053]

[0054] If x(t) is pseudo-random noise 103 (e.g., from a noise generator) fed to the input of a linear system (e.g., signal control circuitry 102 / PLL 104), and y(t) is the output of this linear system (e.g., the phase detector of PLL 104 and / or the output of PLL 104), then r xy (t) is the impulse response of the linear system. In some embodiments, the impulse response of the phase error (e.g., the impulse response at the output of the phase detector) can be directly evaluated as the PLL impulse response of PLL 104, and in other embodiments, the impulse response of the phase error can be used to derive the PLL impulse response (e.g., the impulse response of the system). For example and as further shown herein, the impulse response of the phase error is the sum of the negative impulse response of the system and the Dirac impulse, and therefore the spectrum of the impulse response of the phase error is similar to the spectrum at the output of PLL 104 and can be used to characterize the system. The PLL impulse response / the impulse response of the phase error can be evaluated in the time domain to derive the phase margin of the linear system (i.e., PLL 104) under consideration. The PLL impulse response / the impulse response of the phase error can also be Fourier transformed to analyze the linear system in the frequency domain.

[0055] More specifically, for PLL 104, the cross correlation can be a cross correlation of pseudo-random noise 103 with an output signal, where the output is from PLL 104 (e.g., output phase). The cross correlation derives a PLL impulse response. In order to provide this cross correlation, phase demodulation can be applied to the output phase, which may not be directly available. The PLL provides an output signal, such as a rectangular clock or a sine wave whose phase is determined by a phase demodulator, for example, an independent variable of a sine function. Since this may not be directly available, the output of the phase detector of PLL 104 is used according to an embodiment of the present disclosure, and the output provides a phase error signal for cross correlation. In some specific embodiments, the autocorrelation of the pseudo-random noise is subtracted from the cross correlation result between the phase error and the pseudo-random noise 103 to provide a PLL impulse response (just as a phase demodulator is used). The method does not require a phase demodulator and because a large amount of electronic circuitry is omitted, an impulse response as a system response is provided in a fairly concise manner. In other embodiments, the impulse response of the phase error is used as the system response of the PLL.

[0056] According to the above, various embodiments relate to cross-correlation, while switching between application clock signal 101 or one or more delayed phase-shifted versions of application clock signal 101 according to a control signal carrying pseudo-random noise 103, a linear system processes application signals by adding pseudo-random noise 103 or mixing the application clock signal 101 with the pseudo-random noise 103. Because the application signal of PLL 104 is not correlated with pseudo-random noise 103, the application signal of PLL 104 does not affect the result of cross-correlation, and parameter evaluation of PLL 104 can be completed during application mode. In such embodiments, attention should be paid to mitigating noise or preventing noise from affecting the application. For example, the phase shift of the delay line can be small enough not to affect the overall performance (e.g., phase noise performance) of PLL 104 but can be large enough to allow effective correlation. If additional noise cannot be tolerated in the application, noise can be added during a dedicated self-test interval when the application is turned off. Alternatively, as further shown and described below, the added pseudo-random noise 103 can be subtracted from the output of PLL 104.

[0057] As described above, the impulse response of the phase error (e.g., the output from the phase detector) can be directly processed into the system response of PLL 104, which is sometimes interchangeably referred to herein as the PLL impulse response, or can be used to derive the system response of PLL 104. The phase error impulse response is derived such that the phase error is related to the input signal.

[0058]

[0059] For example, the impulse response of the phase error can be calculated based on:

[0060] h e (f)=1-h(f)→ht e (t) = δ(t) - ht(t)

[0061] where δ(t) is provided by the Dirac delta pulse. The phase transfer function (e.g., the output signal of the PLL as a function of the input) can be defined as:

[0062]

[0063] in is the phase of the output signal, and is the phase of the input reference clock signal (e.g., the input application clock signal). The phase error transfer function can be defined as:

[0064]

[0065] in is the output of the phase detector, for example, The phase error transfer function can be redefined as:

[0066]

[0067] And wherein the system response of the PLL includes:

[0068] Impulse response g(t) = Inverse Laplace transform (h(s)·1) = ht(t)

[0069] And the impulse response of the phase error includes:

[0070] ht e (t) = δ(t) - ht(t)

[0071] In the case where the phase error is directly treated as the system response, the output signal is considered as the folded product between the impulse response of the phase error and the input signal (ie, the pseudo-random noise 103), such as by:

[0072]

[0073] This is sometimes referred to herein as "Method One." Thus, an impulse response of phase error is derived from the cross-correlation of the output of the folded phase detector with the pseudo-random noise used to modulate the input reference (or application) clock signal. Folding is a mathematical operation of signal theory where two signals are multiplied with a certain delay and integrated. In some embodiments, the impulse response can be inverted, however, since the spectra are identical, embodiments may not include inversion.

[0074] In the example provided above, the phase error is directly processed as a system response, and the PLL impulse response is derived from a cross-correlation as a folded product between the phase error (impulse response) and an input signal (e.g., pseudo-random noise). The correlation circuit as further shown herein may include a multiplier, an adder circuit, and a filter circuit that derives the PLL impulse response from a cross-correlation obtained using the folded product of the phase error of the PLL and the pseudo-random noise. For example, the shape of the impulse response can be used to evaluate the performance of the PLL.

[0075] In other embodiments, calculating the cross correlation based on the difference between the input phase and the output phase and the pseudo-random noise results in:

[0076]

[0077] r xy (m)-r xx (m)=-h(m)→h(m)

[0078] This is sometimes referred to herein as "Method Two." According to Method Two, the cross-correlation result is taken as the difference between the autocorrelation of the input noise and the impulse response of the system (e.g., the cross-correlation of the folded product of the phase error and the pseudo-random noise). The PLL impulse response can be obtained from the cross-correlation result by subtracting the autocorrelation of the pseudo-random noise. In some embodiments, although not limited to this, the result can be inverted. As shown by Method Two, the autocorrelation of the pseudo-random noise is subtracted from the cross-correlation result (obtained in a manner consistent with Method One) to obtain the PLL impulse response. Therefore, the PLL pulse is equivalent to a Phase demodulation is performed by cross-correlation of the clock signal at the position and pseudo-random noise. The advantage of method 2 is that the autocorrelation of the pseudo-random noise causes the Dirac pulse to disappear and the Dirac pulse disappearance also exists in the phase error signal, and the noise contribution of the autocorrelation part in the cross-correlation result is removed. Reducing the noise in the signal can increase the sensitivity of the method. Multiple PLL parameters can be analyzed by the results, such as spectrum analysis of the transfer function, shape evaluation, etc.

[0079] In such an embodiment, the correlation circuit includes at least one multiplier, at least one adding circuit, and a filter circuit, wherein the filter circuit derives the PLL pulse response from the cross-correlation obtained using the difference between the phase error and the pseudo-random noise of the PLL. The PLL pulse response is derived and / or evaluated based on the cross-correlation result, such as by subtracting the autocorrelation (e.g., the difference between the autocorrelation of the pseudo-random noise and the pulse response of the phase error and the cross-correlation of the pseudo-random noise) from the cross-correlation result. In some specific embodiments, the PLL pulse response is derived and / or evaluated by inverting the result of subtracting the autocorrelation from the cross-correlation result, although the embodiment is not limited thereto.

[0080] An example pulse response of a first-order PLL may include:

[0081]

[0082] An example pulse response of a second-order PLL may include:

[0083]

[0084] The other order PLLs have similar impulse responses. The phase transfer function and noise at the input can be determined by folding the noise input and the impulse response, as follows:

[0085]

[0086] This can be accomplished by controlling PLL 104 .

[0087] As further shown herein, the device 100 may include various additional components. Example components include noise generator circuits, among other components.

[0088] Figure 2A-2B An example device according to the present disclosure is shown. Figure 2A-2B Can include Figure 1 The device shown in FIG. 1 is a device in which other components are shown separately. Figure 2A As shown, device 210 includes the previously described signal control circuit system (e.g., signal delay circuit 214 and signal delay control circuit 216), PLL 218, and correlation circuit 220. As previously described, the signal control circuit system may include or may be a signal delay circuit system that uses a control signal carrying pseudo-random noise to combine a reference clock signal having (e.g., including) pseudo-random phase noise. However, embodiments are not limited thereto, and other types of circuit systems may be used to use the above combined circuit system. Figure 1 The pseudo-random noise described modulates the reference clock signal.

[0089] In various embodiments, the device 210 includes a pseudo-random noise generator circuit 212. The pseudo-random noise generator circuit 212 provides a control signal carrying pseudo-random noise. For example, the pseudo-random noise is provided to both the signal delay control circuit 216 and the correlation circuit 220 to determine the PLL parameters. The example pseudo-random noise generator circuit 212 may include a linear feedback shift register (LFSR), however, the embodiments are not limited thereto. As previously described, the pseudo-random noise is used to modulate the phase of the input signal of the PLL, such as the reference clock signal of the PLL 218.

[0090] If Figure 2AAs shown, the signal control circuit system may include a separate signal delay circuit 214 and a signal delay control circuit 216. Pseudo-random noise is added to the control signal or otherwise provided to the signal delay control circuit 216 as a control signal. The signal delay control circuit 216 transmits one of the two output signals in response to the control signal carrying the pseudo-random noise. For example, the two output signals include the application clock signal 211 and the delayed clock signal (e.g., a delayed phase-shifted version of the application clock signal 211). The signal delay circuit 214 provides the delayed clock signal to the signal delay control circuit 216. The signal delay control circuit 216 transmits one of the application clock signal and the delayed clock signal as a reference clock signal (e.g., an input signal) to the PLL 218 based on the control signal. Therefore, the reference clock signal provided to the PLL 218 switches between the application clock signal 211 itself or the delayed clock signal according to the control signal carrying the pseudo-random noise. In this way, the reference signal of the PLL is phase modulated.

[0091] As Figure 2B As shown, the example device 222 includes the previously described signal control circuit system (e.g., a variable delay line circuit 226 integrating both a signal delay circuit and a signal delay control circuit), a PLL 228 and a correlation circuit 230, and optionally a pseudo-random noise generator circuit 224 as previously described. In such an embodiment, the signal delay circuit is integrated with the signal delay control circuit as part of the variable delay line circuit 226. Pseudo-random noise is used to modulate the phase of a reference clock signal (reference frequency signal or reference phase signal) by a control signal of the variable delay line circuit 226. The variable delay line circuit 226 adds a variable delay to the delay between the output and input of the delay line, and transmits an output signal in response to the control signal carrying the pseudo-random noise. The output signal includes the application clock signal 211 or the delayed clock signal. In various embodiments, the variable delay line circuit 226 adds a variable delay by using a capacitor bank between two buffers or by using a switchable capacitor between the output and input of the buffer chain. Both embodiments allow switching delays, the latter switching in a more linear manner. In a specific embodiment, for example, the control signal is used by the variable delay line circuit 226 for selecting a delay path to derive the output signal. The signal delay control circuit 216 transmits one of the multiple output signals to the PLL 228 based on the control signal. Therefore, the reference clock signal provided to the PLL 228 switches between applying the clock signal 223 itself or one of the multiple delayed clock signals according to the control signal carrying the pseudo-random noise.

[0092] In by Figure 2AIn the embodiment shown in 2B or 2B, the self-test of the PLL can be performed after the production test, such as when the device is in the field. The self-test of the PLL can occur periodically and / or continuously while processing the application signal, each time the device is powered on. In some embodiments, such as when the processing of the application signal is performed simultaneously with the self-test, the previously generated pseudo-random phase noise can be used to remove at least a portion of the pseudo-random phase noise from the output signal of the PLL provided as the output from the device. The amount of the previously generated pseudo-random phase noise can be determined and used to remove at least a portion of the pseudo-random phase noise at the output of the PLL system. Alternatively, in various embodiments, the noise level added to the input of the PLL can be low enough not to affect the performance of the PLL. In some specific embodiments, the added noise can be effectively maintained at more than 10dB below the system performance. In such an embodiment, the resolution of the system can be high enough to process the added pseudo-random phase noise without a significant clipping effect. When the pseudo-random phase noise is not dominant, the performance of the PLL can be extracted by cross-correlation. Such an embodiment can avoid the need for additional noise reduction circuit systems to compensate for the added noise.

[0093] In various embodiments, such as by Figure 1-2B The cross-correlation performed by the device shown can be used to detect whether the PLL is locked. For example, using the output signal from the phase detector and the input signal (e.g., a reference clock signal), it can be determined whether the PLL is locked, and the PLL can perform a self-test in response to determining whether the PLL is locked, although the embodiment is not limited to this. For example, only in the case of a locked PLL, the PLL output signal is correlated with the input signal. In this way, the phase transfer function and the impulse response can be obtained by the method described above in this embodiment only when the PLL is locked. This may be important because conventional lock detectors are sometimes unreliable because the locking criterion commonly used by conventional lock detectors is that the phase difference measured by the phase comparator remains below a certain limit within a certain time interval. However, this criterion is prone to error due to the phase noise of the PLL itself and / or the input signal of the PLL, so this phase difference will fluctuate. The fluctuation means that a certain headroom needs to be added to the phase difference limit of the lock detector. Selecting such a headroom that is too high will make the lock detector too insensitive to the unlocking situation, while selecting a headroom that is too low will make the lock detector too sensitive to phase noise. Information about lock / unlock is derived based on the time-averaged cross-correlation signal Overcame that.

[0094] In other embodiments and / or additionally, pseudo-random noise is used for the purpose of jitter. In some systems using PLL, the PLL output frequency is intentionally modulated randomly continuously within a small frequency range (e.g., "jittered"). In this way, the PLL output signal will not be concentrated on a single frequency, but on a certain frequency band. Therefore, the unintended electromagnetic emission of the system is also distributed on a specific frequency band. This reduces the interference of the system to its environment and reduces the sensitivity of the system to environmental interference. In such embodiments, the pseudo-random noise has a spectrum and (intended to) make the input clock (e.g., input application clock signal) jitter amplitude to mitigate or avoid idle tones and / or to spread the PLL output clock spectrum over a wider range to reduce electromagnetic interference. For example, noise can be obtained from resistors, dividers or other system components through an amplifier and allows the use of real noise.

[0095] This jittering can be accomplished by modifying the PLL output frequency using a control signal that modifies the divider ratio of the clock divider in the PLL. This control signal can be a deterministic signal or a pseudo-random signal. In the case of using a noise signal, this noise signal can also be used for the correlation method described above. However, in some cases, for example, because lower frequencies are lost, the spectrum of this noise signal used for jittering does not correspond to the spectrum of pseudo-random white noise (or pseudo-random noise with a flat spectrum). In these cases, it may be advantageous to add lower frequency components to the jittering noise signal. Using this (possibly modified) jittering pseudo-random noise signal avoids using a dedicated noise source for the cross-correlation method; in addition, this jittering pseudo-random noise signal does not add additional phase noise that may damage the application.

[0096] Additionally, in a number of embodiments, the PLL may include an all-digital PLL (ADPLL) having a digital loop filter and a phase detector providing a digital signal output. The general advantage of the ADPLL is that signal processing is done primarily in the digital domain. Most, if not all, of the components are digital components. Typically, the oscillator and some other components are analog. Mainly due to the need for large capacitors, the loop filter is composed of a small digital circuit system rather than an analog circuit system that may occupy a large area. In addition, since the ADPLL has a digital loop filter that can be easily reconfigured, it has strong robustness to aging, process expansion, and changes in temperature and power supply voltage. When used in conjunction with the techniques described above, the special advantage of the ADPLL is that noise injection can be performed using a digitally controlled delay line. In this case, a pseudo-random noise signal controls the digital delay line. Because the controllable delay line can be part of the ADPLL and in order to use noise injection, only another instance of the controllable delay line is added. When used in conjunction with the techniques described above, another advantage of the ADPLL is that the phase difference as measured by the phase detector is already available as a digital signal, so that the phase difference can be directly processed by the digital system. Furthermore, if the reference phase word is already digital, then the delay line may not be needed and the pseudo-random phase noise is added directly to the reference phase word.

[0097] In various embodiments of the present disclosure, the calculated phase transfer function of the PLL is used to fine-tune important (e.g., tightly regulated) components of the PLL, such as components that are sensitive to process scaling, voltage variations, temperature, aging, etc. Depending on the details of the PLL, this may be an oscillator and / or other components used to simulate the PLL and / or the loop filter. In some embodiments, the possibility of real-time fine-tuning allows simpler, smaller, or cheaper components to be used for the oscillator and / or the loop filter.

[0098] Figure 3 An example PLL according to the present disclosure is shown. As shown, a reference clock signal 333 is input to PLL 332. The reference clock signal 333 can be switched between at least two output signals according to a control signal. Figure 3 In the specific embodiment shown, the control signal carries pseudo-random noise as described above. PLL 332 includes phase detector 334, low pass filter 336, VCO 338, post divider circuit 340 and feedback divider circuit 342. However, the embodiment is not limited to Figure 3The specific circuit components shown and may include various variations, such as different oscillators and other variations such as ADPLL. As previously described, phase detector 334 provides a phase error signal based on the phase difference between its inputs (i.e., reference clock signal 333 and the feedback signal provided by feedback divider circuit 342). The output of phase detector 334 is provided as an input signal to correlation circuit 337 and is used to provide cross-correlation as previously described.

[0099] As shown, the device can perform self-test on PLL 332 while processing the application clock signal. For example, low pass filter 336 filters the phase error signal output by phase detector 334 (e.g., the phase error signal is proportional to the phase difference between one of the at least two output signals from the signal delay control circuit and the feedback signal from the PLL). VCO 338 provides an output in response to the filtered phase error signal. A feedback loop including feedback divider circuit 342 divides the output of the VCO and provides a feedback signal to phase detector 334 in response to the output of the VCO. For example, the VCO outputs an application clock signal output with a phase, which is fed through optional feedback divider circuit 342 and fed to phase detector 334 as a negative feedback as a divided version of the feedback signal. In addition, the output of the VCO is provided to post divider circuit 340, which divides the output of the VCO and provides an output signal that is the same as the application clock output signal 335.

[0100] Figure 4 An example of a process for self-testing a PLL of a device according to the present disclosure is shown. The self-test of the PLL may include, at 451, a cross-correlation for deriving a PLL pulse response. Based on the cross-correlation, at 453, a phase margin may be calculated (e.g., using the PLL pulse response), and at 455, the phase margin may be compared to a known threshold indicating at least one of a phase margin limit and a previously calculated phase margin limit. Although Figure 4 The calculated phase margin is shown, but other specific parameters such as natural frequency, damping, 3dB bandwidth, etc. can be derived in the same manner. The phase margin limits can include specific values ​​and / or upper and lower limits (e.g., minimum / maximum values). In some embodiments, the phase margin limits can include minimum limits and maximum limits. In various specific embodiments, there may be a lot of noise in the clock input signal, VCO, etc. If so, the phase margin limits can be defined as an upper limit (e.g., peak value) and the slope of the impulse response or directly as defined by Figure 6 The two points shown are to enhance the significance of PLL self-test.

[0101] In various embodiments, at 457, one or more actions may occur in response to the comparison. For example, a self-test of the PLL may indicate a circuit failure. In response to the indication of a circuit failure, the device may perform an action based on the failure, such as rerunning the self-test, providing an error message, restarting the device, powering down the device, and various combinations thereof. As a specific example, using a cross-correlation (e.g., a PLL pulse response derived from the cross-correlation), a phase margin may be determined and used to determine a phase transfer function. The device may fine-tune at least one component of the PLL in response to the determined phase transfer function.

[0102] Figure 5 An example device according to the present disclosure is shown. Device 560 may include Figure 1 and 2A -2B is the device previously shown and described, although the embodiment is not limited thereto. More specifically, the device 560 may include the previously combined Figure 2B The device shown depicts circuit components and includes a pseudo-random noise generator circuit 562, a variable delay line 564 (responsive to an applied clock signal 561 and a control signal carrying the pseudo-random noise) that provides a reference clock signal that carries or includes pseudo-random phase noise, a PLL 568, and a correlation circuit 567. In addition, the device 560 includes noise reduction circuitry such as circuitry 570 for modeling the PLL and other circuitry (e.g., another variable delay line) and for removing at least a portion of the pseudo-random phase noise from the output of the PLL.

[0103] In various embodiments, at least a portion of the pseudo-random phase noise can be removed from the output provided by the PLL. For example, using a cross-correlation of a previous signal corresponding to another output signal from a phase detector with another control signal carrying the pseudo-random noise, a model of the pseudo-random phase noise can be determined and used to remove portions of the pseudo-random phase noise. As described above, embodiments are not limited to the use of noise reduction circuitry, and the noise level added to the reference clock signal of the PLL can be low enough so as not to affect the performance of the PLL system.

[0104] For example, after transmitting a software-implemented model of a PLL, the added pseudo-random phase noise can be subtracted from the output signal of the PLL. Using the pseudo-random noise, the transfer characteristics of this model, such as the transfer characteristics of the PLL, are known from previous parameter evaluations. In this way, the otherwise noise level at the output of the PLL can be significantly reduced, albeit at the expense of additional computational effort. As shown by Figure 5As shown, the device may include a modeling circuit system 570 for modeling the PLL. The modeling circuit system 570 may be used to determine a previous pseudo-random noise estimate and use the previous pseudo-random phase noise estimate to model the current pseudo-random phase noise. The circuit system 570 is a model implemented by software processed by the processing circuit system. The pseudo-random phase noise (or at least a portion thereof) may be subtracted from the application clock output provided by the oscillator of the PLL and provided as an output by the integrated circuit.

[0105] Figure 6-8 The results of an example experimental embodiment according to the present disclosure are shown. To demonstrate the techniques described above, the response of the ADPLL to superimposed pseudo-random white noise is simulated. The amplitude of the superimposed pseudo-random noise is selected so that the total noise of the PLL remains within the specification limits, for example, so that such noise does not interfere with the application.

[0106] Use MATLAB and apply the second method above (sometimes called method 2) to calculate the cross correlation r xy (m). Use FFT to calculate the phase transfer function of the resulting ADPLL. In order to reduce the noise of the transfer function, a sliding average can be calculated.

[0107] More specifically, Figure 6 A graph 671 showing the use of noise correlation to estimate the phase transfer function is shown, and the ideal transfer function is also calculated based on the ADPLL parameters. Graph 671 shows that the noise correlation method (eg, method two) is able to accurately estimate the phase transfer function. Figure 7 A graph 773 is shown showing the simulated PLL pulse response after subtracting the autocorrelation of the pseudo-random noise, the sliding average, and the pulse response calculated from the PLL closed loop parameters in accordance with the present disclosure. As shown, the curve fits the model. Figure 8 A graph 875 showing derived PLL parameters in accordance with the present disclosure is shown.

[0108] As described above, in order to evaluate the benefits of subtracting the autocorrelation component of the pseudorandom noise signal, this method is applied to the simulated cross-correlation (and therefore impulse response) signal. In order to evaluate the matching degree of the calculated impulse response with the impulse response as calculated according to the ADPLL parameters, the calculated impulse response shown by the curve 773 is also plotted. These results show that subtracting the autocorrelation component from the impulse response can significantly reduce the noise added to the calculated transfer function.

[0109] In various embodiments, it is not necessary to calculate the impulse response over a large range. Often, it may be sufficient to derive loop parameters from a limited number of impulse response points and characterize the impulse response in this way.

[0110] Figure 8 More specifically, an example is shown of deriving the damping and natural frequency of a system from two parameters of the impulse response: the starting value h(0) and the slope at the beginning of the impulse response:

[0111]

[0112] Notwithstanding the above description, both the system response and the impulse response of the phase error may be used for this operation due to the similarities between the two.

[0113] As further described below, Fig. 9 and 10A -10B shows an example of how to derive PLL parameters based on phase error and noise data streams. In the case of analyzing only the product of damping and natural frequency, only the upper corresponding part of the example is used. Multiple examples repeat the path to understand the delay path of the noise data stream. In various embodiments, this can be shared. In addition, the multiplier can be shared and the different components can be multiplied in sequence, and the low-pass filter can be updated when the new result is available. However, in modern technology, digital circuit systems are small, and implementing correlation with digital circuits may consume less area and power.

[0114] In these two methods, Fig. 9 and 10A -10B also shows that the noise and phase error are multiplied with a certain phase relationship, which is the delay between the two phases. It is assumed that some possible delays from the circuit system can be compensated. A low-pass filter is used to average the results. For slope calculation, the results of timing point m=0 and timing point m=1 are subtracted and divided by the clock cycle. Any other timing point can also be used for slope calculation. Moreover, the distance can be larger, for example, to increase accuracy and reduce some effects caused by residual noise. In the embodiment shown in this article, the difference is divided by an appropriate multiple of the clock cycle to derive the slope. Method 2 extends method 1 by subtracting the corresponding autocorrelation component of the noise from the cross-correlation result. As shown above, the noise content can be reduced by method 2. Therefore, the low-pass filter can have a larger bandwidth and the detection speed can be higher.

[0115] In the case of adjustable delays, if the characterization takes some time, it is acceptable that impulse response points at different delays cannot be obtained simultaneously and may not be consistent (if the system characteristics vary over time), then the impulse response and system characteristics can be characterized over a larger range with less effort.

[0116] Fig. 9An example correlation circuit for processing phase error as an impulse response of a PLL according to the present disclosure is shown. As described above (e.g., method one), the phase error can be directly processed as a system response of the PLL, such as for a PLL with a high-pass characteristic. Fig. 9 The correlation circuit 980 shown includes at least one adding circuit (e.g., +) and at least one filter circuit (e.g., a low-pass filter (LP)), and the at least one filter circuit is used to derive the PLL impulse response directly from the cross-correlation between the phase error and the pseudo-random noise of the PLL. More specifically, the impulse response is derived from the folded product of the phase error and the pseudo-random noise.

[0117] For example, the output signal of the PLL can be calculated by folding the impulse response of noise and phase error, such as by:

[0118]

[0119] The cross-correlation between the input and output signals again provides the impulse response, and the PLL parameters can be derived from the impulse response. For example:

[0120]

[0121] For a first order PLL, an example calculation in an experimental embodiment may include noise x(t), which includes pseudo-random noise with a certain amplitude (e.g., a cycle length of + / - 0.1 or less). r =100 kHz (eg, as an example, although embodiments are not limited to 100 kHz) may include:

[0122]

[0123] And the impulse response of folded pseudo-random noise and phase error can be defined by:

[0124] y(t)=x(t)*h 1e (t).

[0125] Example calculations for a first order PLL are described above. However, embodiments are not limited to first order PLLs and may include 2nd order (or higher order) PLLs. Using a first order PLL, the impulse response may include:

[0126]

[0127] And the second-order PLL pulse response may include:

[0128]

[0129] Figures 10A-10BAn example correlation circuit using phase error to derive a PLL pulse response according to the present disclosure is shown. That is, Fig. 9 An example circuit implementation of method one is shown, and Figures 10A-10B An example circuit implementation of method 2 is shown. Method 2 is an extension of method 1, for example, where the autocorrelation of the pseudo-random noise is subtracted from the cross-correlation result. Fig. 10A and 10B As shown, the correlation circuits 1090, 1091 include at least one adding circuit and at least one filter circuit, and the at least one filter circuit is used to derive the PLL pulse response from the cross-correlation of the phase error (e.g., the difference between the input phase and the output phase) and the pseudo-random noise. For example, the cross-correlation provides the pulse response of the phase error, and the PLL pulse response is derived from the difference between the cross-correlation result (e.g., the pulse response of the phase error) and the autocorrelation of the pseudo-random noise. In some specific embodiments, for example, the PLL pulse response can be derived by inverting the result of the difference of the cross-correlation result (e.g., the pulse response of the phase error) and subtracting the autocorrelation of the pseudo-random noise (e.g., method two).

[0130] Therefore, the impulse response of the phase error can be used to derive the PLL impulse response. Figures 10A-10B The correlation circuit shown can be implemented by Fig. 9 The process shown in the correlation circuit of FIG. 1 and then subtracting the autocorrelation component of the noise from the cross-correlation result. In this way, the PLL impulse response (e.g., the output of the PLL) is equivalent to Phase demodulation is performed by cross-correlation of the clock signal at and pseudo-random noise. Fig. 10A A generalized version of the correlation circuit is shown, and Fig. 10B The bar on the item indicates that the average value is obtained by the low-pass filter. Fig. 10B As shown, the low-pass filters used for averaging can be shifted without changing the result but eliminating two low-pass filters.

[0131] For example, the output signal of the PLL can be calculated by folding the impulse response of noise and phase error, such as by:

[0132]

[0133] The cross-correlation between the input signal and the output signal again provides an impulse response, and the PLL parameters can be derived from the impulse response. As provided before, examples include:

[0134]

[0135] where r xx(m) is the autocorrelation which can be calculated as follows:

[0136]

[0137] In the case where the delay is zero (0), the above equation returns the maximum value and signal energy according to the following equation:

[0138]

[0139] Therefore, autocorrelations can include:

[0140] R xx (l) = R xx (-l).

[0141] It is shown above that the autocorrelation of the pseudo-random noise is subtracted from the cross-correlation of the phase error and the pseudo-random noise to produce the PLL impulse response. This can advantageously reduce the noise content of the result. In addition, the PLL impulse response can be compared with the ideal model to provide acceptable consistency. Moreover, the phase transfer function can be derived from the PLL impulse response as a spectrum by FFT. If the spectrum of the phase error impulse response is evaluated, the background noise can be 5-10dB lower (e.g., 5-10dB higher sensitivity) than that.

[0142] Fig.11 An example of a low pass filter according to various embodiments is shown. However, the embodiments are not limited thereto.

[0143] As previously described, various safety standards may require that performance parameters be measured in the field. As a specific example, automotive safety standards may require that a certain failure in time (FIT) level be maintained. A FIT is defined as the number of failures in time (FIT) per 10 9 The number of safety-sensitive failures that may not exceed a certain limit within a certain operating hour. The integrated circuit manufacturer may need to provide evidence that the circuit system maintains the FIT level, which can be based on process reliability data showing how many defects may occur during the entire service life and data of the functional safety concept showing how many of these defects are safety-sensitive and how many of the safety-related defects can be reduced by functional safety measures. The limits on safety-related defects may be very strict. As an example, for ASIL B, it may be 100FIT, and for ASIL D, it may be 10FIT. These ratios refer to the complete system, however, each integrated circuit is only allowed to have a small fraction of this failure rate. In a typical automotive radar integrated circuit (IC) or IC chip (compliant with ASIL B requirements; only silicon is considered without considering the package), the allowed failure rate can be as low as 2FIT.

[0144] In addition, as described above, during field operation, integrated circuits sometimes fail due to aging mechanisms such as negative bias temperature instability (NBTI), hot carrier injection (HCI), and time-varying dielectric breakdown (TDDB) or also due to latent defects activated during the service life. Events such as voltage spikes in thunderstorms or customer misuse (e.g., electrostatic discharge (ESD) overload during installation, maintenance, or repair) are relevant causes of integrated circuit failure in the field. Typically, partial (i.e., parameter) failures may be more serious than complete failures. For example, complete failures can be immediately identified and countered, while parameter failures may not be immediately identified. Embodiments according to the present disclosure may allow the parameters of the PLL to be tested by BIST, which may allow compliance with standard requirements and identification of failures within the service life of the circuit system.

[0145] More specifically, the device according to the present disclosure can be used for production testing, verification, and for repeated self-testing in the field, such as for functional checks. And, here, the details depend largely on the existing on-chip infrastructure and requirements. For example, in all three modes (e.g., simultaneous mode, power-on intermittent mode, periodic intermittent mode), the calculated quality factor can be tested for fixed limits. In various embodiments, unfixed test limits can be used, but the PLL parameters can be compared with the PLL parameters of the same PLL in the same integration. Moreover, the device can be used to store one or more determined PLL parameters and compare them with one or more PLL parameters determined after accelerated aging testing (e.g., during verification) or after a certain operating time (e.g., during the field service life), and this test can be performed to detect slow changes in parameters.

[0146] Terms such as up / down, left / right, top / bottom, and above / below, used to illustrate orientation, may be used herein to refer to the relative positions of elements as shown in the accompanying drawings. It should be understood that the use of terms is merely for convenience of representation, and in actual use, the orientation of the disclosed structures may be different from the orientation shown in the accompanying drawings. Therefore, the terms should not be interpreted in a limiting manner.

[0147] Those skilled in the art will recognize that, unless otherwise specified, various terms used in this specification (including claims) imply ordinary meanings in the art. As an example, the specification describes and / or illustrates aspects of the disclosure for implementing the claimed protection through various circuits or circuit systems, which may be shown as or using depictions such as blocks, modules, devices, systems, units, controllers, and / or other circuit types (e.g., Figure 1The reference numerals 102 and 104 of the drawings depict terms such as blocks / modules as described herein. Such circuits or circuit systems are used with other elements to illustrate how certain embodiments are performed in form or structure, steps, functions, operations, activities, etc. For example, in certain embodiments discussed above, one or more modules are discrete logic circuits or programmable logic circuits that are configured and arranged to implement the embodiments as can be performed in a certain manner. Figure 4 In some embodiments, such programmable circuitry is one or more computer circuits that include memory circuitry for storing and accessing a program to be executed as a set (or sets) of instructions (and / or as configuration data for defining how the programmable circuit is to be executed), and the programmable circuitry uses a programmable circuit such as a computer programmable circuit. Figure 4 and Figure 1 The described algorithms or processes are used to perform relevant steps, functions, operations, activities, etc. Depending on the application, the instructions (and / or configuration data) can be configured to be implemented in a logic circuit system, and the instructions (whether represented in the form of object code, firmware or software) are stored in a memory (circuit) and can be accessed from the memory (circuit).

[0148] Based on the above discussion and illustrations, those skilled in the art will readily recognize that various modifications and changes may be made to the various embodiments without strictly following the exemplary embodiments and applications shown and described herein. For example, the methods illustrated in the accompanying drawings may involve steps performed in various orders, wherein one or more aspects of the embodiments herein are retained, or may involve fewer or more steps. For example, by Figure 3 , 9 , 10A, 10B and 11 can be composed of the circuit system shown in Figure 1 As another example, a portion of the circuit system shown in FIG. Figure 4 The method shown can be Figure 1 Such modifications do not depart from the true spirit and scope of the various aspects of the present disclosure, including those set forth in the claims.

Claims

1. A self-testing device, characterized in that: include: signal control circuitry configured and arranged to receive pseudo-random noise and an applied clock signal, phase modulate the applied clock signal by the pseudo-random noise to generate a reference clock signal carrying the pseudo-random phase noise as an input to the PLL, the pseudo-random phase noise being generated by a pseudo-random noise generator circuit; a phase locked loop (PLL), the PLL comprising a phase detector configured and arranged to provide an output phase error signal in response to the reference clock signal, the output phase error being representative of a phase difference between the reference clock signal and a PLL feedback signal; as well as and a correlation circuit configured and arranged to self-test the PLL by cross-correlating the output phase error signal from the phase detector with the pseudo-random noise and, in response, by evaluating a result of the cross-correlation relative to a known threshold of a performance level of the PLL, the known threshold being indicative of a phase margin limit of the PLL, The correlation circuit further includes at least one adding circuit and a filter circuit, wherein the filter circuit is configured and arranged to derive an impulse response of the phase error from the cross-correlation between the phase error and the pseudo-random noise, and to derive a PLL impulse response based on a difference between an autocorrelation of the pseudo-random noise and the impulse response of the phase error.

2. The device according to claim 1, characterized in that The signal control circuit system comprises: signal delay circuit; and a signal delay control circuit configured and arranged to transmit an output signal as the reference clock signal phase modulated by the pseudo-random noise in response to a control signal carrying the pseudo-random noise and the application clock signal, wherein the output signal is derived from the application clock signal and includes at least one output signal delayed by the signal delay circuit relative to another of the output signals.

3. The device according to claim 1, characterized in that The PLL further comprises: a loop filter configured and arranged to filter a phase error signal as output by the phase detector, the phase error signal being proportional to a phase difference between the reference clock signal and a feedback signal of the PLL; an oscillator configured and arranged to provide an output in response to the filtered phase error signal; and A feedback loop including a feedback divider circuit is configured and arranged to provide the feedback signal to the phase detector in response to the output of the oscillator.

4. The device according to claim 1, characterized in that Further including: Noise reduction circuitry configured and arranged to remove at least a portion of the pseudo-random phase noise from an output provided by the PLL using a cross-correlation of a previous signal corresponding to another output signal from the phase detector and another reference clock signal carrying the pseudo-random phase noise.

5. The device according to claim 1, characterized in that The correlation circuit further includes at least one adding circuit and a filter circuit configured and arranged to derive a PLL impulse response from the cross-correlation obtained using a folded product of a phase error of the PLL and the pseudo-random noise.

6. The device according to claim 1, characterized in that The pseudo-random noise has a frequency spectrum and an amplitude configured to dither the input application clock signal to perform at least one of avoiding idle tones and spreading a PLL output clock spectrum over a wider range to reduce electromagnetic interference.

7. A self-testing method, characterized in that: include: receiving, by a signal control circuit system of the device, a pseudo-random noise and an applied clock signal, phase modulating the applied clock signal by the pseudo-random noise to generate a reference clock signal carrying the pseudo-random phase noise as an input to the PLL, the pseudo-random phase noise being generated by a pseudo-random noise generator circuit; providing an output phase error signal by a phase detector of a phase-locked loop (PLL) of the device in response to the reference clock signal, the output phase error signal representing a phase difference between the reference clock signal and a PLL feedback signal; cross-correlating, by correlation circuitry of the device, the output phase error signal from the phase detector with the pseudorandom noise, and in response, self-testing the PLL by evaluating a result of the cross-correlation relative to a known threshold of a performance level of the PLL, the known threshold being indicative of a phase margin limit of the PLL; An impulse response of the phase error is derived from the cross-correlation between the phase error and the pseudo-random noise by a filter circuit of the device, and a PLL impulse response is derived from a difference between an autocorrelation of the pseudo-random noise and the impulse response of the phase error.

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