Semiconductor package with overlapping conductive regions and method of manufacturing the same

Abstract

A semiconductor package capable of bilateral cooling, comprising an upper conductive element having a metal surface exposed outward, a lower carrier substrate having an upper conductive layer, a lower conductive layer and an electrically insulating layer arranged between the upper conductive layer and the lower conductive layer, wherein the lower conductive layer has a surface exposed outward, a first conductive standoff arranged between the upper conductive element and the upper conductive layer, at least one power semiconductor chip arranged between the upper conductive element and the upper conductive layer, a second conductive standoff arranged between the upper conductive element and the power semiconductor chip, wherein a first carrier region of the upper conductive layer of the lower carrier substrate is configured for applying a positive supply voltage, a second carrier region of the upper conductive layer arranged next to the first carrier region is configured in phase, and a first region of the upper conductive element is configured for applying a negative supply voltage, wherein the first region at least partially overlaps the first carrier region.

Description

TECHNICAL FIELD

[0001] The invention relates to a semiconductor package with a dual-sided cooling structure, wherein conductive areas partially overlap in the semiconductor package. The invention further relates to a manufacturing method for a semiconductor package with a dual-sided cooling structure. BACKGROUND

[0002] The requirements for high-current circuit performance are increasing (for example in the electric drive of a motor vehicle), so that further development and improvement of semiconductor packages used in these circuits is required. These circuits can be, for example, inverters with a battery voltage converted into an alternating voltage for driving an electric machine. These circuits can have, for example, an inverter which converts a battery voltage into an alternating voltage for driving an electric machine. Such an inverter can be implemented by a suitable circuit in a semiconductor package, wherein for the performance of the inverter it is decisive that a sufficient cooling, as low an impedance as possible, as low a leakage inductance as possible, etc. are achieved in the semiconductor package. By improving the semiconductor package or by improving the method for manufacturing such a semiconductor package, the performance of such an inverter can be further improved. SUMMARY

[0003] The task on which the invention is based is solved by the features of the independent claims. Advantageous configurations and extensions of the invention are specified in the dependent claims.

[0004] A specific example relates to a semiconductor package with a dual-sided cooling structure, comprising: an upper conductive element having a metal surface exposed to the outside; a lower carrier substrate having an upper conductive layer, a lower conductive layer and an electrically insulating layer arranged between the upper conductive layer and the lower conductive layer, wherein the lower conductive layer has a surface exposed to the outside; a first conductive standoff arranged between the upper conductive element and the upper conductive layer; at least one power semiconductor chip arranged between the upper conductive element and the upper conductive layer; a second conductive standoff arranged between the upper conductive element and the power semiconductor chip; wherein a first carrier area of the upper conductive layer of the lower carrier substrate is configured for applying a positive supply voltage, a second carrier area of the upper conductive layer arranged next to the first carrier area is configured to be in phase, and a first area of the upper conductive element is configured for applying a negative supply voltage, wherein the first carrier area and the first area at least partially overlap.

[0005] A specific example relates to a method for manufacturing a semiconductor package with a double-sided cooling structure, the method comprising: providing a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer and an electrically insulating layer arranged between the upper electrically conductive layer and the lower electrically conductive layer, wherein a first carrier area of the upper electrically conductive layer of the lower carrier substrate is configured for applying a positive supply voltage and a second carrier area of the upper electrically conductive layer arranged next to the first carrier area is configured to be a Phase; arranging a first electrically conductive standoff on the upper electrically conductive layer of the lower carrier substrate; arranging at least one power semiconductor chip on the upper electrically conductive layer of the lower carrier substrate; arranging a second electrically conductive standoff on the power semiconductor chip; arranging an upper electrically conductive element on the standoff opposite to the lower carrier substrate such that a first area of the upper electrically conductive element at least partially overlaps the first carrier area, wherein the first area is configured for applying a negative supply voltage.

[0006] A specific example relates to a semiconductor package with a double-sided cooling structure, the semiconductor package comprising: an upper electrically conductive element having a metal surface exposed outwardly; a lower carrier substrate having an inner electrically conductive layer, an outer electrically conductive layer and an electrically insulating layer, wherein the outer electrically conductive layer has a surface exposed outwardly, the electrically insulating layer is arranged between the inner electrically conductive layer and the outer electrically conductive layer; a first electrically conductive standoff arranged between the upper electrically conductive element and the inner electrically conductive layer; at least one power semiconductor chip arranged between the upper electrically conductive element and the inner electrically conductive layer; a second electrically conductive standoff arranged between the upper electrically conductive element and the power semiconductor chip; a first power connection arranged on the lower carrier substrate; a third power connection arranged on the upper electrically conductive element, wherein the first power connection and the third power connection at least partially overlap. BRIEF DESCRIPTION OF DRAWINGS

[0007] The accompanying drawings illustrate examples and are used in connection with the description to explain the basic features of the invention. Elements of the drawings that are substantially identical can not necessarily be scaled proportionally. Identical reference signs can designate corresponding, similar or identical parts.

[0008] Fig. 1 consists of the sub-figures Figure 1A and 1B showing a side view of a semiconductor package with a double-sided cooling structure in the sub-figures Figure 1A showing a side view of another semiconductor package with a double-sided cooling structure in the sub-figures Figure 1B showing a side view of another semiconductor package with a double-sided cooling structure in the sub-figures

[0009] Figure 2 showing a perspective view of a semiconductor package with a double-sided cooling structure, the semiconductor package further comprising a package body in the sub-figures

[0010] Fig. 3 consists of the sub-figures Figures 3A to 3D and Figure 3A showing a perspective view of a lower carrier substrate of another semiconductor package in the sub-figuresFigure 3B The upper cooling structure is shown in a three-dimensional view, in the sub-section Figure 3C The image shows an assembled semiconductor package in a three-dimensional view. Figure 3D The image shows a side view of a semiconductor package;

[0011] Figure 4 A flowchart illustrating a method for manufacturing semiconductor packages;

[0012] Figure 5 is composed of children Figure 5A To the Son Figure 5C This composition and illustration further demonstrate another example of semiconductor packaging;

[0013] Figure 6 is composed of children Figure 6A Kazuko Figure 6B An example of a semiconductor package comprising and illustrating a power connection terminal with at least partial overlap is shown.

[0014] Figure 7 is composed of children Figure 7A Kazuko Figure 7B Another example of a semiconductor package comprising and illustrating a power connection terminal with at least partial overlap is shown.

[0015] Figure 8 is composed of children Figure 8A Kazuko Figure 8B The diagram shows a lower support substrate and an upper conductive element, which can be used, for example, in the semiconductor packages of Figures 6 and 7.

[0016] Figure 9 is composed of children Figures 9A to 9C Composition, in Figure 9A The detailed side view of Figure 7 is shown in the figure. Figure 9B The image shows a perspective view of the upper conductive element, and... Figure 9C The image shows a top view of the power connection terminal. Detailed Implementation

[0017] In this specification, the terms “coupled,” “electrically coupled,” and / or “electrically connected” do not imply that components must be directly coupled; intermediate elements (such as solder layers) may be provided between “coupled” or “electrically coupled” components.

[0018] Figure 1A A semiconductor package 100 with a dual-sided cooling structure according to the present invention is shown. Here, "dual-sided cooling structure" means that the semiconductor package 100 has an upper conductive element 110 and a lower support substrate 120, which can be used as cooling structures for the semiconductor package 100, respectively. The semiconductor package 100 also includes a first conductive spacing retainer 130, at least one power semiconductor chip 140, and a second conductive spacing retainer 150. The second conductive spacing retainer 150 is disposed between the upper conductive element 110 and the power semiconductor chip 140.

[0019] The lower carrier substrate 120 has an upper electrically conductive layer 121, a lower electrically conductive layer 123 and an electrically insulating layer 122 arranged between the upper electrically conductive layer 121 and the lower electrically conductive layer 123. The lower carrier substrate 120 can be, for example, a substrate of the type DCB (direct copper bonding), DAB (direct aluminum bonding) or AMB (active metal brazing).

[0020] According to an example, the semiconductor package 100 can also have a package body (not shown) which encapsulates the distance holders 130 and 150, the at least one power semiconductor chip 140, the upper electrically conductive element 110 and the lower carrier substrate 120. The gap between the upper electrically conductive element 110 and the lower carrier substrate 120 can be completely or partially filled, in particular, by the package body. However, the metal surface 111 of the upper electrically conductive element 110 and the surface 124 of the lower electrically conductive layer 123 are configured to be completely or at least partially outwardly exposed in any case (i.e. the surfaces 111, 124 are outer surfaces of the semiconductor package 100).

[0021] According to an example, the package body can have or consist of a potting compound or a molding compound. The package body can be manufactured, for example, by means of molding. For manufacturing the package body, the semiconductor package 100, which has not yet been encapsulated, can be placed into a molding tool, a dielectric compound can be injected and the dielectric compound can be cured to the package body.

[0022] The electrically conductive distance holders 130, 150 can consist of a metal or a metal alloy and can have, for example, or consist of aluminum or copper. The first electrically conductive distance holder 130 is physically and electrically connected, for example, by soldering or an electrically conductive adhesive, with the upper electrically conductive element 110 and with the lower carrier substrate 120.

[0023] According to an example, the at least one power semiconductor chip 140 comprises or consists of silicon carbide. According to an example, the at least one power semiconductor chip 140 is an IGBT (insulated gate bipolar transistor) type chip. According to an example, a half-bridge circuit is implemented in the semiconductor package 100. The half-bridge circuit can have a power connection terminal for a positive supply voltage (V DD ), a power connection terminal for a negative supply voltage (V SS ) and power connection terminals configured as a phase.

[0024] The second electrically conductive distance holder 150 can be electrically connected, for example, by soldering or an electrically conductive adhesive, with an electrode (not shown) of the power semiconductor chip 140 and with the upper electrically conductive element 110. The electrode can be a power electrode or a control electrode of the power semiconductor chip 140. The second electrically conductive distance holder 150 can completely or partially cover the power semiconductor chip 140.

[0025] According to an example, the semiconductor package can have external connection terminals in the form of connection pins. At least a portion of these external connection terminals can be designed for electrically connecting electrodes of the at least one power semiconductor chip 140 with the outside. The external connection terminals can be electrically connected with the upper conductive element 110 and / or with the upper conductive layer 121. The connection pins can be part of a lead frame. One of the external connection terminals can be a power connection terminal, which can be electrically connected with a respective power electrode of the at least one power semiconductor chip 140, for example. One or more of the external connection terminals can be a control connection terminal, which is electrically connected with a control electrode (e.g. gate) of the at least one power semiconductor chip 140. One of the external connection terminals can be a measurement connection terminal, which is designed for measuring a V DD SS

[0026] In the semiconductor package 100, the first carrying region of the upper conductive layer 121 is configured for applying a positive supply voltage, the second carrying region of the upper conductive layer 121, which is arranged next to the first carrying region, is configured for a phase, and the first region of the upper conductive element 110 is configured for applying a negative supply voltage, wherein the first region at least partially overlaps the first carrying region. The semiconductor package 100 can be configured such that the first region overlaps the first carrying region to the highest possible extent. The first region can overlap the first carrying region by at least 20%, at least 30%, at least 40% or more, for example.

[0027] The overlap of the first region (on which, for example, V SS ) over the first carrying region (on which, for example, V DD ) can contribute to a reduction of the inductance of the semiconductor package 100. The inductance can be reduced because V SS and V DD are brought closer to each other by the overlap. If the at least one power semiconductor chip 140 involves a silicon carbide-based power semiconductor chip, such a reduction of the inductance can be desirable, for example, because silicon carbide-based power semiconductor chips have a lower interference inductance tolerance than IGBTs.

[0028] Figure 1B The semiconductor package 100_1 is shown, which, apart from the differences described hereinafter, is identical to the semiconductor package 100_0 shown in Fig. 1. The semiconductor package 100_1 comprises a semiconductor package 100, which is identical to the semiconductor package 100_0 shown in Fig. 1, and a semiconductor package 100’, which is identical to the semiconductor package 100_0 shown in Fig. 1. The semiconductor package 100_1 is configured for applying a positive supply voltage to the first carrying region of the upper conductive layer 121 of the semiconductor package 100 and to the first carrying region of the upper conductive layer 121 of the semiconductor package 100’, and for applying a negative supply voltage to the first region of the upper conductive element 110 of the semiconductor package 100 and to the first region of the upper conductive element 110 of the semiconductor package 100’, wherein the first region of the upper conductive element 110 of the semiconductor package 100 overlaps the first carrying region of the upper conductive layer 121 of the semiconductor package 100’, and the first region of the upper conductive element 110 of the semiconductor package 100’ overlaps the first carrying region of the upper conductive layer 121 of the semiconductor package 100. Figure 1A ​​The semiconductor package 100_1 is identical to the semiconductor package 100. In the semiconductor package 100_1, the upper conductive element 110 has an upper carrier substrate 160 with an upper conductive layer 161, a lower conductive layer 163 and an electrically insulating layer 162 arranged between the upper conductive layer 161 and the lower conductive layer 163. Here, the upper conductive layer 161 corresponds to the outwardly exposed metal surface 111.

[0029] The semiconductor package 100_1 can also have outer connection terminals 170, as shown, which are arranged between the upper carrier substrate 160 and the lower carrier substrate 120. According to one example, each of the outer connection terminals 170 can be electrically connected with the lower conductive layer 163 of the upper carrier substrate 160 or with the upper conductive layer 121 of the lower carrier substrate 120. Figure 1B

[0030] The lower conductive layer 163 of the upper carrier substrate 160 and the upper conductive layer 121 of the lower carrier substrate 120 are structured and they may, for example, have chip platforms, line tracks and / or mounting positions for the conductive spacing holders 130, 150.

[0031] Figure 2 A perspective view of a semiconductor package 200 is shown, which can be identical to the semiconductor packages 100 and 100_1. The semiconductor package 200 has a package body 210, which encapsulates the spacing holders 130 and 150, the upper conductive element 110, the lower carrier substrate 120 and at least one power semiconductor chip 140. The surface 111 and the surface 124 (not visible in Figure 2 ) are on opposite sides of the semiconductor package 200 on the package body 210 and are outwardly exposed.

[0032] The package body 210 is composed of a suitable electrically insulating material or has a material, for example, a plastic, a polymer or a resin. The package body 210 may, for example, be a molded body.

[0033] The surface 111 and / or the surface 124 can have an electrically insulating coating and they can be respectively configured for the mounting of cooling bodies.

[0034] ​The semiconductor package 200 has outer connection terminals 220, 230 which are arranged on the following side of the semiconductor package 200 which connects the opposite sides with the metal surface 111 and the surface 124. The outer connection terminal 220 can be designed as a power connection terminal and the outer connection terminal 230 can be designed as a control or measurement connection terminal. According to one example, the power connection terminals are arranged on only one side of the semiconductor package and the control or measurement connection terminals are arranged on only the opposite side. According to another example, the power connection terminals which are configured in phase are arranged on the side with the control or measurement connection terminals. The outer connection terminals 220 and 230 can be part of a common lead frame.

[0035] Figure 3A A perspective view of the lower carrier substrate 120 of the semiconductor package 300 is shown. The semiconductor package 300 can be identical to the semiconductor packages 100, 100_1 and 200. In the perspective view, a first carrier area 310 and a second carrier area 320 of the upper conductive layer 121 can be seen. Between the areas 310 and 320, the upper conductive layer 121 is interrupted. Figure 3A

[0036] According to one example, the area of the first carrier area 310 is as large or approximately as large as the area of the second carrier area 320. The difference of the two areas can be for example about 10%, 20%, 30%, 40%, 50% or 60%.

[0037] The first carrier area 310 can be arranged next to the second carrier area 320. The first carrier area 310 can in particular completely surround the second carrier area 320 on the three sides 301, 302, 303 of the lower carrier substrate 120. On the fourth side 304 of the lower carrier substrate which corresponds to the open side of the first carrier area 310, the first carrier area 310 and the second carrier area 320 can extend to or almost to the outer edge of the lower carrier substrate 120.

[0038] According to one example, the first carrier area 310 can be configured in the shape of a U. The closed side of the U is arranged along the first side 301, the second side 302 and the third side 303 and the open side of the U is arranged on the fourth side 304. The second carrier area 320 can be completely surrounded by the U along the sides 301, 302 and 303.

[0039] The first carrier area 310 can be electrically connected on the fourth side 304 with a first power connection terminal 361 for applying a voltage V DD The second carrier area 320 can be electrically connected on the fourth side 304 with a second power connection terminal 362 which is designed as a phase connection terminal of a half-bridge circuit.

[0040] ​The first carrier region 310 can be electrically connected on the second side 302 with a measurement connection end 366 designed for measuring V DD The second carrier region 320 can be electrically connected on the second side 302 with a second measurement connection end 367 designed for measuring the phase.

[0041] In addition to the first carrier region 310 and the second carrier region 320, one or more further regions can be configured in the upper electrically conductive layer 121 of the lower carrier substrate 120. For example, a further (carrier) region 330 and / or a further (carrier) region 340 and / or a further (carrier) region 350 can be configured.

[0042] The region 330 can be arranged on the fourth side 304 and can be arranged in the opening of the first carrier region 310 next to the second carrier region 320. The region 330 can be electrically connected to the upper carrier substrate 160, for example by means of electrically conductive spacing holders, for example spacing holders 130 arranged on the region 330. The region 330 can be electrically connected on the fourth side 304 with a third power connection end 363 designed for applying V SS The region 330 can be electrically connected on the second side 302 with a third measurement connection end 368 designed for measuring V SS .

[0043] The region 340 can be arranged inside the second carrier region 320 and can be completely surrounded by the second carrier region 320 in the direction of all four sides. The region 340 can be electrically connected to the upper carrier substrate 160, for example by means of electrically conductive spacing holders, for example spacing holders 130. The region 340 can be electrically connected with a first control connection end 364 of the half-bridge circuit arranged on the second side 302.

[0044] The region 350 can be arranged outside the first carrier region 310 and can be arranged along the sides 301, 302 and 303, for example, and can at least partially surround the first carrier region 310 on these sides. According to one example, the region 350 has no electrical connection to the upper carrier substrate 160. The region 350 can comprise a signal line and can be electrically connected with a second control connection end 365 of the half-bridge circuit arranged on the second side 302.

[0045] The semiconductor package 300 has at least one power semiconductor chip. The semiconductor package 300 has, for example, a first power semiconductor chip 311 arranged on the first carrier area 310 and electrically connected thereto and a second power semiconductor chip 321 arranged on the second carrier area 320 and electrically connected thereto. According to one example, the semiconductor package 300 has four first power semiconductor chips 311 and four second power semiconductor chips 321. The first power semiconductor chips 311 can be configured as high-side power semiconductor chips of a half-bridge circuit and the second power semiconductor chips 31 can be configured as low-side power semiconductor chips of a half-bridge circuit of the semiconductor package 300.

[0046] The first and second power semiconductor chips 311 and 321 have, on their lower side, a power electrode, for example a drain, which is coupled to the first carrier area 310 or the second carrier area 320, respectively. The first and second power semiconductor chips 311 and 321 have, on their upper side, a power electrode, for example a source, which is coupled to the upper carrier substrate 160 by means of the electrically conductive standoff 150 arranged on the upper side of the respective power semiconductor chip 311, 321. The power semiconductor chips 311, 321 have, on their upper side, a control electrode, for example a gate, respectively. The control electrode of the first power semiconductor chip 311 is electrically connected to the area 350, for example by means of a bond wire. The control electrode of the second power semiconductor chip 321 is electrically connected to the area 340, for example by means of a bond wire.

[0047] According to one example, the semiconductor package 300 can also have passive elements, for example one or more buffer capacitors 312 and / or a resistance 369_1, arranged on the lower carrier substrate 120. The one or more buffer capacitors can be arranged on the first carrier area 310 and electrically connected thereto. The one or more buffer capacitors 312 can be designed to buffer voltage change processes in the half-bridge circuit. The resistance 369_1 can be a resistance with negative thermal coefficient (English: negative thermal coefficient, NTC) and can be electrically connected to the fourth measurement connection 369. The resistance 369_1 and the fourth measurement connection 369 can be designed to measure the temperature in the semiconductor package 300.

[0048] Figure 3B A perspective view of the upper carrier substrate 160 of the semiconductor package 300 is shown, wherein, in Figure 3B a perspective view of the lower side of the upper carrier substrate 160 is shown (see Figure 3D the arrow for the viewing direction).

[0049] The lower conductive layer 163 of the upper carrier substrate 160 is structured and has a first region 370. The first region 370 at least partially overlaps the first carrier region 310, if the upper carrier substrate 160 is arranged above the lower carrier substrate 120 in the semiconductor package 300. The first region 370 can overlap at least 20%, at least 30%, at least 40% or more of the first carrier region 310.

[0050] The first region 370 can be configured for applying a voltage SS The first region 370 can be configured for electrically connecting (e.g. by means of conductive standoff members) to the region 330 on the lower carrier substrate 120. The first region 370 can be electrically connected (e.g. by means of conductive standoff members arranged on the second power semiconductor chip 321) to the second power semiconductor chip 321.

[0051] The lower conductive layer 163 of the upper carrier substrate 160 can have a second region 380, which can be electrically connected (e.g. by means of one or more conductive standoff members) to the first carrier region 310. The second region 380 can electrically connect the two arms of the first carrier region 310 (which are the portions of the first carrier region arranged along the sides 301 and 303) to each other. The second region 380 can be electrically connected to the first measurement connection 366. The second region 380 can extend along the first side 301 and at least partially along the fourth side 304.

[0052] The lower conductive layer 163 of the upper carrier substrate 160 can have a third region 390, which is electrically connected to the second carrier region 320 of the lower carrier substrate 120. The third region 390 can have a plurality of spatially separated partial regions, e.g. four partial regions as in the example shown in Figure 3B These partial regions can be electrically connected to the second carrier region 320 (and thus also to each other) by conductive standoff members, respectively. Each of these partial regions can cover a first power semiconductor chip 311 and be electrically connected to said first power semiconductor chip by means of standoff members arranged on the respective first power semiconductor chip.

[0053] The lower conductive layer 163 can have a fourth region 395, which is electrically connected to a control electrode of at least one power semiconductor chip of the semiconductor package 300. According to one example, the fourth region 395 is electrically connected to the region 340 of the lower carrier substrate 120. According to one example, the fourth region 395 is electrically connected to a control electrode of the second power semiconductor chip 321.

[0054] Figure 3C It is shown that the upper carrier substrate 160 is arranged in the semiconductor package 300 Figure 3Asemiconductor package 300 after the assembly of the at least one power semiconductor chip 110 on the upper conducting layer 161 of the upper carrier substrate 160. For the sake of clarity, only the lower conducting layer 163 of the upper carrier substrate 160 is shown in Figure 3C The first region 370 at least partially or even mostly overlaps the first carrier region 310. The base surfaces of the upper and lower carrier substrates 120, 160 can be identical or almost identical, and the carrier substrates 120, 160 can be arranged on top of each other in register or almost in register.

[0055] According to an example, the semiconductor package 300 has a package body (see Figure 2 which is not shown in Figure 3C for the sake of clarity.

[0056] Figure 3D A side view of the semiconductor package 300 along the direction of the arrow in Figure 3C is shown.

[0057] Figure 4 A flow chart of a method 400 for manufacturing a semiconductor package having a double-sided cooling structure is shown. According to the method 400, for example, the semiconductor packages 100, 100_1, 200 and 300 can be manufactured.

[0058] The method 400 comprises providing a lower carrier substrate having an upper conducting layer, a lower conducting layer and an electrically insulating layer arranged between the upper and lower conducting layers, wherein a first carrier region of the upper conducting layer of the lower carrier substrate is configured for applying a positive supply voltage and a second carrier region of the upper conducting layer arranged next to the first carrier region is configured for applying a negative supply voltage. The method 400 comprises arranging a first electrically conducting standoff on the upper conducting layer of the lower carrier substrate. The method 400 comprises arranging at least one power semiconductor chip on the upper conducting layer of the lower carrier substrate. The method 400 comprises arranging a second electrically conducting standoff on the power semiconductor chip. The method 400 comprises arranging an upper conducting element on the standoffs opposite the lower carrier substrate such that a first region of the upper conducting element at least partially overlaps the first carrier region, wherein the first region is configured for applying a negative supply voltage.

[0059] According to one example, the upper conductive element has an upper carrier substrate having an upper conductive layer, a lower conductive layer, and an electrically insulating layer disposed between the upper and lower conductive layers. Method 400 may further include electrically connecting a second region of the upper conductive element to two arms of the first carrier region. Method 400 may further include electrically connecting a third region of the upper conductive element to the second carrier region. Method 400 may further include encapsulating a spacing maintainer, at least one power semiconductor chip, the upper conductive element, and the lower carrier region into a package. Method 400 may further include placing a second power semiconductor chip on the upper conductive layer of the lower carrier substrate and electrically connecting the power semiconductor chips into a half-bridge circuit. Method 400 may further include etching the upper conductive layer of the lower carrier substrate to create the first and second carrier regions.

[0060] The following shows another example of semiconductor package 500 with reference to FIG5. Semiconductor package 500 may be similar to semiconductor packages 100, 100_1, 200 and 300, and differs from these semiconductor packages only from those shown below. Semiconductor package 500 may be manufactured according to a manufacturing method such as method 400.

[0061] Figure 5A The lower support substrate 501 of a semiconductor package 500 is shown. The lower support substrate 501 has a first support region 510 and a second support region 520. The first support region has a first power semiconductor chip, and the second support region is disposed adjacent to the first support region 510 and has a second power semiconductor chip. The first support region 510 may, for example, be designed to apply V... DD Furthermore, the second bearing area 520 can be designed as a phase, for example.

[0062] According to one example, a first power connection 531, a second power connection 532, and a third power connection 533 may be disposed on a first side of the lower support substrate 501. The first power connection and the second power connection 531, 532 may be electrically connected to the first support region 510 and, for example, designed as V... DD Connection terminal. The third power connection terminal 533 can be arranged between the first power connection terminal 531 and the second power connection terminal 532 and can be designed for connection with the first region 540 of the upper carrier substrate 502 (see...). Figure 5B Electrical connection. The second power connection terminal can be designed, for example, as V. SS Connection end.

[0063] According to one example, a fourth power connection 534 of the semiconductor package 500 may be electrically connected to a second carrier region 520, and the fourth power connection may be configured as a phase connection. The fourth power connection 534 may be disposed on a second side of the lower carrier substrate 501 opposite to the first side.

[0064] Figure 5B A semiconductor package 500 is shown after the upper carrier substrate 502 is placed on the lower carrier substrate 501. The upper carrier substrate has a first region 540 and a second region 550. The first region 540 can be configured for applying V SS , and the second region 550 can be configured for applying V DD . The first region 540 is electrically connected with the third power connection 533. The second region 550 is connected with the upper power electrode (e.g. source) of the first power semiconductor chip by a first electrically conductive standoff 561 and with the second carrier region by a second electrically conductive standoff 562, respectively.

[0065] As shown in Figure 5B , the first region 540 of the upper carrier substrate 502 at least partially overlaps the first carrier region 510 of the lower carrier substrate 501.

[0066] According to an example, the semiconductor package 500 further has a package body at least partially encapsulating the upper carrier substrate 501 and the lower carrier substrate 502. For the sake of clarity, such a package body is not shown in Figure 5B . The semiconductor package 500 can also have further structured regions (e.g. control lines) and further connection terminals (e.g. measurement or control connection terminals) on the lower carrier substrate 501 and / or on the upper carrier substrate 502. These are also not shown for the sake of clarity.

[0067] According to an example, the border between the first carrier region 510 and the second carrier region 520 is not straight but has a sawtooth. According to an example, a top view of the border between the first carrier region 510 and the second carrier region 520 having such a sawtooth is shown in Figure 5C . Such an extension of the carrier regions 510, 520 can facilitate an optimal overlap of the first carrier region 510 with the first region 540 of the upper carrier substrate 502.

[0068] Another example of a semiconductor package 600 is shown below with reference to Figure 6A and Figure 6B . The semiconductor package 600 can be similar to 100, 100_1, 200, 300 and 500 and only have the differences shown below compared to these semiconductor packages. The semiconductor package 600 can be manufactured according to a manufacturing method such as method 400.

[0069] It is shown with respect to the semiconductor packages 200, 300 and 500 that the power connection terminals designed for applying V DD or V SS are arranged side by side laterally to each other. However, it is also possible that the power connection terminals are arranged on top of each other as in the case of the semiconductor package 600.

[0070] Figure 6A A perspective view of the semiconductor package 600 is shown in a manufacturing stage before the package 630 is manufactured. The manufactured semiconductor package 600 is shown in Figure 6B . The semiconductor package 600 has a first power connection 601, a second power connection 602 and a third power connection 603. According to an example, the first power connection 601 can be configured for applying V DD , the second power connection 602 can be configured as a ground connection, and the third power connection 603 can be designed for applying V SS .

[0071] According to an example, the first and second power connections 601, 602 can be part of the same leadframe. The third power connection 603 can be, for example, part of another leadframe. The third power connection 603 can be arranged above the first power connection 601 by "pick and place" assembly.

[0072] According to an example, the first and third power connections 601, 603 are arranged on a first side of the semiconductor package 600, and the second power connection 602 is arranged on an opposite second side.

[0073] The first and third power connections 601, 603 are arranged such that they at least partially overlap, for example, in an overlap region 604. The overlap region 604 can in particular directly adjoin an edge of the upper conductive element 610 or of the lower carrier substrate 620 of the semiconductor package 600.

[0074] The use of overlapping or at least partially overlapping first and third power connections 601, 603 can contribute to reducing inductance in the semiconductor package 600. As described with respect to the semiconductor package 300 of Fig. 3, in case the semiconductor package 600 also has an overlap of the V DD region of the upper conductive element 610 and the V SS region of the lower carrier substrate 620, a more strongly reduced inductance can be achieved than in case of the semiconductor package 300.

[0075] The first and third power connections 601, 603 can each have an eyelet 605 arranged in a region of the first or third power connection 601, 603 that adjoins the overlap region 604. The eyelet 605 can protrude the first or third power connection 601, 603 along the z-axis in Figure 6A .

[0076] The upper or lower edge of the aperture 605 is particularly capable of being coplanar with the upper surface 611 of the upper conductive element 610 or the lower surface (not shown in FIG. 6) of the lower support substrate 620. Furthermore, the package 630 is capable of being coplanar with both the upper and lower surfaces of the lower support substrate 620. In any case, the aperture 605 is configured such that it is exposed on the package 630. This can be achieved, for example, by having the upper and lower sides of the aperture 605 abut against the wall of the mold during molding of the package 630, thus sealing the interior of the aperture 605. For example, in Figure 6B As shown, the remainder of the first power connection and the third power connection 601, 603 (especially the overlapping area 604) can be covered by the package 630. In this way, the aperture 605 allows the first power connection and the third power connection 601, 603 to be electrically connected from the outside.

[0077] The following is for reference Figure 7A and Figure 7B Another example of semiconductor package 700 is shown. Semiconductor package 700 may be similar to semiconductor package 600 and differs from semiconductor package 600 only from the differences shown below.

[0078] exist Figure 7A The image shows a semiconductor package 700 in the manufacturing stage, where the package body has not yet been manufactured. Figure 7B The semiconductor package 700 is shown after manufacturing.

[0079] Semiconductor package 700 can be distinguished from semiconductor package 600 only in that the first power connection and the third power connection do not have apertures 605. Instead, the upper surface 704 of the third power connection 703 and the lower surface (not shown in FIG. 7) of the first power connection 701 are exposed on the package body 730.

[0080] According to one example, the upper surface 704 of the third power connection 703 is coplanar with the upper surface 711 of the upper conductive element 710 and / or with the upper surface of the package 730, and the lower surface of the first power connection 701 is coplanar with the lower surface of the lower carrier substrate 720 and / or the lower surface of the package 730. This can be achieved, for example, by having the power connections 701 and 703 layered along the z-axis of FIG7.

[0081] According to another example, the upper surface 704 of the third power connection terminal 703 and the lower surface of the first power connection terminal 701 are arranged in a plane that is different from the upper surface 711 of the upper conductive element 710 or the lower surface of the lower supporting substrate 720.

[0082] Alternatively, during the manufacturing of the package 730, the upper surface 704 of the third power connection 703 and the lower surface of the first power connection 701 can be encapsulated together (e.g., by molding), and then, for example, the upper and lower surfaces can be exposed from the package 730 by milling. According to another example, a film can be used during molding to cover the upper surface 704 of the third power connection 703 and the lower surface of the first power connection 701.

[0083] Figure 8A A perspective view of the lower support substrate 820 is shown. This lower support substrate may be the same as lower support substrates 120, 620, and 720. The lower support substrate has a first support region 821 and a second support region 822.

[0084] Similar to the above text about Figure 3A As described in the lower support substrate 120, the first support region 821 can be designed to apply V DD Furthermore, the second bearing area 822 can be designed as a phase. The first bearing area 821 is electrically connected to the first power connection terminal 801, and the second bearing area 822 is electrically connected to the second power connection terminal 802.

[0085] exist Figure 8B In the middle, the upper conductive element 810 is arranged above the lower support substrate 820. The upper conductive element 810 may be substantially the same as the upper conductive element 110 and the upper support substrate 160.

[0086] The upper conductive element 810 has a first region 811 and a second region 812. The first region 811 can be configured for applying V. SS It is also electrically connected to the third power connection terminal 803. The second region 812 can be configured as a phase.

[0087] Regarding the electrical connection between the carrying areas 821, 822 and areas 811, 812, please refer to the implementation scheme of semiconductor package 300 mentioned above.

[0088] As described in relation to semiconductor packages 600 and 700, the first power connection 801 and the third power connection 803 are arranged to overlap each other.

[0089] The overlapping first and third power connections of semiconductor packages 600, 700, and 800 can be arranged on the internal metal surfaces (e.g., conductive layers 121 or 163, see FIG. 1) of the upper conductive elements 610, 710, 810 or the lower supporting substrates 620, 720, 820, respectively. However, alternatively, as in... Figure 9A and Figure 9BAs shown, the first power connection terminal and the third power connection terminal 601, 603, 701, 703, 801, 803 can also be arranged on the electrical insulating layer (e.g., insulating layer 122 or 162, see FIG. 1) of the upper conductive element 610, 710, 810 or the lower supporting substrate 620, 720, 820, and the first and third power connection terminals are adjacent to the corresponding internal metal surfaces.

[0090] Figure 9A Along Figure 7A The x-axis shows an enlarged side view of the first power connection terminal and the third power connection terminals 701 and 703 of the semiconductor package 700, the lower support substrate 720, and the upper conductive element 710.

[0091] As in Figure 9A As shown, the upper conductive element 710 may have an inner conductive layer 716, an electrically insulating layer 714, and an outer conductive layer 712. The lower supporting substrate 720 may have an inner conductive layer 726, an electrically insulating layer 724, and an outer conductive layer 722. The first power connection terminal and the third power connection terminal 701, 703 may be directly disposed on the electrically insulating layer 714 of the upper conductive element 710 or directly disposed on the electrically insulating layer 724 of the lower supporting substrate, respectively. The first power connection terminal 701 may be directly connected to the sidewall of the inner conductive layer 726, and the third power connection terminal 703 may be directly connected to the sidewall of the inner conductive layer 716.

[0092] As in Figure 9A As shown, by directly mounting the power connection terminals 701 and 703 on the upper conductive element 710 or the lower supporting substrate 720, electrical intermediate connectors such as bonding wires or bonding strips can be omitted, so that the power connection terminals 701 and 703 can be connected to the corresponding inner conductive layers 716 and 726. More specifically, the power connection terminals 701 and 703 can be electrically connected to the corresponding inner conductive layers 726 and 716 by brazing, sintering, fusion welding, plugging, or any other direct connection.

[0093] By arranging the overlapping power connectors 701 and 703 on the insulating layers 714 and 724 instead of on the inner conductive layers 716 and 726, the minimum required distance 'a' between the upper conductive element 710 and the lower carrier substrate 720 can be reduced. Eliminating the bonding wires or bonding strips between the power connectors 701 and 703 and the conductive layers 716 and 726 also helps to reduce distance 'a'. In this way, it is possible to manufacture a flatter semiconductor package.

[0094] exist Figure 9AThe gap 901 between the first power connection and the third power connection 701, 703 is an air gap, as shown in the middle. However, it is also possible that the gap 901 is filled with a dielectric, for example in order to improve the electrical insulation between the connections 701, 703. The dielectric can for example involve a thin film or a molding compound (e.g. the encapsulation 730).

[0095] Figure 9B A perspective view showing one example of the upper conductive element 710, in which components such as connections are omitted for the sake of clarity. The inner conductive layer 716 has a recess 902 designed to receive the third power connection 703. The recess 902 can have any suitable shape (with the third power connection 703 having the same shape), for example Figure 9B a sawtooth as shown in the middle.

[0096] Figure 9C A top view showing one example of the third power connection 703, which is shaped such that it fits into the recess 902. The sawtooth can help to improve the electrical and mechanical contact between the third power connection 703 and the inner conductive layer 726.

[0097] The first power connection 701 can be similarly configured as the third power connection 703 and fixed on the lower carrier substrate 720 on a recess similar to the recess 902. According to one example, it is also possible that the second power connection 702 is also fixed on the lower carrier substrate 720 in a recess like the recess 902.

[0098] While specific embodiments have been shown and described in detail to illustrate the application, it will be readily understood by those skilled in the art that various modifications and / or alterations can be made to the specific embodiments without departing from the scope of the present application. The application is intended to cover all modifications or variations of the specific embodiments discussed herein. It is therefore desired that the application be limited only by the scope of the appended claims and their equivalents.

Claims

1. A semiconductor package capable of double-sided cooling, the semiconductor package comprising: An encapsulation made of electrically insulating molding compound; An upper conductive element having an outwardly exposed metal surface that protrudes from a first side of the package. A lower carrier substrate has an upper conductive layer, a lower conductive layer, and an electrically insulating layer, wherein the lower conductive layer has an outwardly exposed surface that exposes from a second side of the package opposite to a first side, and the electrically insulating layer is disposed between the upper conductive layer and the lower conductive layer. A first conductive spacing retainer is disposed between the upper conductive element and the upper conductive layer. A power semiconductor chip, wherein the power semiconductor chip is disposed between the upper conductive element and the upper conductive layer. A second conductive spacing retainer is disposed between the upper conductive element and the power semiconductor chip. The first bearing region of the upper conductive layer of the lower bearing substrate is electrically connected to the first power connection terminal of the semiconductor package, which is capable of being cooled on both sides. The upper conductive layer is disposed in a second carrier region adjacent to the first carrier region, which is electrically connected to the connection terminal of the semiconductor package capable of being cooled on both sides. The first region of the upper conductive element is connected to the second power connection terminal of a semiconductor package capable of being cooled on both sides. The first bearing area has a U-shaped shape, and the second bearing area is surrounded by the first bearing area.

2. The semiconductor package according to claim 1, wherein, The exposed metal surface of the upper conductive element and the first side of the package constitute the first outer surface of the semiconductor package, wherein the exposed metal surface of the lower conductive element and the second side of the package constitute the second outer surface of the semiconductor package.

3. The semiconductor package according to claim 1, wherein, The first power connection terminal is a first pin extending from the package, and the second power connection terminal is a second pin extending from the package.

4. The semiconductor package according to claim 1, wherein, The upper conductive element has an upper carrier substrate, the upper carrier substrate has an upper conductive layer, a lower conductive layer and an electrically insulating layer disposed between the upper conductive layer and the lower conductive layer, wherein the upper conductive layer corresponds to the outwardly exposed metal surface, the metal surface being exposed from a first side of the package.

5. The semiconductor package according to claim 1, wherein, The third region of the upper conductive element is electrically connected to the second bearing region.

6. The semiconductor package according to claim 1, wherein, The fourth region of the upper conductive element is electrically connected to the control electrode of the power semiconductor chip.

7. The semiconductor package according to claim 1, wherein, The first carrier region is at least partially surrounded on three sides by signal lines on the upper conductive layer of the lower carrier substrate, wherein the signal lines are configured to apply a control voltage.

8. The semiconductor package according to claim 1, further comprising: Control connection terminals and measurement connection terminals, The first and second power connection terminals and the phase connection terminal are arranged on the first side of the semiconductor package, which is capable of being cooled on both sides, and the control connection terminal and the measurement connection terminal are arranged on the second side of the semiconductor package, which is capable of being cooled on both sides, opposite to the first side.

9. The semiconductor package according to claim 8, wherein, The first and second power connection terminals, the phase connection terminal, the control connection terminal, and the measurement connection terminal are part of the lead frame.

10. The semiconductor package according to claim 1, wherein, The power semiconductor chip includes silicon carbide.

11. The semiconductor package of claim 1, further comprising: A buffer capacitor is disposed on the first bearing area.

12. A semiconductor package capable of double-sided cooling, the semiconductor package comprising: An upper conductive element having an outwardly exposed metal surface. A lower support substrate has an upper conductive layer, a lower conductive layer, and an electrically insulating layer, wherein the lower conductive layer has an outwardly exposed surface, and the electrically insulating layer is disposed between the upper conductive layer and the lower conductive layer. A first conductive spacing retainer is disposed between the upper conductive element and the upper conductive layer. First and second power semiconductor chips, the first and second power semiconductor chips being disposed between the upper conductive element and the upper conductive layer. A second conductive spacing retainer is disposed between the upper conductive element and the power semiconductor chip. The first and second semiconductor chips are arranged in a half-bridge circuit, such that the first semiconductor chip is the high-side power semiconductor chip of the half-bridge circuit, and the second semiconductor chip is the low-side power semiconductor chip of the half-bridge circuit. The first bearing region of the upper conductive layer of the lower bearing substrate is configured to apply a first supply voltage to the first semiconductor chip. The second carrier region of the upper conductive layer of the lower carrier substrate is arranged along the first carrier region and is configured as the phase node of the half-bridge circuit. The first region of the upper conductive element is configured to apply a second supply voltage to the second semiconductor chip. The first bearing area has a U-shaped shape, and the second bearing area is surrounded by the first bearing area.

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