Display Devices

Abstract

A display device is provided. The display device comprises: a substrate; a lower conductive layer, comprising a protection pattern and an auxiliary conductive pattern on the substrate; a buffer layer, located on the lower conductive layer; an active pattern, located on the buffer layer and overlapping the protection pattern; a first insulating layer, located on the active pattern; and a first conductive layer, located on the first insulating layer, the first conductive layer comprising a gate electrode overlapping the active pattern and a load matching line overlapping the auxiliary conductive pattern.

Description

Technical Field

[0001] Exemplary embodiments of the inventive concept relate to a display apparatus. Background Art

[0002] Recently, display devices with light weight and small size have been manufactured. Cathode ray tube (CRT) display devices have been used due to performance and competitive price. However, CRT display devices have weaknesses in size or portability. Therefore, display devices such as plasma display devices, liquid crystal display devices, and organic light emitting display devices have been highly valued due to small size, light weight, and low power consumption.

[0003] Display devices having display areas with areas of different sizes beyond a simple rectangular shape have been developed. However, for each area with different sizes, problems of brightness deviation and display quality degradation due to structural reasons, manufacturing reasons, etc. have been found. Summary of the invention

[0004] According to aspects of one or more exemplary embodiments of the inventive concept, a display device having a region including regions of different sizes has an improved manufacturing yield and improved brightness uniformity regardless of the region.

[0005] According to one or more exemplary embodiments of the inventive concept, a display device includes: a substrate; a lower conductive layer, including a protection pattern and an auxiliary conductive pattern on the substrate; a buffer layer, located on the lower conductive layer; an active pattern, located on the buffer layer and overlapping the protection pattern; a first insulating layer, located on the active pattern; and a first conductive layer, located on the first insulating layer, the first conductive layer including a gate electrode overlapping the active pattern and a load matching line overlapping the auxiliary conductive pattern.

[0006] In an exemplary embodiment, the display device further includes: an interlayer insulating layer on the first conductive layer; and a second conductive layer on the interlayer insulating layer, the second conductive layer including a load matching electrode overlapping the load matching line.

[0007] In an exemplary embodiment, the first conductive layer may further include a connection line separated from the load matching line.

[0008] In exemplary embodiments, the connection line may be electrically connected to the auxiliary conductive pattern through a first contact hole formed penetrating the first insulating layer and the buffer layer, and electrically connected to the load matching electrode through a second contact hole formed penetrating the interlayer insulating layer.

[0009] In exemplary embodiments, the first contact hole and the second contact hole may not overlap each other.

[0010] In an exemplary embodiment, the substrate may include: a first pixel region; a second pixel region connected to the first pixel region and having a size smaller than that of the first pixel region; a first peripheral region as a non-display region and adjacent to the first pixel region; and a second peripheral region as a non-display region and adjacent to the second pixel region. The load matching line may include a plurality of load matching lines corresponding to the gate line in the second pixel region. The connection line may include a plurality of connection lines.

[0011] In an exemplary embodiment, the auxiliary conductive pattern, the load matching line, and the layer between the auxiliary conductive pattern and the load matching line may form a first load matching capacitor. The load matching line, the load matching electrode, and the layer between the load matching line and the load matching electrode may form a second load matching capacitor.

[0012] In an exemplary embodiment, the first conductive layer may further include a first storage electrode. The display device may further include: a second insulating layer on the first conductive layer; and a third conductive layer on the second insulating layer, the third conductive layer including a second storage electrode overlapping the first storage electrode.

[0013] In an exemplary embodiment, the display device may further include: a third insulating layer located on the first conductive layer; and a light emitting structure located on the third insulating layer, the light emitting structure including a first electrode, a second electrode facing the first electrode, and a light emitting layer located between the first electrode and the second electrode.

[0014] In an exemplary embodiment, the second electrode may overlap with the load matching electrode.

[0015] In an exemplary embodiment, a second power source (ELVSS) may be applied to the second electrode. A first power source (ELVDD) may be applied to the auxiliary conductive pattern and the load matching electrode.

[0016] In an exemplary embodiment, the substrate may include: a first pixel region; a second pixel region connected to the first pixel region and having a size smaller than that of the first pixel region; a first peripheral region as a non-display region and adjacent to the first pixel region; and a second peripheral region as a non-display region and adjacent to the second pixel region. The auxiliary conductive pattern and the load matching line may be located in the second peripheral region. The active pattern and the gate electrode may constitute a thin film transistor. The thin film transistor may be located in the second pixel region.

[0017] In an exemplary embodiment, the second pixel region may be disposed adjacent to an upper side of the first pixel region, and the second peripheral region may include an upper second peripheral region located adjacent to the upper side of the second pixel region. The load matching line may be located in the upper second peripheral region.

[0018] In an exemplary embodiment, the first conductive layer may further include a gate line. The load matching line may be physically connected to the gate line.

[0019] In an exemplary embodiment, the substrate may further include: a third pixel region spaced apart from the second pixel region and connected to the first pixel region and having a size smaller than that of the first pixel region; and a third peripheral region as a non-display region adjacent to the third pixel region. The recess may be formed between the second pixel region and the third pixel region.

[0020] In an exemplary embodiment, the substrate may include at least one polyimide layer and at least one barrier layer.

[0021] In exemplary embodiments, the lower conductive layer may further include molybdenum (Mo).

[0022] In exemplary embodiments, the auxiliary conductive pattern may include a slit.

[0023] According to one or more exemplary embodiments of the inventive concept, a display device includes: a first region; a second region adjacent to the first region and having a size smaller than that of the first region; and a third region adjacent to the first region and spaced apart from the second region to form a recess between the second region and the third region. The display device also includes: a gate line located in the second region; a first load matching capacitor electrically connected to the gate line; and a second load matching capacitor electrically connected to the gate line and overlapping the first load matching capacitor.

[0024] In an exemplary embodiment, the display device further includes: a substrate; an auxiliary conductive pattern located on the substrate; a load matching line located on the auxiliary conductive pattern and formed of the same layer as the gate line; and a load matching electrode located on the load matching line. A first load matching capacitor may be formed by the auxiliary conductive pattern, the load matching line, and an insulating layer located between the auxiliary conductive pattern and the load matching line. A second load matching capacitor may be formed by the load matching line, the load matching electrode, and an insulating layer located between the load matching line and the load matching electrode.

[0025] According to one or more exemplary embodiments of the present invention, a display device includes: a substrate; a lower conductive layer including a protection pattern and an auxiliary conductive pattern on the substrate; a buffer layer located on the lower conductive layer; an active pattern located on the buffer layer and overlapping the protection pattern; a first insulating layer located on the active pattern; and a first conductive pattern located on the first insulating layer, the first conductive pattern including a gate electrode overlapping the active pattern and a load matching line overlapping the auxiliary conductive pattern. Therefore, since the scan line and the load matching line are physically connected in the manufacturing process, use, etc. of the display device, and are not connected to each other through a contact hole, etc., it is possible to provide a structure that minimizes or reduces the characteristic changes and damage of the thin film transistor caused by static electricity flowing into the active pattern through the contact hole.

[0026] In addition, since the load matching capacitor is formed by using the lower conductive layer, the possibility of short circuit with the gate conductive layer is reduced compared with the case where the load matching capacitor is formed using the active layer.

[0027] In addition, since the thin film transistor can be protected by the protection pattern, the display quality of the display device can be improved.

[0028] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other features of the inventive concept will become more apparent by describing some exemplary embodiments of the inventive concept in further detail with reference to the accompanying drawings, in which:

[0030] Figure 1 is a plan view showing a display device according to an exemplary embodiment of the inventive concept;

[0031] Figure 2 is a block diagram of a pixel and a driver according to an example embodiment of the inventive concept;

[0032] Figure 3 It is shown Figure 2 A view of an embodiment of a first pixel shown in FIG.

[0033] Figure 4 is a cross-sectional view showing the display device in a display area;

[0034] Figure 5 It is shown Figure 1 A plan view of area "A";

[0035] Figure 6 is along Figure 5 A cross-sectional view taken along line II';

[0036] Fig. 7A , Figure 7B , Figure 7C and Fig.7D It is shown separately Figure 5 and 6 A plan view of an auxiliary conductive pattern, a first contact hole, a first gate conductive layer, and a second contact hole of a display device;

[0037] Figure 8 is a plan view showing an auxiliary conductive pattern of a display device according to another embodiment of the present invention;

[0038] Fig. 9 is a plan view showing a first gate conductive layer of a display device according to another embodiment of the present invention;

[0039] Fig.10 is a block diagram illustrating an electronic device according to an example embodiment;

[0040] Fig.11A It shows that Fig.10 FIG. 1 is a diagram of an example in which the electronic device is implemented as a television; and

[0041] Fig. 11B It shows that Fig.10 The electronic device is implemented as an example of a smart phone. DETAILED DESCRIPTION

[0042] Here, the inventive concept will be further explained in detail with reference to some exemplary embodiments and the accompanying drawings, wherein the same reference numerals always represent the same elements. In this regard, the present embodiment may have different forms and should not be construed as being limited to the description set forth herein. Therefore, the embodiments are described below only by reference to the accompanying drawings to explain the various aspects of this description. As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. When a statement such as "at least one (kind / person) of ... " is after a column of elements, the entire column of elements is modified, rather than the individual elements in the column.

[0043] It will be understood that although the terms "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another.

[0044] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0045] It will be understood that the terms “comprising,” “including,” and “having” used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0046] For the convenience of description, the size and thickness of the components in the drawings may be exaggerated. In other words, since the size and thickness of the components in the drawings may be arbitrarily shown for the convenience of description, the following embodiments are not limited thereto.

[0047] When specific embodiments can be implemented differently, the specific process order can be performed in a different order than described. For example, two consecutively described processes can be performed substantially simultaneously or in a reverse order to the described order.

[0048] It will be understood that when a layer, region, or component is referred to as being “connected to” another layer, region, or component, the layer, region, or component may be directly connected to the other layer, region, or component, or may be indirectly connected to the other layer, region, or component with one or more intermediate layers, regions, or components interposed therebetween. For example, it will be understood that when a layer, region, or component is referred to as being “electrically connected to” another layer, region, or component, the layer, region, or component may be directly electrically connected to the other layer, region, or component, or may be indirectly electrically connected to the other layer, region, or component with one or more intermediate layers, regions, or components interposed therebetween.

[0049] For ease of description purposes, spatially relative terms such as "under," "below," "below," "above," "above," etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the accompanying drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, an element described as "under" or "below" other elements or features will subsequently be positioned as "above" the other elements or features. Thus, the exemplary term "under" may include both above and below orientations. The device may be otherwise positioned (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein interpreted accordingly.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments of the inventive concepts belong. It will also be understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0051] Figure 1 is a plan view illustrating a display device according to an exemplary embodiment of the inventive concept.

[0052] Reference Figure 1 The display device may include a substrate 100, pixels PXL1, PXL2, and PXL3 (referred to herein as PXL) disposed on the substrate 100, a driving portion (not shown) disposed on the substrate 100 and driving the pixels, a power supply unit for supplying power to the pixels, and a wiring portion connecting the pixels to the driving portion.

[0053] The substrate 100 may include a plurality of regions. At least two regions may have different sizes. For example, the substrate 100 may include three regions, namely, a first region A1, a second region A2, and a third region A3.

[0054] Each of the first area A1, the second area A2, and the third area A3 may have a different shape. For example, each of the first area A1, the second area A2, and the third area A3 may have any shape among a closed polygon including straight sides, a circle or an ellipse including curved sides, and a semicircle or a semiellipse including straight sides and curved sides.

[0055] In some embodiments, each of the first area A1, the second area A2, and the third area A3 may have a substantially rectangular shape, and a corner portion may have a rounded shape.

[0056] The first area A1, the second area A2, and the third area A3 may have pixel areas PXA1, PXA2, and PXA3 (referred to as PXA) and peripheral areas PPA1, PPA2, and PPA3 (referred to as PPA). The pixel area PXA is an area in which pixels for displaying an image are arranged. Each pixel will be described later.

[0057] In some embodiments, each of the first pixel region PXA1 , the second pixel region PXA2 , and the third pixel region PXA3 may correspond to shapes of the first region A1 , the second region A2 , and the third region A3 , respectively.

[0058] The peripheral area PPA is an area in which no pixels are arranged, and is a non-display area in which no image is displayed. A driving part for driving pixels, a power supply unit for applying power to the pixels, and a wiring part for connecting the pixels to the driving part may be arranged in the peripheral area PPA. The peripheral area PPA may correspond to a frame of the display device, and the width of the frame may be determined according to the width of the peripheral area.

[0059] Here, the first area A1, the second area A2, and the third area A3 will be described.

[0060] The first area A1 may have the largest area among the first, second and third areas A1, A2 and A3. The first area A1 may have a first pixel area PXA1 as a display area and a first peripheral area PPA1 surrounding at least a portion of the first pixel area PXA1 and as a non-display area.

[0061] The first pixel area PXA1 may be provided in a shape corresponding to that of the first area A1.

[0062] The first peripheral area PPA1 may be disposed on at least one side of the first pixel area PXA1. In some example embodiments, the first peripheral area PPA1 may surround a boundary of the first pixel area PXA1 and may be disposed at a position other than the positions where the second area A2 and the third area A3, which will be described later, are located. In some embodiments, the first peripheral area PPA1 may include a horizontal portion extending in a width direction and a vertical portion extending in a longitudinal direction. The vertical portion of the first peripheral area PPA1 may be disposed as a pair of partitioning portions along the width direction of the first pixel area PXA1. In an embodiment, among the pair of partitioning portions, the partitioning portion located at the relatively left side in the first direction DR1 may be referred to as a left vertical portion, and the partitioning portion located at the relatively right side may be referred to as a right vertical portion.

[0063] The second area A2 may have a size smaller than that of the first area A1. The second area A2 may have a second pixel area PXA2 as a display area and a second peripheral area PPA2 surrounding at least a portion of the second pixel area PXA2 and as a non-display area. The second peripheral area PPA2 may include an upper second peripheral area PPA2U disposed on an upper side of the second pixel area PXA2 (a direction opposite to the second direction DR2) and a right second peripheral area PPA2R and a left second peripheral area PPA2L disposed at the right and left sides of the second pixel area PXA2 (the first direction DR1 and a direction opposite to the first direction DR1), respectively.

[0064] The second pixel region PXA2 may be provided in a shape corresponding to that of the second region A2. The second pixel region PXA2 may be provided to protrude from the first pixel region PXA1 and may be directly connected to the first pixel region PXA1. In other words, an edge of the second pixel region PXA2 closest to the first pixel region PXA1 may coincide with an edge of the first pixel region PXA1.

[0065] The second peripheral area PPA2 may be disposed on at least one side of the second pixel area PXA2. In some example embodiments, the second peripheral area PPA2 may surround the second pixel area PXA2 and may not be disposed at a location where the first pixel area PXA1 and the second pixel area PXA2 are connected. In some example embodiments, the second peripheral area PPA2 may also include an upper second peripheral area PPA2U extending in the width direction and a left second peripheral area PPA2L and a right second peripheral area PPA2R extending in the longitudinal direction.

[0066] The third area A3 may have a size smaller than that of the first area A1. In an embodiment, the third area A3 may have the same size as that of the second area A2. The third area A3 may have a third pixel area PXA3 in which an image is displayed and a third peripheral area PPA3 surrounding at least a portion of the third pixel area PXA3 and serving as a non-display area. Similar to the second peripheral area PPA2, the third peripheral area PPA3 may also include an upper third peripheral area PPA3U disposed on the upper side of the third pixel area PXA3 (in a direction opposite to the second direction DR2) and a right third peripheral area PPA3R and a left third peripheral area PPA3L disposed on the right and left sides of the third pixel area PXA3 (the first direction DR1 and a direction opposite to the first direction DR1).

[0067] The third pixel area PXA3 may be provided in a shape corresponding to that of the third area A3.

[0068] The third pixel region PXA3 may be disposed to protrude from the first pixel region PXA1 and may be directly connected to the first pixel region PXA1. In other words, an edge of the third pixel region PXA3 closest to the first pixel region PXA1 may coincide with an edge of the first pixel region PXA1.

[0069] The third peripheral area PPA3 may be disposed on at least one side of the third pixel area PXA3. In some example embodiments, the third peripheral area PPA3 may surround the third pixel area PXA3 and may not be disposed at a location where the first pixel area PXA1 and the third pixel area PXA3 are connected. In some example embodiments, the third peripheral area PPA3 may also include an upper third peripheral area PPA3U extending in the width direction and a left third peripheral area PPA3L and a right third peripheral area PPA3R extending in the longitudinal direction.

[0070] In some example embodiments, the third area A3 may have a shape that is linearly symmetrical to that of the second area A2 based on the center line of the first area A1. In this case, the arrangement relationship of each component disposed in the third area A3 may be substantially the same as that of each component disposed in the second area A2, except for some wiring.

[0071] Therefore, the substrate 100 may have a shape in which the second area A2 and the third area A3 protrude from the first area A1 in a direction opposite to the second direction DR2. In an embodiment, the second area A2 and the third area A3 are separated, and the substrate 100 may have a concave shape between the second area A2 and the third area A3. Therefore, the substrate 100 may have a notch NH disposed between the second area A2 and the third area A3.

[0072] In some example embodiments, the left and right vertical portions of the first peripheral area PPA1 may be connected to the left second peripheral area PPA2L of the second peripheral area PPA2 and the right third peripheral area PPA3R of the third peripheral area PPA3, respectively.

[0073] In some example embodiments, the second peripheral area PPA2 and the third peripheral area PPA3 may be connected by a notch peripheral area NPA. For example, the notch peripheral area NPA may be disposed between the second pixel area PXA2 and the third pixel area PXA3 to connect the second peripheral area PPA2 to the third peripheral area PPA3. Therefore, the notch peripheral area NPA may be disposed on one side of the first pixel area PXA1 between the second area A2 and the third area A3.

[0074] The pixel may be arranged in the pixel area PXA on the substrate 100, that is, in the first pixel area PXA1, the second pixel area PXA2, and the third pixel area PXA3. Each pixel may be arranged as a minimum unit for displaying a plurality of images. The pixel may include a display element that emits colored light. For example, the display element may be a liquid crystal display device (LCD device), an electrophoretic display device (EPD device), an electrowetting display device (EWD device), or an organic light emitting diode device (OLED device). Hereinafter, for ease of explanation, an organic light emitting diode device will be described as an example of a display element.

[0075] Each pixel may emit light of one color among red, green and blue, but is not limited thereto. For example, each pixel may emit light of colors such as cyan, magenta, yellow and white.

[0076] The pixel may include a first pixel PXL1 arranged in a first pixel area PXA1, a second pixel PXL2 arranged in a second pixel area PXA2, and a third pixel PXL3 arranged in a third pixel area PXA3. In some example embodiments, a plurality of first pixels PXL1, second pixels PXL2, and third pixels PXL3 may be arranged in a matrix along rows extending in a first direction DR1 and columns extending in a second direction DR2. However, the arrangement form of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 is not particularly limited and may be arranged in any of various forms. For example, the first pixel PXL1 may be arranged so that the first direction DR1 is a row direction, but the second pixel PXL2 may be arranged in another direction other than the first direction DR1; for example, a direction inclined relative to the first direction DR1 may be a row direction of the second pixel PXL2. It should be noted that the third pixel PXL3 may be arranged in the same or different direction as the first pixel PXL1 and / or the second pixel PXL2. Alternatively, in some example embodiments, the row direction may be the second direction DR2, and the column direction may be the first direction DR1.

[0077] In the second area A2 and the third area A3, the number of the second pixels PXL2 and the number of the third pixels PXL3 may vary according to the row. For example, in the second area A2 and the third area A3, the number of the second pixels PXL2 and the number of the third pixels PXL3 arranged in the row corresponding to the rounded corner may be smaller than the number of the second pixels PXL2 and the number of the third pixels PXL3 arranged in the row corresponding to the corner formed by the straight line. In addition, the number of the second pixels PXL2 and the number of the third pixels PXL3 arranged in the row may decrease as the row length becomes shorter.

[0078] The driving section may supply a signal to each pixel through the wiring section, thereby controlling the driving of each pixel.

[0079] In an embodiment, the driving part may include a scan driver (not shown) for providing a scan signal to each pixel along a scan line, a light emitting driver (not shown) for providing a light emitting control signal to each pixel along an emission control line (hereinafter, may also be referred to as a "light emitting control line"), a data driver DDV for supplying a data signal to each pixel along a data line, and a timing controller (not shown). The timing controller may control the scan driver, the light emitting driver, and the data driver DDV.

[0080] In some example embodiments, the scan driver may include a first scan driver ( Figure 2 SDV1), a second scanning driver ( Figure 2SDV2) and a third scan driver ( Figure 2 In some example embodiments, the light emitting driver may include a first light emitting driver ( Figure 2 EDV1), a second light emitting driver ( Figure 2 EDV2) and a third light emitting driver ( Figure 3 EDV3).

[0081] The first scan driver SDV1 may be disposed on the vertical portions of the first peripheral area PPA1. Since the vertical portions of the first peripheral area PPA1 are disposed as a pair of partitions along the width direction of the first pixel area PXA1, the first scan driver SDV1 may be disposed on at least one of the vertical portions of the first peripheral area PPA1. The first scan driver SDV1 may extend in the longitudinal direction of the first peripheral area PPA1.

[0082] In a similar manner, the second scan driver SDV2 may be disposed in the second peripheral area PPA2, and the third scan driver SDV3 may be disposed in the third peripheral area PPA3.

[0083] In some example embodiments, the scan driver may be directly mounted on the substrate 100. When the scan driver is directly mounted on the substrate 100, they may be formed together in the process of forming the pixel. However, the location and method of setting the scan driver are not limited thereto. For example, the scan driver may be formed on a separate chip in the form of a chip on glass and disposed on the substrate 100, or may be mounted on a printed circuit board and connected to the substrate 100 through a connecting member.

[0084] Similar to the first scan driver SDV1, the first light emitting driver EDV1 may also be disposed on the vertical portions of the first peripheral area PPA1. The first light emitting driver EDV1 may be disposed on at least one of the vertical portions of the first peripheral area PPA1. The first light emitting driver EDV1 may extend in the longitudinal direction of the first peripheral area PPA1.

[0085] In a similar manner, the second light emitting driver EDV2 may be disposed in the second peripheral area PPA2 , and the third light emitting driver EDV3 may be disposed in the third peripheral area PPA3 .

[0086] In some example embodiments, the light emitting driver may be directly mounted on the substrate 100. When the light emitting driver is directly mounted on the substrate 100, they may be formed together in the process of forming the pixel. However, the location and method of setting the light emitting driver are not limited thereto. For example, the light emitting driver may be formed on a separate chip in the form of a chip on glass and disposed on the substrate 100, or may be mounted on a printed circuit board and connected to the substrate 100 through a connecting member.

[0087] In some example embodiments, the scan driver and the light emitting driver may be disposed adjacent to each other and may be formed on only one of the vertical portions of the peripheral area PPA. However, the present invention is not limited thereto. The arrangement of the scan driver and the light emitting driver may be changed in various ways.

[0088] The data driver DDV may be disposed on the first peripheral area PPA1. Specifically, the data driver DDV may be disposed on a horizontal portion of the first peripheral area PPA1. The data driver DDV may extend in a width direction of the first peripheral area PPA1.

[0089] In some example embodiments, the positions of the scan driver, the light emitting driver and / or the data driver DDV may be changed.

[0090] The timing controller (not shown) may be connected to the first scan driver SDV1, the second scan driver SDV2, and the third scan driver SDV3, the first light-emitting driver EDV1, the second light-emitting driver EDV2, and the third light-emitting driver EDV3, and the data driver DDV by wiring, and the position of the timing controller is not particularly limited. For example, the timing controller may be mounted on a printed circuit board and may be connected to the first scan driver SDV1, the second scan driver SDV2, and the third scan driver SDV3, the first light-emitting driver EDV1, the second light-emitting driver EDV2, and the third light-emitting driver EDV3, and the data driver DDV by a flexible circuit board. The printed circuit board may be disposed at any of various positions such as one side of the substrate 100 or the rear side of the substrate 100.

[0091] The power supply unit may include at least one power supply line ELVDD and ELVSS. For example, the power supply unit may include a first power supply line ELVDD to which a first power supply voltage is applied (hereinafter, also referred to as "first power supply ELVDD") and a second power supply line ELVSS to which a second power supply voltage is applied (hereinafter, also referred to as "second power supply ELVSS") (see Figure 2 ). The first power line ELVDD and the second power line ELVSS may supply power to the first pixel PXL1 , the second pixel PXL2 , and the third pixel PXL3 .

[0092] The first power line ELVDD may be arranged to correspond to one side of the first pixel area PXA1. For example, the first power line ELVDD may be positioned in a region where the data driver DDV of the first peripheral area PPA1 is disposed. In addition, the first power line ELVDD may extend in a width direction of the first pixel area PXA1.

[0093] In addition, the first power line ELVDD may be arranged in the upper second peripheral area PPA2U and the upper third peripheral area PPA3U to extend in the first direction DR1. Portions of the first power line ELVDD disposed in the upper second peripheral area PPA2U and the upper third peripheral area PPA3U may be used as load matching electrodes (refer to Figure 6 in LCE).

[0094] In the above example, it is assumed that the first power line ELVDD is arranged to correspond to one side of the first pixel area PXA1 in the first peripheral area PPA1, and the second power line ELVSS is arranged in the remaining peripheral area. However, the present invention is not limited thereto. For example, the first power line ELVDD and the second power line ELVSS may be arranged to surround the first pixel area PXA1, the second pixel area PXA2, and the third pixel area PXA3.

[0095] The first power voltage applied to the first power line ELVDD may be higher than the second power voltage applied to the second power line ELVSS.

[0096] Here, due to the difference in structure, the scan line GL disposed in the second pixel region PXA2 may have electrical characteristics different from those of the scan line disposed in the first pixel region PXA1. Therefore, a load deviation of the scan line may occur. In order to compensate for this load deviation, a load matching line LML (see Figure 5 ) may be formed in the second peripheral area PPA2 and connected to a scan line (e.g., gate line) GL of the second pixel area PXA2. Although not shown, the scan line arranged in the third pixel area PXA3 may have a structure similar to that of the scan line GL and the load matching line LML. For example, the scan line GL may be formed by a first gate conductive layer (refer to Figure 6 The load matching line LML in the upper second peripheral area PPA2U may be formed by extending through the right second peripheral area PPA2R in the first direction DR1. Although two scan lines and two load matching lines are shown in the drawings, a plurality of load matching lines corresponding to the scan lines of the second pixel area PXA2 may be formed.

[0097] Although the load matching line is described only with respect to the scan lines in the drawings, a similarly conceived load matching line may be applied to lines crossing the first direction DR1 , for example, emission control lines.

[0098] Figure 2 is a block diagram of a pixel and a driver according to an example embodiment of the inventive concept.

[0099] Reference Figure 1 and Figure 2 , a display device may include pixels, a driving portion, and a wiring portion.

[0100] The pixel may include a first pixel PXL1, a second pixel PXL2, and a third pixel PXL3. The driving unit may include a first scan driver SDV1, a second scan driver SDV2, and a third scan driver SDV3, a first light emitting driver EDV1, a second light emitting driver EDV2, and a third light emitting driver EDV3, a data driver DDV, and a timing controller (or referred to as a "timing control unit") TC. Figure 2 In the figure, for the convenience of explanation, the positions of the first scan driver SDV1, the second scan driver SDV2 and the third scan driver SDV3, the first light-emitting driver EDV1, the second light-emitting driver EDV2 and the third light-emitting driver EDV3, the data driver DDV and the timing controller TC are set, and when the display device is implemented, the first scan driver SDV1, the second scan driver SDV2 and the third scan driver SDV3, the first light-emitting driver EDV1, the second light-emitting driver EDV2 and the third light-emitting driver EDV3, the data driver DDV and the timing controller TC can be arranged at other positions in the display device. For example, the data driver DDV can be arranged closer to the first area A1 than to the second area A2 and the third area A3, but is not limited thereto.

[0101] The wiring part may provide a signal of the driving part to each pixel, and may include a scan line, a data line, an emission control line, a power line, and an initialization power line (not shown).

[0102] The scan lines may include first scan lines S11 to S1n, second scan lines S21 and S22, and third scan lines S31 and S32, respectively connected to the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. The emission control lines may include first emission control lines E11 to E1n, second emission control lines E21 and E22, and third emission control lines E31 and E32, respectively connected to the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. The data lines D1 to Dm and the power lines may be connected to the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3.

[0103] The first pixel PXL1 may be positioned in the first pixel area PXA1. The first pixel PXL1 is connected to the first scan lines S11 to S1n, the first light emission control lines E11 to E1n, and the data lines D1 to Dm. When the scan signal is supplied from the first scan lines S11 to S1n, the first pixel PXL1 is provided with the data signal from the data lines D1 to Dm. The first pixel PXL1 receiving the data signal controls the amount of current flowing from the first power source ELVDD to the second power source ELVSS via the organic light emitting diode (not shown).

[0104] The second pixel PXL2 is disposed in the second pixel area PXA2. The second pixel PXL2 is connected to the second scan lines S21, S22, the second light emission control lines E21, E22, and the data lines D1 to D3. When the scan signals are supplied from the second scan lines S21, S22 and the third scan lines S31, S32, the second pixel PXL2 is supplied with the data signals from the data lines D1 to D3. The second pixel PXL2 receiving the data signal controls the amount of current flowing from the first power source ELVDD to the second power source ELVSS via the organic light emitting diode.

[0105] In addition, although Figure 2 6 second pixels PXL2 are shown to be arranged in the second pixel area PXA2 by two second scan lines S21, S22, two second light emission control lines E21, E22 and three data lines D1 to D3, but it is not limited thereto. That is, the plurality of second pixels PXL2 are arranged to correspond to the size of the second pixel area PXA2, and the numbers of the second scan lines, the second light emission control lines and the data lines can be set differently to correspond to the second pixels PXL2.

[0106] The third pixel PXL3 is disposed in the third pixel area PXA3 and is connected to the third scan lines S31, S32, the third light emission control lines E31, E32 and the data lines Dm-2 to Dm. When the scan signals are supplied from the third scan lines S31, S32 and the second scan lines S21, S22, the third pixel PXL3 is supplied with the data signals from the data lines Dm-2 to Dm. The third pixel PXL3 receiving the data signal controls the amount of current flowing from the first power source ELVDD to the second power source ELVSS via the organic light emitting diode.

[0107] In addition, although Figure 2 6 third pixels PXL3 are shown to be arranged in the third pixel area PXA3 by two third scan lines S31, S32, two third light emission control lines E31, E32 and three data lines Dm-2 to Dm, but not limited thereto. That is, the plurality of third pixels PXL3 are arranged to correspond to the size of the third pixel area PXA3, and the numbers of the third scan lines, the third light emission control lines and the data lines can be differently set to correspond to the third pixels PXL3.

[0108] The first scan driver SDV1 supplies a scan signal to the first scan lines S11 to S1n in response to a first gate control signal GCS1 from the timing control unit TC. For example, the first scan driver SDV1 may sequentially supply the scan signal to the first scan lines S11 to S1n. When the scan signal is sequentially supplied to the first scan lines S11 to S1n, the first pixels PXL1 are sequentially selected in units of horizontal lines.

[0109] The second scan driver SDV2 supplies scan signals to the second scan lines S21 and S22 in response to the second gate control signal GCS2 from the timing control unit TC. Here, the scan signals supplied to the second scan lines S21 and S22 are supplied to the third scan lines S31 and S32 via the scan line connection portion. The second scan driver SDV2 may sequentially supply scan signals to the second scan lines S21 and S22. When the scan signals are sequentially supplied to the second scan lines S21 and S22, the second pixels PXL2 and the third pixels PXL3 are sequentially selected in units of horizontal lines.

[0110] The third scan driver SDV3 supplies a scan signal to the third scan lines S31 and S32 in response to a third gate control signal GCS3 from the timing control unit TC. Here, the scan signal supplied to the third scan lines S31 and S32 is supplied to the second scan lines S21 and S22 via the scan line connection portion. The third scan driver SDV3 may sequentially supply the scan signal to the third scan lines S31 and S32. When the scan signal is sequentially supplied to the third scan lines S31 and S32, the second pixel PXL2 and the third pixel PXL3 are sequentially selected in units of horizontal lines.

[0111] In an embodiment, since the second scan lines S21, S22 and the third scan lines S31, S32 are electrically connected through the scan line connecting parts, the scan signals supplied from the second scan driver SDV2 and the scan signals supplied from the third scan driver SDV3 are supplied such that they are synchronized with each other.

[0112] In addition, the second scan driver SDV2 and the third scan driver SDV3 may be driven so that they are synchronized with each other, and thus, the second scan driver SDV2 and the third scan driver SDV3 may be driven by the same gate control signal GCS. For example, the third gate control signal GCS3 supplied to the third scan driver SDV3 may be set to the same signal as the second gate control signal GCS2.

[0113] The first light emitting driver EDV1 supplies light emitting control signals to the first light emitting control lines E11 to E1n in response to the fourth gate control signal GCS4 from the timing control unit TC. For example, the first light emitting driver EDV1 may sequentially supply light emitting control signals to the first light emitting control lines E11 to E1n.

[0114] Here, the light emitting control signal may be set to have a width greater than that of the scan signal. For example, the light emitting control signal supplied to the i-th (i is a natural number greater than 1) first light emitting control line E1i may be supplied so that it overlaps with the scan signal supplied to the i-1-th first scan line S1i-1 and the scan signal supplied to the i-th first scan line S1i for at least a partial period of time.

[0115] The second light emitting driver EDV2 supplies light emitting control signals to the second light emitting control lines E21, E22 in response to the fifth gate control signal GCS5 from the timing control unit TC. The second light emitting driver EDV2 may sequentially supply light emitting control signals to the second light emitting control lines E21, E22.

[0116] The third light emitting driver EDV3 supplies light emitting control signals to the third light emitting control lines E31, E32 in response to the sixth gate control signal GCS6 from the timing control unit TC. The third light emitting driver EDV3 may sequentially supply light emitting control signals to the third light emitting control lines E31, E32.

[0117] In addition, the light emission control signal can be set to a gate-off voltage (e.g., a high voltage) so that the transistor included in the pixel PXL can be turned off, and the scan signal can be set to a gate-on voltage (e.g., a low voltage) so that the transistor included in the pixel PXL can be turned on.

[0118] In an embodiment, the light emitting control signal supplied from the second light emitting driver EDV2 to the second light emitting control line E21 may be supplied at the same time as the light emitting control signal supplied from the third light emitting driver EDV3 to the third light emitting control line E31. Similarly, the light emitting control signal supplied from the second light emitting driver EDV2 to the second light emitting control line E22 may be supplied at the same time as the light emitting control signal supplied from the third light emitting driver EDV3 to the third light emitting control line E32.

[0119] In an embodiment, the second light emitting driver EDV2 and the third light emitting driver EDV3 may be driven so that they are synchronized with each other, and thus, the second light emitting driver EDV2 and the third light emitting driver EDV3 may be driven by the same gate control signal GCS. For example, the sixth gate control signal GCS6 supplied to the third light emitting driver EDV3 may be set to the same signal as the fifth gate control signal GCS5.

[0120] The data driver DDV may supply data signals to the data lines D1 to Dm in response to the data control signal DCS. The data signals supplied to the data lines D1 to Dm are supplied to the pixels PXL selected by the scan signal.

[0121] The timing control unit TC supplies gate control signals GCS1 to GCS6 generated based on a timing signal supplied from the outside to the scan driver SDV and the light emitting driver EDV, and supplies a data control signal DCS to the data driver DDV.

[0122] Each of the gate control signals GCS1 to GCS6 includes a start pulse and a clock signal. The start pulse controls the timing of the first scan signal or the first light emission control signal. The clock signal is used to shift the start pulse.

[0123] The data control signal DCS includes a source start pulse and a clock signal. The source start pulse controls the starting time point of data sampling. The clock signal is used to control the sampling operation.

[0124] In an embodiment, when the display device is sequentially driven, the first scan driver SDV1 may be provided with the last output signal of the second scan driver SDV2 as a start pulse. Similarly, when the display device is sequentially driven, the first light emitting driver EDV1 may be provided with the last output signal of the second light emitting driver EDV2 as a start pulse.

[0125] The load matching capacitor LMCAP may be connected to the scan lines S21, S22, S31, and S32 and the emission control lines E21, E22, E31, and E32 arranged in the second area A2 and the third area A3. The load matching capacitor LMCAP may be formed to correspond to each of the scan lines S21, S22, S31, and S32 and the emission control lines E21, E22, E31, and E32, respectively. Each of the load matching capacitors LMCAP may include one electrode connected to the scan lines S21, S22, S31, and S32 or the emission control lines E21, E22, E31, and E32 and another electrode connected to the first power supply ELVDD.

[0126] Figure 3 It is shown Figure 2 A view of an embodiment of a first pixel is shown in FIG.

[0127] exist Figure 3 In the figure, for convenience of explanation, the first pixel PXL1 connected to the mth data line Dm, the i-th first scan line S1i and the i-th first light emission control line E1i is shown.

[0128] Reference Figure 3, the first pixel PXL1 according to an embodiment of the present disclosure is provided with an organic light emitting diode OLED, first to seventh transistors T1 to T7 , and a storage capacitor CST.

[0129] The anode of the organic light emitting diode OLED is connected to the first transistor T1 via the sixth transistor T6, and the cathode of the organic light emitting diode OLED is connected to the second power source ELVSS. Such an organic light emitting diode OLED generates light of a specific brightness corresponding to the amount of current supplied from the first transistor T1.

[0130] The first power source ELVDD may be set to a higher voltage than the second power source ELVSS so that current may flow to the organic light emitting diode OLED.

[0131] The seventh transistor T7 is connected between the initialization power supply VINT and the anode of the organic light emitting diode OLED. In addition, the gate electrode of the seventh transistor T7 is connected to the i-1th first scan line S1i-1 or the i+1th first scan line S1i+1. When the scan signal is supplied to the i-1th first scan line S1i-1 or the i+1th first scan line S1i+1, such a seventh transistor T7 is turned on and supplies the voltage of the initialization power supply VINT to the anode of the organic light emitting diode OLED. Here, the initialization power supply VINT can be set to a voltage lower than the data signal.

[0132] The sixth transistor T6 is connected between the first transistor T1 and the organic light emitting diode OLED. In addition, the gate electrode of the sixth transistor T6 is connected to the i-th first light emission control line E1i. When the light emission control signal is supplied to the i-th first light emission control line E1i, such a sixth transistor T6 is turned off, and in other cases, the sixth transistor T6 is turned on.

[0133] The fifth transistor T5 is connected between the first power source ELVDD and the first transistor T1. In addition, the gate electrode of the fifth transistor T5 is connected to the i-th first light emitting control line E1i. When the light emitting control signal is supplied to the i-th first light emitting control line E1i, such a fifth transistor T5 is turned off, and in other cases, the fifth transistor T5 is turned on.

[0134] A first electrode of the first transistor T1 (driving transistor) is connected to the first power source ELVDD via the fifth transistor T5, and a second electrode of the first transistor T1 is connected to the anode of the organic light emitting diode OLED via the sixth transistor T6. In addition, a gate electrode of the first transistor T1 is connected to the first node N1. Such a first transistor T1 controls the amount of current flowing from the first power source ELVDD to the second power source ELVSS via the organic light emitting diode OLED in response to the voltage of the first node N1.

[0135] The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. In addition, the gate electrode of the third transistor T3 is connected to the i-th first scan line S1i. When the scan signal is supplied to the i-th first scan line S1i, such a third transistor T3 is turned on and electrically connects the second electrode of the first transistor T1 and the first node N1. Therefore, when the third transistor T3 is turned on, the first transistor T1 is connected in a diode form.

[0136] The fourth transistor T4 is connected between the first node N1 and the initialization power supply VINT. In addition, the gate electrode of the fourth transistor T4 is connected to the i-1th first scan line S1i-1. When the scan signal is supplied to the i-1th first scan line S1i-1, such a fourth transistor T4 is turned on and supplies the voltage of the initialization power supply VINT to the first node N1.

[0137] The second transistor T2 is connected between the mth data line Dm and the first electrode of the first transistor T1. In addition, the gate electrode of the second transistor T2 is connected to the i-th first scan line S1i. When the scan signal is supplied to the i-th first scan line S1i, such a second transistor T2 is turned on and electrically connects the mth data line Dm and the first electrode of the first transistor T1.

[0138] The storage capacitor CST is connected between the first power source ELVDD and the first node N1. Such a storage capacitor CST stores a data signal and a voltage corresponding to a threshold voltage of the first transistor T1.

[0139] In an embodiment, the second pixel PXL2 and the third pixel PXL3 may be implemented in the same circuit as that of the first pixel PXL1. Therefore, a detailed description of the second pixel PXL2 and the third pixel PXL3 is omitted.

[0140] Figure 4 is a cross-sectional view showing the display device in a display area.

[0141] Reference Figure 4 In an embodiment, the display device may include a substrate 100, a lower conductive layer, a buffer layer 110, an active pattern ACT, a first gate insulating layer 120, a first gate conductive layer, a second gate insulating layer 130, a second gate conductive layer, an interlayer insulating layer 140, a first data conductive layer, a first insulating layer 150, a second insulating layer 160, a second data conductive layer, a third insulating layer 170, a pixel defining layer PDL, a light emitting structure 180 and a thin film encapsulation layer TFE.

[0142] A substrate 100 including any material of a transparent or opaque insulating material may be provided. For example, the substrate 100 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluoride-doped quartz substrate, a soda-lime glass substrate, an alkali-free glass substrate, etc. Alternatively, the substrate 100 may include a flexible transparent material such as a flexible transparent resin substrate (e.g., a polyimide substrate). For example, the substrate 100 may include a first polyimide layer 101, a first barrier layer 102 disposed on the first polyimide layer 101, a second polyimide layer 103 disposed on the first barrier layer 102, and a second barrier layer 104 disposed on the second polyimide layer 103.

[0143] A lower conductive layer including a protective pattern BML1 may be provided on the substrate 100. The protective pattern BML1 may be provided to overlap the active pattern ACT and serve as a protective layer for preventing or substantially preventing the electrical characteristics of the active pattern ACT of the thin film transistor TFT from being degraded. For example, in a process of manufacturing the display device 100, the thin film transistor TFT may be protected from laser light or moisture flowing from the bottom of the substrate 100 as a flexible substrate. The protective pattern BML1 may minimize or reduce a change in the threshold voltage of the thin film transistor TFT caused by laser light irradiated into the active pattern ACT of the thin film transistor TFT through the substrate 100. The lower conductive layer may be formed of a metal having a low light transmittance. For example, the lower conductive layer may include molybdenum (Mo).

[0144] In an embodiment, the buffer layer 110 may be completely disposed on the substrate 100 on which the lower conductive layer is disposed. The buffer layer 110 may prevent or substantially prevent metal atoms and / or impurities from diffusing from the substrate 100 into the active pattern ACT. In addition, the buffer layer 110 may control a heat transfer rate in a crystallization process for forming the active pattern ACT, thereby obtaining a substantially uniform active pattern ACT.

[0145] The active pattern ACT may be disposed on the buffer layer 110. In an embodiment, the active pattern ACT may include amorphous silicon or polycrystalline silicon. In some example embodiments, the active pattern ACT may include an oxide of at least one substance selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The active pattern ACT may include a channel region C and a source region S and a drain region D doped with impurities.

[0146] The first gate insulating layer 120 may be disposed on the buffer layer 110. The first gate insulating layer 120 may be uniformly formed on the buffer layer 110 along the contour of the active pattern ACT. The first gate insulating layer 120 may include silicon compounds, metal oxides, etc. In an embodiment, the first gate insulating layer 120 may be formed of a plurality of layers.

[0147] A first gate conductive layer including a scan line, a gate electrode GE and a first storage electrode CE1 may be disposed on the first gate insulating layer 120. The gate electrode GE may overlap the active pattern ACT. The first gate conductive layer may be formed using metal, alloy, metal nitride, conductive metal oxide or transparent conductive material.

[0148] The second gate insulating layer 130 may be disposed on the first gate insulating layer 120 on which the first gate conductive layer is disposed. For example, the second gate insulating layer 130 may be uniformly formed on the first gate insulating layer 120 along the contour of the first gate conductive layer. Here, the second gate insulating layer 130 may have a relatively small thickness so that a step portion may be formed at a portion of the second gate insulating layer 130 adjacent to the first gate conductive layer. In some example embodiments, the second gate insulating layer 130 may have a relatively large thickness to fully cover the first gate conductive layer so that the second gate insulating layer 130 may have a substantially horizontal surface. The second gate insulating layer 130 may include a silicon compound or a metal oxide, etc. In an embodiment, the second gate insulating layer 130 may be formed of a plurality of layers.

[0149] A second gate conductive layer including a second storage electrode CE2 may be disposed on the second gate insulating layer 130. The second storage electrode CE2 may overlap the first storage electrode CE1 to form a storage capacitor. The second gate conductive layer may be formed using metal, alloy, metal nitride, conductive metal oxide, or transparent conductive material.

[0150] The interlayer insulating layer 140 may be disposed on the second gate insulating layer 130 on which the second gate conductive layer is disposed. For example, the interlayer insulating layer 140 may have a relatively large thickness to sufficiently cover the second gate conductive layer so that the interlayer insulating layer 140 may have a substantially horizontal surface. In some example embodiments, the interlayer insulating layer 140 may be uniformly formed on the second gate insulating layer 130 along the contour of the second gate conductive layer. In embodiments, the interlayer insulating layer 140 may be formed of a plurality of layers.

[0151] The first data conductive layer may be disposed on the interlayer insulating layer 140. The first data conductive layer may be formed using metal, alloy, metal nitride, conductive metal oxide, or transparent conductive material, etc. The first data conductive layer may include a first source-drain pattern SD1 and a data line, and the first source-drain pattern SD1 is electrically connected to the active pattern ACT through a contact hole formed by penetrating the first gate insulating layer 120, the second gate insulating layer 130, and the interlayer insulating layer 140.

[0152] The active pattern ACT and the gate electrode GE may be included in the thin film transistor TFT. For example, the thin film transistor TFT may be about Figure 3 Any of the transistors described.

[0153] The first insulating layer 150 may be disposed on the interlayer insulating layer 140 on which the first data conductive layer is disposed. The first insulating layer 150 may be formed using an inorganic material such as a silicon compound, a metal, or a metal oxide.

[0154] The second insulating layer 160 may be disposed on the first insulating layer 150. The second insulating layer 160 may have a single-layer structure or a multi-layer structure including at least two insulating films. In an embodiment, the second insulating layer 160 may be formed using an organic material. For example, the second insulating layer 160 may include a photoresist, an acrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, etc.

[0155] A second data conductive layer including a second source-drain pattern SD2 electrically connected to the first source-drain pattern SD1 through a contact hole formed penetrating the first and second insulating layers 150 and 160 may be disposed on the second insulating layer 160 .

[0156] The third insulating layer 170 may be disposed on the second insulating layer 160 on which the second data conductive layer is disposed. The third insulating layer 170 may have a single-layer structure or a multi-layer structure including at least two insulating films. In an embodiment, the third insulating layer 170 may be formed using an organic material. For example, the third insulating layer 170 may include a photoresist, an acrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, etc.

[0157] The light emitting structure 180 may include a first electrode 181 , a light emitting layer 182 , and a second electrode 183 .

[0158] The first electrode 181 may be disposed on the third insulating layer 170. The first electrode 181 may be electrically connected to a contact pad (also referred to as a "pad" or "bonding pad") through a contact hole formed through the third insulating layer 170.

[0159] Depending on the emission type of the display device, the first electrode 181 may include a reflective material or a transmissive material. For example, the first electrode 181 may be formed using aluminum, an alloy containing aluminum, aluminum nitride, silver, an alloy containing silver, tungsten, tungsten nitride, copper, an alloy containing copper, nickel, an alloy containing nickel, chromium, chromium nitride, molybdenum, an alloy containing molybdenum, titanium, titanium nitride, platinum, tantalum, tantalum nitride, neodymium, scandium, strontium ruthenium oxide, zinc oxide, indium tin oxide, tin oxide, indium oxide, gallium oxide, indium zinc oxide, etc. These materials may be used alone or in combination with these materials. In an example embodiment, the first electrode 181 may have a single-layer structure or a multilayer structure, which may include a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and / or a transparent conductive film.

[0160] The pixel defining layer PDL may be disposed on the third insulating layer 170 on which the first electrode 181 is disposed. The pixel defining layer PDL may be formed using an organic material. For example, the pixel defining layer PDL may include a photoresist, an acrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, or the like. In some example embodiments, an opening exposing the first electrode 181 may be formed by etching the pixel defining layer PDL. The emission region and the non-emission region of the display device may be defined by the opening of the pixel defining layer PDL. For example, the portion where the opening of the pixel defining layer PDL is located may correspond to the emission region, and the non-emission region may correspond to a portion adjacent to the opening of the pixel defining layer PDL.

[0161] The light emitting layer 182 may be disposed on the first electrode 181 exposed by the opening of the pixel defining layer PDL. In addition, the light emitting layer 182 may extend on the sidewall of the opening of the pixel defining layer PDL. In some example embodiments, the light emitting layer 182 may include an organic light emitting layer (EL), a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), an electron injection layer (EIL), etc. In some example embodiments, in addition to the organic light emitting layer, the hole injection layer, the hole transport layer, the electron transport layer, and the electron injection layer may be formed together to correspond to a plurality of pixels. In some example embodiments, a plurality of organic light emitting layers may be formed using a light emitting material for generating light of different colors (such as red light, green light, and blue light) according to the color pixels of the display device. In some example embodiments, the organic light emitting layer of the light emitting layer 182 may include a plurality of stacked light emitting materials for generating red light, green light, and blue light, thereby emitting white light. Here, the elements of the light emitting layer 182 are formed together to correspond to a plurality of pixels, and each pixel may be divided by a color filter layer.

[0162] The second electrode 183 may be disposed on the pixel defining layer PDL and the light emitting layer 182. Depending on the emission type of the display device, the second electrode 183 may include a transmissive material or a reflective material. For example, the second electrode 183 may be formed using aluminum, an alloy containing aluminum, aluminum nitride, silver, an alloy containing silver, tungsten, tungsten nitride, copper, an alloy containing copper, nickel, an alloy containing nickel, chromium, chromium nitride, molybdenum, an alloy containing molybdenum, titanium, titanium nitride, platinum, tantalum, tantalum nitride, neodymium, scandium, strontium ruthenium oxide, zinc oxide, indium tin oxide, tin oxide, indium oxide, gallium oxide, indium zinc oxide, etc. These materials may be used alone or in combination. In an example embodiment, the second electrode 183 may also have a single-layer structure or a multilayer structure, which may include a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and / or a transparent conductive film.

[0163] The thin film encapsulation layer TFE may be disposed on the second electrode 183. The thin film encapsulation layer TFE may prevent or substantially prevent moisture and oxygen from penetrating from the outside. In an embodiment, the thin film encapsulation layer TFE may include at least one organic layer and at least one inorganic layer. At least one organic layer and at least one inorganic layer may be alternately stacked with each other. For example, the thin film encapsulation layer TFE may include two inorganic layers and an organic layer located between the two inorganic layers, but is not limited thereto. In some example embodiments, a sealing substrate for shielding external air and moisture from penetrating into the display device can be provided instead of the thin film encapsulation layer TFE.

[0164] Figure 5 It is shown Figure 1 A plan view of area "A"; Figure 6 is along Figure 5 A cross-sectional view taken along line II'; Fig. 7A , Figure 7B , Figure 7C and Fig.7D It is shown separately Figure 5 and Figure 6 A plan view of an auxiliary conductive pattern, a first contact hole, a first gate conductive layer, and a second contact hole of a display device.

[0165] Reference Figure 1 and Figures 4 to 7D , in the upper second peripheral area PPA2U, the display device may include a substrate 100, a lower conductive layer, a buffer layer 110, a first gate insulating layer 120, a first gate conductive layer, a second gate insulating layer 130, an interlayer insulating layer 140, a first insulating layer 150, a second insulating layer 160, a third insulating layer 170, a second electrode 183 and a thin film encapsulation layer TFE.

[0166] The lower conductive layer may further include an auxiliary conductive pattern BML2. The auxiliary conductive pattern BML2 may be used to form a capacitor with the load matching line LML to appropriately compensate for the load of the scan line connected to the load matching line LML. In an embodiment, the auxiliary conductive pattern BML2 may be formed of the same layer as the layer of the protection pattern BML1. Therefore, it is possible to compensate for the load of the scan line by using the lower conductive layer without using a separate additional layer structure.

[0167] The first gate conductive layer may further include a load matching line LML and a connection line CTL.

[0168] The load matching line LML may overlap with the auxiliary conductive pattern BML2. The load matching line LML may extend in the first direction DR1. The load matching line LML may be formed for each scan line requiring load compensation. The connection line CTL may be separated from the load matching line LML. The connection line CTL may be connected to the auxiliary conductive pattern BML2 through a first contact hole CNT1 formed by penetrating the first gate insulating layer 120 and the buffer layer 110. The connection line CTL may be connected to the load matching electrode LCE through a second contact hole CNT2 formed by penetrating the second gate insulating layer 130 and the interlayer insulating layer 140. The first contact hole CNT1 and the second contact hole CNT2 may be arranged not to overlap each other, and a plurality of contact holes may be alternately arranged along the connection line CTL.

[0169] The first data conductive layer may include a load matching electrode LCE. The load matching electrode LCE may overlap with the load matching line LML to form a capacitor. That is, in order to reduce the load deviation of the scan line, a load matching capacitor corresponding to the scan line requiring load compensation may be formed. The load matching capacitor may include a first load matching capacitor and a second load matching capacitor, the first load matching capacitor being formed by the auxiliary conductive pattern BML2, the load matching line LML, and an insulating layer between the auxiliary conductive pattern BML2 and the load matching line LML, and the second load matching capacitor being formed by the load matching line LML, the load matching electrode LCE, and an insulating layer between the load matching line LML and the load matching electrode LCE.

[0170] Although the load matching electrode LCE and the auxiliary conductive pattern BML2 are connected through the connection line CTL in the present embodiment, they may be directly connected to each other or may be connected to each other through a conductive pattern of another layer.

[0171] The second electrode 183 may overlap the load matching electrode LCE.

[0172] The second power source ELVSS may be applied to the second electrode 183, and the first power source ELVDD may be applied to the auxiliary conductive pattern BML2 and the load matching electrode LCE. In some example embodiments, the second power source ELVSS may be applied to the load matching electrode LCE.

[0173] In addition, the load matching capacitor is formed by the auxiliary conductive pattern BML2 and the load matching electrode LCE, so that it has a more stable structure compared with the case where the load matching capacitor is formed using the active pattern ACT and the first gate conductive layer. This is because when the load matching capacitor is formed using the active pattern ACT and the first gate conductive layer, a short circuit defect occurs between the active pattern ACT and the first gate conductive layer due to a narrow gap.

[0174] On the other hand, in the notch peripheral area NPA, not only Figure 1 The load matching line LML in the region "A" (which is the peripheral region adjacent to the notch peripheral region NPA) and the auxiliary conductive pattern BML2 may also be formed for load matching. The display device may have a structure similar to Figure 6 The structure of the cross-sectional view is shown in FIG.

[0175] Figure 8 is a plan view showing an auxiliary conductive pattern of a display device according to another embodiment of the present invention.

[0176] In addition to the plurality of slits SLT formed in the auxiliary conductive pattern BML2, the display device Figures 1 to 7D The display devices of the present invention are substantially the same. Therefore, repeated descriptions will be omitted.

[0177] In an embodiment, the auxiliary conductive pattern BML2 may be formed with a slit SLT. The slit SLT may be arranged not to overlap with the load matching line LML. The connection line CTL may be arranged not to overlap with the slit SLT or to overlap with the slit SLT.

[0178] exist Fig. 7A In the embodiment shown in FIG. 1 , the auxiliary conductive pattern BML2 has a plate shape. Figure 8 In the embodiment shown in FIG. 1 , the slits SLT are formed in the auxiliary conductive patterns BML2 . However, the shape of the auxiliary conductive patterns BML2 is not limited thereto and may be variously modified.

[0179] Fig. 9 is a plan view showing a first gate conductive layer of a display device according to another embodiment of the present invention.

[0180] In addition to the arrangement of the load matching line LML and the connection line CTL, the display device and Figures 1 to 7D The display devices of the present invention are substantially the same. Therefore, repeated descriptions will be omitted.

[0181] exist Figure 7C In the embodiment of FIG. 1 , the connection line CTL is arranged above and below the four load matching lines LML, respectively. Fig. 9 In the embodiment of FIG. 1 , one connection line CTL is arranged for each of the two load matching lines LML. However, the arrangement and number of the load matching lines LML and the connection lines CTL are not limited thereto and may be variously changed.

[0182] According to an exemplary embodiment of the present invention, a display device includes: a substrate; a lower conductive layer including a protection pattern and an auxiliary conductive pattern disposed on the substrate; a buffer layer disposed on the lower conductive layer; an active pattern disposed on the buffer layer and overlapping the protection pattern; a first gate insulating layer disposed on the active pattern; and a first gate conductive pattern disposed on the first gate insulating layer, including a gate electrode overlapping the active pattern and a load matching line overlapping the auxiliary conductive pattern. Therefore, since the scan line and the load matching line are physically connected and are not connected to each other through a contact hole or the like in a manufacturing process, use, etc. of the display device, it is possible to provide a structure that minimizes or reduces characteristic changes and damages of a thin film transistor caused by static electricity flowing into the active pattern through the contact hole.

[0183] In addition, since the load matching capacitor is formed by using the lower conductive layer, the possibility of a short circuit with the gate conductive layer can be reduced compared to the case where the load matching capacitor is formed using the active layer.

[0184] In addition, since the thin film transistor can be protected by the protection pattern, the display quality of the display device can be improved.

[0185] Fig.10 is a block diagram illustrating an electronic device according to an example embodiment; Fig.11A It shows that Fig.10 FIG. 1 is a diagram showing an example in which the electronic device is implemented as a television; Fig. 11B It shows that Fig.10 FIG. 1 is an example in which the electronic device is implemented as a smart phone.

[0186] Reference Figures 10 to 11B , the electronic device 500 may include a processor 510, a memory device 520, a storage device 530, an input / output (I / O) device 540, a power supply 550, and a display device 560. Here, the display device 560 may correspond to Figure 1 In addition, the electronic device 500 may also include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, etc. In an exemplary embodiment, as Fig.11A As shown in , the electronic device 500 may be implemented as a television. In another example embodiment, as Fig. 11B As shown in , the electronic device 500 can be implemented as a smart phone. However, the electronic device 500 is not limited thereto. For example, the electronic device 500 can be implemented as a cellular phone, a video phone, a smart tablet, a smart watch, a tablet PC, a car navigation system, a computer monitor, a laptop, a head mounted display (HMD), etc.

[0187] The processor 510 may perform various computing functions. The processor 510 may be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 510 may be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 510 may be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus. The memory device 520 may store data for the operation of the electronic device 500. For example, the memory device 520 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistance random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc.). The storage device 530 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 540 may include an input device such as a keyboard, a keypad, a mouse device, a touch pad, a touch screen, etc. and an output device such as a printer, a speaker, etc. The power supply 550 may provide power for the operation of the electronic device 500.

[0188] The display device 560 may be coupled to other components via a bus or other communication link. In some example embodiments, the display device 560 may be included in the I / O device 540. As described above, the display device 560 may have a display area formed with a notch, the display area formed with the notch includes areas with different surface areas, and the display device 560 may have uniform brightness regardless of the area. However, since this has been described above, its repeated description is omitted.

[0189] The present invention can be applied to a display device and an electronic device including the display device. For example, the present invention can be applied to a cellular phone, a smart phone, a video phone, a smart tablet, a smart watch, a tablet PC, a car navigation system, a television, a computer monitor, a laptop, a head-mounted display, etc.

[0190] The foregoing is an illustration of the inventive concept and should not be construed as limiting it. Although some exemplary embodiments of the inventive concept have been described, it will be readily understood by those skilled in the art that many modifications are possible in the exemplary embodiments without substantially departing from the novel teachings and aspects of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept set forth in the claims. In the claims, means plus function clauses are intended to cover the structures described herein when performing the functions described, and include not only structural equivalents but also equivalent structures. Therefore, it will be understood that the foregoing is an illustration of the inventive concept and will not be construed as limiting the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the appended claims. The inventive concept is defined by the claims included therein and the equivalents of the claims.

Claims

1. A display device, comprising: a substrate including a pixel region and a peripheral region as a non-display region adjacent to the pixel region, the pixel region including an array of pixels; a lower conductive layer, comprising a protection pattern disposed in the pixel region and an auxiliary conductive pattern disposed in the peripheral region on the substrate; a buffer layer, located on the lower conductive layer; an active pattern, located on the buffer layer and overlapping the protection pattern; A first insulating layer, located on the active pattern; as well as A first conductive layer is located on the first insulating layer, the first conductive layer includes a gate electrode overlapping the active pattern, a gate line, and a load matching line overlapping the auxiliary conductive pattern and electrically connected to the gate line, wherein the gate line extends in a first direction in the pixel area.

2. The display device according to claim 1, further comprising: an interlayer insulating layer, located on the first conductive layer; as well as The second conductive layer is located on the interlayer insulating layer, and the second conductive layer includes a load matching electrode overlapping the load matching line.

3. The display device according to claim 2, wherein: The first conductive layer further includes a connecting line separated from the load matching line.

4. The display device according to claim 3, wherein: The connection line is electrically connected to the auxiliary conductive pattern through a first contact hole formed through the first insulating layer and the buffer layer, and is electrically connected to the load matching electrode through a second contact hole formed through the interlayer insulating layer.

5. The display device according to claim 4, wherein: The first contact hole and the second contact hole do not overlap each other.

6. The display device according to claim 3, wherein: The substrate includes: a first pixel region; a second pixel region connected to the first pixel region and having a size smaller than that of the first pixel region; a first peripheral region as a non-display region and adjacent to the first pixel region; and a second peripheral region as a non-display region and adjacent to the second pixel region, and The load matching line includes a plurality of load matching lines corresponding to the gate lines in the second pixel area, and The connecting wires include a plurality of connecting wires.

7. The display device according to claim 2, wherein: The auxiliary conductive pattern, the load matching line, and a layer between the auxiliary conductive pattern and the load matching line form a first load matching capacitor, and The load matching line, the load matching electrode, and a layer located between the load matching line and the load matching electrode form a second load matching capacitor.

8. The display device according to claim 2, wherein: The first conductive layer further includes a first storage electrode, Wherein, the display device further includes: a second insulating layer, located on the first conductive layer; and The third conductive layer is located on the second insulating layer, and the third conductive layer includes a second storage electrode overlapping the first storage electrode.

9. The display device according to claim 8, further comprising: a third insulating layer, located on the first conductive layer; as well as The light emitting structure is located on the third insulating layer, and includes a first electrode, a second electrode facing the first electrode, and a light emitting layer located between the first electrode and the second electrode.

10. The display device according to claim 9, wherein: The second electrode overlaps the load matching electrode.

11. The display device according to claim 9, wherein: A second power source is applied to the second electrode, and A first power source is applied to the auxiliary conductive pattern and the load matching electrode.

12. The display device according to claim 1, wherein: The substrate includes: a first pixel region; a second pixel region connected to the first pixel region and having a size smaller than that of the first pixel region; a first peripheral region as a non-display region and adjacent to the first pixel region; and a second peripheral region as a non-display region and adjacent to the second pixel region, and wherein the auxiliary conductive pattern and the load matching line are located in the second peripheral area, The active pattern and the gate electrode constitute a thin film transistor, and The thin film transistor is located in the second pixel region.

13. The display device according to claim 12, wherein: the second pixel region is adjacent to an upper side of the first pixel region, and the second peripheral region includes an upper second peripheral region located adjacent to the upper side of the second pixel region, Wherein, the load matching line is located in the upper second peripheral area.

14. The display device according to claim 12, wherein: The substrate further includes: a third pixel region separated from the second pixel region, connected to the first pixel region and having a size smaller than that of the first pixel region; and a third peripheral region as a non-display region adjacent to the third pixel region, Wherein, a notch is formed between the second pixel region and the third pixel region.

15. The display device according to claim 1, wherein: The substrate comprises: at least one polyimide layer; and At least one barrier layer.

16. The display device according to claim 1, wherein: The lower conductive layer includes molybdenum.

17. The display device according to claim 1, wherein: The auxiliary conductive pattern includes slits.

18. A display device, comprising: First region; a second region adjacent to the first region and having a size smaller than that of the first region; and a third area adjacent to the first area and spaced apart from the second area to form a notch between the second area and the third area, the display device further comprising: a gate line extending in the first direction and electrically connected to a plurality of pixels in the second pixel area in the second area; a load matching line formed of the same layer as the gate line and disposed in a peripheral area of ​​a non-display area adjacent to the second pixel area; an auxiliary conductive pattern, disposed below the load matching line in the peripheral region and insulated from the load matching line by a first insulating layer; a load matching electrode, disposed above the load matching line in the peripheral region and insulated from the load matching line by a second insulating layer; a first load matching capacitor electrically connected to the gate line and formed by the load matching line and the auxiliary conductive pattern; and A second load matching capacitor is electrically connected to the gate line and overlaps the first load matching capacitor and is formed by the load matching line and the load matching electrode.

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