Semiconductor package and method for manufacturing the semiconductor package

Abstract

A semiconductor package includes: a package substrate; at least one semiconductor chip mounted on the package substrate; and a molding member surrounding the at least one semiconductor chip. The molding member includes fillers. Each filler includes a core and a coating surrounding the core. The core comprises a non-electromagnetic material, and the coating comprises an electromagnetic material. The molding member includes regions each having a different distribution of the filler.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0090056, filed on August 1, 2018, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor package and a method of manufacturing the semiconductor package, and more particularly, to a semiconductor package comprising a molding member surrounding a semiconductor chip and a method of manufacturing the semiconductor package. Background Technology

[0004] Today, with the rapid growth in demand for portable devices in the electronics market, the requirements for smaller size and lighter weight of electronic components mounted on these products are constantly increasing. For small-sized and lightweight electronic components, the semiconductor packages within these components require reduced size and the ability to process large volumes of data. The semiconductor chip mounted within such a semiconductor package is covered by being surrounded by a molding member. Generally, when materials are randomly mixed, the position of the filler contained in the molding member is fixed, making it difficult to selectively change the position of the filler in the molding member according to the type of semiconductor package. Summary of the Invention

[0005] In order to effectively protect the semiconductor chip in the semiconductor package structure, the present invention provides a semiconductor package in which the position of the filler can be controlled in the molding member by means of an electric field and / or a magnetic field.

[0006] To effectively protect the semiconductor chip in the semiconductor package structure, the present invention also provides a method for manufacturing a semiconductor package, wherein the position of the filler can be controlled in the molding component using an electric field and / or a magnetic field.

[0007] The features and effects of this invention are not limited to those described above, and other features and effects will be clearly understood by one of ordinary skill in the art from the following description.

[0008] According to one aspect of the present invention, a semiconductor package includes: a package substrate; at least one semiconductor chip mounted on the package substrate; and a molding member surrounding the semiconductor chip and including fillers. Each filler includes a core and a coating surrounding the core. The core comprises a non-electromagnetic material, and the coating comprises an electromagnetic material. The molding member includes regions each having different distributions of fillers.

[0009] According to another aspect of the present invention, a semiconductor package includes: a package substrate; at least one semiconductor chip mounted on the package substrate; and a molding member surrounding the at least one semiconductor chip. The molding member includes fillers distributed in an epoxy resin material. Each filler includes a core and a coating covering the core. The core is a non-electromagnetic material, and the coating is an electromagnetic material. The fillers are configured to move in a specific direction within the molding member by an electric or magnetic field that can be applied to the molding member, and the molding member includes regions each having a different distribution of the fillers.

[0010] According to another aspect of the present invention, a method of manufacturing a semiconductor package includes: mounting at least one semiconductor chip on a package substrate; coating the package substrate with a molding material including filler to surround the at least one semiconductor chip; moving the filler in a specific direction within the molding material by applying an electric or magnetic field to the molding material; and forming a molded member by curing the molding material. Each filler includes a core and a coating surrounding the core. The core is a non-electromagnetic material, and the coating is an electromagnetic material surrounding the core. Attached Figure Description

[0011] Embodiments of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0012] Figure 1 This is a cross-sectional view of a semiconductor package according to an embodiment;

[0013] Figures 2 to 4 These are cross-sectional views showing semiconductor packages according to other embodiments;

[0014] Figure 5 and Figure 6 These are cross-sectional views of semiconductor packages according to other embodiments;

[0015] Figure 7A This is a flowchart describing a method for manufacturing a semiconductor package according to an embodiment of the present invention, and Figure 7B These are a set of graphs showing the processing time in a method for manufacturing a semiconductor package according to an embodiment.

[0016] Figures 8A to 8D This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment;

[0017] Figures 9A to 9D This is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to another embodiment;

[0018] Figures 10A to 10C This is a cross-sectional view showing the warping of a semiconductor package;

[0019] Figure 11This is a top view showing a semiconductor module including a semiconductor package according to an embodiment; and

[0020] Figure 12 This is a schematic diagram illustrating a system of semiconductor packages according to an embodiment of the present invention. Detailed Implementation

[0021] In the following, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0022] Figure 1 This is a cross-sectional view of a semiconductor package 10 according to an embodiment of the present invention.

[0023] Reference Figure 1 The semiconductor package 10 includes a package substrate 100, a semiconductor chip 200 mounted on the package substrate 100, and a molding member 300 surrounding the semiconductor chip 200.

[0024] The package substrate 100, serving as a support substrate, may include a body 110, a lower protective layer, and an upper protective layer. The package substrate 100 may be formed based on a printed circuit board (PCB), a wafer substrate, a ceramic substrate, a glass substrate, an insertion substrate, or the like. In embodiments according to the present invention, the package substrate 100 may be a PCB. However, the package substrate 100 is not limited to a PCB.

[0025] Meanwhile, interconnects 140 are formed in the package substrate 100, and the interconnects 140 can be electrically connected to the semiconductor chip 200 via at least one of the columnar structure, solder bumps, solder balls and solder layers connected to the upper electrode pad 120 in the upper surface of the package substrate 100.

[0026] Additionally, external connection terminals 150 may be disposed at the lower electrode pad 130 on the lower surface of the package substrate 100. The package substrate 100 may be electrically connected to the module substrate or system board of an electronic device via the external connection terminals 150.

[0027] The interconnect 140 may be multilayered or single-layered and may be formed within the body 110, and the external connection terminals 150 and the semiconductor chip 200 may be electrically connected to each other via the interconnect 140. For example, the lower and upper protective layers protecting the body 110 may include solder resist.

[0028] When the package substrate 100 is a PCB, the body 110 can typically be implemented by the following steps: compressing a polymeric material such as thermosetting resin or epoxy resin (e.g., flame retardant 4 (FR-4), bismaleimide triazine (BT), and Ajinomoto deposited film (ABF)) to a certain thickness, forming the compressed material into a foil, coating copper foil on both surfaces of the foil, and patterning interconnects 140 as transmission paths for electrical signals. Solder resist can be applied to the lower and upper surfaces of the body 110, except for areas connected to terminals (external connection terminal 150 and internal connection terminal 250) (e.g., upper electrode pad 120 and lower electrode pad 130), thus achieving a lower protective layer and an upper protective layer.

[0029] PCBs can be classified as single-layer PCBs where interconnects 140 are formed on only one surface of the PCB, and double-layer PCBs where interconnects 140 are formed on both surfaces of the PCB. Alternatively, copper foil can be designed to have at least three layers using an insulator called prepreg, and multi-layer PCBs can be achieved by forming at least three interconnects 140, depending on the number of layers in the copper foil. The package substrate 100 is not limited to the structure or material of the PCB described above.

[0030] Semiconductor package 10 may have a structure in which a semiconductor chip 200 is mounted on package substrate 100. Although Figure 1 An embodiment is shown in which only one semiconductor chip 200 is mounted on the package substrate 100, but multiple semiconductor chips 200 may be mounted on the package substrate 100.

[0031] Semiconductor chip 200 can be a memory chip or a logic chip.

[0032] Memory chips can be volatile or non-volatile. Volatile memory chips can include existing volatile memory chips, such as Dynamic Random Access Memory (DRAM), Static RAM (SRAM), Thyristor RAM (TRAM), Zero-Capacitor RAM (ZRAM), or Dual-Transistor RAM (TTRAM), as well as volatile memory chips under development. Non-volatile memory chips can include existing non-volatile memory chips, such as Flash memory, Magnetic RAM (MRAM), Spin-Torque MRAM (SST-MRAM), Ferroelectric RAM (FRAM), Phase-Change RAM (PRAM), Resistive RAM (RRAM), Nanotube RRAM, Polymer RAM, Nanoscale Floating Gate Memory, Holographic Memory, Molecular Electronic Memory, or Insulator Resistance Variation Memory, as well as non-volatile memory chips under development.

[0033] Logic chips can be implemented as, for example, microprocessors, graphics processors, signal processors, network processors, chipsets, audio codecs, video codecs, application processors, or system-on-a-chip (SoC), but are not limited to these. For example, a microprocessor may include a single-core or multi-core processor.

[0034] The semiconductor chip 200 may include a semiconductor substrate 210, a semiconductor device layer 220, a lower connection pad 230, a semiconductor interconnect layer 240, and internal connection terminals 250.

[0035] Semiconductor chip 200 may have an active surface and a passive surface facing the active surface in semiconductor substrate 210. The active surface in semiconductor substrate 210 may be the surface facing the upper surface of package substrate 100. Multiple active / passive components and lower connection pads 230 may be formed in the active surface of semiconductor substrate 210.

[0036] Internal connection terminals 250 may be formed between the package substrate 100 and the active surface of the semiconductor chip 200. The internal connection terminals 250 may contact the lower connection pads 230 respectively. The semiconductor chip 200 may be electrically connected to the package substrate 100 via the internal connection terminals 250.

[0037] The semiconductor substrate 210 may include a semiconductor device layer 220 formed on the active surface of the semiconductor substrate 210. A semiconductor interconnect layer 240 may be formed in the semiconductor device layer 220 and may be electrically connected to the internal interconnect terminal 250 via a lower interconnect pad 230.

[0038] For example, semiconductor substrate 210 may include silicon. Alternatively, semiconductor substrate 210 may include semiconductor elements such as germanium or compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). Alternatively, semiconductor substrate 210 may have a silicon-on-insulator (SOI) structure. For example, semiconductor substrate 210 may include a buried oxide (BOX) layer. Semiconductor substrate 210 may include conductive regions, such as doped wells or doped structures. Additionally, semiconductor substrate 210 may have various device isolation structures such as shallow trench isolation (STI) structures.

[0039] Semiconductor device layer 220 may include semiconductor interconnect layer 240 for connecting multiple individual devices to other interconnects formed in semiconductor substrate 210. Semiconductor interconnect layer 240 may include at least one metal interconnect layer and at least one via plug. For example, semiconductor interconnect layer 240 may have a multilayer structure in which at least two metal interconnect layers or at least two via plugs are stacked alternately.

[0040] The lower connection pad 230 may be placed on the semiconductor device layer 220 and electrically connected to the semiconductor interconnect layer 240 in the semiconductor device layer 220. The semiconductor interconnect layer 240 may be electrically connected to the internal connection terminal 250 via the lower connection pad 230. For example, the lower connection pad 230 may include at least one of Al, Cu, Ni, W, Pt and Au.

[0041] A passivation layer may be formed on the semiconductor device layer 220 to protect the semiconductor interconnect layer 240 on the semiconductor device layer 220 and other structures disposed thereunder from external impacts or moisture. The passivation layer may expose at least a portion of the upper surface of the underlying connection pad 230.

[0042] Internal connection terminals 250 may be disposed on the lower connection pads 230. Internal connection terminals 250 may be used to electrically connect the semiconductor chip 200 to the package substrate 100. At least one of a control signal, a power signal, and a ground signal, serving as signals for operating the semiconductor chip 200, may be provided externally via the internal connection terminals 250; data signals to be stored in the semiconductor chip 200 may be provided externally; or data stored in the semiconductor chip 200 may be provided externally. Internal connection terminals 250 may, for example, include at least one of a columnar structure, solder bumps, solder balls, and a solder layer.

[0043] The molded component 300 can be formed to surround the side, lower, and upper surfaces of the semiconductor chip 200. However, compared with... Figure 1 As shown, the upper surface of the semiconductor chip 200 can be exposed through the upper surface of the molding member 300.

[0044] For example, the molded component 300 may be formed from an epoxy molding compound. The epoxy molding compound may have a Young's modulus of about 15 GPa to about 30 GPa and a coefficient of thermal expansion of about 3 ppm to about 30 ppm.

[0045] The molded component 300 is not limited to epoxy molding compounds, but may also include various materials, such as epoxy materials, thermosetting materials, thermoplastic materials, UV-treated materials, etc. Thermosetting materials may include phenolic, anhydride, and amine curing agents and acrylic polymer additives.

[0046] Simultaneously, the molding component 300 can be formed using a molded underfill (MUF) process, so the material covering the outer contour of the semiconductor chip 200 can be equal to the material filling the area between the semiconductor chip 200 and the package substrate 100. As shown, internal connection terminals 250 can be arranged between the semiconductor chip 200 and the package substrate 100, and the molding component 300 can surround the internal connection terminals 250.

[0047] For the molded component 300, an appropriate amount of molding material is injected onto the package substrate 100 through an injection process, and the shape of the semiconductor package 10 is formed by a curing operation. If necessary, the molding material can be pressed to form the shape of the semiconductor package 10 in a pressing process, such as a pressing process. In this case, processing conditions such as the delay time between injection and pressing of the molding material, the amount of molding material injected, and the pressing temperature / pressure can be set taking into account the physical properties of the molding material (e.g., the viscosity of the molding material).

[0048] The side and top surfaces of the molding member 300 may be right angles of approximately 90 degrees. During the process of cutting the package substrate 100 along a dicing line to manufacture the semiconductor package 10, the side and top surfaces of the molding member 300 are typically formed at right angles. Although not shown, marking patterns (e.g., barcodes, numbers, characters, symbols, etc.) including data from the semiconductor chip may be formed in the region on the side of the semiconductor package 10.

[0049] The molding member 300 protects the semiconductor chip 200 from external influences such as contamination and impact. Thus, the molding member 300 may have a thickness that completely surrounds the semiconductor chip 200. Since the molding member 300 completely surrounds the semiconductor chip 200, the width of the molding member 300 may be substantially equal to the width of the semiconductor package 10.

[0050] Additionally, the molding component 300 formed from the epoxy molding compound may include a large amount of filler 310 in the epoxy molding compound. The filler may be spherical. For example, the molding component 300 may be formed from an epoxy material comprising at least about 50 wt% to about 90 wt% of filler 310. In this case, the filler 310 may be configured with a silica (a silicon oxide- or aluminum oxide-based material) core and include a coating 313 surrounding the core 311.

[0051] In embodiments conceived according to the present invention, the filler 310 may comprise a core of non-electromagnetic material and a coating 313 of electromagnetic material surrounding the core 311. To respond to an electric or magnetic field, the filler 310 may be in the form of spheres, plates, or fibers, which are made by coating with metals, metal oxides, carbon materials, functional polymers, etc. Depending on the direction of the electric or magnetic field applied to the molding member 300, the flow and distribution of the filler 310 may be altered to a desired direction.

[0052] In embodiments of the present invention, regardless of the form of the molding component 300, such as powder, granules, liquid or sheet, the molding component 300 can be used as long as it includes filler 310.

[0053] More specifically, coating 313 may include one of metal, metal oxide, polymer, polymer electrolyte and carbon component material, and coating 313 may be formed into target structure using known methods such as sol-gel method, co-precipitation method, thermal spraying method, emulsion method, hydrothermal synthesis method or spray drying method.

[0054] The coating 313 may be formed from different materials depending on the type of external force applied to the molding member 300. In some embodiments, the coating 313 may include one of a polymer, a polymer electrolyte, and a carbon composite material, which are materials that react with an electric field. In other embodiments, the coating 313 may include one of a metal and a metal oxide, which are materials that react with a magnetic field.

[0055] Here, the case where coating 313 is formed by a material that responds to a magnetic field is described in detail. The material contained in coating 313 and responds to a magnetic field can be interpreted not only as a magnetic material, such as a magnetized magnetic material, but also as particles that are magnetized by a magnetic field and attracted by the magnetic field, such as iron or iron oxide.

[0056] The coating 313 may be a powder particle formed from a ferromagnetic, soft magnetic, or paramagnetic material. For example, the coating 313 may be iron oxide (FeO, Fe2O3, Fe2O4, Fe3O4), ferrite material powder such as Ni-Zn ferrite or Mn-Zn ferrite, permalloy, or aluminum-silicon-iron powder, and may include metal powders such as nickel (Ni), zinc (Zn), manganese (Mn), cobalt (Co), magnesium (Mg), aluminum (Al), barium (Ba), copper (Cu), or iron (Fe). Alternatively, a mixture of ferrite powder and metal powder may be used for the coating 313.

[0057] The material particles contained in coating 313 may have a granular structure of about 1 μm, a few μm or tens of μm.

[0058] In the molded component 300, the area with a relatively high distribution of filler 310 can be called the filler dense layer RF, and the area with a relatively low distribution of filler 310 can be called the epoxy resin dense layer RE.

[0059] By using an electric or magnetic field, the filler 310 can be controlled to be distributed at a higher density in a local area of ​​the molded component 300 than in other areas of the molded component 300. As shown, a dense filler layer RF can be formed such that the filler 310 is arranged around the internal connection terminal 250 and has a relatively high distribution in the area between the semiconductor chip 200 and the package substrate 100.

[0060] During or after the process of forming a molding member 300 including filler 310, filler 310 can be transferred in a target direction in the molding member 300 in order to surround the semiconductor chip 200 by applying an electric field or magnetic field to the molding member 300.

[0061] Electric field unit 420 (see) Figure 8A ) and / or magnetic field unit 430 (see Figure 8A The filler 310 can be placed in the upper or lower region of the molded component 300, and details will be described below. In this case, the filler 310 can be placed by the electric field unit 420 (see...). Figure 8A The electric field formed by or generated by magnetic field unit 430 (see Figure 8A The magnetic field formed moves in a specific direction within the molded component 300. Therefore, as... Figure 1 As shown, a filler dense layer RF can be formed in the lower region of the molding member 300, and an epoxy resin dense layer RE can be formed in the upper region of the molding member 300.

[0062] The positions of the filler dense layer RF and the epoxy resin dense layer RE can be fixed by curing the molded component 300. Curing can be thermosetting or photocuring. The cured molded component 300 loses its fluidity, and when the electric field unit 420 (see...) is removed... Figure 8A ) and magnetic field unit 430 (see Figure 8A When this is done, the positions of the filler dense layer RF and the epoxy resin dense layer RE can be maintained.

[0063] Today, with the rapid growth in demand for portable devices in the electronics market, the requirements for smaller size and lighter weight of electronic components are constantly increasing. For these smaller and lighter electronic components, the semiconductor packages housed within them need to be smaller in size and capable of processing large volumes of data. Achieving high-capacity storage within the limited structure of a semiconductor package requires a small thickness of the semiconductor chip stack; therefore, the thickness of semiconductor packages is steadily decreasing. The semiconductor chips housed within such semiconductor packages are protected by being surrounded by molded components.

[0064] In ordinary semiconductor packages that differ from the semiconductor package 10 conceived according to the present invention, the position of the filler contained in the molding member is fixed in a random mixing state. Therefore, it is difficult to selectively change the position of the filler in the molding member according to the type of semiconductor package.

[0065] On the other hand, in the semiconductor package 10 according to the present invention, the filler 310 can be distributed in the molding member 300, and during the formation of the molding member 300, an electric field or magnetic field can be applied to the molding member 300, which is maintained in a fluid or liquid state, to generate a filler-dense layer RF in a local area of ​​the molding member 300, the filler-dense layer RF being a layer made of filler 310 arranged in a high distribution. Then, by curing the molding member 300, which has a flowability, the filler-dense layer RF can be fixed in the molding member 300 in a flowable state.

[0066] In other words, in the semiconductor package 10 conceived according to the present invention, an electric field or magnetic field can be used to control the position of the filler in the molding member 300, and semiconductor chips can be stacked with small thickness, resulting in a semiconductor package suitable for high integration.

[0067] Figures 2 to 4 These are cross-sectional views showing semiconductor packages 20, 30 and 40 according to other embodiments.

[0068] The components contained in semiconductor packages 20, 30, and 40, and the materials contained in the components, as described below, are consistent with the above references. Figure 1 The components or materials described are substantially the same or similar. Therefore, for ease of explanation, the semiconductor package 10 (see [link to description]) is primarily described. Figure 1 The difference between ) and semiconductor packages 20, 30 and 40.

[0069] Reference Figure 2 In the semiconductor package 20 according to the present invention, the filler dense layer RF, i.e. the region in the molding member 300 where the filler 310 is arranged in a relatively high distribution, can be located away from the semiconductor chip 200 and in the upper region of the molding member 300.

[0070] The packing 310 can be moved in a specific direction within the molded member 300 by a force (e.g., tension) in a first direction of an electric or magnetic field. The packing 310 can be controlled to be arranged in a relatively high distribution in local areas of the molded member 300 compared to other areas of the molded member 300. For example... Figure 2 As shown, a filler dense layer RF can be formed such that the filler 310 is disposed in the outermost region of the molding member 300, and an epoxy resin dense layer RE can be formed such that the filler 310 is disposed in a relatively low distribution in the peripheral region of the semiconductor chip 200 and the region between the semiconductor chip 200 and the package substrate 100.

[0071] The positions of the filler dense layer RF and the epoxy resin dense layer RE can be fixed by curing the molded component 300. The positions of the filler dense layer RF and the epoxy resin dense layer RE can be maintained when the electric or magnetic field is removed.

[0072] Reference Figure 3 In the semiconductor package 30 according to the present invention, the filler dense layer RF, i.e. the region in the molding member 300 where the filler 310 is arranged in a relatively high distribution, can be arranged in the peripheral region of the semiconductor chip 200.

[0073] The filler 310 can be moved in a specific direction within the molding member 300 by a force in a first direction of an electric or magnetic field. The filler 310 can be controlled to be arranged in a relatively high distribution in local areas of the molding member 300 compared to other areas of the molding member 300. As shown, a filler dense layer RF can be formed such that the filler 310 surrounds the peripheral region of the semiconductor chip 200, and an epoxy resin dense layer RE can be formed such that the filler 310 is arranged in a relatively low distribution in the outer region of the semiconductor chip 200, excluding the peripheral region of the semiconductor chip 200.

[0074] The positions of the filler dense layer RF and the epoxy resin dense layer RE can be fixed by curing the molded component 300. The positions of the filler dense layer RF and the epoxy resin dense layer RE can be maintained when the electric or magnetic field is removed.

[0075] Reference Figure 4 In the semiconductor package 40 according to the present invention, the filler dense layer RF, i.e. the region in the molding member 300 where the filler 310 is arranged in a relatively high distribution, can be arranged in the sidewall region of the molding member 300.

[0076] The filler 310 can be moved in a specific direction within the molding member 300 by a force in a first direction of an electric or magnetic field. The filler 310 can be controlled to be arranged in a relatively high distribution in local areas of the molding member 300 compared to other areas. As shown, a filler-dense layer RF can be formed such that the filler 310 is arranged in the outermost region of the sidewalls of the molding member 300, and an epoxy resin-dense layer RE can be formed such that the filler 310 is arranged in a relatively low distribution in the peripheral region of the semiconductor chip 200, the upper region of the molding member 300, and the region between the semiconductor chip 200 and the package substrate 100.

[0077] The positions of the filler dense layer RF and the epoxy resin dense layer RE can be fixed by curing the molded component 300. The positions of the filler dense layer RF and the epoxy resin dense layer RE can be maintained when the electric or magnetic field is removed.

[0078] In other words, according to Figures 2 to 4The semiconductor packages 20, 30, and 40 of the present invention shown can be configured to interact with semiconductor package 10 (see Figure 1 The different positions of the filler dense layer RF and the epoxy resin dense layer RF in the package include the filler dense layer RF and the epoxy resin dense layer RF. Since the filler 310 can move in a specific direction in the molding member 300 due to the force in the first direction of the electric field or magnetic field, the position of the filler 310 can be changed to the target direction according to the design of the semiconductor package.

[0079] Figure 5 and Figure 6 These are cross-sectional views showing semiconductor packages 50 and 60 according to other embodiments of the present invention.

[0080] Including the components and materials in the semiconductor packages 50 and 60 described below, as referenced above. Figure 1 The components or materials described are substantially the same or similar. Therefore, for ease of explanation, the semiconductor package 10 (see [link to description]) will be the primary focus. Figure 1 The difference between semiconductor packages 50 and 60.

[0081] Reference Figure 5 The semiconductor package 50 according to the present invention may have: a first filler dense layer RF1, which is a region in the molding member 300 in which the first filler 310 is arranged in a relatively high distribution; and a second filler dense layer RF2, which is a region in the molding member 300 in which the second filler 320 is arranged in a relatively high distribution.

[0082] The first filler 310 and the second filler 320 included in the molding member 300 included in the semiconductor package 50 may each have a force in a first direction relative to the magnetic field and a force in a second direction opposite to the force in the first direction (e.g., bouncing). Therefore, the first filler 310 and the second filler 320 may be arranged in different regions of the molding member 300.

[0083] Meanwhile, the material included in the core 311 of the first packing 310 can be substantially the same as the material included in the core 321 of the second packing 320. In addition, the diameter 311D of the core 311 in the first packing 310 can be substantially the same as the diameter 321D of the core 321 in the second packing 320.

[0084] The difference between the first filler 310 and the second filler 320 may arise from the coating. The material contained in the coating 313 of the first filler 310 may be different from the material contained in the coating 323 of the second filler 320. However, in this case, the thickness 313T of the coating 313 of the first filler 310 may be substantially the same as the thickness 323T of the coating 323 of the second filler 320.

[0085] More specifically, the material contained in the coating 313 of the first filler 310 may be a ferromagnetic material, while the material contained in the coating 323 of the second filler 320 may be a diamagnetic material. Conversely, the material contained in the coating 313 of the first filler 310 may be a diamagnetic material, while the material contained in the coating 323 of the second filler 320 may be a ferromagnetic material.

[0086] Ferromagnetic materials, such as iron (Fe), cobalt (Fe), and nickel (Ni), are materials that possess a force in a first direction by being magnetized in the same direction as the magnetic field, and retain their magnetism when the magnetic field is removed. On the other hand, diamagnetic materials, such as copper (Cu) and gold (Au), are materials that possess a force in a second direction by being magnetized in the opposite direction to the magnetic field, and return to their original state when the magnetic field is removed.

[0087] Therefore, by utilizing a molding member 300 comprising a first filler 310 and a second filler 320 having different properties, a first filler dense layer RF1 with a relatively high distribution of the first filler 310 and a second filler dense layer RF2 with a relatively high distribution of the second filler 320 can be arranged in different regions of the molding member 300. An epoxy resin dense layer RE can be disposed between the first filler dense layer RF1 and the second filler dense layer RF2.

[0088] In some embodiments, as shown, a first filler dense layer RF1 may be disposed in the region between the semiconductor chip 200 and the package substrate 100, and a second filler dense layer RF2 may be disposed away from the semiconductor chip 200 and in the upper region of the molding member 300. In other embodiments, although not shown, the first filler dense layer RF1 may be disposed in the region of the left side wall of the molding member 300, and the second filler dense layer RF2 may be disposed in the region of the right side wall of the molding member 300. However, the arrangement of the first filler dense layer RF1 and the second filler dense layer RF2 is not limited thereto.

[0089] Reference Figure 6 The semiconductor package 60 according to the present invention may have a third filler dense layer RF3 in the molding member 300 having a third filler 330 arranged in a relatively high distribution and a fourth filler dense layer RF4 having a fourth filler 340 arranged in a relatively high distribution.

[0090] The third filler 330 and the fourth filler 340 included in the molding member 300 of the semiconductor package 60 exhibit strong and weak responses to an electric field, respectively. In other words, the force of the third filler 330 relative to the electric field in a first direction may be greater than the force of the fourth filler 340 relative to the electric field in the first direction. Therefore, the third filler 330 and the fourth filler 340 may be arranged in different regions of the molding member 300.

[0091] Meanwhile, the material included in the core 331 of the third packing 330 may be the same as the material included in the core 341 of the fourth packing 340. In addition, the diameter 331D of the core 331 of the third packing 330 may be substantially the same as the diameter 341D of the core 341 of the fourth packing 340.

[0092] The difference between the third filler 330 and the fourth filler 340 may arise from the coating. The thickness 333T of the coating 333 of the third filler 330 may be different from the thickness 343T of the coating 343 of the fourth filler 340. However, in this case, the material included in the coating 333 of the third filler 330 may be the same as the material included in the coating 343 of the fourth filler 340.

[0093] More specifically, all materials included in the coating 333 of the third filler 330 and the coating 343 of the fourth filler 340 may be polyelectrolytes, and the third filler 330 and the fourth filler 340 may be manufactured by forming the thickness 333T of the coating 333 of the third filler 330 and the thickness 343T of the coating 343 of the fourth filler 340 to be different from each other.

[0094] For example, polyelectrolytes such as polystyrene, polyacrylate, polyallylamine hydrochloride, and polylysine are polymers that have electrolyte groups in each repeating unit and are charged when dissolved in water. Therefore, polyelectrolytes exist in a positively or negatively charged state and respond to an electric field.

[0095] Therefore, by utilizing the molding member 300 which includes a third filler 330 and a fourth filler 340 that respond differently to an electric field, a third filler dense layer RF3 with a relatively high distribution of the third filler 330 and a fourth filler dense layer RF4 with a relatively high distribution of the fourth filler 340 can be arranged in different regions of the molding member 300.

[0096] In some embodiments, as shown in the figures, a third filler dense layer RF3 may be spaced apart from the semiconductor chip 200 and disposed in the uppermost region of the upper region of the molding member 300, and a fourth filler dense layer RF4 may be disposed below the third filler dense layer RF3 in the uppermost region of the molding member 300. An epoxy resin dense layer RE may be disposed below the fourth filler dense layer RF4.

[0097] In other embodiments, although not shown, a third filler dense layer RF3 may be disposed at the lowermost end of the lower region of the molding member 300, and a fourth filler dense layer RF4 may be disposed on the third filler dense layer RF3 in the lower region of the molding member 300. However, the arrangement of the third filler dense layer RF3 and the fourth filler dense layer RF4 is not limited thereto.

[0098] in other words, Figure 5 and Figure 6 The semiconductor packages 50 and 60 shown according to the present invention can be configured to interact with semiconductor package 10 (see Figure 1 The different positions of the filler dense layer RF and the epoxy resin dense layer RE in the ) include the filler dense layer RF and the epoxy resin dense layer RE.

[0099] In some embodiments, the first filler 310 and the second filler 320 may be formed with coatings comprising different materials, and may move in a specific direction within the molding member 300 due to the magnetic field. Therefore, the positions of the first filler 310 and the second filler 320 can be controlled in a target direction depending on the design of the semiconductor package.

[0100] In some embodiments, the third filler 330 and the fourth filler 340 may be formed with coatings of different thicknesses, and may move in a specific direction within the molding member 300 due to an electric field. Therefore, the positions of the third filler 330 and the fourth filler 340 can be controlled in a target direction according to the design of the semiconductor package.

[0101] Figure 7A This is a flowchart of a method for manufacturing a semiconductor package according to an embodiment of the present invention, and Figure 7B This is a set of graphs illustrating the processing time in a method for manufacturing a semiconductor package according to an embodiment of the present invention.

[0102] Reference Figure 7A The method for manufacturing a semiconductor package (S10) may include the processes described below. When embodiments are implemented differently, specific processes may be performed differently from the processes described. For example, the two processes described in sequence may be performed substantially simultaneously, or they may be performed in the reverse order.

[0103] The method (S10) for manufacturing a semiconductor package according to the present invention includes: preparing a package substrate (S100); mounting at least one semiconductor chip on the package substrate (S200); coating the package substrate with a molding material having fillers, each filler having a core comprising a non-electromagnetic material and a coating comprising an electromagnetic material covering the core, to surround the at least one semiconductor chip (S300); moving the fillers in a particular direction in the molding material by applying an electric field or a magnetic field to the molding material (S400); and forming a molded component by curing the molding material (S500).

[0104] Refer to what will be described later. Figures 8A to 9D The technical features of each of the processes are described in detail.

[0105] In the method S10 of manufacturing a semiconductor package according to the present invention (see...) Figure 7A )middle, Figure 7B The relationship between the processing time T400 for applying an electric or magnetic field to the molding material and the processing time T500 for hardening the molding material is shown.

[0106] In some embodiments, the curing process of the molding material can begin after the application of an electric or magnetic field to the molding material. In other words, the processing time T400 for applying the electric or magnetic field to the molding material and the processing time T500 for curing the molding material can be separated from each other.

[0107] In other embodiments, the application of an electric or magnetic field to the molding material can begin before the curing process begins, and the application of the electric or magnetic field to the molding material and the curing process can be performed simultaneously. Alternatively, the application of the electric or magnetic field to the molding material can begin before the curing process begins, and the curing process can be completed after the application of the electric or magnetic field to the molding material is finished. In other words, the time T400 for applying the electric or magnetic field to the molding material and the time T500 for curing the molding material can at least partially overlap. However, the processing times T400 and T500 are not limited thereto.

[0108] Figures 8A to 8D This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment.

[0109] Reference Figure 8A A shell 400 is prepared that defines an internal region 400S, in which a molded component 300 will be formed (see...). Figure 8DThe package substrate 100 on which the semiconductor chip 200 is mounted is arranged in the inner region 400S. The housing 400 may include an electric field unit 420 (e.g., an RF generator) that generates an electric field and / or a magnetic field unit 430 (e.g., a magnetron) that generates a magnetic field.

[0110] The molding component 300, which can be formed by a transfer molding process, can be realized in a form defined by the housing 400 (see Figure 8D Therefore, the molded component 300 to be formed (see...) can be used as a basis. Figure 8D Predetermine the housing size 400.

[0111] Meanwhile, the housing 400 may include an injection path 410 and an ejection path (not shown) to inject the molding material 300M (see... Figure 8B The molding material 300M is injected into the injection path 410 and fills the internal region 400S of the housing 400 (see...). Figure 8B It can be launched through the launch path.

[0112] Reference Figure 8B Molding material 300M can be injected into the internal region 400S of housing 400. Molding material 300M may include a large number of spherical fillers 310 randomly dispersed in epoxy molding compound. For example, molding material 300M can be formed from an epoxy resin-based material comprising at least about 50 wt% to about 90 wt% of filler 310.

[0113] The molding material 300M is injected into the internal region 400S of the housing 400 in a fluid state, and the molding material 300M can be injected until the internal region 400S is completely filled. The process of injecting the molding material 300M into the housing 400 can be performed under vacuum conditions.

[0114] An appropriate amount of molding material 300M is injected onto the package substrate 100 via an injection process. Pressure can be applied to the molding material 300M as needed, such as through a pressing process. In this case, the physical properties of the molding material 300M (e.g., viscosity) can be taken into account to determine factors such as the delay time between injection and pressurization, the amount of molding material 300M injected, and the processing conditions of pressurization temperature / pressure.

[0115] Molding material 300M is injected to fill the internal region 400S without any empty areas. Achieving high-capacity memory within the limited structure of a semiconductor package requires a small thickness of the semiconductor chip stack; therefore, the thickness of the semiconductor package steadily decreases. In the semiconductor package, the size of the internal connection terminals 250 continues to decrease, and the process of filling the area between the semiconductor chip 200 and the package substrate 100 can be extremely difficult to perform.

[0116] In the method for manufacturing a semiconductor package according to the present invention, when the molding material 300M is injected, an electric field unit 420 that generates an electric field or a magnetic field unit 430 that generates a magnetic field can be operated, and the filler 310 can be arranged to fill between the semiconductor chip 200 and the package substrate 100 by means of the electric field or the magnetic field.

[0117] Based on the movement of the filler 310, the molding material 300M can move in a direction similar to the direction of movement of the filler 310. In other words, the filler 310 is moved by an electric field or magnetic field to arrange it around the internal connection terminal 250. Therefore, the molding material 300M, which can be simultaneously affected by the movement of the filler 310 and the injection pressure, can be easily injected to surround the internal connection terminal 250 without any gaps.

[0118] Reference Figure 8C After the internal region 400S of the housing 400 is filled (e.g., completely filled) with the molding material 300M, the molding material 300M can be cured.

[0119] In the method for manufacturing a semiconductor package according to the present invention, after the molding material 300M is injected, an electric field unit 420 for generating an electric field or a magnetic field unit 430 for generating a magnetic field can be operated, and the filler 310 can be arranged to fill between the semiconductor chip 200 and the package substrate 100 by the electric field or the magnetic field.

[0120] In this case, the filler 310 can be moved in a specific direction in the molding material 300M by the force between the electric fields generated by the electric field unit 420 or the magnetic fields generated by the magnetic field unit 430 in a first direction. Therefore, as shown, the filler dense layer RF can be formed in the lower region of the molding material 300M, and the epoxy resin dense layer RE can be formed in the upper region of the molding material 300M.

[0121] The positions of the filler dense layer RF and the epoxy resin dense layer RE can be fixed by curing the molding material 300M. Curing can be thermosetting or photocuring. The cured molding material 300M loses its fluidity, and the positions of the filler dense layer RF and the epoxy resin dense layer RE can be maintained when the electric or magnetic field is removed.

[0122] By utilizing the method for manufacturing a semiconductor package according to the present invention, the filler dense layer RF and the epoxy resin dense layer RE can be formed in different regions of the molding material 300M. Since the filler 310 can move in a specific direction in the molding member 300 due to a force in a first direction of an electric or magnetic field, the position of the filler 310 can be changed to a target direction according to the design of the semiconductor package.

[0123] Unlike the diagram, the filler dense layer RF, i.e. the region in the molding material 300M where the filler 310 is arranged in a relatively high distribution, can be spaced apart from the semiconductor chip 200 and arranged in the upper region of the molding material 300M, in the sidewall region of the molding material 300M, or in the peripheral region of the semiconductor chip 200.

[0124] Reference Figure 8D A prepared semiconductor package can be fabricated on the package substrate 100, and a molding member 300 surrounding the semiconductor chip 200 can be formed in the prepared semiconductor package. The side surfaces and top surfaces of the molding member 300 can be right angles of approximately 90 degrees.

[0125] A prepared semiconductor package having molded component 300 can be coupled to housing 400 (see...) Figure 8C Separation. Although not shown, a process for forming a marking pattern (barcode, number, character, symbol, etc.) including data of the semiconductor chip 200 can be performed in the area on the side of the molded component.

[0126] Figures 9A to 9D This is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to another embodiment;

[0127] Reference Figure 9A A housing 500 can be fabricated, in which a molded component 300 will be formed (see...). Figure 9D The housing 500 may include a bottom housing 500B and a top housing 500T. The bottom housing 500B is filled with molding material 300M, and a package substrate 100 on which a plurality of semiconductor chips 200 are mounted is disposed in the top housing 500T. The housing unit 500 may include an electric field unit 520 (e.g., an RF generator) for generating an electric field and / or a magnetic field unit 530 (e.g., a magnetron) for generating a magnetic field.

[0128] The molding component 300, which can be formed by compression molding, can be realized in a form defined by the housing 500 (see Figure 9D Therefore, the molded component 300 to be formed (see...) can be used as a basis. Figure 9D Predetermine the housing size 500.

[0129] Meanwhile, the housing 500 may include a bottom housing 500B and a top housing 500T. The bottom housing 500B includes a molding material 300M, and the top housing 500T includes a package substrate 100 on which a plurality of semiconductor chips 200 are mounted above the bottom housing 500B.

[0130] Reference Figure 9B The molding material 300M can be moved into the internal region 510 of the housing 500. The molding material 300M may include a large amount of spherical filler 310 in an epoxy molding compound. For example, the molding material 300M can be formed from an epoxy resin-based material comprising at least about 50 wt% to about 90 wt% of filler 310.

[0131] The molding material 300M can be moved in a fluid state into the internal region 510 of the housing 500, and can be moved until the internal region 510 is completely filled with the molding material 300M. The filler 310 can be arranged in a random distribution state in the molding material 300M. In other words, the electric field unit 520 and / or magnetic field unit 530 may not yet have generated an electric field or magnetic field.

[0132] Reference Figure 9C In the method of manufacturing semiconductor packages, when moving the molding material 300M, an electric field is generated by operating the electric field unit 420 or a magnetic field is generated by operating the magnetic field unit 430. The filler 310 can be spaced apart from the plurality of semiconductor chips 200 by the electric field or magnetic field and is arranged in the upper region of the molding material 300M.

[0133] In this case, the filler 310 can be moved in a specific direction in the molding material 300M by the force between the electric fields generated by the electric field unit 420 or between the magnetic fields generated by the magnetic field unit 430 in a first direction. Therefore, as shown, the filler dense layer RF can be formed in the upper region of the molding material 300M, and the epoxy resin dense layer RE can be formed in the lower region of the molding material 300M.

[0134] The positions of the filler dense layer RF and the epoxy resin dense layer RE can be fixed by curing the molding material 300M. Curing can be thermosetting or photocuring. After curing, the molding material 300M loses its fluidity and retains the positions of the filler dense layer RF and the epoxy resin dense layer RE when the electric or magnetic field is removed.

[0135] Unlike the illustration, the filler dense layer RF, i.e. the region in the molding material 300M where the filler 310 is arranged in a relatively high distribution, can be arranged to fill between the plurality of semiconductor chips 200 and the package substrate 100, and the filler dense layer RF can be arranged in the sidewall region of the molding material 300M, or alternatively, the filler dense layer RF can be arranged in the peripheral region of the plurality of semiconductor chips 200.

[0136] Reference Figure 9D It can manufacture prepared semiconductor packages, wherein the molded component 300 surrounds a plurality of semiconductor chips 200 on the package substrate 100.

[0137] Through a series of semiconductor processing steps, the prepared semiconductor package can be arranged in the form of a package substrate 100, multiple semiconductor chips 200, and a molding component 300. Individually segmented semiconductor packages can be manufactured by performing a cutting process in a cutting line DL using a mechanical cutter or a razor cutter.

[0138] The dicing line DL is used to divide the prepared semiconductor package into individual semiconductor packages. Therefore, the side surfaces of the package substrate 100 and the side surfaces of the molding member 300 can be substantially on the same plane. Additionally, the side and top surfaces of the molding member 300 can be right angles of approximately 90°.

[0139] Figures 10A to 10C This is a cross-sectional view showing the warping of a semiconductor package;

[0140] Will Figures 10A to 10C Referring to the semiconductor package 10, a plurality of semiconductor chips 200 are mounted on the top surface of the package substrate 100, and a molding member 300 is formed around the plurality of semiconductor chips 200. Thus, the top surface of the package substrate 100 is substantially and completely covered by the molding member 300.

[0141] In the semiconductor package 10 having the above-described structure, the materials included in the package substrate 100, the plurality of semiconductor chips 200, and the molding member 300 are different from each other and may have different coefficients of thermal expansion. Therefore, during the manufacturing process of the semiconductor package 10, changes in the environment such as temperature and pressure can cause the semiconductor package 10 to warp.

[0142] For example, in the case of the package substrate 100, the molded component 300 may shrink or expand at room temperature or high temperature, resulting in deformations such as warping of the semiconductor package 10. Additionally, as... Figure 10A and Figure 10B As shown, when the filler 310 included in the molded component 300 is arranged in a randomly mixed state, the effect on the filler 310 can be ignored.

[0143] When the coefficients of thermal expansion of the package substrate 100 and the molding member 300 in the semiconductor package 10 are different, warping can occur when compressive stress is applied to the molding member 300 and tensile stress is applied to the package substrate 100, causing the semiconductor package 10 to have a shape in which the central region bends downward, such as... Figure 10A As shown. On the other hand, when tensile stress is applied to the molding member 300 and compressive stress is applied to the package substrate 100, warping can occur, causing the semiconductor package 10 to have a shape in which the central region bends upward, as shown. Figure 10B As shown. In other words, due to the warping of the semiconductor package 10, the semiconductor package 10 may not be flat and may have height differences WA and WB between the central region and the peripheral region.

[0144] like Figure 10C As shown, in the semiconductor package 10 according to the present invention, the coefficient of thermal expansion can vary in different regions depending on the distribution of the filler 310. Therefore, the coefficients of thermal expansion in the upper and lower regions of the molded member 300 can be different from each other. Thus, by controlling the distribution of the filler 310 in the target direction, compared with a reference... Figure 10A and Figure 10B Compared to the described warpage of the semiconductor package 10, the warpage of the semiconductor package 10 can be reduced. In other words, when the filler 310 is arranged in a high distribution in a local area of ​​the molding member 300, the warpage of the semiconductor package 10 can be reduced due to the effect of the filler 310. Although not shown, the filler 310 in the molding member 300 may each comprise at least two materials with different coefficients of thermal expansion.

[0145] As a result, in the semiconductor package 10 conceived according to the present invention, taking into account the coefficients of thermal expansion of the materials included in the package substrate 100, the plurality of semiconductor chips 200 and the molding member 300, by controlling the position of the filler 310 using an electric field or magnetic field, the tensile stress and compressive stress applied to the semiconductor package 10 can be effectively controlled, and the warpage of the semiconductor package 10 can be reduced and / or minimized.

[0146] Figure 11 This is a top view showing a semiconductor module 1000 including a semiconductor package 1030 according to an embodiment.

[0147] Reference Figure 11 The semiconductor module 1000 includes a module substrate 1010, a control chip 1020 mounted on the module substrate 1010, and a plurality of semiconductor packages 1030 mounted on the module substrate 1010.

[0148] Multiple input / output terminals 1050, which can be coupled to a motherboard, are arranged on one side of the module substrate 1010. Multiple semiconductor packages 1030 may be semiconductor packages 10, 20, 30, 40, 50, or 60 according to the present invention. Multiple semiconductor packages 1030 may be manufactured according to a method (S10) for manufacturing semiconductor packages according to the present invention.

[0149] Figure 12 This is a schematic diagram illustrating a system 1100 of a semiconductor package manufactured in a method for manufacturing a semiconductor package according to an embodiment of the present invention.

[0150] Reference Figure 12 The system 1100 includes a controller 1110, an input / output device 1120, a memory 1130, an interface 1140, and a bus 1150.

[0151] System 1100 may be a system for sending or receiving data or a mobile system. In some embodiments, the mobile system may be a portable computer, a network tablet, a mobile phone, a digital music player, or a memory card.

[0152] The controller 1110 used to control the program executing in system 1100 may include a microprocessor, digital signal processor, microcontroller, etc.

[0153] Input / output device 1120 can be used to input or output data to system 1100. System 1100 connects to external devices such as personal computers or networks using input / output device 1120 and exchanges data with external devices. For example, input / output device 1120 may be a touchpad, keyboard, or display.

[0154] The memory 1130 may store data for operation of the controller 1110 or data processed in the controller 1110. The memory 1130 may be a semiconductor package 10, 20, 30, 40, 50 or 60 according to the present invention. In addition, the memory 1130 may be manufactured according to the method S10 for manufacturing a semiconductor package according to the present invention.

[0155] Interface 1140 can serve as a data transmission path between system 1100 and external devices. Controller 1110, input / output device 1120, memory 1130 and interface 1140 can communicate with each other via bus 1150.

[0156] While the inventive concept has been specifically shown and described with reference to the accompanying drawings, it should be understood by one of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept. Therefore, it should be understood that the above embodiments do not limit the scope of the inventive concept.

Claims

1. A semiconductor package, comprising: Package substrate; At least one semiconductor chip is mounted on the substrate of the package; as well as Molded components surrounding the at least one semiconductor chip, The molded component includes filler. Each of the fillers includes a core and a coating surrounding the core. The core comprises a non-electromagnetic material. The coating includes electromagnetic materials, and The molded component includes regions having different distributions of the filler. The packing material includes a first packing material and a second packing material. The first packing material is configured to respond to an electric field in a relatively stronger manner compared to the second packing material. The second packing is configured to respond relatively weakly to an electric field compared to the first packing, and The first filler and the second filler are arranged in different regions of the various regions of the molded component.

2. The semiconductor package according to claim 1, wherein, The at least one semiconductor chip is electrically connected to the package substrate using solder bumps, and The filler in the molding member is arranged around each of the solder bumps, and in each region of the molding member, in the region between the at least one semiconductor chip and the package substrate, the filler in the molding member has a relatively high distribution.

3. The semiconductor package according to claim 1, in, The filler in the molding member is arranged in a relatively high distribution in the peripheral region of the at least one semiconductor chip.

4. The semiconductor package according to claim 1, in, The filler is spaced apart from the semiconductor chip, and in each region of the molding member, the filler is arranged in a relatively high distribution in the upper region of the molding member.

5. The semiconductor package according to claim 1, wherein, The filler in the molded component is configured to move in a direction that reduces the warpage of the package substrate, and The molded component is configured to have different coefficients of thermal expansion in different regions of the molded component depending on the different distribution of the filler.

6. The semiconductor package according to claim 5, wherein, The molded component includes an upper region and a lower region. The coefficients of thermal expansion in the upper region of the molded component and the coefficients of thermal expansion in the lower region of the molded component are different from each other.

7. The semiconductor package according to claim 1, wherein, The diameter of the first packing is different from the diameter of the second packing, and The material in the coating of the first filler is the same as the material in the coating of the second filler.

8. A semiconductor package, comprising: Package substrate; At least one semiconductor chip is mounted on the substrate of the package; as well as Molded components surrounding the at least one semiconductor chip, The molded component includes filler. Each of the fillers includes a core and a coating surrounding the core. The core comprises a non-electromagnetic material. The coating includes electromagnetic materials, and The molded component includes regions having different distributions of the filler. The packing material includes a first packing material and a second packing material. The first packing material responds to the magnetic field by having a force in a first direction. The second packing material has a force in the second direction in response to the magnetic field. The second direction is opposite to the first direction, and The first filler and the second filler are arranged in different regions of the various regions of the molded component.

9. The semiconductor package according to claim 8, wherein, The material in the coating of the first filler is different from the material in the coating of the second filler.

10. A semiconductor package, comprising: Package substrate; At least one semiconductor chip is mounted on the substrate of the package; as well as Molded components surrounding the at least one semiconductor chip, The molded component includes fillers distributed in an epoxy resin material. Each of the fillers includes a core and a coating covering the core. The core is made of a non-electromagnetic material. The coating is an electromagnetic material. The filler is configured to move in a specific direction within the molding member in response to an electric or magnetic field applied to the molding member, and The molded component includes regions having different distributions of the filler. The packing includes a first packing and a second packing. The first packing material is configured to respond to an electric field in a relatively stronger manner compared to the second packing material. The second packing material is configured to respond relatively weakly to an electric field compared to the first packing material. The first filler and the second filler are arranged in different regions of the various regions of the molded component.

11. The semiconductor package of claim 10, wherein, The core comprises silicon oxide or aluminum oxide, and The coating comprises one of a metal, a metal oxide, a polymer, a polymer electrolyte, and a carbon composite material.

12. The semiconductor package of claim 11, wherein, The electromagnetic material in the coating of the first filler and the electromagnetic material in the coating of the second filler both include polymer electrolytes, and The thickness of the coating of the first filler is different from the thickness of the coating of the second filler.

13. The semiconductor package of claim 10, wherein, The shape of the filler includes at least one of spheres, plates, and fibers.

14. A semiconductor package, comprising: Package substrate; At least one semiconductor chip is mounted on the substrate of the package; as well as Molded components surrounding the at least one semiconductor chip, The molded component includes fillers distributed in an epoxy resin material. Each of the fillers includes a core and a coating covering the core. The core is made of a non-electromagnetic material. The coating is an electromagnetic material. The filler is configured to move in a specific direction within the molding member in response to an electric or magnetic field applied to the molding member, and The molded component includes regions having different distributions of the filler. The packing material includes a first packing material and a second packing material. The first packing is configured to have a force in a first direction in response to a magnetic field. The second packing is configured to have a force in the second direction in response to a magnetic field. The second direction is opposite to the first direction. The electromagnetic material in the coating of the first filler is a ferromagnetic material. The electromagnetic material in the coating of the second filler is a diamagnetic material, and The coatings of the first filler and the second filler have the same thickness.

15. A method for manufacturing a semiconductor package, the method comprising: At least one semiconductor chip is mounted on a package substrate; A molding material is applied to the package substrate to surround the at least one semiconductor chip. The molding material includes filler. Each of the fillers includes a core and a coating surrounding the core. The core comprises a non-electromagnetic material, and The coating includes an electromagnetic material; The filler is moved in a specific direction by applying an electric or magnetic field to the molding material; as well as The molding material is cured to form a molded component. During the application of the molding material, The packing includes a first packing and a second packing. The first packing material is configured to respond to an electric field in a relatively stronger manner compared to the second packing material. The second packing is configured to respond relatively weakly to an electric field compared to the first packing, and The first filler and the second filler are arranged in different regions of the various regions of the molded component.

16. The method according to claim 15, wherein, The step of mounting the semiconductor chip includes mounting the semiconductor chip onto the package substrate using solder bumps, and The step of moving the filler includes: applying an electric or magnetic field to move the filler to arrange the filler around each of the solder bumps and to arrange the filler in a relatively high distribution in the region between the semiconductor chip and the package substrate in the molding material.

17. The method according to claim 15, wherein, Moving the filler includes applying an electric or magnetic field such that the filler is arranged in a relatively high distribution in the molding material in the peripheral region of the semiconductor chip.

18. The method according to claim 15, wherein, Moving the filler includes applying an electric or magnetic field such that the filler is spaced apart from the semiconductor chip and the filler is arranged in a relatively high distribution in the upper region of the molding material.

19. The method according to claim 15, wherein, In the step of moving the filler, an electric or magnetic field is applied to the filler, causing the filler to move in a direction that reduces the warpage of the package substrate, and In the step of forming the molded component, the coefficient of thermal expansion in different regions of the molded component varies according to the distribution of the filler.

20. The method according to claim 19, wherein, After an electric or magnetic field is applied, the coefficient of thermal expansion in the upper region of the molded material is different from that in the lower region of the molded material.

21. The method according to claim 15, wherein, During the process of coating the molding material The molding material includes the filler distributed in the epoxy resin material. The core comprises silicon oxide or aluminum oxide, and The coating comprises one of a metal, a metal oxide, a polymer, a polymer electrolyte, and a carbon composite material.

22. The method according to claim 15, in, The time during which an electric or magnetic field is applied to the molding material while the filler is moved in the specific direction, and the time during which the molding material is cured, overlap at least partially with each other.

23. The method according to claim 15, wherein, The electromagnetic material in the coating of the first filler and the electromagnetic material in the coating of the second filler both include polymer electrolytes, and The thickness of the coating of the first filler is different from the thickness of the coating of the second filler.

24. A method for manufacturing a semiconductor package, the method comprising: At least one semiconductor chip is mounted on a package substrate; A molding material is applied to the package substrate to surround the at least one semiconductor chip. The molding material includes filler. Each of the fillers includes a core and a coating surrounding the core. The core comprises a non-electromagnetic material, and The coating includes an electromagnetic material; The filler is moved in a specific direction by applying an electric or magnetic field to the molding material; as well as The molding material is cured to form a molded component. During the application of the molding material, The packing includes a first packing and a second packing. The first packing is configured to have a force in a first direction in response to a magnetic field. The second packing is configured to have a force in a second direction opposite to the first direction in response to a magnetic field. The electromagnetic material in the coating of the first filler is a ferromagnetic material, and The electromagnetic material in the coating of the second filler is an antimagnetic material.

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