Packaging structure of power semiconductor device

Abstract

The invention belongs to but not limited to the technical field of power semiconductor packaging, and discloses a packaging structure of a power semiconductor device. The power module comprises a lead frame, a plastic package body, a base island, a bonding wire and a semiconductor chip assembly, a first power unit and a second power unit are integrated, the first unit comprises two driving ICs, six IGBTs and six FRD chips, the second unit comprises two driving ICs and six MOS chips, 46 pins are provided, and functions are clearly divided. All the IC chips and the FRD chips are arranged on the same base island, the back faces of the chips are welded to the base island, and the front faces of the chips are connected with pins in a standard mode through bonding wires. The structure solves the problems of complex packaging layout, disordered connection and the like in the prior art, can drive the compressor and the fan respectively, realizes high integration level and compact layout, shortens an electric connection path, reduces parasitic parameters, reduces the overall size and cost, and improves reliability and engineering compatibility.

Description

Technical Field

[0001] This invention belongs to, but is not limited to, the field of power semiconductor packaging technology, and particularly relates to a packaging structure for a power semiconductor device. Background Technology

[0002] Power semiconductor devices are primarily used for the conversion, modulation, and control of electrical energy. They are key fundamental components in power electronic systems and are widely used in industrial automation, home appliances, new energy power generation, transportation, and motor drives. In a typical power electronic system, power semiconductor devices not only acquire and convert electrical energy from the power source but also provide stable and controllable power output to loads such as motors, compressors, and fans. Therefore, their performance and packaging directly affect the system's efficiency, reliability, and integration.

[0003] As power electronics technology advances towards higher power density, miniaturization, and system-level integration, traditional power semiconductor packaging methods are gradually revealing their limitations. Structures represented by traditional discrete packages such as the TO series typically use a single chip or a small number of chips as basic units, resulting in limited functional integration and making it difficult to achieve multiple power outputs or collaborative operation of multiple devices within a single package. In practical applications, to meet complex loads or multifunctional requirements, multiple discrete modules often need to be combined, which not only increases the number of external connections and wiring complexity but also negatively impacts system reliability and cost control.

[0004] To address the aforementioned issues, existing technologies have proposed a hybrid power module packaging structure composed of IGBTs and MOSFETs. This solution utilizes the complementary advantages of the high-speed switching characteristics of MOSFETs and the high voltage and current carrying capacity of IGBTs by connecting MOSFETs and IGBTs in parallel within the same module, adapting to application scenarios that balance switching speed and power handling capabilities. Simultaneously, this existing technology employs certain packaging structure optimization techniques to reduce spatial distribution parameters such as parasitic inductance within the module, thereby mitigating the adverse effects of packaging on the high-speed switching performance of MOSFETs.

[0005] However, this existing hybrid power module packaging structure still has significant shortcomings. Its so-called packaging optimization mainly focuses on parasitic parameter control; the overall structure still follows the traditional packaging approach of parallel or distributed multi-chip arrangements, lacking a systematic design for chip mounting methods, back-side soldering structures, base island configuration, and the overall coordination between bonding wires and lead frames. When integrating multiple power units or different types of chips, this structure struggles to achieve high-density, regular layouts, and the module size and structural complexity are difficult to control effectively.

[0006] Furthermore, the existing technology does not provide a unified packaging system compatible with multiple power units and multiple chip types. The internal connections, bond wire layouts, and pin assignments between power chips, driver ICs, control ICs, and diodes still rely on traditional packaging experience for localized design. When application requirements expand further, necessitating the integration of multiple IGBT and MOSFET units within the same module along with corresponding control and drive circuits, the existing packaging structure faces significant limitations in terms of connection complexity, thermal management, and electrical isolation, making it difficult to meet the application requirements of high integration and high reliability.

[0007] Therefore, although existing hybrid power module packaging structures composed of IGBTs and MOSFETs have explored device combination forms, they still have problems such as complex layout, inconsistent structure, and limited scalability under multi-unit, high-integration packaging conditions, making it difficult to meet the needs of power electronic systems to continue to develop towards high integration. Summary of the Invention

[0008] To address the problems existing in the prior art, the present invention provides a packaging structure for a power semiconductor device that integrates two power units to drive a compressor and a fan respectively, thereby reducing the overall size and cost.

[0009] The present invention is implemented as follows: a package structure for a power semiconductor device includes: a first power unit and a second power unit; the first power unit includes two IC chips, six IGBT chips and six FRD chips; the second power unit includes two IC chips and six MOS chips.

[0010] The package structure includes a lead frame, a molding compound, bonding wires, and multiple semiconductor chips. The package structure includes pins 1 to 46; pins 1 to 8 are the control and signal input terminals for the first power unit; pins 9 to 17 are the power output and common terminals for the first power unit; pins 18 to 28 are the control and signal input terminals for the second power unit; and pins 29 to 46 are the power output terminals for the second power unit. Pins 7 and 27 are common control terminals, enabling synchronous signal transmission between the two IC chips in the first power unit and the two IC chips in the second power unit, respectively, to avoid signal interference. Pins 39 and 40 are unused (NC) pins.

[0011] The first IC chip is connected to pins 1 through 8, and the first IGBT chip through the third IGBT chip via bonding wires; the second IC chip is connected to pins 7 through 17, and the fourth IGBT chip through the sixth IGBT chip via bonding wires; each IGBT chip is connected to the FRD chip and pins below via bonding wires; the third IC chip is connected to pins 18 through 28, and the first MOS chip through the third MOS chip via bonding wires; the fourth IC chip is connected to pins 27 through 32, and the fourth MOS chip through the sixth MOS chip via bonding wires; each MOS chip is connected to the pins below; the back of the semiconductor chips is soldered onto the lead frame, and all IC chips and diodes are located on the same base island.

[0012] Furthermore, the packaging structure also includes an IGBT semiconductor chip encapsulated within the lead frame by the molding compound, wherein the back side of the IGBT semiconductor chip is soldered onto the lead frame, and the front side is connected to the IC semiconductor chip and the FRD semiconductor chip via bonding wires.

[0013] Furthermore, the packaging structure also includes a MOS semiconductor chip encapsulated within the lead frame by the molding compound, wherein the back side of the MOS semiconductor chip is soldered onto the lead frame and the front side is connected to the IC semiconductor chip via bonding wires.

[0014] Furthermore, the packaging structure also includes an FRD semiconductor chip encapsulated within the lead frame by the molding compound, wherein the back side of the FRD semiconductor chip is soldered onto the lead frame, and the front side is connected to the IGBT chip and pins via bonding wires.

[0015] Furthermore, the IC semiconductor chip is a multi-terminal active device. The front side of the IC semiconductor chip has all functional electrodes, including input, output, and control terminals, while the back side only provides support and heat dissipation. The input terminal is soldered to the lead frame, the output terminal is electrically connected to the pin soldering area via bonding wires, and the control terminal is electrically connected to the pin soldering area via bonding wires. The IGBT semiconductor chip is a three-terminal active device. The front side of the IGBT semiconductor chip has a control terminal and a first power terminal, while the back side has a second power terminal. The second power terminal is soldered to the corresponding base island of the lead frame. The first power terminal is electrically connected to an external pin via a bonding wire; the MOS semiconductor chip is a three-terminal active device, with a control terminal and a first current-carrying terminal on the front side and a second current-carrying terminal on the back side, the second current-carrying terminal being soldered to the corresponding base island of the lead frame, and the first current-carrying terminal being electrically connected to an external pin via a bonding wire; the FRD semiconductor chip is a two-terminal passive device, with an anode on the front side and a cathode on the back side; the cathode is soldered to the corresponding base island of the lead frame, and the anode is electrically connected to an external pin via a bonding wire.

[0016] Furthermore, the packaging structure is applicable to the DIP-46 packaging form.

[0017] Furthermore, the encapsulation body is made of epoxy encapsulation material, the lead frame is made of copper alloy material, and the bonding wire is made of copper wire, gold wire, aluminum wire, or alloy wire.

[0018] Another object of the present invention is to provide a power module, including a substrate and a power semiconductor device with a packaging structure of the power semiconductor device, wherein the power semiconductor device is mounted on the substrate.

[0019] Furthermore, any one of the IGBT device, the IC device, the MOS device, and the IGBT device encapsulated with a fast recovery diode.

[0020] Furthermore, the power module is in a through-hole package or a surface-mount package. The first power unit drives the compressor motor, and the second power unit drives the fan motor. The output power of the first power unit is greater than the output power of the second power unit.

[0021] This invention provides a packaging structure solution with a clear structure, compact layout, standardized connection, and suitable for multi-unit composites by constructing base islands in the same lead frame, unifying back-side soldering, standardizing bonding wire connections, strictly arranging driving, power and FRD chips in a partitioned manner, significantly improving packaging integration and manufacturability.

[0022] The packaging structure provided by this invention addresses the problems of dispersed chips and complex wiring in existing power semiconductor devices. By forming continuous base islands in the middle of the lead frame and centrally arranging IC chips and FRD chips, multiple types of semiconductor chips can be highly integrated in the same package, reducing internal connection layers and improving the overall consistency and layout stability of the packaging structure.

[0023] This invention constructs a power unit containing multiple power transistors and diodes in the same package structure, enabling high-power devices to be configured in a single package. This solves the problems of large size and redundant connections caused by side-by-side installation of multiple devices in existing solutions, and allows the package structure to achieve higher load-bearing capacity while maintaining compactness.

[0024] This invention further integrates a MOS chip and its corresponding IC chip within the same lead frame and molding compound, enabling different types of power control units to share the basic packaging structure. This avoids the process complexity caused by repetitive packaging designs and significantly improves the versatility and platformization of the packaging form.

[0025] This invention achieves a more compact spatial layout by welding power transistors and diodes together in the same base island region and forming a clear top-to-bottom correspondence. This shortens the electrical connection path, reduces parasitic parameters, and provides a significant structural optimization compared to traditional cross-region connection methods.

[0026] This invention clarifies the function of the front and back electrodes of various chips, enabling IC chips, power transistors, and diodes to form a clear end-face connection relationship within the package. This avoids structural interference caused by the mixing of functional electrodes and improves the standardization and controllability of electrical connections within the package.

[0027] This invention, by uniformly defining the packaging materials and packaging form, enables the packaging structure to balance structural strength, conductivity reliability, and engineering compatibility. It adapts to existing through-hole assembly systems without changing the core structure, demonstrating good engineering feasibility and expansion value. Attached Figure Description

[0028] Figure 1 This is a product framework diagram provided for an embodiment of the present invention.

[0029] Figure 2 The product wiring diagram provided for embodiments of the present invention.

[0030] Figure 3 This is a top view of the product outline provided in an embodiment of the present invention.

[0031] Figure 4 This is a front view of the external shape provided in an embodiment of the present invention.

[0032] Figure 5 This is a rear view of the external shape provided in an embodiment of the present invention.

[0033] Figure 6 A side view of the product provided for an embodiment of the present invention.

[0034] Figure 7 This is a structural diagram of a power semiconductor packaging system provided in an embodiment of the present invention.

[0035] Figure 8 A flowchart illustrating the packaging implementation method of a power semiconductor device provided in an embodiment of the present invention.

[0036] In the diagram: 1. Lead frame; 2. Base island; 3. IC chip (driver chip); 4. IGBT chip (power transistor chip); 5. FRD chip (diode chip); 6. MOS chip (metal oxide semiconductor chip); 7. Bonding wire; 8. Pin; 9. Molded package. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0038] like Figures 1 to 4 As shown, this power semiconductor device adopts a plastic encapsulation structure. The lead frame 1 is embedded inside the encapsulation body 9. A continuous base island 2 structure is formed in the middle of the lead frame 1 (the base island 2 is an integrally molded structure of the lead frame 1, made of copper alloy, with a length of 10mm and a width of 4mm, adapted to the chip layout size). IC chip 3 and FRD chip 5 are concentrated on the base island 2, and IGBT chip 4 and MOS chip 6 are arranged sequentially along the length of the base island 2. The back of each semiconductor chip is fixed to the surface of the base island 2 of the lead frame 1 by soldering with solder paste. The soldering temperature is 260-280℃, and the solder layer thickness is 0.1-0.2mm, so that each chip can be stably mounted on the same mounting plane. The pins 8 are led out from the lead frame 1 to the outside of the encapsulation body 9, forming corresponding electrical connections with the internal chips. The overall structure is compact and orderly arranged.

[0039] Each IC chip 3 is located above the base island 2. Its front side is connected to the corresponding pin 8 soldering area and the corresponding IGBT chip 4 or MOS chip 6 via multiple bonding wires 7. The bonding wires 7 are made of copper wire with a diameter of 0.1-0.2mm and a bonding pull force ≥5g. The IGBT chip 4 is connected to the FRD chip 5 arranged below and its corresponding pin 8 via the bonding wires 7, forming an anti-parallel connection. The MOS chip 6 is connected to the IC chip 3 and its pin 8 via the bonding wires 7, forming an independent power control loop. All bonding wires 7 are located inside the plastic package 9 and, together with the lead frame 1, form the signal and power current transmission channel.

[0040] When the device is operating, external control signals are input via pin 8 and transmitted to the corresponding IC chip 3 along the lead frame 1. After processing the input signals, IC chip 3 outputs drive signals to the control terminals of the corresponding IGBT chip 4 or MOS chip 6 via bonding wire 7, enabling them to switch between on and off states according to control commands. The main current is introduced through the power pin and transmitted to the inside of IGBT chip 4 via the lead frame 1, completing current conduction in the vertical direction. When IGBT chip 4 is in the off state, its parallel-connected FRD chip 5 forms a freewheeling path, thus ensuring current continuity.

[0041] All IC chips 3 and FRD chips 5 are arranged on the same base island 2, forming a unified heat conduction path in terms of spatial position. During device operation, the heat generated by the IGBT chip 4 and MOS chip 6 is directly conducted to the base island 2 and lead frame 1 through the back soldering area, and further diffused to the external heat dissipation environment through the molding compound 9. The lead frame 1 not only realizes electrical connection but also has a heat dissipation function, allowing the IC chip 3 and the power chip to work together in a relatively consistent thermal environment, thereby improving the stability and reliability of device operation.

[0042] With this design layout, a 0.8-1.2mm gap is set between each pin 8 lead-out area and the lead frame 1, ensuring that there will be no breakdown short circuit between the first and second lead-out areas and the lead frame 1. This gives the package structure better safety and allows for automated placement using surface mount technology. In this design, multiple chips, bonding wires 7, and pins 8 are more rationally arranged, and the bonding wires 7 do not interfere with each other. By integrating two power units, the compressor and fan can be driven separately, reducing the overall size and cost.

[0043] The number of IC chips 3 is 4, the number of IGBT chips 4 is 6, the number of MOS chips 6 is 6, and the packaging structure also includes FRD chips 5 encapsulated in the lead frame 1 by the molding compound 9, and the number of FRD semiconductor chips 5 is 6.

[0044] The packaging structure also includes an IGBT semiconductor chip 4 encapsulated within the lead frame 1 by the molding compound 9. The back side of the IGBT chip 4 is soldered to the base island 2 of the lead frame 1, and the front side is electrically connected to the soldering area of ​​the pin 8 via bonding wires 7.

[0045] The packaging structure also includes a MOS semiconductor chip 6 encapsulated within the lead frame 1 by the molding compound 9. The back side of the MOS chip 6 is soldered to the base island 2 of the lead frame 1, and the front side is electrically connected to the soldering area of ​​the pin 8 via bonding wires 7.

[0046] The packaging structure also includes an FRD chip 5 encapsulated within the lead frame 1 by the molding compound 9. The back side of the FRD semiconductor chip 5 is soldered onto the base island 2 of the lead frame 1, and the front side is connected to the IGBT chip 4 and corresponding pins 8 via bonding wires 7.

[0047] The IC chip 3, IGBT chip 4, FRD chip 5, MOS chip 6, and pin 8 are connected via... Figure 1 The product framework diagram shown is arranged as follows: IC chip 3 is located at both ends of base island 2; IGBT chip 4 and FRD chip 5 are arranged vertically on one side of the middle of base island 2; and MOS chip 6 is arranged on the other side of the middle of base island 2. The IC chip 3, IGBT chip 4, FRD chip 5, MOS chip 6, and pin 8 are connected via... Figure 2 The product wire bonding diagram shown illustrates the bonding wire arrangement: the IC chip and the power chip are directly bonded, the power chip and the corresponding FRD chip are perpendicularly bonded, and there is no intersection or interference between the pins and the chip bonding wires.

[0048] In the packaging structure of the power semiconductor device provided by this invention, the IC chip 3 is a multi-terminal active device. The front side of the IC chip 3 has all functional electrodes, including the input terminal, output terminal, and control terminal, while the back side of the IC chip 3 only has support and heat dissipation functions. The input terminal is soldered to the lead frame 1, the output terminal is electrically connected to the soldering area of ​​the pin 8 via a bonding wire 7, and the control terminal is electrically connected to the soldering area of ​​the pin 8 via a bonding wire 7. The IGBT chip 4 is a three-terminal active device. The front side of the IGBT chip 4 has a control terminal and a first power terminal (emitter). The IGBT chip 4 has a second power terminal (collector) on its back side; the second power terminal is soldered to the corresponding base island 2 of the lead frame 1, and the first power terminal is electrically connected to an external pin 8 via a bonding wire 7; the MOS chip 6 is a three-terminal active device, the MOS chip 6 has a control terminal and a first current-carrying terminal (source) on its front side, and a second current-carrying terminal (drain) on its back side, the second current-carrying terminal is soldered to the corresponding base island 2 of the lead frame 1, and the first current-carrying terminal is electrically connected to an external pin 8 via a bonding wire 7; the FRD semiconductor chip 5 is a two-terminal passive device, the FRD semiconductor chip 5 has an anode on its front side and a cathode on its back side; the cathode is soldered to the corresponding base island 2 of the lead frame 1, and the anode is electrically connected to an external pin 8 via a bonding wire 7.

[0049] The encapsulation body 9 is made of epoxy encapsulation material, the lead frame 1 is made of copper alloy material, and the bonding wire 7 is made of copper wire, gold wire, aluminum wire or alloy wire.

[0050] The packaging structure is applicable to the DIP-46 packaging form.

[0051] This invention provides a power module, including a substrate and a power semiconductor device having the packaging structure of the power semiconductor device, wherein the power semiconductor device is mounted on the substrate.

[0052] The power module integrates any one of the following: IGBT devices, IC devices, MOS devices, and IGBT devices with encapsulated fast recovery diodes. The power module is a through-hole package (DIP-45). The first power unit drives the compressor motor, and the second power unit drives the fan motor. The output power of the first power unit is greater than the output power of the second power unit (800W for the first power unit and 200W for the second power unit).

[0053] Example 1

[0054] In this embodiment, the IC chip is selected as IR2110, the IGBT chip is selected as IGBT40N60 power transistor, the FRD chip is selected as FRD10A60 fast recovery diode, and the MOS chip is selected as MOSFET IRF3205 metal-oxide-semiconductor transistor.

[0055] The lead frame is made of C194 copper alloy, with a base island size of 10mm×4mm and 46 pins; the encapsulation body is made of EP-820 epoxy encapsulation material, with an overall package size of 30mm×15mm×5mm; the bonding wire is made of 0.15mm diameter copper wire, with a bonding temperature of 270℃ and a solder layer thickness of 0.15mm.

[0056] The two IC chips in the first power unit are connected to pins 1-8 and 7-17 respectively, with pin 7 serving as the common control terminal to synchronize the signals of the two IC chips. Six IGBT chips correspond one-to-one with six FRD chips, and the emitter of each IGBT chip is connected to the anode of the corresponding FRD chip via a bonding wire, and also connected to power output pins 9-17. The two IC chips in the second power unit are connected to pins 18-28 and 27-32 respectively, with pin 27 serving as the common control terminal. Six MOS chips are arranged 0.8mm apart along the length of the base island, with their sources connected to power output pins 29-32 via bonding wires. Each FRD chip is connected to pins 33-46 as the power output terminal, with pins 39-40 being unused (NC).

[0057] The power module in this embodiment is applied to a household air conditioning system. The first power unit drives the compressor motor (output power 800W), and the second power unit drives the fan motor (output power 200W). Example 2

[0058] In this embodiment, the IC chip is an IRS21844 IC chip, the IGBT chip is an IGBT60N120 power transistor, the FRD chip is an FRD15A120 fast recovery diode, and the MOS chip is a MOSFET IRF4905 metal-oxide-semiconductor transistor.

[0059] The lead frame is made of C2680 copper alloy, with a base island size of 12mm×5mm, 46 pins, and a pin pitch of 2.54mm; the encapsulation body is made of EP-900 epoxy encapsulation material, with an overall package size of 35mm×18mm×6mm; the bonding wires are made of 0.2mm diameter gold wire, with a bonding temperature of 280℃ and a solder layer thickness of 0.2mm.

[0060] The two IC chips in the first power unit are connected to pins 1-8 and 7-17 respectively. Pin 7 is the common control terminal. Six IGBT chips and six FRD chips are arranged vertically and vertically. The emitters of the IGBT chips are bonded to the anodes of the FRD chips and connected to pins 9-17. The two IC chips in the second power unit are connected to pins 18-28 and 27-32 respectively. Pin 27 is the common control terminal. Six MOS chips are arranged at 1.0mm intervals along the length of the base island. The sources are connected to pins 29-32. Each FRD chip is connected to pins 33-46, which are the power output terminals. Pins 39-40 are unused (NC).

[0061] The power module in this embodiment is applied to a small refrigeration device. The first power unit drives the compressor motor (output power 1000W), and the second power unit drives the cooling fan motor (output power 300W). During operation, the maximum temperature of the device is ≤120℃, and the parasitic inductance is ≤5nH.

[0062] Example 3: Stacked Power Execution and Freewheeling Co-packaging Example In this embodiment, a continuous base island is formed in the middle of the lead frame. Multiple freewheeling chips are first soldered onto this base island, and a power switch chip is soldered above the corresponding area of ​​each freewheeling chip, creating a one-to-one correspondence between the two in the thickness direction of the base island. The front side of the power switch chip is connected to the lead frame pins via bonding wires, forming a direct current path between the freewheeling chips and the power switch chip. This structure allows the freewheeling current during turn-off transients to be locally closed within the base island, significantly shortening the power loop length, reducing parasitic parameters, and improving high-frequency switching stability.

[0063] Example 4: Parallel Integration of Power Execution Unit and Control Unit Based on Embodiment 1, multiple power control chips are soldered to one side of the same base island along its length. These power control chips and power switch chips are connected via independent bonding wires. The power control chips do not participate in main current transmission but instead form a signal-driven relationship with the power execution chip. By integrating the control unit and execution unit onto the same base island, the introduction of external signal loops is avoided, significantly shortening the control signal path and reducing control delay and interference.

[0064] Example 5: Multi-channel power execution integration example Multiple pairs of power switch chips and freewheeling chips are arranged on the same base island, with each pair forming a power execution channel. These multiple power execution channels share the same power control chip, connected by different bonding wires to achieve separate driving. This implementation achieves multi-channel power output within a single plastic package, avoiding the wiring complexity and inconsistency issues caused by side-by-side mounting of multiple devices, demonstrating the advantages of highly integrated system-in-package (SIP).

[0065] Example 6: Separate Wiring Example for Power and Control Signals Based on Embodiment 2 or Embodiment 3, bonding wire routing areas with different orientations are set for the power transmission path and the control signal path. Power bonding wires are concentrated in the central area near the base island, while control signal bonding wires are arranged at the edge of the base island, thus physically separating the two types of signals. This embodiment effectively reduces the impact of electromagnetic interference generated during power switching on the control signal, improving system reliability.

[0066] Example 7: Collaborative Heat Dissipation Example of Common-Base Island Welding Area In this embodiment, the power switch chip and its corresponding freewheeling chip are soldered to the same base island soldering area, forming a parallel relationship between the two types of chips in the heat conduction path. Heat generated during operation is simultaneously diffused to the lead frame and the molding compound through the base island, avoiding heat concentration in a single chip area. This collaborative heat dissipation mechanism ensures that the package maintains good thermal stability under high power density conditions.

[0067] Example 8: Implementation Method of Integrated Packaging In the packaging process, the lead frame is first fixed in the mold to form continuous base islands. Then, the freewheeling chip, power switch chip, and power control chip are soldered and arranged sequentially. The electrical connection of all chips is completed in a single bonding process, and finally, the entire chip is molded. This method avoids multiple assembly and molding processes, allowing power execution and control functions to be completed in the same process flow, which helps improve packaging consistency and production efficiency.

[0068] The above embodiments systematically demonstrate the implementation method and technical effect of the packaging solution from multiple dimensions such as spatial structure, functional coordination, signal path, thermal path and manufacturing process. It fully illustrates that the technical solution is not a simple device splicing, but an overall technical concept formed around the power-control coordination mechanism on the same base island, which can stably and repeatedly achieve high integration and high reliability power semiconductor packaging.

[0069] In the description of this invention, unless otherwise stated, "a plurality of" means two or more; the terms "upper," "lower," "left," "right," "inner," "outer," "front end," "rear end," "head," "tail," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0070] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention, and within the spirit and principles of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A packaging structure for a power semiconductor device, characterized in that, This includes lead frames, molding compounds, base islands, bonding wires, and semiconductor chip assemblies; The lead frame is disposed inside the encapsulation body, and a series of base islands are formed in the middle of the lead frame; The semiconductor chip assembly includes at least one set of first power chip units and at least one set of second power chip units, wherein the first power chip units and the second power chip units are disposed on the same base island; The first power chip unit includes a power switch chip and a freewheeling chip, wherein the power switch chip and the corresponding freewheeling chip are arranged side by side on the base island in a one-to-one correspondence. The second power chip unit includes a power control chip, which is arranged side by side with the first power chip unit along the length of the base island; The back side of each semiconductor chip is soldered to the base island or lead frame, and the front side of each semiconductor chip is electrically connected to the lead soldering area of ​​the lead frame via bonding wires. By implementing the spatial stacking and parallel collaborative arrangement of power switch chips, freewheeling chips and power control chips on the same base island, the power transmission path, control signal path and freewheeling path form a compact and collaborative electrical connection relationship within the package.

2. The packaging structure of the power semiconductor device according to claim 1, characterized in that, The power switch chip is located in the area above the freewheeling chip, so that the two form a direct correspondence in the vertical direction, thereby shortening the equivalent current path of the power circuit and the freewheeling circuit.

3. The packaging structure of the power semiconductor device according to claim 1, characterized in that, The power control chip and the power switch chip are electrically connected by independent bonding wires, so that the control signal path and the power transmission path are physically separated but electrically coordinated on the base island.

4. The packaging structure of the power semiconductor device according to claim 1, characterized in that, The first power chip unit and the second power chip unit share the same lead frame and molding compound to achieve functional integration of power devices and control devices within a single package.

5. A power semiconductor packaging system, characterized in that, It includes at least one base island, a first power unit and a second power unit disposed on the base island, and a lead frame electrically connected to the first power unit and the second power unit; The first power unit includes multiple power switch chips and multiple freewheeling chips that correspond to each other. Each power switch chip and its corresponding freewheeling chip are arranged vertically and vertically on the same base island along the thickness direction. The second power unit includes multiple power control chips, which are distributed along the length of the base island. The first power unit and the second power unit form a collaborative working system for power driving and power execution through a lead frame and bonding wires, so that the control signal directly drives the corresponding power switch chip inside the package.

6. The power semiconductor packaging system according to claim 5, characterized in that, The power control chip is used to centrally drive and control multiple power switch chips, thereby forming a multi-channel power output structure within the same package system.

7. The power semiconductor packaging system according to claim 5, characterized in that, The freewheeling chip and the corresponding power switch chip are soldered to the same base island region, so that the freewheeling current generated during the power turn-off process can be directly closed within the base island region.

8. A method for packaging a power semiconductor device, characterized in that, Includes the following steps: The lead frame is placed in the mold and forms a continuous base island structure; The power switch chip and the freewheeling chip are soldered on the same base island, and the power switch chip and the freewheeling chip are arranged vertically and vertically correspondingly in the thickness direction of the base island. The power control chip is soldered onto the base island and arranged side by side with the power switch chip along the length of the base island. Each power switch chip, freewheeling chip, and power control chip is electrically connected to the corresponding pin soldering area of ​​the lead frame using bonding wires. The lead frame, base island, and semiconductor chip assembly are integrally molded to form a power semiconductor device with integrated power execution and control functions.

9. The packaging implementation method for the power semiconductor device according to claim 8, characterized in that, When soldering power switch chips and freewheeling chips, they share the same base island soldering area to reduce the number of soldering interfaces and shorten the power loop.

10. The packaging implementation method of the power semiconductor device according to claim 8, characterized in that, During the bonding wire connection process, separate bonding wire connection paths are set for the power control signal and the power transmission signal to reduce electromagnetic interference between the signals.

Images