A medical digital adjustable time-delay exposure circuit

Abstract

The present invention discloses a medical digital adjustable delayed exposure circuit, comprising: a power supply circuit, an exposure drive circuit, and a timed exposure preparatory drive circuit. Based on a digital chip with stable performance, mature semiconductor transistor elements, and standardized resistors and capacitors, the circuit has a stronger shockproof function than a mechanical timing device. Moreover, compared with a solution using programmable devices, the circuit solution of pure logic gates and triggers does not have soft errors and has more stable performance. Through the design of a universal interface, the circuit can be adapted to mainstream radiological equipment on the market, such as: small X-ray machines, bedside DR machines, bone densitometry machines, oral dental radiographs, CBCT machines, etc., so it has strong versatility, is easy to promote, and has important application value in actual clinical work.

Description

Technical Field

[0001] The invention belongs to the field of medical electronics, and in particular relates to a medical digital adjustable delayed exposure circuit. Background Art

[0002] Medical imaging technicians are exposed to concentrated and frequent radiation, particularly from bedside DR machines, bone densitometry machines, dental radiographs, CBCT machines, and mobile C-arms. Large hospitals frequently use these devices, and during their use, they are also exposed to X-ray radiation. Extending the device control cables or using infrared remote controls can address these two issues. While these can provide some degree of radiation protection, extending the cables presents the following challenges: It places unnecessary psychological strain on patients; the inconvenience of long cables and the unsanitary nature of the cord rails dragging on the floor create cross-infection risks and pose a risk of equipment failure. Infrared remote controls require technicians to aim the remote at the main unit and operate only when the remote is close to the machine and unobstructed. This exposure persists, however. Wireless remote controls can be ineffective due to distance or walls, resulting in inconsistent exposure. Summary of the Invention

[0003] In response to the above-mentioned deficiencies in the prior art, the present invention provides a medical digital adjustable delayed exposure circuit that solves the problems of the prior art of extending the equipment control line or infrared remote control, which are inconvenient, unhygienic, and leave potential fault risks and incomplete protection for technicians.

[0004] In order to achieve the above-mentioned object of the invention, the technical solution adopted by the present invention is: a medical digital adjustable delayed exposure circuit, comprising: a power supply circuit, an exposure drive circuit and a timed exposure preparation drive circuit;

[0005] The power supply circuit is connected to the timing exposure preparation drive circuit;

[0006] The exposure driving circuit is connected to the timing exposure preparation driving circuit.

[0007] Furthermore: the power supply circuit includes: a terminal CN3, a rectifier bridge BD1, a capacitor EC1, a grounding capacitor C1, a voltage regulator chip IC6, a capacitor EC3, a grounding capacitor C3, a resistor R1, a light-emitting diode LED1, a capacitor EC2, a grounding capacitor C2, a voltage regulator chip IC7, a capacitor EC4 and a grounding capacitor C6;

[0008] Pin 1 of the connection terminal CN3 is connected to the first AC input terminal of the rectifier bridge BD1, and pin 2 thereof is connected to the second AC input terminal of the rectifier bridge BD1;

[0009] The first DC output terminal of the rectifier bridge BD1 is respectively connected to the positive electrode of the capacitor EC1, the grounding capacitor C1, the Vin terminal of the voltage regulator chip IC6, the positive electrode of the capacitor EC2, the grounding capacitor C2 and the Vin terminal of the voltage regulator chip IC7;

[0010] The +5V terminal of the voltage stabilizing chip IC6 is connected to the positive electrode of the capacitor EC3, the grounding capacitor C3 and the other end of the resistor R1, and serves as the +5V terminal of the power supply circuit;

[0011] The +12V terminal of the voltage stabilizing chip IC7 is connected to the positive electrode of the capacitor EC4 and the grounding capacitor C6 respectively, and serves as the +12V terminal of the power supply circuit;

[0012] The other end of the resistor R1 is connected to the positive electrode of the light emitting diode LED1;

[0013] The second DC output terminal of the rectifier bridge BD1, the cathode of the capacitor EC1, the GND terminal of the voltage regulator chip IC6, the cathode of the capacitor EC3, the cathode of the light-emitting diode LED1, the cathode of the capacitor EC2, the GND terminal of the voltage regulator chip IC7 and the cathode of the capacitor EC4 are all grounded.

[0014] Further: the exposure drive circuit includes: capacitor EC5, sliding rheostat RW2, triple-five trigger IC3, grounding capacitor C14, terminal CN6, diode D4, relay RL2, light-emitting diode LED4, resistor R17, resistor R18 and transistor BG5;

[0015] The triple-five flip-flop IC3 The VDD terminal is connected to the positive electrode of capacitor EC5, the positive electrode of light-emitting diode LED4, the 2nd pin of terminal CN6, the negative electrode of diode D4, one end of the coil of relay RL2 and the DIS terminal of triple-five trigger IC3 respectively. The terminal is connected and serves as the NE12V terminal of the exposure drive circuit;

[0016] The GND terminal of the triple-five trigger IC3 is grounded, and its Vc terminal is connected to the ground capacitor C14;

[0017] The Vo terminal of the triple-five trigger IC3 is connected to one end of the resistor R18;

[0018] The movable end and the second fixed end of the sliding rheostat RW2 are grounded;

[0019] The base of the transistor BG5 is connected to the other end of the resistor R18, the emitter thereof is grounded, and the collector thereof is respectively connected to one end of the resistor R17, the other end of the coil of the relay RL2, the anode of the diode D4 and pin 1 of the terminal CN6;

[0020] The other end of the resistor R17 is connected to the cathode of the light emitting diode LED4.

[0021] Furthermore, the timing exposure preparation drive circuit includes: resistor R22, dual D flip-flop IC2, grounding resistor R15, resistor R4, transistor BG1, resistor R6, light-emitting diode LED2, resistor R5, terminal CN2, sliding rheostat RW1, capacitor C10, resistor R7, timer IC4, switch S1, resistor R20, resistor R21, button AN1, terminal CN5, grounding resistor R2, grounding capacitor C8, inverter IC1, resistor R23, terminal CN 1. Variable resistor R3, grounded capacitor C9, NMOS transistor BG4, resistor R14, OR gate IC8, resistor R11, resistor R10, transistor BG3, grounded resistor R12, capacitor C11, grounded resistor R13, AND gate IC5, resistor R8, transistor BG2, relay RL1, grounded capacitor C16, bell ringer BZ1, resistor R16, light-emitting diode LED3, diode D1, grounded capacitor C12, grounded capacitor C13, grounded capacitor C15, and grounded capacitor C17;

[0022] The 1Q terminal of the dual D flip-flop IC2 is respectively connected to the 2CP terminal of the dual D flip-flop IC2, one end of the resistor R15, one end of the variable resistor R3, the 1 pin of the wiring group CN1 and the SEL terminal of the timer IC4;

[0023] The dual D flip-flop IC2 The terminals are connected to one end of the resistor R22 and the A5 terminal of the inverter IC1 respectively, the 1CP terminal is connected to the Y2 terminal of the inverter IC1, the 1RD terminal is connected to the Y terminal of the OR gate IC8, the 1D terminal serves as the 5V terminal of the timing exposure preparation drive circuit, the 1SD terminal, the GND terminal and the 2SD terminal are grounded, the VDD terminal is connected to the 5V terminal of the timing exposure preparation drive circuit, the 2Q terminal is connected to one end of the resistor R4, and the 1D terminal is connected to the 5V terminal of the timing exposure preparation drive circuit. The terminals are connected to the A3 terminal of the inverter IC1 and the 2D terminal of the dual D flip-flop IC2 respectively;

[0024] The other end of the resistor R22 is connected to the 5V terminal of the timing exposure preparation drive circuit;

[0025] The other end of the resistor R15 is grounded;

[0026] The base of the transistor BG1 is connected to the other end of the resistor R4, and the emitter thereof is grounded;

[0027] The RTC terminal of the timer IC4 is connected to the first fixed terminal of the sliding rheostat RW1, the sliding terminal of the sliding rheostat RW1, the 2nd pin of the terminal CN2 and the 3rd pin of the terminal CN2 respectively, its CTC terminal is connected to one end of the capacitor C10, its RS terminal is connected to one end of the resistor R7, its AR terminal, GND terminal and MODE terminal are grounded, and its Its terminals are connected to one end of resistor R5, the collector of transistor BG1 and one end of resistor R6 respectively, its VDD terminal is connected to the 5V terminal of the time exposure preparation drive circuit, its B terminal is connected to one end of resistor R20 and pin 2 of switch S1 respectively, its A terminal is connected to one end of resistor R21 and pin 1 of switch S1 respectively, and its Q terminal is connected to terminal A4 of inverter IC1;

[0028] The other end of the resistor R6, the positive electrode of the light-emitting diode LED2, the grounding capacitor C12, the grounding capacitor C13, the grounding capacitor C15, the grounding capacitor C17, the other end of the resistor R20 and the other end of the resistor R21 are all connected to the 5V terminal of the timing exposure preparation drive circuit;

[0029] The other end of the resistor R5 is connected to the cathode of the light emitting diode LED2;

[0030] The other end of the resistor R7 is connected to the other end of the capacitor C10, the second fixed end of the sliding resistor RW1 and the pin 1 of the terminal CN2 respectively;

[0031] Pins 3 and 4 of the switch S1 are grounded;

[0032] The inverter IC1 has its A1 terminal connected to one end of the button AN1, pin 2 of the terminal CN5, the grounding resistor R2, and the grounding capacitor C2, its Y1 terminal connected to the A2 terminal, its Y3 terminal connected to the B terminal of the AND gate IC5, its GND terminal connected to ground, its VDD terminal connected to the 5V terminal of the timing exposure preparation drive circuit, its A6 terminal connected to one end of the resistor R23, its Y5 terminal connected to one end of the resistor R11, and its Y4 terminal connected to the A terminal of the AND gate IC5;

[0033] The other end of the resistor R23, the other end of the button AN1 and the pin 1 of the terminal CN5 are all connected to the 5V terminal of the timer exposure preparation drive circuit;

[0034] The gate of the NMOS transistor BG4 is connected to one end of the resistor R14, the drain thereof is respectively connected to the grounded capacitor C9, the A end of the OR gate IC8, the other end of the variable resistor R3 and the 2nd pin of the terminal CN1, and the source thereof is grounded;

[0035] The B terminal of the OR gate IC8 is respectively connected to the other end of the resistor 14, the grounding resistor R12, one end of the capacitor C11 and the 2RD terminal of the dual D flip-flop IC2, its VCC is connected to the 5V terminal of the timing exposure preparation drive circuit, and its GND terminal is grounded;

[0036] The GND terminal of the AND gate IC5 is grounded, the VCC terminal thereof is connected to the 5V terminal of the timing exposure preparation drive circuit, and the Y terminal thereof is connected to one end of the resistor R8;

[0037] The other end of the capacitor C11 is connected to the grounding resistor R13 and the collector of the transistor BG3;

[0038] The base of the transistor BG3 is connected to the other end of the resistor R11 and one end of the resistor R10 respectively, and the emitter thereof and the other end of the resistor R10 are both connected to the 5V terminal of the timing exposure preparation drive circuit;

[0039] The other end of the resistor R8 is connected to the base of the transistor BG2;

[0040] The emitter of the transistor BG2 is grounded, and the collector thereof is connected to the anode of the diode D1, one end of the coil of the relay RL1, one end of the resistor R16 and one end of the bell BZ1;

[0041] The cathode of the diode D1 is connected to the other end of the coil of the relay RL1, one end of the first contact of the relay RL1 and the anode of the light-emitting diode LED3, and serves as the +12V terminal of the timed exposure preparation drive circuit;

[0042] The other end of the first contact of the relay RL1 is connected to the grounding capacitor C16 and the other end of the bell BZ1 respectively, and serves as the NE12V terminal of the timed exposure preparation drive circuit;

[0043] The other end of the resistor R16 is connected to the cathode of the light emitting diode LED3.

[0044] The NE12V terminal of the timing exposure preparation driving circuit is connected to the NE12V terminal of the exposure driving circuit;

[0045] The 5V terminal of the timing exposure preparation driving circuit is connected to the +5V terminal of the power supply circuit;

[0046] The +12V terminal of the time exposure preparation drive circuit is connected to the +12V terminal of the power supply circuit.

[0047] Furthermore, the model of the voltage regulator chip IC6 is LM7805CT, and the model of the voltage regulator chip IC7 is LM7812CT.

[0048] Furthermore: the model of the dual D flip-flop IC2 is CD4013.

[0049] Furthermore: the model of the inverter IC1 is CD40106.

[0050] Furthermore, the model of the OR gate IC8 is NL17SZ32DFT2G, the model of the AND gate IC5 is NL17SZ08DFT2G, and the model of the timer IC4 is CD4541.

[0051] The beneficial effects of the present invention are as follows: the device is based on digital chips with stable performance, mature semiconductor transistor elements and standard unified resistors and capacitors, and is more shock-proof than timing devices with mechanical structures; and the circuit scheme of pure logic gates and triggers will not have soft errors and has more stable performance than the scheme using programmable devices; through the design of a universal interface, it can be adapted to mainstream radiation equipment on the market, such as: small X-ray machines, bedside DR machines, bone density, oral dental film machines, CBCT, etc., so it has strong versatility and is easy to promote, and has important application value in actual clinical work. Since the device is directly connected to the cable end of the radiation equipment, there is no need to extend the cable of the equipment control line. The technician only needs to press the button AN1 and wait for a period of delay to realize the operation of the radiation equipment, and the waiting delay time can be flexibly adjusted through the switch S1. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 This is a circuit diagram of a medical digital adjustable time-delay exposure circuit;

[0053] Figure 2 is a circuit diagram of a power supply circuit;

[0054] Figure 3 is a circuit diagram of an exposure drive circuit;

[0055] Figure 4 and Figure 5 Circuit diagram of the drive circuit for timed exposure preparation. DETAILED DESCRIPTION

[0056] The specific embodiments of the present invention are described below to facilitate understanding of the present invention by those skilled in the art. However, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all inventions and creations utilizing the concepts of the present invention are protected.

[0057] like Figure 1 As shown, a medical digital adjustable delayed exposure circuit includes: a power supply circuit, an exposure drive circuit and a timed exposure preparation drive circuit;

[0058] The power supply circuit is connected to the timing exposure preparation drive circuit;

[0059] The exposure driving circuit is connected to the timing exposure preparation driving circuit.

[0060] like Figure 2 As shown, the power supply circuit includes: terminal CN3, rectifier bridge BD1, capacitor EC1, grounding capacitor C1, voltage regulator chip IC6, capacitor EC3, grounding capacitor C3, resistor R1, light emitting diode LED1, capacitor EC2, grounding capacitor C2, voltage regulator chip IC7, capacitor EC4 and grounding capacitor C6;

[0061] Pin 1 of the connection terminal CN3 is connected to the first AC input terminal of the rectifier bridge BD1, and pin 2 thereof is connected to the second AC input terminal of the rectifier bridge BD1;

[0062] The first DC output terminal of the rectifier bridge BD1 is respectively connected to the positive electrode of the capacitor EC1, the grounding capacitor C1, the Vin terminal of the voltage regulator chip IC6, the positive electrode of the capacitor EC2, the grounding capacitor C2 and the Vin terminal of the voltage regulator chip IC7;

[0063] The +5V terminal of the voltage stabilizing chip IC6 is connected to the positive electrode of the capacitor EC3, the grounding capacitor C3 and the other end of the resistor R1, and serves as the +5V terminal of the power supply circuit;

[0064] The +12V terminal of the voltage stabilizing chip IC7 is connected to the positive electrode of the capacitor EC4 and the grounding capacitor C6 respectively, and serves as the +12V terminal of the power supply circuit;

[0065] The other end of the resistor R1 is connected to the positive electrode of the light emitting diode LED1;

[0066] The second DC output terminal of the rectifier bridge BD1, the cathode of the capacitor EC1, the GND terminal of the voltage regulator chip IC6, the cathode of the capacitor EC3, the cathode of the light-emitting diode LED1, the cathode of the capacitor EC2, the GND terminal of the voltage regulator chip IC7 and the cathode of the capacitor EC4 are all grounded.

[0067] like Figure 3 As shown, the exposure drive circuit includes: capacitor EC5, sliding rheostat RW2, triple-five trigger IC3, grounding capacitor C14, terminal CN6, diode D4, relay RL2, light-emitting diode LED4, resistor R17, resistor R18 and transistor BG5;

[0068] The triple-five flip-flop IC3 The VDD terminal is connected to the positive electrode of capacitor EC5, the positive electrode of light-emitting diode LED4, the 2nd pin of terminal CN6, the negative electrode of diode D4, one end of the coil of relay RL2 and the DIS terminal of triple-five trigger IC3 respectively. The terminal is connected and serves as the NE12V terminal of the exposure drive circuit;

[0069] The GND terminal of the triple-five trigger IC3 is grounded, and its Vc terminal is connected to the ground capacitor C14;

[0070] The Vo terminal of the triple-five trigger IC3 is connected to one end of the resistor R18;

[0071] The movable end and the second fixed end of the sliding rheostat RW2 are grounded;

[0072] The base of the transistor BG5 is connected to the other end of the resistor R18, the emitter thereof is grounded, and the collector thereof is respectively connected to one end of the resistor R17, the other end of the coil of the relay RL2, the anode of the diode D4 and pin 1 of the terminal CN6;

[0073] The other end of the resistor R17 is connected to the cathode of the light emitting diode LED4.

[0074] like Figures 4-5 As shown, the timed exposure preparation drive circuit includes: resistor R22, dual D flip-flop IC2, grounding resistor R15, resistor R4, transistor BG1, resistor R6, light-emitting diode LED2, resistor R5, terminal CN2, sliding rheostat RW1, capacitor C10, resistor R7, timer IC4, switch S1, resistor R20, resistor R21, button AN1, terminal CN5, grounding resistor R2, grounding capacitor C8, inverter IC1, resistor R23, terminal CN1 , variable resistor R3, grounded capacitor C9, NMOS tube BG4, resistor R14, OR gate IC8, resistor R11, resistor R10, transistor BG3, grounded resistor R12, capacitor C11, grounded resistor R13, AND gate IC5, resistor R8, transistor BG2, relay RL1, grounded capacitor C16, bell ringer BZ1, resistor R16, light-emitting diode LED3, diode D1, grounded capacitor C12, grounded capacitor C13, grounded capacitor C15 and grounded capacitor C17;

[0075] The 1Q terminal of the dual D flip-flop IC2 is respectively connected to the 2CP terminal of the dual D flip-flop IC2, one end of the resistor R15, one end of the variable resistor R3, the 1 pin of the wiring group CN1 and the SEL terminal of the timer IC4;

[0076] The dual D flip-flop IC2 The terminals are connected to one end of the resistor R22 and the A5 terminal of the inverter IC1 respectively, the 1CP terminal is connected to the Y2 terminal of the inverter IC1, the 1RD terminal is connected to the Y terminal of the OR gate IC8, the 1D terminal serves as the 5V terminal of the timing exposure preparation drive circuit, the 1SD terminal, the GND terminal and the 2SD terminal are grounded, the VDD terminal is connected to the 5V terminal of the timing exposure preparation drive circuit, the 2Q terminal is connected to one end of the resistor R4, and the 1D terminal is connected to the 5V terminal of the timing exposure preparation drive circuit. The terminals are connected to the A3 terminal of the inverter IC1 and the 2D terminal of the dual D flip-flop IC2 respectively;

[0077] The other end of the resistor R22 is connected to the 5V terminal of the timing exposure preparation drive circuit;

[0078] The other end of the resistor R15 is grounded;

[0079] The base of the transistor BG1 is connected to the other end of the resistor R4, and the emitter thereof is grounded;

[0080] The RTC terminal of the timer IC4 is connected to the first fixed terminal of the sliding rheostat RW1, the sliding terminal of the sliding rheostat RW1, the 2nd pin of the terminal CN2 and the 3rd pin of the terminal CN2 respectively, its CTC terminal is connected to one end of the capacitor C10, its RS terminal is connected to one end of the resistor R7, its AR terminal, GND terminal and MODE terminal are grounded, and its Its terminals are connected to one end of resistor R5, the collector of transistor BG1 and one end of resistor R6 respectively, its VDD terminal is connected to the 5V terminal of the time exposure preparation drive circuit, its B terminal is connected to one end of resistor R20 and pin 2 of switch S1 respectively, its A terminal is connected to one end of resistor R21 and pin 1 of switch S1 respectively, and its Q terminal is connected to terminal A4 of inverter IC1;

[0081] The other end of the resistor R6, the positive electrode of the light-emitting diode LED2, the grounding capacitor C12, the grounding capacitor C13, the grounding capacitor C15, the grounding capacitor C17, the other end of the resistor R20 and the other end of the resistor R21 are all connected to the 5V terminal of the timing exposure preparation drive circuit;

[0082] The other end of the resistor R5 is connected to the cathode of the light emitting diode LED2;

[0083] The other end of the resistor R7 is connected to the other end of the capacitor C10, the second fixed end of the sliding resistor RW1 and the pin 1 of the terminal CN2 respectively;

[0084] Pins 3 and 4 of the switch S1 are grounded;

[0085] The inverter IC1 has its A1 terminal connected to one end of the button AN1, pin 2 of the terminal CN5, the grounding resistor R2, and the grounding capacitor C2, its Y1 terminal connected to the A2 terminal, its Y3 terminal connected to the B terminal of the AND gate IC5, its GND terminal connected to ground, its VDD terminal connected to the 5V terminal of the timing exposure preparation drive circuit, its A6 terminal connected to one end of the resistor R23, its Y5 terminal connected to one end of the resistor R11, and its Y4 terminal connected to the A terminal of the AND gate IC5;

[0086] The other end of the resistor R23, the other end of the button AN1 and the pin 1 of the terminal CN5 are all connected to the 5V terminal of the timer exposure preparation drive circuit;

[0087] The gate of the NMOS transistor BG4 is connected to one end of the resistor R14, the drain thereof is respectively connected to the grounded capacitor C9, the A end of the OR gate IC8, the other end of the variable resistor R3 and the 2nd pin of the terminal CN1, and the source thereof is grounded;

[0088] The B terminal of the OR gate IC8 is respectively connected to the other end of the resistor 14, the grounding resistor R12, one end of the capacitor C11 and the 2RD terminal of the dual D flip-flop IC2, its VCC is connected to the 5V terminal of the timing exposure preparation drive circuit, and its GND terminal is grounded;

[0089] The GND terminal of the AND gate IC5 is grounded, the VCC terminal thereof is connected to the 5V terminal of the timing exposure preparation drive circuit, and the Y terminal thereof is connected to one end of the resistor R8;

[0090] The other end of the capacitor C11 is connected to the ground resistor R13 and the collector of the transistor BG3;

[0091] The base of the transistor BG3 is connected to the other end of the resistor R11 and one end of the resistor R10 respectively, and the emitter thereof and the other end of the resistor R10 are both connected to the 5V terminal of the timing exposure preparation drive circuit;

[0092] The other end of the resistor R8 is connected to the base of the transistor BG2;

[0093] The emitter of the transistor BG2 is grounded, and the collector thereof is connected to the anode of the diode D1, one end of the coil of the relay RL1, one end of the resistor R16 and one end of the bell BZ1;

[0094] The cathode of the diode D1 is connected to the other end of the coil of the relay RL1, one end of the first contact of the relay RL1 and the anode of the light-emitting diode LED3, and serves as the +12V terminal of the timed exposure preparation drive circuit;

[0095] The other end of the first contact of the relay RL1 is connected to the grounding capacitor C16 and the other end of the bell BZ1 respectively, and serves as the NE12V terminal of the timed exposure preparation drive circuit;

[0096] The other end of the resistor R16 is connected to the cathode of the light emitting diode LED3;

[0097] The NE12V terminal of the timing exposure preparation driving circuit is connected to the NE12V terminal of the exposure driving circuit;

[0098] The 5V terminal of the timing exposure preparation driving circuit is connected to the +5V terminal of the power supply circuit;

[0099] The +12V terminal of the time exposure preparation drive circuit is connected to the +12V terminal of the power supply circuit.

[0100] The model of the voltage regulator chip IC6 is LM7805CT, and the model of the voltage regulator chip IC7 is LM7812CT.

[0101] The model of the dual D flip-flop IC2 is CD4013.

[0102] The model of inverter IC1 is CD40106.

[0103] The model of the OR gate IC8 is NL17SZ32DFT2G, the model of the AND gate IC5 is NL17SZ08DFT2G, and the model of the timer IC4 is CD4541.

[0104] After the timing exposure preparation drive circuit is powered on, the button AN1 is not pressed, and due to the effect of the pull-up resistor R22, the dual D trigger IC2 The high level is converted to a low level through the inverter A5 terminal and output through the Y5 terminal of the inverter IC1. The transistor BG3 is turned on. Due to the presence of the capacitor C11, a short high level output is output on the ground resistor R12. At the same time, the NMOS tube BG4 is turned on, discharging the voltage across the capacitor C9 to prepare for charging the capacitor C9. When the NMOS tube BG4 is turned on instantaneously, the A terminal of the OR gate IC8 inputs a low level. At this time, the A terminal of the OR gate IC8 inputs a low level and its B terminal inputs a high level, then the Y terminal of the OR gate IC8 outputs a high level. The high level output of the Y terminal of the OR gate IC8 is input to the 1RD terminal of the dual D flip-flop IC2, so that the D flip-flop IC2A of the dual D flip-flop IC2 (the dual D flip-flop IC2 includes: D flip-flop IC2A and D flip-flop IC2B) is reset, that is, the 1Q terminal of the dual D flip-flop IC2 outputs a low level, and the dual D flip-flop IC2 is reset. The terminal outputs high level.

[0105] At the same time, due to the instantaneous high level on the resistor R12, the 2RD terminal of the dual D flip-flop IC2 inputs a high level, and the D flip-flop IC2B of the dual D flip-flop IC2 is reset. The 2Q terminal of the dual D flip-flop IC2 outputs a low level, the transistor BG1 is cut off, the collector of the transistor BG1 is high, and the timer IC4 is The input of high level to the terminal resets the timer IC4. Since the 1Q terminal of the dual D flip-flop IC2 outputs low level, the input of low level to the SEL terminal of the timer IC4 causes the Q terminal of the timer IC4 to output low level. The low level output of the Q terminal of the timer IC4 is converted to high level through the A4 terminal of the inverter IC1, and the high level is output through the Y4 terminal of the inverter IC1. The input of high level to the A terminal of the AND gate IC5 is; the dual D flip-flop IC2 The terminal outputs a high level (the initial state output is a high level), through the A3 terminal - Y3 terminal of the inverter IC1, the Y3 terminal of the inverter IC1 outputs a low level, that is, the B terminal of the AND gate IC5 inputs a low level, then the Y terminal of the AND gate IC5 outputs a low level, the transistor BG2 is cut off, and the relay RL1 does not work.

[0106] When the button AN1 is pressed, the A1 terminal of the inverter IC1 inputs a high level, the Y2 terminal of the inverter IC1 outputs a high level, the 1CP terminal of the dual D flip-flop IC2 inputs a high level, the 1Q terminal of the dual D flip-flop IC2 outputs a high level, the 2CP terminal of the dual D flip-flop IC2 inputs a high level, the 2Q terminal of the dual D flip-flop IC2 outputs a high level, the transistor BG1 is turned on, and the timer IC4 The input of the terminal is low, the reset fails and the timing starts. The A3-Y3 terminal of the inverter IC1 outputs a low level, and the Y3 terminal of the inverter IC1 outputs a high level, and the B terminal of the AND gate IC5 inputs a high level; the high level output by the 1Q terminal of the dual D flip-flop IC2 is input into the SEL terminal of the timer IC4, and the Q terminal of the timer IC4 outputs a high level, and the A terminal of the inverter IC1 outputs a low level through the A4-Y4 terminal of the inverter IC1, and the A terminal of the AND gate IC5 inputs a low level; then the Y terminal of the AND gate IC5 outputs a low level, the transistor BG2 is not turned on, and the relay RL1 does not work.

[0107] When the timer IC4 reaches the end of the time, the Q terminal of the timer IC4 outputs a low level, and the dual D flip-flop IC2 The output of the terminal is still low, and capacitor C9 is charged through resistor R3. Due to the existence of capacitor C9, the 1RD terminal of the dual D flip-flop IC2 is temporarily pulled low, maintaining the normal operation of the D flip-flop IC2A. At this time, the input of terminal A of AND gate IC5 is high.

[0108] At the same time, the dual D flip-flop IC2 The terminal outputs a low level, through the A3-Y3 terminal of the inverter IC1, the Y3 terminal of the inverter IC1 outputs a high level, the B terminal of the AND gate IC5 inputs a high level, and the Y terminal of the AND gate IC5 outputs a high level.

[0109] At this time, both the B and A terminals of the AND gate IC5 input high level, so that the Y terminal of the AND gate IC5 outputs high level, the first contact and the second contact of the relay RL1 are closed, the light-emitting diode LED3 is on, and the bell BZ1 works.

[0110] After passing through the time constant of the variable resistor R3 and the grounding capacitor C9, the voltage on the grounding capacitor C9 is greater than 1 / 2VCC (VCC is the highest voltage on the capacitor C9), which resets the D flip-flop IC2A of the dual D flip-flop IC2 and restores the D flip-flop IC2A to its initial state. Then the capacitor C9 is high, the A terminal of the OR gate IC8 inputs a high level, the Y terminal of the OR gate IC8 outputs a high level, the 1RD terminal of the dual D flip-flop IC2 inputs a high level, the D flip-flop IC2A is reset, the 1Q terminal of the dual D flip-flop IC2 outputs a low level, and the dual D flip-flop IC2 is The terminal outputs a high level, and after passing through the inverter A5-Y5 terminal, it outputs a low level, causing the transistor BG3 to be turned on. Due to the existence of capacitor C11, a short high level appears on the grounding resistor R12. The high level of the grounding resistor R12 resets the D flip-flop IC2B of the dual D flip-flop IC2. At the same time, the NOMS tube BG4 is turned on, so that the voltage across the grounding capacitor C9 is discharged, preparing for the next charging.

[0111] When the 2Q terminal of the dual D flip-flop IC2 outputs a low level, transistor BG1 is cut off, and the timer IC4 The input of high level to the terminal is reset, and the Q terminal of timer IC4 outputs low level (the initial state of the Q terminal of timer IC4 depends on the input state of the SEL terminal of timer IC4), and then passes through the A4 terminal - Y4 terminal of inverter IC1, the Y4 terminal of inverter IC1 outputs high level, the A terminal of AND gate IC5 inputs high level, and the dual D flip-flop IC2 The terminal outputs a high level, passes through the inverter A3-Y3 terminal, and the B terminal of the AND gate IC5 inputs a low level. The Y terminal of the AND gate IC5 outputs a low level, and the transistor BG2 is cut off, so that the first and second contacts of the relay RL1 are released, and the ringing bell BZ1 stops working and waits for the next press of the button AN1, and the cycle continues.

[0112] When the first contact of relay RL1 is closed, it provides working voltage for exposure drive circuit. Due to the existence of capacitor EC5, a short high level appears on sliding rheostat RW2. The voltage of sliding rheostat RW2 is greater than 2 / 3 of 12V. Triple-five trigger IC3 determines that The terminal is high, making the Vo terminal of the three-five trigger IC3 output a low level, the transistor BG5 is cut off, the relay RL2 does not work, and as the capacitor EC5 charges, the voltage on the sliding rheostat RW2 is pulled down by the capacitor EC5. When the voltage on the sliding rheostat RW2 is less than 1 / 3 of 12V, the three-five trigger IC3 determines that it is The Vo terminal of the triple-five flip-flop IC3 outputs a high level, turning on the transistor BG5 and closing the first contact of the relay RL2.

[0113] In this design, by setting the capacitance of capacitor C9, the resistance of rheostat R3, the capacitance of capacitor EC5 and the resistance of sliding rheostat RW2, the contact closing time of relay RL1 is greater than the contact closing time of relay RL2.

[0114] By connecting the two ends of the second contact of the relay RL1 in the circuit to the exposure start end of the radiation device, it is used to control the power supply of the radiation device, and connecting the two ends of the first contact of the relay RL2 to the exposure operation end of the radiation device to control the operation of the radiation device.

[0115] The beneficial effects of the present invention are as follows: the device is based on digital chips with stable performance, mature semiconductor transistor elements and standard unified resistors and capacitors, and is more shock-proof than timing devices with mechanical structures; and the circuit scheme of pure logic gates and triggers will not have soft errors and has more stable performance than the scheme using programmable devices; through the design of a universal interface, it can be adapted to mainstream radiation equipment on the market, such as: small X-ray machines, bedside DR machines, bone density, oral dental film machines, CBCT, etc., so it has strong versatility and is easy to promote, and has important application value in actual clinical work. Since the device is directly connected to the cable end of the radiation equipment, there is no need to extend the cable of the equipment control line. The technician only needs to press the button AN1 and wait for a period of delay to realize the operation of the radiation equipment, and the waiting delay time can be flexibly adjusted through the switch S1.

Claims

1. A medical digital adjustable delayed exposure circuit, characterized in that: include: Power supply circuit, exposure drive circuit and timed exposure preparation drive circuit; The power supply circuit is connected to the timing exposure preparation drive circuit; The timing exposure preparation drive circuit includes: a resistor R22, a dual D trigger IC2, a grounding resistor R15, a resistor R4, a transistor BG1, a resistor R6, a light emitting diode LED2, a resistor R5, a terminal CN2, a sliding rheostat RW1, a capacitor C10, a resistor R7, a timer IC4, a switch S1, a resistor R20, a resistor R21, a button AN1, a terminal CN5, a grounding resistor R2, a grounding capacitor C8, an inverter IC1, a resistor R23, a terminal CN1, Variable resistor R3, grounded capacitor C9, NMOS transistor BG4, resistor R14, OR gate IC8, resistor R11, resistor R10, transistor BG3, grounded resistor R12, capacitor C11, grounded resistor R13, AND gate IC5, resistor R8, transistor BG2, relay RL1, grounded capacitor C16, bell ringer BZ1, resistor R16, light-emitting diode LED3, diode D1, grounded capacitor C12, grounded capacitor C13, grounded capacitor C15, and grounded capacitor C17; The other end of the resistor R6, the positive electrode of the light-emitting diode LED2, the grounding capacitor C12, the grounding capacitor C13, the grounding capacitor C15, the grounding capacitor C17, the other end of the resistor R20 and the other end of the resistor R21 are all connected to the 5V terminal of the timing exposure preparation drive circuit; The VDD terminal of the inverter IC1 is connected to the 5V terminal of the timing exposure preparation drive circuit; The other end of the resistor R23, the other end of the button AN1 and the pin 1 of the terminal CN5 are all connected to the 5V terminal of the timer exposure preparation drive circuit; The VCC of the OR gate IC8 is connected to the 5V terminal of the timing exposure preparation drive circuit; The VCC terminal of the AND gate IC5 is connected to the 5V terminal of the timing exposure preparation drive circuit; The emitter of the transistor BG3 and the other end of the resistor R10 are both connected to the 5V terminal of the timing exposure preparation drive circuit; The cathode of the diode D1 is connected to the other end of the coil of the relay RL1, one end of the first contact of the relay RL1 and the anode of the light-emitting diode LED3, and serves as the +12V terminal of the timed exposure preparation drive circuit; The other end of the first contact of the relay RL1 is connected to the grounding capacitor C16 and the other end of the bell BZ1 respectively, and serves as the NE12V terminal of the timed exposure preparation drive circuit; The NE12V terminal of the timing exposure preparation driving circuit is connected to the NE12V terminal of the exposure driving circuit; The 5V terminal of the timing exposure preparation driving circuit is connected to the +5V terminal of the power supply circuit; The +12V terminal of the time exposure preparation driving circuit is connected to the +12V terminal of the power supply circuit; The exposure driving circuit is connected to the timing exposure preparation driving circuit.

2. The medical digital adjustable delayed exposure circuit according to claim 1, characterized in that: The power supply circuit includes: a terminal CN3, a rectifier bridge BD1, a capacitor EC1, a grounding capacitor C1, a voltage stabilizing chip IC6, a capacitor EC3, a grounding capacitor C3, a resistor R1, a light-emitting diode LED1, a capacitor EC2, a grounding capacitor C2, a voltage stabilizing chip IC7, a capacitor EC4 and a grounding capacitor C6; Pin 1 of the connection terminal CN3 is connected to the first AC input terminal of the rectifier bridge BD1, and pin 2 thereof is connected to the second AC input terminal of the rectifier bridge BD1; The first DC output terminal of the rectifier bridge BD1 is respectively connected to the positive electrode of the capacitor EC1, the grounding capacitor C1, the Vin terminal of the voltage regulator chip IC6, the positive electrode of the capacitor EC2, the grounding capacitor C2 and the Vin terminal of the voltage regulator chip IC7; The +5V terminal of the voltage stabilizing chip IC6 is connected to the positive electrode of the capacitor EC3, the grounding capacitor C3 and the other end of the resistor R1, and serves as the +5V terminal of the power supply circuit; The +12V terminal of the voltage stabilizing chip IC7 is connected to the positive electrode of the capacitor EC4 and the grounding capacitor C6 respectively, and serves as the +12V terminal of the power supply circuit; The other end of the resistor R1 is connected to the positive electrode of the light emitting diode LED1; The second DC output terminal of the rectifier bridge BD1, the cathode of the capacitor EC1, the GND terminal of the voltage regulator chip IC6, the cathode of the capacitor EC3, the cathode of the light-emitting diode LED1, the cathode of the capacitor EC2, the GND terminal of the voltage regulator chip IC7 and the cathode of the capacitor EC4 are all grounded.

3. The medical digital adjustable delayed exposure circuit according to claim 2, characterized in that: The exposure drive circuit includes: a capacitor EC5, a sliding rheostat RW2, a triple-five trigger IC3, a grounding capacitor C14, a terminal CN6, a diode D4, a relay RL2, a light-emitting diode LED4, a resistor R17, a resistor R18 and a transistor BG5; The triple-five flip-flop IC3 The VDD terminal is connected to the positive electrode of capacitor EC5, the positive electrode of light-emitting diode LED4, the 2nd pin of terminal CN6, the negative electrode of diode D4, one end of the coil of relay RL2 and the DIS terminal of triple-five trigger IC3 respectively. The terminal is connected and serves as the NE12V terminal of the exposure drive circuit; The GND terminal of the triple-five trigger IC3 is grounded, and its Vc terminal is connected to the ground capacitor C14; The Vo terminal of the triple-five trigger IC3 is connected to one end of the resistor R18; The movable end and the second fixed end of the sliding rheostat RW2 are grounded; The base of the transistor BG5 is connected to the other end of the resistor R18, the emitter thereof is grounded, and the collector thereof is respectively connected to one end of the resistor R17, the other end of the coil of the relay RL2, the anode of the diode D4 and pin 1 of the terminal CN6; The other end of the resistor R17 is connected to the cathode of the light emitting diode LED4.

4. The medical digital adjustable delayed exposure circuit according to claim 2, characterized in that: The model of the voltage stabilizing chip IC6 is LM7805CT, and the model of the voltage stabilizing chip IC7 is LM7812CT.

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