Resistive memory device

Abstract

A resistive memory device includes an array of memory cells including a memory cell connected between a first signal line and a second signal line; a control circuit configured to generate a write control signal for controlling a data write operation performed on the memory cell and a read control signal for controlling a data read operation for reading data stored in the memory cell; a write circuit configured to supply a write current to support the data write operation; a read circuit configured to supply a read current to support the data read operation; a column decoder circuit configured to electrically connect the write circuit to the first signal line based on the write control signal; and a row decoder circuit configured to electrically connect the read circuit to the second signal line based on the read control signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0092667, filed on August 8, 2018, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to resistive memory devices, and more specifically, to resistive memory devices in which write current and read current are applied in different directions. Background Technology

[0004] Due to the need for larger storage capacity and lower power consumption in memory devices, next-generation non-volatile memory devices that do not require refresh operations are being researched. Next-generation memory devices can combine the high integration of Dynamic Random Access Memory (DRAM), the non-volatility of Flash Memory, and the high speed of Static Random Access Memory (SRAM). Currently, some next-generation memory devices that have attracted widespread attention and meet these requirements include Phase-Change Random Access Memory (PRAM), Nanofloating Gate Memory (NFGM), Polymer Random Access Memory (PoRAM), Magnetic Random Access Memory (MRAM), Ferroelectric Random Access Memory (FeRAM), and Resistive Random Access Memory (ReRAM). Summary of the Invention

[0005] Some exemplary embodiments of the present invention provide resistive memory devices configured to reduce degradation caused by spike currents that occur when data is read.

[0006] According to some exemplary embodiments of the present invention, a resistive memory device may include a plurality of first signal lines and a plurality of second signal lines. Each of the plurality of second signal lines may intersect with each of the plurality of first signal lines. The resistive memory device may include a memory cell array comprising a plurality of memory cells. Each of the plurality of memory cells may have a first end connected to one of the plurality of first signal lines and a second end connected to one of the plurality of second signal lines. The resistive memory device may include a write circuit configured to supply a write current to at least one of the plurality of memory cells through at least one of the plurality of first signal lines, the write current being associated with writing data into the at least one memory cell. The resistive memory device may include a read circuit configured to supply a read current to the at least one of the plurality of memory cells through at least one of the plurality of second signal lines, the read current being associated with reading data stored in the at least one memory cell.

[0007] According to some exemplary embodiments of the present invention, a resistive memory device may include a plurality of first signal lines spaced apart from each other in a first direction, each of the plurality of first signal lines extending in a second direction perpendicular to the first direction. The resistive memory device may include a plurality of second signal lines spaced apart from each other in the second direction, each of the plurality of second signal lines extending in the first direction, spaced apart from the plurality of first signal lines in a third direction perpendicular to both the first and second directions. The resistive memory device may include a memory cell array comprising a plurality of memory cells. Each of the plurality of memory cells may be connected at a first end to one of the plurality of first signal lines and at a second end to one of the plurality of second signal lines. The resistive memory device may include a write circuit configured to supply a write current to at least one of the plurality of memory cells such that the write current flows through the at least one memory cell from a corresponding first signal line to a corresponding second signal line of the plurality of second signal lines, the write current being associated with writing data into the at least one memory cell. The resistive memory device may include a read circuit configured to supply a read current to the at least one memory cell such that the read current flows from a corresponding second signal line through the at least one memory cell to a corresponding first signal line, the read current being associated with reading data stored in the at least one memory cell.

[0008] According to some exemplary embodiments of the present invention, a resistive memory device may include a memory cell array comprising memory cells connected between a first signal line and a second signal line. The resistive memory device may include control circuitry configured to generate write control signals for controlling data write operations performed on memory cells and read control signals for controlling data read operations to read data stored in memory cells. The resistive memory device may include: a write circuit configured to supply write current to support data write operations; a read circuit configured to supply read current to support data read operations; a column decoder circuit configured to electrically connect the write circuit to the first signal line based on the write control signals; and a row decoder circuit configured to electrically connect the read circuit to the second signal line based on the read control signals. Attached Figure Description

[0009] Example embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram illustrating a memory system according to some example embodiments;

[0011] Figure 2 This is a block diagram of a memory device according to some example embodiments;

[0012] Figure 3 This is a block diagram illustrating the construction of a memory cell array;

[0013] Figure 4 This illustrates some example embodiments. Figure 3 The circuit diagram of the area shown is shown.

[0014] Figures 5A to 5C They are shown separately. Figure 4 Circuit diagram of an example embodiment of a memory cell;

[0015] Figure 6A This is a circuit diagram illustrating the construction of each of the line decoder and read circuit according to some example embodiments;

[0016] Figure 6B This is a circuit diagram illustrating the construction of each of the column decoder and write circuit according to some example embodiments;

[0017] Figure 7A It is a diagram illustrating the movement of columns when a data write operation is performed, according to some example embodiments;

[0018] Figure 7B This is a diagram illustrating the movement of columns when a data read operation is performed, according to some example embodiments;

[0019] Figure 8AIt is a graph showing the logarithmic voltage-current curves of selected elements according to some example embodiments;

[0020] Figure 8B This is a graph showing the peak current according to each of some example embodiments and comparative examples;

[0021] Figure 8C It is a graph showing the resistance value distribution of memory cells according to each of some example embodiments and comparative examples;

[0022] Figure 9 This is a circuit diagram illustrating an implementation example of a slice according to some example embodiments;

[0023] Figure 10 It is a diagram, based on some example embodiments, illustrating the direction of the current applied when performing write and read operations;

[0024] Figure 11 It is a diagram, based on some example embodiments, illustrating the direction of the current applied when performing write and read operations;

[0025] Figure 12 This is a timing diagram of the write current applied to a memory cell according to some example embodiments; and

[0026] Figure 13 This is a block diagram illustrating a computing system including a memory system according to some example embodiments. Detailed Implementation

[0027] The following description will focus on exemplary embodiments with reference to the accompanying drawings.

[0028] Figure 1 This is a block diagram illustrating a memory system 1 according to some example embodiments.

[0029] Reference Figure 1 The memory system 1 may include a memory controller 10 and a memory device 100. The memory controller 10 may be implemented by one or more circuit instances, including processing circuit instances (e.g., a processor device). The memory device 100 may include a memory cell array 110, control logic 120, write circuitry 150, and read circuitry 160. In some example embodiments, the memory device 100 may also include multiple circuits that perform write and read operations on the memory cell array 110 under the control of the control logic 120. The memory cell array 110 may include multiple resistive memory cells. Therefore, the memory device 100 may be referred to as a resistive memory device, and the memory system 1 may be referred to as a resistive memory system. As described above, it should be understood that the control logic 120 may be an instance of control circuitry of the memory device 100 including a processor, an instance of processing circuitry, or some combination thereof.

[0030] Reference Figure 1 And other references Figure 2 The memory device 100 may include an internal data bus, and for example, Figure 2 As shown, one or more of the elements of the memory device 100 can be communicatively coupled to each other via the internal data bus of the memory device 100.

[0031] In response to a write / read request from a host, memory controller 10 can control memory device 100 to write data to or read data stored in memory device 100. Specifically, memory controller 10 can provide address ADDR, command CMD, and control signal CTRL to memory device 100 to control programming (e.g., write) operations, read operations, and erase operations on memory device 100. In some example embodiments, the data DT to be written and the data DT to be read can be sent and received between memory controller 10 and memory device 100. For example, when multiple memory cells (not shown) included in memory cell array 110 are arranged in a multi-row, multi-column configuration, address ADDR can include row addresses and column addresses.

[0032] Although not shown, the memory controller 10 may also include random access memory (RAM), a processor, a host interface, and a memory interface. The RAM may be used as working memory, and the processor may control the operation of the memory controller 10. The host interface may include protocols for performing data exchange between the host and the memory controller 10. For example, the memory controller 10 may be configured to communicate with an external device (e.g., a host) via at least one of various interface protocols, such as: Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0033] The memory cell array 110 may include the plurality of memory cells (not shown), which are respectively disposed in a plurality of regions defined by the intersections of a plurality of first signal lines and a plurality of second signal lines, wherein each of the plurality of second signal lines intersects with each of the plurality of first signal lines. In some example embodiments, the plurality of first signal lines may be a plurality of word lines, and the plurality of second signal lines may be a plurality of bit lines. In some example embodiments, the plurality of first signal lines may be a plurality of bit lines, and the plurality of second signal lines may be a plurality of word lines. The memory device 100 including the memory cell array 110 may be referred to as a crosspoint memory device.

[0034] The memory cell array 110 may include the plurality of memory cells arranged in multiple rows and columns. In some example embodiments, the plurality of memory cells may include multiple resistive memory cells, each including a variable resistor (not shown). For example, when the variable resistor includes a phase change material (e.g., Ge-Sb-Te (GST)) and its resistance varies with temperature, the memory device 100 may include phase change RAM (PRAM). As another example, when the variable resistor includes a top electrode, a bottom electrode, and a composite metal oxide therebetween, the memory device 100 may include resistive RAM (ReRAM). As another example, when the variable resistor includes a top electrode of magnetic material, a bottom electrode of magnetic material, and a dielectric therebetween, the memory device 100 may include magnetic RAM (MRAM). Examples in which the memory device 100 includes PRAM will be described below.

[0035] In some example embodiments, each of the plurality of memory cells may be a single-layer cell (SLC) storing 1 bit of data, and in this case, the memory cell may have two resistance distributions based on the stored data. In some example embodiments, each of the plurality of memory cells may be a multi-layer cell (MLC) storing 2 bits of data, and in this case, the memory cell may have four resistance distributions based on the stored data. In some example embodiments, each of the plurality of memory cells may be a three-layer cell (TLC) storing 3 bits of data, and in this case, the memory cell may have eight resistance distributions based on the stored data. However, the inventive concept is not limited thereto. In some example embodiments, the memory cell array 110 may include memory cells storing 4 bits or more of data. In some example embodiments, the memory cell array 110 may include SLC and MLC or TLC.

[0036] Furthermore, in some example embodiments, the memory cell array 110 may include memory cells with a two-dimensional (2D) horizontal structure. In some example embodiments, the memory cell array 110 may include memory cells with a three-dimensional (3D) vertical structure.

[0037] Control logic 120 can control the overall operation of memory device 100 and can control write circuit 150 and read circuit 160 to perform memory operations including write operations and read operations. For example, memory device 100 may include power generating means (not shown) that generate various voltages for write operations and read operations, and the voltage levels can be adjusted based on the control logic 120.

[0038] The write circuit 150 can perform write operations on memory cells. The write circuit 150 may include a write driver connected to the memory cells via multiple bit lines and multiple word lines and writes data into the memory cells.

[0039] The read circuit 160 can perform a read operation on data stored in each of the memory cells. The read circuit 160 may include a read amplifier connected to the memory cells via the plurality of bit lines and the plurality of word lines and amplifying the data read from each of the memory cells.

[0040] In some example embodiments, write circuit 150 and read circuit 160 can provide (“supply”, “apply”, etc.) write current and read current to each of the memory cells via different signals. For example, write circuit 150 can provide write current to the memory cell via a word line, and read circuit 160 can provide read current to the memory cell via a bit line. As another example, write circuit 150 can provide write current to the memory cell via a bit line, and read circuit 160 can provide read current to the memory cell via a word line.

[0041] According to some example embodiments, write current and read current can be input to each of the memory cells in different directions, thus allowing selective thermoelectric cooling to occur within the memory cells. For example, when each of the memory cells includes a variable resistor and a heating element, the write current can be applied in the direction from the heating element to the variable resistor (e.g., the direction in which heat transfer increases). In some example embodiments, the read current can be applied in the direction from the variable resistor to the heating element (e.g., the direction in which heat transfer increases). Therefore, in the present invention, read disturbances caused by spike currents (SIRDs) that occur when reading data can be reduced, and data reliability can be improved.

[0042] The memory controller 10 and the memory device 100 may be integrated into a single semiconductor device. For example, the memory controller 10 and the memory device 100 may be integrated into a single semiconductor device to construct a memory card. For example, the memory controller 10 and the memory device 100 may be integrated into a single semiconductor device to construct a Personal Computer Card (PCMCIA), a Compact Flash Memory Card (CF), a Smart Media Card (SM / SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, or MMCmicro), a Secure Digital Card (SD) (SD, miniSD, or microSD), Universal Flash Storage (UFS), etc. As another example, the memory controller 10 and the memory device 100 may be integrated into a single semiconductor device to construct a Solid State Drive (SSD).

[0043] Figure 2 This is a block diagram of a memory device 100 according to some example embodiments. For example, Figure 2 Can be Figure 1 Detailed block diagram of the memory device 100.

[0044] Reference Figure 2 The memory device 100 may include a memory cell array 110, control logic 120, row decoder 130, column decoder 140, write circuitry 150, and read circuitry 160. As described above, the control logic 120 may be referred to as a control circuit. The row decoder 130 may be referred to herein as a row decoder circuit. The column decoder 140 may be referred to herein as a column decoder circuit. The elements included in the memory device 100 will be described in detail below.

[0045] Multiple memory cells included in the memory cell array 110 can be connected to multiple first signal lines and multiple second signal lines. In some example embodiments, the multiple first signal lines can be multiple word lines WL, and the multiple second signal lines can be multiple bit lines BL. Various voltage or current signals can be provided through the multiple word lines WL and the multiple bit lines BL. Therefore, data DT can be written to or read from a selected memory cell, and write or read operations can be prevented on other unselected memory cells. Hereinafter, in this specification, selecting a memory cell can indicate a memory cell among the multiple memory cells to which memory operations such as write, read, and / or erase operations are performed. In some example embodiments, non-selected memory cells can indicate memory cells among the multiple memory cells other than the selected memory cell.

[0046] Based on the command CMD, address ADDR, and control signal CTRL received from the memory controller 10, the control logic 120 can write data DT into the memory cell array 110 or output various control signals (e.g., read control signal CTRL_R and write control signal CTRL_W) for writing data DT into the memory cell array 110. Therefore, the control logic 120 can control various operations of the memory device 100 as a whole.

[0047] Control logic 120 may receive an address ADDR indicating the memory cell to be accessed based on command CMD, and the address ADDR may include a row address X_ADDR for selecting the word line WL of memory cell array 110 and a column address Y_ADDR for selecting the bit line BL of memory cell array 110. The address ADDR provided to memory device 100 may correspond to a physical address obtained based on a logical address from the host through a translation performed in the memory system.

[0048] Row decoder 130 may perform a word line selection operation in response to row address X_ADDR. In some example embodiments, row decoder 130 may be connected to read circuitry 160 and may perform control such that read current output from read circuitry 160 is applied to some word lines WL based on row address X_ADDR. Row decoder 130 may electrically connect read circuitry 160 to at least one of the plurality of second signal lines (e.g., word lines WL) of memory device 100 based on a read control signal CTRL_R generated by control logic 120. The word line to which read current is applied may be referred to as the selected word line. Read circuitry 160 may read data DT based on the read current applied to the selected memory cell. In some example embodiments, read circuitry 160 may provide a / failure signal P / F to control logic 120 based on a determination performed on the read data DT. Control logic 120 may control write and read operations of memory cell array 110 with reference to the / failure signal P / F.

[0049] Column decoder 140 may perform a bit line selection operation in response to column address Y_ADDR. In some example embodiments, column decoder 140 may be connected (e.g., electrically connected) to write circuitry 150. Column decoder 140 may perform control such that write current output from write circuitry 150 is applied to some bit lines BL based on column address Y_ADDR. Column decoder 140 may electrically connect write circuitry 150 to at least one of the plurality of first signal lines (e.g., bit lines BL) of memory device 100 based on a write control signal CTRL_W generated by control logic 120. The bit line to which write current is applied may be referred to as the selected bit line. Write circuitry 150 may write data DT according to the write current applied to the selected bit line.

[0050] In some example embodiments, a write circuit 150 is shown connected to the bit line BL via a column decoder 140, and a read circuit 160 is connected to the word line WL via a row decoder 130. Alternatively, the write circuit 150 can be connected to the word line WL via the row decoder 130, and the read circuit 160 can be connected to the bit line BL via the column decoder 140. In other words, in this inventive concept, write current can be input to the memory cell via one of a first signal line and a second signal line, and read current can be input to the memory cell via the other signal line. Therefore, write current and read current can be input to each of the memory cells in different directions.

[0051] Figure 3 This is a block diagram illustrating the construction of the memory cell array 110. For example, Figure 3 Can be shown Figure 2 The construction of the memory cell array 110.

[0052] Reference Figure 3The memory cell array 110 may include multiple blocks Bank_0 to Bank_N (where N is a positive integer). The multiple blocks Bank_0 to Bank_N may be arranged in one direction within the memory cell array 110. Each of the multiple blocks Bank_0 to Bank_N may include multiple tiles Tile 1 to Tile M (where M is a positive integer). For example, a block may be a unit comprising the multiple tiles Tile 1 to Tile M, and a tile may be a unit comprising multiple memory cells. In the accompanying drawings, block units and tile units are shown for ease of description, but the current embodiment is not limited thereto. For example, a block may be divided into multiple bay units, a bay may be divided into multiple bars, and a bar may be divided into multiple tile units.

[0053] Figure 4 It is shown Figure 3 The circuit diagram shows an example implementation of Tile 1.

[0054] Reference Figure 4 Tile 1 can include multiple word lines WL1 to WLk (where k is a positive integer), multiple bit lines BL1 to BLj (where j is a positive integer), and multiple memory cells MC. For example... Figure 4 As shown, memory cells MC selected for the same word line can be defined as page cells. Therefore, it should be understood that the memory cell array 110 includes a plurality of memory cells MC. In some example embodiments, and as... Figure 4 As shown, the plurality of first signal lines of the memory device 100 may include the plurality of bit lines BL1 to BLj, and the plurality of second signal lines of the memory device 100 may include the plurality of word lines WL1 to WLk, wherein each of the plurality of second signal lines (e.g., each word line WL1 to WLk) intersects with each of the first signal lines (e.g., each bit line BL1 to BL1). Here, the number of word lines WL1 to WLk, the number of bit lines BL1 to BLj, and the number of memory cells MC may vary according to some example embodiments. Figure 4 The image shows a 2D memory with a horizontal structure, but the inventive concept is not limited thereto. In other embodiments, Tile 1 may be a 3D memory with a vertical structure.

[0055] like Figure 4 As shown, each memory cell MC of the memory cell MC can be connected to the bit line at the first terminal 401 and to the word line at the second terminal 402. Therefore, as Figure 4As shown, each memory cell MC of the plurality of memory cells in the memory cell array 110 can be connected at a first end 401 to one of a plurality of first signal lines (e.g., bit lines BL1 to BLj), and at a second end 402 to one of a plurality of second signal lines (e.g., word lines WL1 to WLk). In some example embodiments, a write current can be applied to each of the memory cells MC via one of the word lines and the bit lines connected to the corresponding memory cell MC, and a read current can be applied to each of the memory cells MC via the other line. For example, in a write operation, the write current can flow through the memory cell MC in the direction from the bit line to the word line, and in a read operation, the read current can flow through the memory cell MC in the direction from the word line to the bit line.

[0056] Figures 5A to 5C They are shown separately. Figure 4 Circuit diagram of an embodiment of each of the memory cells MC.

[0057] Reference Figure 5A The memory cell MC may include a variable resistive element R, a selection element SW, and a heating element H. Here, the variable resistive element R may be referred to as a variable resistor (e.g., a variable resistive material), and the selection element SW may be referred to as a switching element. In some example embodiments, the heating element H may be referred to as a heating electrode (e.g., a heating electrode layer).

[0058] In some example embodiments, the variable resistor element R may be connected between the selection element SW and the heating element H, the selection element SW may be connected to the bit line BL1, and the heating element H may be connected to the word line WL1. In other words, at least as... Figure 5A As shown, one end of the selection element SW can be connected to bit line BL1 (e.g., one of the multiple first signal lines of memory device 100), and the other end of the selection element SW can be connected to the variable resistor element R. In some example embodiments, at least as shown... Figure 5A As shown, one end of the heating element H can be connected to word line WL1 (e.g., one of the multiple second signal lines of memory device 100), and the other end of the heating element H can be connected to the variable resistor element R. Therefore, one end of the variable resistor element R can be connected to the selection element SW, and the other end of the variable resistor element R can be connected to the heating element H.

[0059] A variable resistive element R can change to one of a plurality of resistive states based on an electrical pulse (e.g., a write current) applied to it. According to some example embodiments, the variable resistive element R may include a phase change material whose crystallization state changes based on the amount of current. The variable resistive element R may include a phase change material whose resistance changes based on the temperature of the phase change material. The phase change material can be a variety of materials, such as: various materials of GaSb, InSb, InSe, Sb₂Te₃ and GeTe produced by mixing two elements; GeSbTe(GST), GaSeTe, InSbTe, SnSb₂Te₄ and InSbGe produced by mixing three elements; and AgInSbTe, (GeSn)SbTe, GeSb(SeTe) and Te produced by mixing four elements. 81 Ge 15 Sb2S2.

[0060] Phase change materials can have an amorphous state with relatively high resistance and a crystalline state with relatively low resistance. Phase change materials can have a phase that changes through Joule heating based on the amount of current. In some example embodiments, data can be written using phase change. For example, a high-resistance state (e.g., a reset state) can be defined as 0, and a low-resistance state (e.g., a set state) can be defined as 1, thus storing data in a variable resistive element R.

[0061] In some example embodiments, the variable resistor element R may include a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material, rather than a phase change material.

[0062] The selection element SW can control the current supply to the variable resistor element R based on the current or voltage applied to the bit line BL1 connected thereto. The selection element SW may include and / or be a bidirectional threshold switch (OTS) comprising chalcogenide compounds. The OTS may have materials comprising arsenic (As), germanium (Ge), selenium (Se), tellurium (Te), silicon (Si), bismuth (Bi), sodium (S), and antimony (Sb). Specifically, the OTS may comprise a six-element material, wherein Se and S are added to the compound comprising Ge, Si, As, and Te.

[0063] When a data write operation is performed (e.g., a reset / set operation), the heating element H can heat the variable resistance element R. The heating element H may include a conductive material that generates heat sufficient to cause a phase change in the variable resistance element R without reacting with it. For example, the heating element H may include a carbon-based conductive material.

[0064] In some example embodiments, the heating element H may include TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, TiAlON, WON, TaON, carbon (C), SiC, SiCN, carbon nitride (CN), TiCN, TaCN, or a refractory metal corresponding to a combination thereof, or a nitride thereof.

[0065] Reference Figure 5B The memory cell MCa may include a variable resistor Ra, which may be connected between bit line BL1 and word line WL1. The memory cell MCa may store data based on a write current applied to it through bit line BL1. In some example embodiments, data stored in the memory cell MCa may be read based on a read current applied to it through word line WL1. To reiterate, a write current applied to a memory cell (e.g., memory cell MCa) may be associated with writing data into the memory cell, and a read current applied to a memory cell (e.g., memory cell MCa) may be associated with reading data stored in the memory cell.

[0066] Reference Figure 5C The memory cell MCb may include a variable resistor element Rb and a bidirectional diode Db. The variable resistor element Rb may include resistive material for storing data. The bidirectional diode Db may be connected between the variable resistor element Rb and the bit line BL1, and the variable resistor element Rb may be connected between the word line WL1 and the bidirectional diode Db. The bidirectional diode Db may interrupt leakage current flowing to the non-selective resistor memory cell.

[0067] Figure 6A This is a circuit diagram illustrating the construction of each of the line decoder and read circuit according to some example embodiments. Figure 6B This is a circuit diagram illustrating the construction of each of the column decoder and write circuit according to some example embodiments. Hereinafter, reference will be made to... Figure 2 describe Figure 6A and Figure 6B .

[0068] Reference Figure 6AThe read circuit 160 may include a first current source CS1, a sense amplifier SAMP, and a capacitor C. The first current source CS1 may output a reference current IREF. A portion of the reference current IREF may be applied as a read current I_R to the line decoder 130, and another current I1 may be charged into the capacitor C. One end of the capacitor C may be connected to ground voltage GND, and the other end may be connected to the first node N1. For example, the capacitor C may be a parasitic capacitor of word line WL1. As another example, the capacitor C may be a capacitor disposed within or outside the memory cell array 110 for reading data.

[0069] The sense amplifier SAMP may include an input terminal to which a reference voltage VREF is applied and an input terminal connected to a first node N1. The sense amplifier SAMP can compare the reference voltage VREF with a first voltage V1 of the first node N1 (i.e., the voltage applied to capacitor C) to output a comparison result SAOUT.

[0070] The line decoder 130 may include a first transistor T1, a second transistor T2, and a third transistor T3. The first transistor T1 may receive a complementary non-selection signal nDIS as its gate voltage. Figure 6A As shown, one end of the first transistor T1 (e.g., the source terminal) can be connected to the suppression voltage Vinhibit, and its other end (e.g., the drain terminal) can be connected to word line WL1 (e.g., one of the plurality of second signal lines of the memory device 100). The second transistor T2 can receive a complementary read enable signal nENRD as its gate voltage. Figure 6A As shown, one end of the second transistor T2 (e.g., the source terminal) can be connected to the first node N1 (and thus, to the read circuit 160), and its other end (e.g., the drain terminal) can be connected to the word line WL1 (e.g., the same second signal line to which the other end of the first transistor T1 is connected). The third transistor T3 can receive the write enable signal EN as its gate voltage. Figure 6A As shown, one end (e.g., the source terminal) of the third transistor T3 can be connected to ground voltage GND, and its other end (e.g., the drain terminal) can be connected to word line WL1 (e.g., the same second signal line to which the other end of the first transistor T1 and the other end of the second transistor T2 are connected).

[0071] A complementary non-select signal nDIS, a complementary read enable signal nENRD, and a write enable signal EN can be applied from control logic 120. In some example embodiments, the complementary non-select signal nDIS, the complementary read enable signal nENRD, and the write enable signal EN can be applied from control logic 120 based on a read control signal CTRL_R, such that the first transistor T1 through the third transistor T3 can be configured to be switched (“switched”) according to control based on the read control signal CTRL_R. In some example embodiments, each of the first transistor T1 and the second transistor T2 is shown to be a P-channel metal-oxide-semiconductor (PMOS) transistor, and the third transistor T3 is an N-channel metal-oxide-semiconductor (NMOS) transistor. These are merely some example embodiments and are not limited thereto.

[0072] Reference Figure 6B The write circuit 150 may include a second current source CS2. The second current source CS2 may output a write current (e.g., a reset current I_RESET). In some example embodiments, for ease of description, examples in which the write current is the reset current I_RESET will be described below; however, those skilled in the art will understand that the write circuit 150 may also include a current source that outputs a setting current as the write current.

[0073] The column decoder 140 may include a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. The fourth transistor T4 may receive a complementary write enable signal nEN as its gate voltage. For example... Figure 6B As shown, one end of the fourth transistor T4 (e.g., the source terminal) can be connected to the second current source CS2 (and thus to the write circuit 150), and its other end (e.g., the drain terminal) can be connected to the bit line BL1 (e.g., one of the plurality of first signal lines of the memory device 100). The fifth transistor T5 can receive a non-selection signal DIS as a gate voltage. Figure 6B As shown, one end of the fifth transistor T5 (e.g., the source terminal) can be connected to bit line BL1 (e.g., the same first signal line to which the other end of the fourth transistor T4 is connected), and its other end (e.g., the drain terminal) can be connected to the suppression voltage Vinhibit. The sixth transistor T6 can receive the read enable signal ENRD as its gate voltage. Figure 6B As shown, one end (e.g., the source terminal) of the sixth transistor T6 can be connected to ground voltage GND, and its other end (e.g., the drain terminal) can be connected to bit line BL1 (e.g., the same first signal line to which the other end of the fourth transistor T4 and the other end of the fifth transistor T5 are connected).

[0074] A non-selection signal DIS, a read enable signal ENRD, and a complementary write enable signal nEN can be applied from control logic 120. In some example embodiments, the non-selection signal DIS, the read enable signal ENRD, and the complementary write enable signal nEN can be applied from control logic 120 based on a write control signal CTRL_W, so that the fourth transistor T4 through the sixth transistor T6 can be configured to be switched (“switched”) according to control based on the write control signal CTRL_W. In some example embodiments, the fourth transistor T4 is shown to be a PMOS transistor, and each of the fifth transistor T5 and the sixth transistor T6 is an NMOS transistor. These are merely some example embodiments and are not limited thereto.

[0075] For example, when word line WL1 is an unselected word line, the first transistor T1 is turned on ("on") and the second transistor T2 and the third transistor T3 are turned off ("off"). Therefore, a suppression voltage Vinhibit can be applied to the unselected word line. In some example embodiments, when bit line BL1 is an unselected bit line, the fifth transistor T5 is turned on, and the fourth transistor T4 and the sixth transistor T6 are turned off. Therefore, a suppression voltage Vinhibit can be applied to the unselected bit line. In the following, examples in which word line WL1 is a selected word line and bit line BL1 is an unselected bit line will be described in some example embodiments.

[0076] During a data read operation, the second transistor T2 of the row decoder 130 is turned on, and the first transistor T1 and the third transistor T3 are turned off. To reiterate, a data read operation may include turning on the second transistor T2 and turning off both the first transistor T1 and the third transistor T3. In some example embodiments, during a data read operation, the sixth transistor T6 of the column decoder 140 is turned on, and the fourth transistor T4 and the fifth transistor T5 are turned off. To reiterate, a data read operation may include turning on the sixth transistor T6 and turning off both the fourth transistor T4 and the fifth transistor T5. Therefore, a read current I_R can be applied to the memory cell MC connected to the word line WL1 and the bit line BL1 via the word line WL1. That is, the read current I_R can flow through the word line WL1, the memory cell MC, and the bit line BL1.

[0077] During a data write operation, the third transistor T3 of the row decoder 130 is turned on, and the first transistor T1 and the second transistor T2 are turned off. To reiterate, a data write operation may include turning on the third transistor T3 and turning off both the first transistor T1 and the second transistor T2. In some example embodiments, during a data write operation, the fourth transistor T4 of the column decoder 140 is turned on, and the fifth transistor T5 and the sixth transistor T6 are turned off. To reiterate, a data write operation may include turning on the fourth transistor T4 and turning off both the fifth transistor T5 and the sixth transistor T6. Therefore, a write current I_RESET can be applied to the memory cell MC via the bit line BL1. That is, the write current I_RESET can flow through the bit line BL1, the memory cell MC, and the word line WL1.

[0078] Figure 7A The movement of columns is illustrated when a data write operation is performed, according to some example embodiments. Figure 7B The movement of a column is illustrated when a data read operation is performed, according to some example embodiments.

[0079] Reference Figure 7A The write current I_RESET can flow through the bit line BL, the memory cell MC, and the word line WL. In some example embodiments, the memory cell MC may include: a heating element H connected to the word line WL on one side and a variable resistor R on the other side; a variable resistor R connected to the heating element H on one side and a select element SW on the other side; and a select element SW connected to the variable resistor R on one side and the bit line BL on the other side. Although not shown, an intermediate electrode may also be provided between the select element SW and the variable resistor R, and a top electrode may also be provided between the bit line BL and the select element SW.

[0080] Therefore, the write current I_RESET can flow in the direction of the selection element SW, the variable resistor element R, and the heating element H. Since the write current I_RESET flows as described above, heat can be generated in the heating element H, and this heat can be transferred in the first direction T_E1 (i.e., from the heating element H to the variable resistor element R). Due to the heat transferred from the heating element H, a phase transition can occur in the portion M_R1 of the variable resistor element R.

[0081] Reference Figure 7BThe read current I_R can flow through the word line WL, memory cell MC, and bit line BL. Therefore, the read current I_R can flow in the direction of the heating element H, the variable resistor element R, and the selection element SW. Since the read current I_R flows as described above, heat can be generated in the heating element H, and this heat can be transferred in a second direction T_E2 (i.e., from the variable resistor element R to the heating element H), which is different from the first direction T_E1. In other words, the heat generated in the heating element H can be absorbed again by the variable resistor element R.

[0082] The direction of thermal motion based on the direction of each of the write current I_RESET and the read current I_R can be affected by the Peltier effect or the Thomson effect of thermoelectric effects. Therefore, the phase change caused by the heat generated by the read current I_R can occur only in the portion M_R2 of the variable resistor element R, thus reducing read interference caused by the heat generation.

[0083] Figure 8A This is a graph showing the logarithmic voltage-current curves of selected elements according to some example embodiments. Figure 8B This is a graph showing the peak current according to each of some example embodiments and comparative examples. Figure 8C It is a graph showing the resistance value distribution of memory cells according to each of some example embodiments and comparative examples.

[0084] Reference Figure 8A When the voltage V applied to the selection element SW CELL As the voltage gradually increases from 0 to the threshold voltage Vth, almost no current I flows through the selected component SW. CELL Flow (①). However, the voltage applied to the selection element SW may exceed the threshold voltage Vth, and the current flowing in the selection element SW may increase rapidly simultaneously, resulting in a current spike (②). Subsequently, the voltage applied to the selection element SW may decrease to the saturation voltage Vs (③), and as the current applied to the memory cell MC decreases, the voltage applied to the selection element SW may remain at the saturation voltage Vs (④). This characteristic of the selection element SW can be called the snapback characteristic.

[0085] Reference Figure 8B In steps ① to ④, a graph of the current Icell applied to the selection element of a memory device according to some example embodiments is shown as a function of time T. The graph of the current Icell applied to the selection element of the memory device according to the comparative example as a function of time T. The spike current applied to the selection element according to the comparative example in step ② may have a level higher than the write current I_RESET (specifically, the reset current) at a certain time. On the other hand, the spike current applied to the selection element according to some example embodiments in step ② may have a level lower than the reset current. Therefore, the memory device according to some example embodiments can solve the problem of memory cells being damaged by spike currents.

[0086] Reference Figure 8C This shows the distribution of the number of units relative to the resistance value. Figure 8C middle, This can represent the distribution of memory devices according to some example embodiments, and This can be represented by the distribution according to the comparative example. In the comparative example, due to the spike current that occurs during the data read operation, the set resistance distribution (SET) can be widened, so a portion of the set resistance distribution (SET) can overlap with a portion of the reset resistance distribution (RESET, RST). On the other hand, in some example embodiments, the level of the spike current that occurs during the data read operation can be improved, so the degradation of the set resistance distribution (SET) caused by the spike current can be reduced.

[0087] Figure 9 This is a circuit diagram illustrating an implementation example of a slice according to some example embodiments.

[0088] Reference Figure 9 Tile 1a may include multiple first word lines WL1_1 to WL1_3, multiple second word lines WL2_1 to WL2_3, and multiple bit lines BL1 to BL4. The first word lines WL1_1 to WL1_3, the multiple second word lines WL2_1 to WL2_3, or combinations thereof may be referred to herein as multiple second signal lines, and the multiple bit lines BL1 to BL4 may be referred to herein as multiple first signal lines. In some example embodiments, Tile 1a may include multiple memory cells (e.g., MC1) arranged between the multiple first word lines WL1_1 to WL1_3 and the multiple bit lines BL1 to BL4, and multiple memory cells (e.g., MC2) arranged between the multiple second word lines WL2_1 to WL2_3 and the multiple bit lines BL1 to BL4. That is, Tile 1a may be implemented by multiple memory cells (e.g., MC1 or MC2) arranged in a three-dimensional (3D) structure. Here, the number of first word lines, the number of second word lines, and the number of bit lines can be modified differently according to some example embodiments.

[0089] The first word lines WL1_1 to WL1_3 may be arranged at specific intervals in the second direction and may extend in the first direction. Bit lines BL1 to BL4 may be arranged at specific intervals in the first direction and may extend in the second direction. Bit lines BL1 to BL4 may be spaced apart from the first word lines WL1_1 to WL1_3 in a third direction. To reiterate, and at least as... Figure 9 As shown, bit lines BL1 to BL4 (e.g., a plurality of first signal lines) may be spaced apart from each other in a first direction and may each extend in a second direction perpendicular to the first direction. First word lines WL1_1 to WL1_3 (e.g., the plurality of second signal lines) may be spaced apart from each other in the second direction and may each extend in the first direction. The first word lines WL1_1 to WL1_3 are further spaced apart from bit lines BL1 to BL4 in a third direction, wherein the third direction is perpendicular to both the first and second directions. Furthermore, the plurality of second signal lines include first word lines WL1_1 to WL1_3 and second word lines WL2_1 to WL2_3; however, it should be understood that the first word lines WL1_1 to WL1_3 and the second word lines WL2_1 to WL2_3 may be spaced apart from each other in a third direction, at least as shown in the diagram. Figure 9 As shown.

[0090] The second word lines WL2_1 to WL2_3 may be arranged at specific intervals in a second direction and may extend in a first direction. The second word lines WL2_1 to WL2_3 may be spaced apart from the bit lines BL1 to BL4 in a third direction.

[0091] In a memory cell, a memory cell (e.g., MC1) comprising one end 901 (e.g., a first end) connected to one of the first word lines WL1_1 to WL1_3 and the other end 902 (e.g., a second end) connected to one of the bit lines BL1 to BL4 can constitute a first layer. In a memory cell, a memory cell (e.g., MC2) comprising one end connected to one of the bit lines BL1 to BL4 and the other end connected to one of the second word lines WL2_1 to WL2_3 can constitute a second layer. Therefore, Tile1a can have a structure in which multiple layers are stacked. In some example embodiments, only two layers are shown, but this is not a limitation. In other embodiments, multiple layers may be arranged with the same connection method.

[0092] In some example embodiments, in a memory cell included in at least one of the first and second layers, the direction of the write current applied to it during a data write operation may differ from the direction of the read current applied to it during a data read operation. For example, in a data write operation performed on the first memory cell MC1, the write current can be applied through the first bit line BL1, and therefore, the write current can flow in the direction of the first bit line BL1, the first memory cell MC1, and the first word line WL1_1. To reiterate, the write circuit 150 ( Figure 1 As shown, a write current can be supplied (“applied”, “output”, etc.) to at least one memory cell (e.g., memory cell MC1), such that the write current flows through said at least one memory cell (e.g., MC1) from the corresponding first signal line (e.g., bit line BL1) to the corresponding second signal line (e.g., word line WL1_1). In some example embodiments, during a data read operation performed on the first memory cell MC1, a read current can be applied through the first word line WL1_1, so the read current can flow in the direction of the first word line WL1_1, the first memory cell MC1, and the first bit line BL1. To reiterate, the read circuit 160 ( Figure 1 As shown, a read current can be supplied (“applied”, “output”, etc.) to at least one memory cell (e.g., memory cell MC1) such that a write current flows through the at least one memory cell (e.g., MC1) from the corresponding second signal line (e.g., word line WL1_1) to the corresponding first signal line (e.g., bit line BL1).

[0093] Figure 10 This is a diagram used to describe the direction of the current applied when a write and read operation is performed, according to some example embodiments. For example, Figure 10 It shows Figure 9 Examples of the first memory unit MC1 and the second memory unit MC2.

[0094] Reference Figure 10 The second memory unit MC2, included in the second layer F2, can be arranged on the first memory unit MC1 included in the first layer F1. The first memory unit MC1 may include a first heating element H1, a first variable resistor element R1, and a first selection element SW1, and the second memory unit MC2 may include a second heating element H2, a second variable resistor element R2, and a second selection element SW2.

[0095] Overall reference Figures 9 to 10It should be understood that the memory cell array 110 may include a first layer F1 and a second layer F2, wherein the first layer F1 includes a plurality of first memory cells MC1, wherein each first memory cell MC1 is connected at one end to a bit line (e.g., BL1) of the plurality of bit lines BL1 to BL4, and at the other end to a first word line (e.g., WL1_1) of the plurality of first word lines WL1_1 to WL1_4, and the second layer includes a plurality of second memory cells MC2, wherein each second memory cell MC2 is connected at one end to a bit line (e.g., BL1) of the plurality of bit lines BL1 to BL4, and at the other end to a second word line (e.g., WL2_1) of the plurality of second word lines WL2_1 to WL2_4.

[0096] In some example embodiments, a first heating element H1 may be stacked on a corresponding first word line WL1_1, a first variable resistor element R1 may be stacked on a first heating element H1, a first selection element SW1 may be stacked on a first variable resistor element R1, and a corresponding first word line (e.g., BL1) may be stacked on a first selection element SW1. In some example embodiments, a second selection element SW2 may be stacked on a corresponding first word line BL1, a second variable resistor element R2 may be stacked on a second selection element SW2, a second heating element H2 may be stacked on a second variable resistor element R2, and a corresponding second word line (e.g., WL2_1) may be stacked on a second heating element H2.

[0097] During a data write operation, a first write current I_RESET1 can be applied to the first memory cell MC1 through the first bit line BL1. Therefore, the first write current I_RESET1 flows from the first bit line BL1 through the first select element SW1, the first variable resistor element R1, and the first heating element H1 to the first word line WL1_1. In some example embodiments, during a data write operation, a second write current I_RESET2 can be applied to the second memory cell MC2 through the first bit line BL1. Therefore, the second write current I_RESET2 flows from the first bit line BL1 through the second select element SW2, the second variable resistor element R2, and the second heating element H2 to the second word line WL2_1.

[0098] For example, the first write current I_RESET1 and the second write current I_RESET2 can be the same current applied when performing the same write operation. As another example, the first write current I_RESET1 and the second write current I_RESET2 can be different currents applied when performing different write operations.

[0099] In a data read operation, a first read current I_R1 can be applied to a first memory cell MC1 through a first word line WL1_1. Therefore, the first read current I_R1 can flow from the first word line WL1_1 through a first heating element H1, a first variable resistor element R1, and a first selection element SW1 to the first bit line BL1. Reiterating, the read circuit 160 can be configured to supply the first read current I_R1 such that the first read current I_R1 flows from the corresponding first word line (e.g., WL1_1) through the corresponding first memory cell (e.g., MC1) to the corresponding bit line (e.g., BL1) to support read operations performed on the plurality of first memory cells MC1. In some example embodiments, in a data read operation, a second read current I_R2 can be applied to a second memory cell MC2 through a second word line WL2_1. Therefore, the second read current I_R2 can flow from the second word line WL2_1 through a second heating element H2, a second variable resistor element R2, and a second selection element SW2 to the first bit line BL1. To reiterate, the read circuit 160 may be configured to supply a second read current I_R2 such that the second read current I_R2 flows from the corresponding second word line (e.g., WL2_1) through the corresponding second memory cell (e.g., MC2) to the corresponding bit line (e.g., BL1) to support read operations performed on the plurality of second memory cells MC2.

[0100] For example, the first read current I_R1 and the second read current I_R2 can be the same current applied when performing the same read operation. As another example, the first read current I_R1 and the second read current I_R2 can be different currents applied when performing different read operations.

[0101] Figure 11 This is a diagram used to illustrate the direction of the current applied when performing write and read operations, according to some example embodiments. (The details regarding...) Figure 11 The shown and Figure 10 The same component description.

[0102] Reference Figure 11 The direction of the first read current I_R1a applied when performing a data read operation on the first memory cell MC1a may be different from the direction of the second read current I_R2a applied when performing a data read operation on the second memory cell MC2a. In other words, the read current applied to the memory cells included in the first layer F1 and the read current applied to the memory cells included in the second layer F2 may be applied in different directions.

[0103] For example, in a data read operation performed on the first memory cell MC1a, a first read current I_R1a can be applied through the first word line WL1_1. Therefore, the first read current I_R1a can flow from the first word line WL1_1 through the first heating element H1, the first variable resistor element R1, and the first selection element SW1 to the first bit line BL1. To reiterate, the read circuit 160 can be configured to supply the first read current I_R1a such that the first read current I_R1a flows from the corresponding first word line (e.g., WL1_1) through the corresponding first memory cell (e.g., MC1) to the corresponding bit line (e.g., BL1) to support read operations performed on the plurality of first memory cells MC1.

[0104] During a data read operation performed on the second memory cell MC2a, a second read current I_R2a can be applied through the first bit line BL1. Therefore, the second read current I_R2a can flow from the first bit line BL1 through the second selection element SW2, the second variable resistor element R2, and the second heating element H2 to the second word line WL2_1. To reiterate, the read circuit 160 can be configured to supply the second read current I_R2a such that it flows from the corresponding bit line (e.g., BL1) through the corresponding second memory cell (e.g., MC2) to the corresponding second word line (e.g., WL2_1) to support read operations performed on the plurality of second memory cells MC2.

[0105] Figure 12 This is a timing diagram of the write current (I_CELL) applied to a memory cell according to some example embodiments. Figure 12 This can be illustrated as an application to a memory cell (e.g., during a data write operation). Figure 4 Timing diagram of the current level of MC.

[0106] Reference Figure 12 Multiple loops LOOP1 and LOOP2 can be executed sequentially, allowing data to be written to the memory cell MC. Loop 1 can be divided into a write cycle PGM1 and a write verification cycle VFY, and loop LOOP2 can be divided into a write cycle PGM2 and a write verification cycle VFY. During write cycles PGM1 and PGM2, write pulses Ipgm1 and Ipgm2 corresponding to loops LOOP1 and LOOP2 can be input via either the word line or the bit line. As the corresponding loops are executed sequentially, the amplitudes of write pulses Ipgm1 and Ipgm2 can increase.

[0107] In the write verification cycle VFY of each of loops LOOP1 and LOOP2, a read operation can be performed to detect whether the write processing based on the write pulses Ipgm1 and Ipgm2 corresponding to loops LOOP1 and LOOP2, respectively, was successful. In some example embodiments, in the write verification cycle VFY, a verification pulse Ivfy can be applied through a line on the word line and bit line that is different from the line on each of the input write pulses Ipgm1 and Ipgm2. For example, write pulses Ipgm1 and Ipgm2 can be applied to the memory cell MC through the bit line, and the verification pulse Ivfy can be applied to the memory cell MC through the word line. In some example embodiments, different verification pulses can be applied in multiple steps in the write verification cycle VFY. In some example embodiments, only two loops are shown. However, this is only for ease of description, and the number of loops is not limited to this.

[0108] Figure 13 This is a block diagram illustrating a computing system 1000 including a memory system according to some example embodiments.

[0109] Reference Figure 13 The computing system 1000 may include a memory system 1100, a processor 1200, RAM 1300, input / output (I / O) devices 1400, and a power supply 1500. Although Figure 13 Although not shown, the computing system 1000 may also include multiple ports for communicating with video cards, sound cards, memory cards, and USB devices, or with other electronic devices. The computing system 1000 may be implemented as a personal computer (PC) or as a portable electronic device, such as a laptop computer, mobile phone, personal digital assistant (PDA), smartphone, or camera.

[0110] Processor 1200 can perform arithmetic operations or tasks. According to some example embodiments, processor 1200 may be a microprocessor, a central processing unit (CPU), etc. Processor 1200 can communicate with RAM 1300, I / O devices 1400, and memory system 1100 via bus 1600 (such as an address bus, control bus, or data bus). According to some example embodiments, processor 1200 may be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0111] The memory system 1100 may include a memory device 1110 and a memory controller 1120. In this case, it can be achieved by utilizing... Figures 1 to 12 The embodiment implements memory system 1100. Therefore, the reliability of data stored in memory system 1100 can be improved.

[0112] RAM 1300 can store data required for the operation of computing system 1000. For example, RAM 1300 can be implemented using dynamic random access memory (DRAM), mobile DRAM, static random access memory (SRAM), PRAM, ferroelectric random access memory (FeRAM), resistive random access memory (ReRAM), and / or magnetic random access memory (MRAM).

[0113] I / O device 1400 may include input devices such as a keyboard, keypad, or mouse, a printer, and output devices such as a display. Power supply 1500 may supply the dynamic voltage required for the operation of computing system 1000.

[0114] While the inventive concept has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the claims.

Claims

1. A resistive memory device, comprising: Multiple first signal lines and multiple second signal lines, wherein each of the multiple second signal lines intersects with each of the multiple first signal lines; A memory cell array comprising a plurality of memory cells, each of the plurality of memory cells being connected at a first end to one of a plurality of first signal lines and at a second end to one of a plurality of second signal lines; A write circuit is configured to supply write current to at least one of the plurality of memory cells via at least one of the plurality of first signal lines, the write current being associated with writing data into the at least one memory cell; A read circuit is configured to supply a read current to at least one of the plurality of memory cells via at least one of the plurality of second signal lines, the read current being associated with reading data stored in the at least one memory cell. The control circuit is configured to generate write control signals for controlling data write operations and read control signals for controlling data read operations. as well as A line decoder circuit is configured to electrically connect the read circuit to at least one of the plurality of second signal lines based on the read control signal. Specifically, during a reset operation, the write circuit outputs a reset current as the write current to the at least one first signal line, and during a set operation, it outputs a set current as the write current to the at least one first signal line. The line decoder circuit includes at least one transistor configured to switch on and off according to control based on the read control signal. The at least one transistor includes a second transistor. The second transistor is connected to the read circuit at one end and to one of the plurality of second signal lines at the other end.

2. The resistive memory device according to claim 1, wherein, The at least one memory unit includes a variable resistance element, a selection element, and a heating element. One end of the selection element is connected to one of the plurality of first signal lines, and the other end of the selection element is connected to the variable resistor element. One end of the variable resistor element is connected to the selection element, and the other end of the variable resistor element is connected to the heating element. One end of the heating element is connected to the variable resistor element, and the other end of the heating element is connected to one of the plurality of second signal lines.

3. The resistive memory device according to claim 2, wherein, The selection element includes a bidirectional threshold switch.

4. The resistive memory device according to claim 1, wherein, The plurality of first signal lines include a plurality of bit lines, and The multiple second signal lines include multiple word lines.

5. The resistive memory device according to claim 1, further comprising: A column decoder circuit is configured to electrically connect the write circuit to at least one of the plurality of first signal lines based on the write control signal.

6. The resistive memory device according to claim 5, wherein, The at least one transistor further includes a first transistor and a third transistor. The first transistor has a suppression voltage connected to one end and is connected to one of the plurality of second signal lines at the other end. The third transistor is connected to ground voltage at one end and to one of the plurality of second signal lines at the other end.

7. The resistive memory device according to claim 6, wherein, The data read operation includes turning on the second transistor and turning off both the first transistor and the third transistor.

8. The resistive memory device according to claim 6, wherein, The data write operation includes turning on the third transistor and turning off both the first transistor and the second transistor.

9. The resistive memory device according to claim 5, wherein, The column decoder circuit includes a fourth transistor, a fifth transistor, and a sixth transistor, each of which is configured to switch on and off according to control based on the write control signal. The fourth transistor is connected at one end to the write circuit, and at the other end to one of the plurality of first signal lines. The fifth transistor is connected to a suppression voltage at one end and to one of the plurality of first signal lines at the other end. The sixth transistor is connected to ground at one end and to one of the plurality of first signal lines at the other end.

10. The resistive memory device according to claim 9, wherein, The data read operation includes turning on the sixth transistor and turning off both the fourth and fifth transistors.

11. The resistive memory device according to claim 9, wherein, The data write operation includes turning on the fourth transistor and turning off both the fifth and sixth transistors.

12. A resistive memory device, comprising: Multiple first signal lines are spaced apart from each other in a first direction, and each of the multiple first signal lines extends in a second direction perpendicular to the first direction; Multiple second signal lines are spaced apart from each other in the second direction, each of the multiple second signal lines extends in the first direction, and the multiple second signal lines are spaced apart from the multiple first signal lines in a third direction, the third direction being perpendicular to both the first direction and the second direction; A memory cell array comprising a plurality of memory cells, each of the plurality of memory cells being connected at a first end to one of the plurality of first signal lines and at a second end to one of the plurality of second signal lines; A write circuit is configured to supply write current to at least one of the plurality of memory cells such that the write current flows from a corresponding first signal line of the plurality of first signal lines through the at least one memory cell to a corresponding second signal line of the plurality of second signal lines, the write current being associated with writing data into the at least one memory cell; as well as A read circuit is configured to supply a read current to the at least one memory cell such that the read current flows from the corresponding second signal line through the at least one memory cell to the corresponding first signal line, the read current being associated with reading data stored in the at least one memory cell; The control circuit is configured to generate write control signals for controlling data write operations and read control signals for controlling data read operations. A column decoder circuit is configured to electrically connect the write circuit to at least one of the plurality of first signal lines based on the write control signal; as well as A line decoder circuit is configured to electrically connect the read circuit to at least one of the plurality of second signal lines based on the read control signal. Specifically, the write circuit outputs the reset current as the write current to the first signal line during a reset operation, and outputs the setting current as the write current to the first signal line during a setting operation. The line decoder circuit includes at least one transistor configured to switch on and off according to control based on the read control signal. The at least one transistor includes a second transistor. The second transistor is connected to the read circuit at one end and to one of the plurality of second signal lines at the other end.

13. The resistive memory device according to claim 12, wherein, The multiple first signal lines include multiple bit lines. The plurality of second signal lines include a plurality of first word lines and a plurality of second word lines, wherein the plurality of first word lines and the plurality of second word lines are spaced apart from each other in the third direction, and The memory cell array further includes: The first layer includes a plurality of first memory cells, each of the plurality of first memory cells being connected at one end to one of the plurality of bit lines and at the other end to one of the plurality of first word lines; and The second layer includes a plurality of second memory cells, each of which is connected at one end to one of the plurality of bit lines and at the other end to one of the plurality of second word lines.

14. The resistive memory device according to claim 13, wherein, The read circuit is configured to supply a first read current such that the first read current flows from the corresponding first word line among the plurality of first word lines through the corresponding first memory cell among the plurality of first memory cells to the corresponding bit line among the plurality of bit lines, thereby supporting read operations performed on the plurality of first memory cells, and The read circuit is configured to supply a second read current such that the second read current flows from the corresponding second word line among the plurality of second word lines through the corresponding second memory cell among the plurality of second memory cells to the corresponding bit line among the plurality of bit lines, thereby supporting read operations performed on the plurality of second memory cells.

15. The resistive memory device according to claim 13, wherein, The read circuit is configured to supply a first read current such that the first read current flows from the corresponding first word line among the plurality of first word lines through the corresponding first memory cell among the plurality of first memory cells to the corresponding bit line among the plurality of bit lines, thereby supporting read operations performed on the plurality of first memory cells, and The read circuit is configured to supply a second read current such that the second read current flows from the corresponding bit line among the plurality of bit lines through the corresponding second memory cell among the plurality of second memory cells to the corresponding second word line among the plurality of second word lines, thereby supporting read operations performed on the plurality of second memory cells.

16. The resistive memory device according to claim 13, wherein, At least one of the plurality of first memory cells includes a first variable resistor element, a first selection element, and a first heating element, and The first heating element is stacked on the corresponding first word line of the plurality of first word lines, the first variable resistor element is stacked on the first heating element, the first selection element is stacked on the first variable resistor element, and the corresponding bit line of the plurality of bit lines is stacked on the first selection element.

17. The resistive memory device according to claim 13, wherein, At least one of the plurality of second memory units includes a second variable resistor element, a second selection element, and a second heating element, and The second selection element is stacked on the corresponding bit line of the plurality of bit lines, the second variable resistor element is stacked on the second selection element, the second heating element is stacked on the second variable resistor element, and the corresponding second word line of the plurality of second word lines is stacked on the second heating element.

18. A resistive memory device, comprising: A memory cell array, comprising memory cells connected between a first signal line and a second signal line; A control circuit is configured to generate a write control signal for controlling a data write operation performed on the memory cell and a read control signal for controlling a data read operation to read data stored in the memory cell. A write circuit, configured to supply write current to support the data write operation; A read circuit, configured to supply read current to support the data read operation; A column decoder circuit is configured to electrically connect the write circuit to the first signal line based on the write control signal; as well as A line decoder circuit is configured to electrically connect the read circuit to the second signal line based on the read control signal. Specifically, during a reset operation, the write circuit outputs a reset current as the write current to the first signal line, and during a set operation, it outputs a set current as the write current to the second signal line. The column decoder circuit includes at least one transistor configured to switch on and off according to control based on the write control signal. The at least one transistor includes a fourth transistor. The fourth transistor is connected to the write circuit at one end and to one of the plurality of first signal lines at the other end.

19. The resistive memory device according to claim 18, wherein, The memory unit includes a selection element, a variable resistance element, and a heating element, and The write circuit is configured to supply the write current such that the write current flows from the selection element through the variable resistor element to the heating element to support the data write operation.

20. The resistive memory device according to claim 19, wherein, The read circuit is configured to supply the read current such that the read current flows from the heating element through the variable resistor element to the selection element to support the data read operation.

21. The resistive memory device according to claim 19, wherein, The variable resistance element comprises a phase change material whose resistance is based on the temperature change of the phase change material.

22. The resistive memory device according to claim 19, wherein, The selection element includes a bidirectional threshold switch, and the bidirectional threshold switch includes a sulfide compound.

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