Semiconductor device with gate isolation layer

Abstract

The present disclosure provides semiconductor devices with gate isolation layers. A semiconductor device includes a substrate having a first region and a second region; first active fins extending in a first direction in the first region; second active fins extending in the first direction in the second region; first field isolation layers located between the first active fins and extending in a second direction; second field isolation layers located between the second active fins and extending in the second direction; gate lines extending in the second direction on the second field isolation layers, the gate lines being linearly arranged with the first field isolation layers; gate isolation layers located between the first field isolation layers and the gate lines; and gate spacers extending in the second direction, the gate spacers being in contact with two sidewalls of each of the first field isolation layers, the gate lines, and the gate isolation layers.

Description

[0001] Cross-references to related applications

[0002] The full text of Korean Patent Application No. 10-2018-0092505, entitled "Semiconductor Device with Gate Isolation Layer", filed with the Korean Intellectual Property Office on August 8, 2018, is incorporated herein by reference. Technical Field

[0003] The device and method according to the example embodiments relate to a semiconductor device including a gate isolation layer and a method for manufacturing the same. Background Technology

[0004] As the integration density of semiconductor devices increases, achieving the transistor performance required by users becomes increasingly difficult. To overcome these technical challenges, various field-effect transistor (FET) structures have been proposed. For example, a high-k dielectric metal gate structure has been proposed to replace the conventional FETs that use silicon oxide and polysilicon as the gate insulating layer and gate electrode materials, respectively. Summary of the Invention

[0005] According to an example embodiment, a semiconductor device is provided, the semiconductor device comprising: a substrate having a first region and a second region; a first active fin extending in a first direction in the first region; a second active fin extending in the first direction in the second region; a first field insulating layer located between the first active fins and configured to extend in a second direction; a second field insulating layer located between the second active fins and configured to extend in a second direction; a gate line configured to extend in a second direction on the second field insulating layer, the gate line being arranged linearly together with the first field insulating layer; a gate isolation layer disposed between the first field insulating layer and the gate line; and a gate spacer configured to extend in a second direction, the gate spacer contacting two sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.

[0006] According to an example embodiment, a semiconductor device is provided, the semiconductor device comprising: active fins extending in a first direction on a substrate; a set of outer gate spacers intersecting with a plurality of active fins and extending in a second direction, the set of outer gate spacers being spaced apart from each other in the first direction; a pair of inner gate spacers extending in the second direction between the set of outer gate spacers; a first field insulating layer located between the set of outer gate spacers in a plan view; a gate line spaced apart from the first field insulating layer in the first direction, the gate line being located between the set of outer gate spacers and the pair of inner gate spacers; and a gate isolation layer located between the set of outer gate spacers and the pair of inner gate spacers, the gate isolation layer being in contact with the first field insulating layer and the gate line.

[0007] According to an example embodiment, there is provided a semiconductor device, comprising: a substrate comprising a first region and a second region; a first active fin extending in a first direction in the first region; a second active fin extending in the first direction in the second region; a diffusion break region in contact with a short axis sidewall of the first active fin; a gate line spaced apart from the diffusion break region in a second direction, the gate line being in contact with a short axis sidewall of the second active fin; a gate isolation layer located between the diffusion break region and the gate line, arranged linearly together with the gate line in the second direction; and an inner gate spacer in contact with a first side surface of the diffusion break region, an inner side surface of the gate isolation layer, and an inner side surface of the gate line. BRIEF DESCRIPTION OF DRAWINGS

[0008] Features will become apparent to those of ordinary skill in the art upon examination of the following details description of example embodiments in conjunction with the accompanying drawings, of which:

[0009] Figures 1A-1F A diagram of a semiconductor device according to an embodiment is shown;

[0010] Figures 2A-2E A diagram of a semiconductor device according to an embodiment is shown;

[0011] Figures 3A-3D A diagram of a semiconductor device according to an embodiment is shown; and

[0012] Figures 4A-10B Stages in a method of manufacturing a semiconductor device according to an embodiment are shown. DETAILED DESCRIPTION

[0013] Hereinafter, a semiconductor device according to an embodiment and a method of manufacturing the same will be described with reference to the accompanying drawings.

[0014] Figure 1A The layout of a local region of a semiconductor device according to an embodiment is shown schematically. Figure 1B A perspective view is shown, showing vertical cross-sections taken along Figure 1A lines A-A’ and B-B’ of Figure 1C A vertical cross-sectional view is shown, taken along Figure 1A lines I-I’ and II-II’ of Figure 1D A vertical cross-sectional view is shown, taken along Figure 1A lines III-III’ and IV-IV’ of Figure 1A In Figure 1B In

[0015] Reference is made to Figures 1A-1DThe semiconductor device 100a can include a substrate 101, active regions AR1 and AR2, active fins F1 and F2, device isolation layers STI and DTI, a first field insulating layer SDB, a second field insulating layer IFR, gate lines GL and GLB, a gate insulating layer IG, a gate spacer 114, source or drain regions 120, and interlayer insulating layers 130 and 135.

[0016] The substrate 101 can include a first region P and a second region N. For example, the first region P can be a P-type metal-oxide-semiconductor (PMOS) region, and the second region N can be an N-type MOS (NMOS) region. The substrate 101 can include a semiconductor material such as silicon and germanium. For example, the substrate 101 can be formed of at least one material selected from silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium phosphide (GaP), gallium arsenide (GaAs), silicon carbide (SiC), silicon-germanium-carbide (SiGeC), indium arsenide (InAs), and indium phosphide (InP). However, the substrate 101 can be a silicon-on-insulator (SOI) substrate.

[0017] The active regions AR1 and AR2 can include a first active region AR1 and a second active region AR2. The first active region AR1 can be in the first region P, and the second active region AR2 can be in the second region N. The active regions AR1 and AR2 can extend in a first direction. The active regions AR1 and AR2 can be spaced apart from each other in a second direction that intersects the first direction. The active regions AR1 and AR2 can protrude in a third direction that intersects the first and second directions, the third direction being perpendicular to (e.g., orthogonal to) a surface of the substrate 101. Top ends of the first and second active regions AR1 and AR2 can be located at a relatively high level LV_AR1. In an embodiment, top ends of a portion of the second active region AR2 can be located at a relatively low level LV_AR2.

[0018] The active fins F1 and F2 can include a first active fin F1 in the first region P and a second active fin F2 in the second region N. The first active fin F1 can be located on the first active region AR1 and the second active fin F2 can be located on the second active region AR2. The active fins F1 and F2 can extend in the first direction. Each of the active fins F1 and F2 can include a long-axis sidewall L extending in the first direction and a short-axis sidewall S extending in the second direction. The long-axis sidewall L is longer than the short-axis sidewall S. The active fins F1 and F2 can be spaced apart from each other in the first direction such that the short-axis sidewall S of the active fin F1 and the short-axis sidewall S of the active fin F2 can face each other. The active fins F1 and F2 can be spaced apart from each other in the second direction such that the long-axis sidewall L of the active fin F1 and the long-axis sidewall L of the active fin F2 can face each other. The active fins F1 and F2 can protrude in the third direction from the active regions AR1 and AR2. Although two active fins F1 and F2 are shown to be located on one of the active regions AR1 and AR2, there can be one or at least three active fins on one of the active regions AR1 and AR2.

[0019] The active regions AR1 and AR2 and the active fins F1 and F2 can be part of the substrate 101 and can include an epitaxial layer grown from the substrate 101. In an embodiment, the active regions AR1 and AR2 and the active fins F1 and F2 can include a semiconductor material. For example, the active regions AR1 and AR2 and the active fins F1 and F2 can include silicon (Si), silicon germanium (SiGe), or the like. The active regions AR1 and AR2 and the active fins F1 and F2 can include the same material as the substrate 101. For example, when the substrate 101 includes Si, the active regions AR1 and AR2 and the active fins F1 and F2 can also include Si. However, the substrate 101 can include a different material than the active regions AR1 and AR2 and the active fins F1 and F2.

[0020] The device isolation layers STI and DTI can include a shallow device isolation layer STI and a deep device isolation layer DTI. The device isolation layers STI and DTI can define the active regions AR1 and AR2 and the active fins F1 and F2. For example, the device isolation layers STI and DTI can cover sidewalls of the active regions AR1 and AR2 on the substrate 101. The device isolation layers STI and DTI can cover lower sidewalls of the active fins F1 and F2 but can not cover upper portions thereof. In an embodiment, the shallow device isolation layer STI can be in the first region P and the second region N and the deep device isolation layer DTI can be in the first region P and the second region N. A bottom surface of the deep device isolation layer DTI can be located at a lower level than a bottom surface of the shallow device isolation layer STI, for example, closer to the substrate 101 along the third direction. The device isolation layers STI and DTI can include any one of an oxide, an oxynitride, a nitride, or the like.

[0021] The first field insulating layer SDB can be in contact with the short sidewall S of the first active fin Fl in the first region P and extend in the second direction. The first field insulating layer SDB can be located on the device isolation layer STI and DTI, and a local region of the first field insulating layer SDB can extend downward, e.g., along the third direction, toward the substrate 101, and the first field insulating layer SDB can be located between the first active fins Fl. The local region of the first field insulating layer SDB can be between the first active regions ARl. That is, the local region of the first field insulating layer SDB can extend downward, e.g., along the third direction, toward the substrate 101, such that a level LV1 of a bottom end of the extended portion of the first field insulating layer SDB can be lower than a level LV F of the top end of the active fins Fl and F2 and higher than a level LV AR1 of the top end of the first active regions ARl. Alternatively, the local region of the first field insulating layer SDB can extend further downward, e.g., along the third direction, toward the substrate 101, such that the level LV1 of the bottom end of the extended portion of the first field insulating layer SDB is lower than the level LV AR1 of the top end of the first active regions ARl. A level of a top surface of the first field insulating layer SDB can be higher than the level LV F of the top end of the active fins Fl and F2 and higher than a level of the top end of the source or drain region 120, i.e., further away from the substrate 101 along the third direction.

[0022] In an embodiment, two first field insulating layers SDB can be adjacent to each other in the first direction (e.g., there is no other component extending in the second direction between them) and can be parallel to each other and extend in the second direction. One source or drain region 120 can be between the two first field insulating layers SDB.

[0023] In an embodiment, the first field insulating layer SDB can include a compressive stress material and / or a tensile stress material. For example, the compressive stress material can be a material capable of applying a compressive stress to an active region, and the tensile stress material can be a material capable of applying a tensile stress to an active region. For example, the first field insulating layer SDB can include silicon nitride.

[0024] The second field insulating layer IFR can contact a short-axis sidewall S of the second active fin F2 in the second region N and extend in the second direction. The second field insulating layer IFR can contact the device isolation layers STI and DTI. A bottom surface of the second field insulating layer IFR can contact a portion of the second active region AR2, a top end of which has a relatively low level LV AR2 (e.g., closer to the substrate 101 along the third direction than a top end of the first active region AR1). A width of the second field insulating layer IFR in the first direction can be greater than a width of the first field insulating layer SDB. In embodiments, a level LV2 of the bottom surface of the second field insulating layer IFR can be different from a level LV1 of the bottom end of the first field insulating layer SDB. A level LV3 of a top surface of the second field insulating layer IFR can be lower than a level LV F of the top ends of the active fins F1 and F2 and higher than top surfaces of the device isolation layers STI and DTI. However, the level LV3 of the top surface of the second field insulating layer IFR can be higher than the level LV F of the top ends of the active fins F1 and F2, or the level LV3 of the top surface of the second field insulating layer IFR can be lower than or equal to the level of the top surfaces of the device isolation layers STI and DTI.

[0025] In embodiments, the second field insulating layer IFR can be formed of the same material as the device isolation layers STI and DTI. While the boundary between the second field insulating layer IFR and the device isolation layers STI and DTI is clearly shown, the second field insulating layer IFR can be integrally formed with the device isolation layers STI and DTI. That is, the second field insulating layer IFR can be a portion of the device isolation layers STI and DTI. In embodiments, the second field insulating layer IFR can include a tensile stress material and / or a compressive stress material. For example, the second field insulating layer IFR can include an oxide, such as tetraethyl orthosilicate (TEOS).

[0026] The gate lines GL can cross the active fins F1 and F2 on the device isolation layers STI and DTI and extend in the second direction. The gate lines GL can be spaced apart from the first field insulating layer SDB in the first direction and parallel to the first field insulating layer SDB. The gate lines GLB can be spaced apart from the first field insulating layer SDB in the second direction and spaced apart from the gate lines GL in the first direction. The widths of the gate lines GL and GLB in the first direction can be substantially equal to the width of the top end of the first field insulating layer SDB in the first direction.

[0027] Either of the gate lines GL and GLB (e.g., GLB) can contact a top surface of the second field insulating layer IFR and cross the second field insulating layer IFR. For example, as shown in FIG. 1A, the gate line GLB can contact the top surface of the second field insulating layer IFR and cross the second field insulating layer IFR. In embodiments, the gate line GLB can be formed of the same material as the second field insulating layer IFR. While the boundary between the gate line GLB and the second field insulating layer IFR is clearly shown, the gate line GLB can be integrally formed with the second field insulating layer IFR. That is, the gate line GLB can be a portion of the second field insulating layer IFR. In embodiments, the gate line GLB can include a tensile stress material and / or a compressive stress material. For example, the gate line GLB can include an oxide, such as tetraethyl orthosilicate (TEOS). Figure 1A 、 Figure 1C and Figure 1DAs shown, the first gate line GLB can cover the first end portion of the second active fin F2 and a portion of the top surface of the second field insulating layer IFR, while the second gate line GLB can cover a second end portion of the second active fin F2 opposite the first end portion across the second field insulating layer IFR and another portion of the top surface of the second field insulating layer IFR. Thus, in the first field insulating layer SDB and the second field insulating layer IFR, a field insulating layer having a width corresponding to the gate lines GL and GLB can be referred to as a “single diffusion break region.” Further, in the first field insulating layer SDB and the second field insulating layer IFR, a field insulating layer having a width in the first direction that is greater than the shortest distance in the first direction between the gate lines GL and GLB can be referred to as a “double diffusion break region.” That is, Figure 1C The first field insulating layer SDB as shown can be a single diffusion break region, and the second field insulating layer IFR can be a double diffusion break region.

[0028] The gate lines GL and GLB can include gate electrodes 115 and 115b, gate insulating layers 116 and 116b, and gate cover layers 117 and 117b, respectively. Each of the gate electrodes 115 and 115b can include at least two stacked layers. In an embodiment, each of the gate electrodes 115 and 115b can include a first gate metal layer and a second gate metal layer. The first gate metal layer can control a work function, and the second gate metal layer can fill spaces in the first gate metal layer. For example, the first gate metal layer can include at least one of titanium nitride (TiN), tungsten nitride (WN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), titanium carbide (TiC), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), combinations thereof, or the like. Additionally, for example, the second gate metal layer can include at least one of tungsten (W), aluminum (Al), cobalt (Co), titanium (Ti), tantalum (Ta), poly-silicon (poly-Si), silicon germanium (SiGe), metal alloys, or the like.

[0029] Gate insulating layers 116 and 116b can be between gate electrodes 115 and 115b and active fins Fl and F2, respectively. Further, gate insulating layers 116 and 116b can be between gate electrodes 115 and 115b and device isolation layers DTI and STI, respectively. In an embodiment, gate insulating layer 116 can extend in the second direction along the profile of active fins Fl and F2 that protrude from device isolation layers DTI and STI. Gate insulating layers 116 and 116b can extend in the third direction along the side surfaces of gate electrodes 115. Gate insulating layers 116 and 116b can include a high-k dielectric material having a higher dielectric constant than silicon oxide. For example, gate insulating layers 116 and 116b can include hafnium oxide (HFO2), zirconium oxide (ZrO2), lanthanum oxide (LAO), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), etc. Gate electrodes 115 and 115b and gate insulating layers 116 and 116b can be formed, for example, utilizing a replacement process (or a gate-last process).

[0030] Gate cover layers 117 and 117b can be on gate electrodes 115 and 115b and gate insulating layers 116 and 116b. For example, gate cover layers 117 and 117b can include at least one of a silicon nitride film and a silicon oxynitride film.

[0031] In an embodiment, gate lines GLB and first field insulating layer SDB can form lines in the second direction, e.g., first field insulating layer SDB can be in the first region P and gate lines GLB can be in the second region N. Gate lines GLB can be spaced apart from first field insulating layer SDB in the second direction, e.g., by gate isolation layer IG. Short-axis sidewalls Sg of gate lines GLB extending in the first direction can face short-axis sidewalls Ss of first field insulating layer SDB. From above (e.g., in plan view) and along the third direction, gate lines GLB can overlap a portion of second field insulating layer IFR.

[0032] In an embodiment, gate electrode 115b and first field insulating layer SDB can form lines in the second direction, e.g., can overlap along the second direction. Gate electrode 115b can be spaced apart from first field insulating layer SDB in the second direction. A first side surface (i.e., a short-axis sidewall) of gate electrode 115b extending in the first direction can face a short-axis sidewall Ss of first field insulating layer SDB.

[0033] The gate insulating layer 116b can cover a bottom surface of the gate electrode 115b, a short-axis side surface of the gate electrode 115b extending in the first direction, and a long-axis side surface of the gate electrode 115b extending in the second direction. The gate insulating layer 116b can be located between the second field insulating layer IFR and the gate electrode 115b, between the second active fin F2 and the gate electrode 115b, and between the device isolation layers STI and DTI and the gate electrode 115b. That is, the gate insulating layer 116b can extend along the contours of the device isolation layers STI and DTI, the second field insulating layer IFR, and the second active fin F2 in the second direction. The gate insulating layer 116b can extend along the side surfaces of the gate electrode 115b in the third direction. In other words, the gate insulating layer 116b can separate the gate electrode 115b from other components next to it.

[0034] The gate isolation layer IG can be located on the device isolation layers STI and DTI between the first field insulating layer SDB and the gate line GLB. A first side surface Sigl of the gate isolation layer IG can be in contact with the short-axis sidewall Ss of the first field insulating layer SDB. A second side surface Sig2 of the gate isolation layer IG can be in contact with the short-axis sidewall Sg of the gate line GLB. That is, the second side surface Sig2 of the gate isolation layer IG can be in contact (e.g., direct contact) with the gate insulating layer 116b and the gate capping layer 117b. The gate isolation layer IG can be in contact with a portion of the gate insulating layer 116b extending in the third direction between the gate electrode 115b and the gate isolation layer IG. In an embodiment, the gate isolation layer IG can be formed of a single insulating material or multiple insulating materials. For example, the gate isolation layer IG can be formed of silicon oxide, silicon nitride, air spacers, combinations thereof, or the like.

[0035] The gate spacers 114 and 114b can be located on the two sidewalls of the gate lines GL and GLB, respectively. That is, the gate spacers 114 and 114b can extend in the second direction and be in contact with the two side surfaces of the gate insulating layers 116 and 116b and the two side surfaces (e.g., two side surfaces spaced apart along the first direction) of the gate capping layers 117 and 117b, respectively. In addition, the gate spacers 114 can extend in the second direction and can also be located on the two sidewalls of the gate isolation layer IG and the two sidewalls of the first field insulating layer SDB.

[0036] In an embodiment, the gate spacer 114 can include a first gate spacer 114a, a second gate spacer 114b, and a third gate spacer 114c. The first gate spacer 114a can be located on two sidewalls of the first field insulating layer SDB. The second gate spacer 114b can be located on two sidewalls of the gate line GLB which can overlap the first field insulating layer SDB along the second direction. The third gate spacer 114c can be located on two sidewalls of the gate insulating layer IG between the first gate spacer 114a and the second gate spacer 114b in the second direction. The first gate spacer 114a can be connected to the third gate spacer 114c, and the second gate spacer 114b can be connected to the third gate spacer 114c, such that the first gate spacer 114a, the second gate spacer 114b, and the third gate spacer 114c can integrally form the gate spacer 114. In an embodiment, the gate spacer 114 can include nitride. A level of a top end of the gate spacer 114 can be equal to a level of a top surface of the gate cover layers 117 and 117b and a level of a top surface of the first field insulating layer SDB. For example, the gate spacer 114 can include at least one of silicon nitride, silicon oxynitride, silicon oxide, silicon oxycarbonitride, a combination thereof, etc.

[0037] The source or drain regions 120 can be located on both sides of the gate lines GL and GLB and the gate spacer 114. The source or drain regions 120 can be in the active fins F1 and F2. That is, the source or drain regions 120 can be formed in partially etched regions of the active fins F1 and F2. Although the source or drain regions 120 are shown as being in contact with each other in the second direction, the source or drain regions 120 can be spaced apart from each other along the second direction. In an embodiment, the source or drain regions 120 can be raised source or drain regions. Accordingly, top ends of the source or drain regions 120 can be located at a higher level than top ends of the active fins F1 and F2. Figure 1B

[0038] In an embodiment, the source or drain regions 120 in the first region P can include a compressive stress material. For example, the compressive stress material can be a material (e.g., SiGe) having a higher lattice constant than a lattice constant of silicon. The compressive stress material can apply a compressive stress to the active fins F1 and F2 (i.e., channel regions) under the gate lines GL and GLB and increase a mobility of a carrier in the channel regions. Meanwhile, the source or drain regions 120 in the second region N can include a same material as the substrate 101 or a tensile stress material. For example, when the substrate 101 includes silicon, the source or drain regions 120 can include silicon or a material (e.g., silicon carbide (SiC) and silicon phosphide (SiP)) having a smaller lattice constant than a lattice constant of silicon. The tensile stress material can apply a tensile stress to the active fins F1 and F2 (i.e., channel regions) under the gate lines GL and GLB and increase a mobility of a carrier in the channel regions.

[0039] ​In an embodiment, the source or drain region 120 can be formed using an epitaxial growth process. A silicide layer can be formed on the source or drain region 120. The silicide layer can be formed along a top surface of the source or drain region 120. The silicide layer can be used to reduce sheet resistance, contact resistance, etc. when the source or drain region 120 is in contact with the first contact CA1. The silicide layer can include a conductive material such as platinum (Pt), nickel (Ni), cobalt (Co), etc. The silicide layer can be a layer formed by silicidizing the source or drain region 120 in contact with the first contact CA1.

[0040] The first interlayer insulating layer 130 can cover the source or drain region 120, the gate lines GL and GLB, the gate spacers 114, the first field insulating layer SDB, and the device isolation layers STI and DTI. The second interlayer insulating layer 135 can cover the first interlayer insulating layer 130. For example, the first and second interlayer insulating layers 130 and 135 can include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, etc.

[0041] The first contact CA1 can pass through (e.g., extend along the third direction) the first interlayer insulating layer 130 to contact the source or drain region 120. The first contact CA1 can electrically connect the source or drain region 120 with the first intermediate connection M1. For example, the first contact CA1 can have an elongated shape extending along the second direction when viewed from above (e.g., in a plan view). The first contact CA1 can include a conductive material. For example, the first contact CA1 can include tungsten (W), aluminum (Al), copper (Cu), etc. The first contact CA1 can include a barrier layer and a conductive layer.

[0042] The first via V1 can extend through the second interlayer insulating layer 135 along the third direction to contact the first contact CA1. The first via V1 can electrically connect the first contact CA1 with the first intermediate connection M1. The first intermediate connection M1 can be located on the second interlayer insulating layer 135. The first intermediate connection M1 can be electrically connected to the first via V1.

[0043] The second contact CA2 can be located on the gate line GL. The second contact CA2 can extend through the first interlayer insulating layer 130 and the gate cover layer 117 along the third direction to contact the gate electrode 115. The second contact can extend along the first direction. The second via V2 can extend through the second interlayer insulating layer 135 along the third direction to contact the second contact CA2. The second via V2 can electrically connect the second contact CA2 with the second intermediate connection M2. The second intermediate connection M2 can be located on the second interlayer insulating layer 135. The second intermediate connection M2 can be electrically connected to the second via V2.

[0044] Figure 1E and Figure 1FA vertical cross-sectional view taken along line IV-IV’ of Figure 1A of FIG. 1A is shown according to an embodiment. Hereinafter, for the sake of brevity, the same description as in Figures 1A-1D will be omitted.

[0045] Referring to Figure 1E , the second field insulating layer IFR can extend along the second direction and be in contact with the gate isolation layer IG, for example, an upper portion of a sidewall of the second field insulating layer IFR can be in contact with a lower portion of the gate isolation layer IG. Although a portion of one side surface of the gate isolation layer IG is shown to be in contact with a portion of the other side surface of the second field insulating layer IFR, the second field insulating layer IFR can also extend in the second direction such that a bottom surface of the gate isolation layer IG can be in contact with an upper surface of the second field insulating layer IFR. A level LV3 of a bottom surface of the gate line GLB can be higher than a level of a bottom surface of the gate isolation layer IG and higher than levels LV_TI of top surfaces of the device isolation layers STI and DTI.

[0046] Referring to Figure 1F , each of the gate electrode 115b and the gate cover layer 117b can be in contact with the gate isolation layer IG. That is, unlike Figure 1D and Figure 1E , the gate insulating layer 116b can be located only under the gate line GLB and can not extend in the third direction between the gate isolation layer IG and the gate electrode 115b.

[0047] Figure 2A A layout of a partial region of a semiconductor device according to an embodiment is shown. Figure 2B is a perspective view showing vertical cross-sections taken along lines A-A’ and B-B’ of Figure 2A . Figure 2C is a vertical cross-sectional view taken along lines I-I’ and II-II’ of Figure 2A . Figure 2D is a vertical cross-sectional view taken along lines III-III’ and IV-IV’ of Figure 2A . Figure 2E is a vertical cross-sectional view taken along line I-I’ of Figure 2A of FIG. 1A according to an embodiment. Hereinafter, for the sake of brevity, the same description as in Figures 1A-1F will be omitted.

[0048] Referring to Figures 2A-2D , the semiconductor device 100b can include a first field insulating layer DB; a plurality of pairs of outer gate spacers 114a, 114b, and 114c; and a plurality of pairs of inner gate spacers 114a’, 114b’, and 114c’.

[0049] The first field insulating layer DB can contact a short-axis sidewall S of the active fin Fl in the first region P and extend in the second direction. In an embodiment, a width of a top surface of the first field insulating layer DB in the second direction can be at least twice a width of a top surface of the first field insulating layer SDB in the second direction. A width of a top surface of the first field insulating layer DB in the first direction can be greater than a shortest distance between the gate lines GL in the first direction. Thus, the first field insulating layer DB can be referred to as a "double diffusion break region". Thus, while the diffusion break regions in both the first region P and the second region N can be double diffusion break regions, they have different structures.

[0050] In an embodiment, the first field insulating layer DB can include a first portion DB1, a second portion DB2, and a third portion DB3. Some portions of the first portion DB1 and some portions of the second portion DB2 can extend downward, e.g., along the third direction, toward the substrate 101, and be located between the first active fin Fl and the device isolation layers STI and DTI. Alternatively, some portions of the first portion DB1 and some portions of the second portion DB2 can further extend downward and be located between the first active fin Fl, the first active region AR1, and the device isolation layers STI and DTI. The third portion DB3 can be located between the first portion DB1 and the second portion DB2, e.g., can extend therebetween along the first direction. The third portion DB3 can be formed by extending an upper portion of the second portion DB2 in a direction toward the second portion DB2 and extending an upper portion of the second portion DB2 in a direction toward the first portion DB1. In an embodiment, a bottom surface of the third portion DB3 can be located at a higher level than a top end of the first active fin Fl. The first active fin Fl, the source or drain region 120, and the first interlayer insulating layer 130 can be located between the first portion DB1 and the second portion DB2 and below the third portion DB3. As an example, the bottom surface of the third portion DB3 can have a convex shape or a U shape.

[0051] In an embodiment, each of the two gate lines GLB can be spaced apart from the first field insulating layer DB in the second direction and in the second region N. The two gate lines GLB can be spaced apart from each other and parallel to each other in the first direction. Short-axis sidewalls Sg of the two gate lines GLB extending in the first direction can face short-axis sidewalls Sd of the first field insulating layer DB. For example, a first one of the two gate lines GLB can extend linearly from the first portion DB1 of the first field insulating layer DB, and a second one of the two gate lines GLB can extend linearly from the second portion DB2 of the first field insulating layer DB.

[0052] The gate isolation layer IG can be disposed on the device isolation layers STI and DTI in the second direction between the first field insulation layer DB and the gate line GLB. The gate isolation layer IG can be located between the first portion DB1 of the first field insulation layer DB and the gate line GLB, can be formed in a line with the first portion DB1, for example, can overlap along the second direction. Further, the gate isolation layer IG can be located in a straight line with the second portion DB2 of the first field insulation layer DB and the gate line GLB, for example, can overlap along the second direction, together with the second portion DB2. One side surface Sig1 of the gate isolation layer IG can be in contact with the first portion DB1, and the other side surface Sig2 of the gate isolation layer IG can be in contact with the gate line GLB.

[0053] The side surface Sig1 of the gate isolation layer IG can be in contact with the first portion DB1 and the second portion DB2 of the first field insulation layer DB. The side surface Sig2 of the gate isolation layer IG can be in contact with the gate insulation layer 116b and the gate cover layer 117b.

[0054] The gate spacers 114 can include a plurality of pairs of outer gate spacers 114a, 114b, and 114c; and a plurality of pairs of inner gate spacers 114a', 114b', and 114c'. The plurality of pairs of outer gate spacers 114a, 114b, and 114c can extend in the second direction over the first region P and the second region N. The plurality of pairs of outer gate spacers 114a, 114b, and 114c can include a first outer gate spacer 114a, a second outer gate spacer 114b, and a third outer gate spacer 114c. The first outer gate spacer 114a can cover two outer sidewalls of the first field insulation layer DB that can extend in the second direction. That is, the first outer gate spacer 114a can cover the outer sidewall of the first portion DB1 and the outer sidewall of the second portion DB2 of the first field insulation layer DB. When viewed from above, for example, in a plan view, the first field insulation layer DB can be located between the first outer gate spacers 114a.

[0055] The second outer gate spacer 114b can cover an outer sidewall of the gate line GLB. The third outer gate spacer 114c can cover an outer sidewall of the gate isolation layer IG. The first outer gate spacer 114a can be connected to the third outer gate spacer 114c, and the second outer gate spacer 114b can be connected to the third outer gate spacer 114c, such that the first outer gate spacer 114a, the second outer gate spacer 114b, and the third outer gate spacer 114c can integrally form the outer gate spacer.

[0056] The plurality of pairs of inner gate spacers 114a', 114b', and 114c' can extend in a second direction over the first region P and the second region N. The plurality of pairs of inner gate spacers 114a', 114b', and 114c' can include a first inner gate spacer 114a', a second inner gate spacer 114b', and a third inner gate spacer 114c'. The first inner gate spacer 114a can cover an inner side surface of the first field insulating layer DB. That is, the first inner gate spacer 114a can cover the inner side surface of the first portion DB1 and the inner side surface of the second portion DB2 of the first field insulating layer DB, and the first portion DB1 can be located between the first outer gate spacer 114a and the first inner gate spacer 114a'. A top end of the first inner gate spacer 114a' can be in contact with a bottom surface of the third portion DB3 of the first field insulating layer DB. The top end of the first inner gate spacer 114a' can be located at a lower level than the top end of the first outer gate spacer 114a.

[0057] The second inner gate spacer 114b' can cover an inner side wall of the gate line GLB, and the gate line GLB can be located between the second outer gate spacer 114b and the second inner gate spacer 114b'. A top end of the second inner gate spacer 114b' can be located at a higher level than the top end of the first inner gate spacer 114a'.

[0058] The third inner gate spacer 114c' can cover an inner side wall of the gate insulating layer IG, and the gate insulating layer IG can be located between the third outer gate spacer 114c and the third inner gate spacer 114c'. A top end of the third inner gate spacer 114c' can be located at the same level as the top ends of the outer gate spacers 114a, 114b, and 114c. The top end of the third inner gate spacer 114c' can be located at the same level as the top end of the second inner gate spacer 114b'. The first inner gate spacer 114a' can be connected to the third inner gate spacer 114c', and the second inner gate spacer 114b' can be connected to the third inner gate spacer 114c', such that the first inner gate spacer 114a', the second inner gate spacer 114b', and the third inner gate spacer 114c' can integrally form an inner gate spacer.

[0059] In an embodiment, one end of the third inner gate spacer 114c' can be in contact with a portion of a side surface of the first field insulating layer DB extending in the second direction. For example, one end of the third inner gate spacer 114c' can be in contact with a portion of one side surface of the third portion DB3 of the first field insulating layer DB.

[0060] Referring to Figure 2Esemiconductor device 100b can include a first field insulation layer DB and a pair of outer gate spacers 114a in the first region P. The first field insulation layer DB can include a first portion DB1, a second portion DB2, and a third portion DB3. In an embodiment, a level LV_DB3 of a highest portion of a bottom surface of the third portion DB3 can be lower than or equal to a level LV_F of a top end of the first active fin F1. Some portions of the first active fin F1 and the source or drain region 120 can be located between the first portion DB1 and the second portion DB2, and below the third portion DB3. As an example, the bottom surface of the third portion DB3 can have a concave or inverted U shape.

[0061] The pair of outer gate spacers 114a can be located on outer sidewalls of the first portion DB1 and the second portion DB2, respectively. Unlike shown in Figure 2C , a pair of inner gate spacers can be located only on inner sidewalls of the gate isolation layer and the gate line, e.g., can not be located on inner sidewalls of the first field insulation layer DB.

[0062] Figure 3A Layouts of partial regions of semiconductor devices according to embodiments are schematically shown. Figure 3B Vertical cross-sectional views along lines I-I’ and II-II’ of Figure 3A are shown. Figure 3C and Figure 3D Vertical cross-sectional views along line I-I’ of Figure 3A according to an embodiment are shown. Hereinafter, for brevity, descriptions identical to those in Figures 1A-2E will be omitted.

[0063] Referring to Figure 3A and Figure 3B , a semiconductor device 100c can include a first field insulation layer DB and a pair of inner gate spacers 114d and 114e. In an embodiment, the first field insulation layer DB can have a relatively large width in the first direction in the first region P. For example, a width of a top surface of the first field insulation layer DB in the first direction can be at least twice a width of the gate line GL. In an embodiment, a bottom surface of the first field insulation layer DB can have a curved shape. For example, a middle portion of the bottom surface of the first field insulation layer DB can have a concave indented shape that is indented upward. Thus, the middle portion of the bottom surface of the first field insulation layer DB can be at a level LV_DB3 that is higher than a level LV1 of a lowermost end of the first field insulation layer DB. The bottom surface of the first field insulation layer DB can be formed by further extending the third portion DB3 of Figure 2E downward.

[0064] The pair of inner gate spacers 114d and 114e can extend in the second direction in the second region N, and some portions of the pair of inner gate spacers 114d and 114e can be located in the first region P. The pair of inner gate spacers 114d and 114e can include a first inner gate spacer 114d and a second inner gate spacer 114e. The first inner gate spacer 114d can be in contact with the inner side surface of the gate line GLB in the second region N. The second inner gate spacer 114e can be in contact with the inner side surface of the gate isolation layer IG in the first region P and the second region N. The first inner gate spacer 114d can be connected to the second inner gate spacer 114e to integrally form a spacer. In an embodiment, one end of the pair of inner gate spacers 114d and 114e can be in contact with the first side surface of the first field insulating layer DB. That is, the first end of the second inner gate spacer 114e can be in contact with one side surface of the first field insulating layer DB.

[0065] Referring to Figure 3C , the bottom surface of the first field insulating layer DB can have a curved shape. For example, the middle portion of the bottom surface of the first field insulating layer DB can have a protruding shape convex downward. Thus, the middle portion of the bottom surface of the first field insulating layer DB can be at a lower level LV_DB3 than the lowermost end of the first field insulating layer DB.

[0066] Referring to Figure 3D , the bottom surface of the first field insulating layer DB can be a curved surface (e.g., a continuous convex surface whose bottom is at the level LV_DB3) or can be a flat surface.

[0067] Figures 4A-10B are diagrams illustrating stages in a method of manufacturing a semiconductor device according to an embodiment. Specifically, Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A and Figure 9A show layouts of partial regions of a semiconductor device according to an embodiment. Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B and Figure 10A show vertical cross-sectional views taken along lines I-I' and II-II'. Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Figure 9C and Figure 10B show vertical cross-sectional views taken along lines III-III' and IV-IV'. In Figures 1A-10BIn the following description, like numbers refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application can be practiced without these specific details. In other instances, well-known structures and functions have not been described in detail in order to avoid obscuring the present application. Figures 1A-3D

[0068] Referring to Figures 4A-4C , the substrate 101 can be partially etched to form active regions AR1 and AR2 and active fins F1 and F2. Along the second direction, the widths of the active regions AR1 and AR2 and the active fins F1 and F2 can gradually decrease, for example, upward along a third direction away from the substrate 101, while the widths of the bottom surfaces of the active fins F1 and F2 can gradually be smaller than the widths of the top surfaces of the active regions AR1 and AR2. An insulating film can be formed on the substrate 101 to cover the active regions AR1 and AR2 and the active fins F1 and F2. The insulating film can then be partially removed to form device isolation layers STI and DTI. In an embodiment, a back-etching process for partially removing the insulating film can be performed to leave the device isolation layers STI and DTI. After the device isolation layers STI and DTI are formed, the active fins F1 and F2 can protrude along the third direction from the top surfaces of the device isolation layers STI and DTI that are to be exposed out. As an example, the device isolation layers STI and DTI can be formed of silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like.

[0069] Then, the device isolation layers STI and DTI, the active fins F1 and F2, and the second active region AR2 can be partially etched in the second region N, thereby forming a lower trench LT. The lower trench LT can be formed by performing an etching process with a mask layer covering the device isolation layers STI and DTI and the first active fin F1 in the first region P and partially exposing the device isolation layers STI and DTI and the second active fin F2 in the second region N. Thus, the lower trench LT is only in the second region N. A second field insulating layer IFR can be formed within the lower trench LT. After the lower trench LT is filled with the second field insulating layer IFR, the mask layer can be removed.

[0070] A dummy gate structure DG can be formed on the active fins F1 and F2 and the device isolation layers STI and DTI, and it can extend over the active fins F1 and F2. A portion of the dummy gate structure DG can also extend over the second field insulating layer IFR in the second region N. For example, the dummy gate structure DG can extend along the second direction to completely cover the second field insulating layer IFR, while the dummy gate structure DG can overlap with a portion of the second field insulating layer IFR and the second active fin F2 along the first direction.

[0071] ​The dummy gate structure DG can include dummy gate lines 111, 112 and 113; and gate spacers 114. The dummy gate lines 111, 112 and 113 can include a dummy gate insulating layer 111, a dummy gate electrode 112 and a dummy gate cover layer 113 stacked in order. The dummy gate insulating layer 111 can include silicon oxide, and can be formed using a method such as a CVD process or an ALD process. The dummy gate electrode 112 can include polysilicon. The dummy gate cover layer 113 can be formed of silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. The gate spacers 114 can be located on both sidewalls of the dummy gate structure DG. That is, the gate spacers 114 can be located on both sidewalls of the dummy gate insulating layer 111, the dummy gate electrode 112 and the dummy gate cover layer 113. The gate spacers 114 can be formed of silicon nitride, silicon oxynitride, a combination thereof or the like.

[0072] Referring to Figures 5A-5C The source or drain regions 120 can be formed on the active fins F1 and F2 on both sides of the dummy gate structure DG. Exposed portions of the active fins F1 and F2 not covered by the dummy gate structure DG can be removed to form recesses. Then, the source or drain regions 120 can be formed in the recesses by an epitaxial growth process.

[0073] Next, a first interlayer insulating layer 130 can be formed to cover the active fins F1 and F2, the device isolation layers STI and DTI, the second field insulating layer IFR and the dummy gate structure DG. For example, a planarization process such as a chemical mechanical polishing (CMP) process, an etch-back process or the like can be performed so that a top surface of the first interlayer insulating layer 130 can be located at the same level as a top surface of the dummy gate structure DG, for example, from the substrate 101 along the third direction. A mask layer 140 can be formed to cover the planarized first interlayer insulating layer 130 and the planarized dummy gate structure DG. A portion of the mask layer 140 can be etched to form an opening region OP1 exposing top surfaces of at least two adjacent dummy gate structures DG, for example, in the middle of an interface of the first region P and the second region N. The opening region OP1 can extend in the first direction. The top surface of the first interlayer insulating layer 130 can also be exposed through the opening region OP1.

[0074] The etching process can be performed using the mask layer 140, the first interlayer insulating layer 130, and the gate spacers 114 as etching masks. The dummy gate insulating layer 111, the dummy gate electrode 112, and the dummy gate cover layer 113, whose top surfaces are exposed through the opening region OP1, can be partially removed due to the etching process. Accordingly, the adjacent dummy gate lines 111, 112, and 113 exposed through the opening region OP1 can be divided into first dummy gate lines 111a, 112a, and 113a; and second dummy gate lines 111b, 112b, and 113b. The gate spacers 114 can be divided into first gate spacers 114a in contact with the first dummy gate lines 111a, 112a, and 113a; second gate spacers 114b in contact with the second dummy gate lines 111b, 112b, and 113b; and third gate spacers 114c exposing inner side surfaces between the first gate spacers 114a and the second gate spacers 114b. In addition, the dummy gate structure DG partially removed due to the etching process can be divided into a first dummy gate structure DGa and a second dummy gate structure DGb. Specifically, the first dummy gate structure DGa extends in the second direction from the opening region OP1 toward the outer edge of the first region P, and the second dummy gate structure DGb extends in the second direction from the opening region OP1 toward the outer edge of the second region N.

[0075] The gate recess regions GR exposing a portion of the top surfaces of the device isolation layers STI and DTI can be formed between the third gate spacers 114c in the first direction, and between the first dummy gate lines 111a, 112a, and 113a and the second dummy gate lines 111b, 112b, and 113b in the second direction. The first side surface of the first dummy gate insulating layer 111a, the first side surface of the first dummy gate electrode 112a, and the first side surface of the first dummy gate cover layer 113a can be exposed through the gate recess regions GR. In addition, the second side surface of the second dummy gate insulating layer 111b, the second side surface of the second dummy gate electrode 112b, and the second side surface of the second dummy gate cover layer 113b can be exposed through the gate recess regions GR. Furthermore, the inner side surface of the third gate spacers 114c can be exposed through the gate recess regions GR.

[0076] Referring to Figures 6A-6CThe mask layer 140 can be removed to expose top surfaces of the dummy gate structures DG, DGa and DGb; and a top surface of the first ILD layer 130. A gate isolation layer IG can be formed to fill the gate recessed regions GR. The formation of the gate isolation layer IG can include depositing an insulating material to a thickness sufficient to fill the gate recessed regions GR, thereby covering the top surface of the first ILD layer 130; and etching back or planarizing the insulating material until the top surface of the first ILD layer 130 is exposed. In an embodiment, the gate isolation layer IG can be formed of silicon oxide, silicon nitride, air spacers, combinations thereof, or the like. The gate isolation layer IG can be in contact with the inner side surfaces of the third gate spacers 114c, the first sidewalls of the first dummy gate lines 111a, 112a and 113a, the second sidewalls of the second dummy gate lines 111b, 112b and 113b, and the top surfaces of the device isolation layers STI and DTI.

[0077] Referring to Figures 7A-7C The dummy gate lines 111, 112 and 113 can be removed to form dummy gate trenches GT. The first dummy gate lines 111a, 112a and 113a can be removed to form first dummy gate trenches GTa, and the second dummy gate lines 111b, 112b and 113b can be removed to form second dummy gate trenches GTb. The inner side surfaces of the first and second gate spacers 114a and 114b, the upper portions of the active fins Fl and F2, a portion of the top surfaces of the device isolation layers STI and DTI, and a portion of the upper portions of the second field insulating layers IFR can be exposed by the dummy gate trenches GTa and GTb. In addition, two side surfaces of the gate isolation layer IG can be exposed by the dummy gate trenches GTa and GTb.

[0078] Referring to Figures 8A-8C Gate lines GL can be formed within the dummy gate trenches GT. The gate electrodes 115, the gate insulating layers 116 and the gate capping layers 117 can fill the dummy gate trenches GT and cover the first ILD layer 130, and then an etch back process and a planarization process can be performed to expose the top surface of the first ILD layer 130, the top surfaces of the gate spacers 114 and 114c, and the top surface of the gate isolation layer IG. Similarly, for example, at the same time, the gate electrodes 115a, the gate insulating layers 116a and the gate capping layers 117a can fill the dummy gate trenches GTa and the gate electrodes 115b, the gate insulating layers 116b and the gate capping layers 117b can fill the dummy gate trenches GTb, and the gate spacers 114a and 114b can be exposed. Thus, first gate lines GLa filling the first dummy gate trenches GTa and second gate lines GLb filling the second dummy gate trenches GTb can be formed with the gate isolation layer IG therebetween, for example, along the second direction.

[0079] Referring to Figures 9A-9CAn etching process can be performed using a mask layer 145, a first gate spacer 114a, and a first interlayer insulating layer 130 as an etching mask to remove the first gate line Gla. The mask layer 145 may cover the first region P and the second region N, and may have an opening region OP2 in the first region P. A portion of the top surface of the first interlayer insulating layer 130, as well as the top surfaces of the first gate line Gla and the first gate spacer 114a, may be exposed through the opening region OP2.

[0080] The first gate electrode 115a, the first gate insulating layer 116a, and the first gate capping layer 117a of the first gate line GLa can be removed to form a gate line trench GLT in the first region P. The upper part of the first active fin F1, some portions of the top surfaces of the device isolation layers STI and DTI, and the first side surface of the gate isolation layer IG can be exposed through the gate line trench GLT.

[0081] Reference Figure 10A and Figure 10B The upper portion of the first active fin F1 exposed through the gate line trench GLT can be etched in the first region P to form a fin recess FR. That is, the fin recess FR can be formed by extending some portions of the gate line trench GLT downwards. The fin recess FR can be connected to the gate line trench GLT to integrally form a space. The device isolation layers STI and DTI in the first region P can be partially etched during the formation of the fin recess FR such that some portions of the top surfaces of the device isolation layers STI and DTI exposed through the gate line trench GLT are at a lower level than the unexposed portions of the top surfaces of the device isolation layers STI and DTI. In an embodiment, during the formation of the fin recess FR, the first interlayer insulating layer 130 and the gate spacer 114a' exposed through the opening region OP2 on their top surfaces can be partially etched through the opening region OP2. Then, as... Figure 2C As shown, the first field insulating layer DB can fill the fin recess FR and the gate line trench GLT.

[0082] Return to reference Figure 10A and Figure 10B The first interlayer insulating layer 130', gate spacer 114a', source or drain region 120, and first active fin F1 can be etched through opening region OP2 to form a wide fin recess and a wide gate line trench. Then, as... Figures 3B-3D As shown, a first field insulating layer DB can be formed to fill the wide fin recess and the wide gate line trench.

[0083] According to example embodiments, semiconductor devices with different diffusion breakage regions (e.g., different structures and / or different types) in the PMOS and NMOS regions can be configured to improve the performance of each of the PMOS and NMOS regions. Furthermore, in the process of manufacturing semiconductor devices with different diffusion breakage regions in the PMOS and NMOS regions, a gate isolation layer can be used to prevent gate line loss in the NMOS region, thereby fundamentally eliminating the cause of transistor performance degradation.

[0084] The example embodiments aim to provide a semiconductor device that improves its performance by providing an optimized diffusion breakage region for each of the P-type metal-oxide-semiconductor (PMOS) region and the N-type MOS (NMOS) region.

[0085] Additionally, the example embodiments aim to provide a method of manufacturing a semiconductor device in which an optimized diffusion break region is provided to each of the PMOS and NMOS regions, thereby addressing problems caused near the gate line and the diffusion break region.

[0086] This document has disclosed exemplary embodiments, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, as should be apparent to one of ordinary skill in the art, unless otherwise stated, features, characteristics, and / or elements described in connection with specific embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, along with the filing of this application. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A semiconductor device comprising: a substrate having a first region and a second region; first active fins extending in a first direction in the first region; second active fins extending in the first direction in the second region; first field insulation layers located between the first active fins and extending in a second direction; second field insulation layers located between the second active fins and extending in the second direction; a gate line extending in the second direction on the second field insulation layers, the gate line overlapping the first field insulation layers along the second direction; a gate isolation layer located between the first field insulation layers and the gate line; and a gate spacer extending in the second direction, the gate spacer in contact with two sidewalls of each of the first field insulation layers, the gate line, and the gate isolation layer. the gate line comprising:

2. The semiconductor device of claim 1, wherein, a gate electrode comprising a metal, and a gate insulation layer extending in the second direction between the gate electrode and the second field insulation layers, and extending in a third direction between the gate electrode and the gate isolation layer. a first side surface of the gate isolation layer is in contact with a portion of the gate insulation layer between the gate electrode and the gate isolation layer.

3. The semiconductor device of claim 2, wherein, a second side surface of the gate isolation layer is in contact with a minor sidewall of the first field insulation layer.

4. The semiconductor device of claim 3, wherein, the gate isolation layer is in contact with the second field insulation layer.

5. The semiconductor device of claim 1, wherein, two first field insulation layers are adjacent to each other to be parallel to each other, and a source or drain region is located between the two first field insulation layers.

6. The semiconductor device of claim 1, wherein, the first field insulation layers comprise a different material than the second field insulation layers.

7. The semiconductor device of claim 1, wherein, the first field insulation layers comprise silicon nitride, and the second field insulation layers comprise an oxide.

8. The semiconductor device of claim 7, wherein, 9. A semiconductor device comprising: active fins extending in a first direction on a substrate; a pair of outer gate spacers crossing a plurality of active fins and extending in a second direction, the pair of outer gate spacers being spaced apart from each other in the first direction; a pair of inner gate spacers extending in the second direction between the pair of outer gate spacers; first field insulation layers located between the pair of outer gate spacers in a plan view, and outer sidewalls of the first field insulation layers being covered by the pair of outer gate spacers; a gate line spaced apart from the first field insulation layers in the first direction, the gate line being located between the pair of outer gate spacers and the pair of inner gate spacers; and a gate isolation layer located between the pair of outer gate spacers and the pair of inner gate spacers, the gate line and the first field insulation layers being spaced apart in the second direction by the gate isolation layer, the gate isolation layer being in contact with the first field insulation layers and the gate line.

10. The semiconductor device of claim 9, further comprising second field insulation layers located between the active fins and under the gate line. the first field insulation layers comprising: a first portion and a second portion located between the plurality of active fins and extending parallel to each other in the second direction, and 11. The semiconductor device of claim 10, wherein, ​ ​ a third portion formed by extending an upper portion of the first portion in a direction toward the second portion and extending an upper portion of the second portion in a direction toward the first portion of the first field insulating layer.

12. The semiconductor device of claim 11, wherein, a bottom surface of the third portion is located at a higher level than a top end of the plurality of active fins.

13. The semiconductor device of claim 11, wherein, a source or drain region is located between the first portion and the second portion and below the third portion.

14. The semiconductor device of claim 11, wherein, the pair of inner gate spacers includes a first inner gate spacer in contact with an inner side surface of the first portion, an inner side surface of the second portion, and a bottom surface of the third portion.

15. The semiconductor device of claim 14, wherein, a top end of the first inner gate spacer is located at a lower level than a top end of the pair of outer gate spacers.

16. The semiconductor device of claim 14, wherein, the pair of inner gate spacers includes a second inner gate spacer in contact with a top surface of the second field insulating layer and an inner side surface of the gate line and a third inner gate spacer in contact with an inner side surface of the gate isolation layer.

17. The semiconductor device of claim 16, wherein, the first inner gate spacer, the second inner gate spacer, and the third inner gate spacer are integrally connected to each other.

18. The semiconductor device of claim 16, wherein, a top end of the first inner gate spacer is located at a lower level than a top end of the second inner gate spacer and a top end of the third inner gate spacer.

19. The semiconductor device of claim 16, wherein, a portion of one side surface of the third portion of the first field insulating layer is in contact with an upper portion of the other end portion of the third inner gate spacer.

20. A semiconductor device, comprising: a substrate including a first region and a second region; a first active fin extending in a first direction in the first region; a second active fin extending in the first direction in the second region; a diffusion break region in contact with a short axis sidewall of the first active fin; a gate line spaced apart from the diffusion break region in a second direction, the gate line in contact with a short axis sidewall of the second active fin; a gate isolation layer located between the diffusion break region and the gate line, overlapping the gate line in the second direction; and an inner gate spacer in contact with one side surface of the diffusion break region, one side surface of the gate isolation layer, and one side surface of the gate line.

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