Storage Components

Abstract

The invention relates to a phase change memory element, comprising a stack of amorphous layers in a first portion, the thickness of each layer in the stack being less than or equal to 5 nm.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from French patent application No. 18 / 57391, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present disclosure relates generally to memory elements, and more particularly to phase change memory elements. Background Art

[0004] Phase change materials are materials that can switch between a crystalline phase and an amorphous phase under the action of heat. Since the resistance of amorphous materials is significantly greater than that of crystalline materials, this phenomenon can be used to define two memory states (e.g., 0 and 1), which are distinguished by the resistance measured through the phase change material.

[0005] The reduction in size of the phase change memory element, and more particularly, the reduction in the thickness of the phase change material layer and the volume of the phase change material may result in an increase in the crystallization temperature and an increase in the thermal stability of the material in the amorphous phase.

[0006] The most common phase change material in memory elements is an alloy composed of germanium, antimony and tellurium. Such alloys are usually in stoichiometric proportions. Alloys with non-stoichiometric proportions may be preferred over alloys with stoichiometric proportions because they may have desirable properties, such as higher crystallization temperatures. However, the manufacture of memory elements including such alloys has various disadvantages. In particular, crystallization and / or phase separation of such alloys may result in a lack of uniformity in the alloy, which may result in reduced efficiency. Summary of the invention

[0007] One embodiment overcomes all or part of the disadvantages of known memory elements.

[0008] One embodiment provides a phase change memory element including a stack of amorphous layers in a first portion, the thickness of each layer in the stack being less than or equal to 5 nm.

[0009] According to one embodiment, the stack comprises a set of at least two layers made of different materials.

[0010] According to one embodiment, the layers in the stack are made of chemical elements or alloys of chemical elements from groups 13, 14, 15 and 16 of the periodic table.

[0011] According to one embodiment, the stack comprises an alternation of first layers and second layers, the first layers and the second layers being made of different materials.

[0012] According to one embodiment, the first layer is made of an alloy based on germanium, antimony and tellurium and the second layer is made of antimony or germanium.

[0013] According to one embodiment, the materials of each layer in the stack have a stoichiometric ratio.

[0014] According to one embodiment, the element comprises a second portion intersecting at least some of the layers in the stack, which is made of an alloy of at least a portion of the components of the layers in the stack.

[0015] According to one embodiment, the proportions of the materials of the second portion are not stoichiometric.

[0016] According to one embodiment, the first portion and the second portion are separated by a skin layer, the skin layer being made of the material of one of the layers in the stack.

[0017] According to one embodiment, the element comprises a resistive element in contact with the second portion.

[0018] According to one embodiment, the material of the second portion is a phase change material.

[0019] According to one embodiment, a layer of the set of stacked layers is doped.

[0020] According to an embodiment, the layers of the set of layers are doped with one or more dopants of nitrogen, carbon and silicon.

[0021] According to one embodiment, the doping of the layers in the set of layers is graded.

[0022] One embodiment provides a phase change memory cell comprising a storage element such as described above.

[0023] One embodiment provides a method of manufacturing a memory element, comprising forming a stack of amorphous layers, each layer having a thickness less than or equal to 5 nm.

[0024] According to one embodiment, the method comprises the step of heating a portion of the stack such that the portion comprises an alloy of at least a portion of the components of the layers in the stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in conjunction with the accompanying drawings.

[0026] Figure 1 is a simplified partial cross-sectional view of one embodiment of a memory element;

[0027] Figure 2 Schematically and partially shows the manufacturing Figure 1 The structure obtained during the storage element;

[0028] Figure 3 shows the resistivity of two phase change materials as a function of temperature; and

[0029] Figure 4 is a simplified partial cross-sectional view of another embodiment of a memory element. DETAILED DESCRIPTION

[0030] In different figures, the same elements have been denoted by the same reference numerals. In particular, structural and / or functional elements common to different embodiments may be denoted by the same reference numerals and may have the same structure, size and material properties.

[0031] For clarity, only those steps and elements useful for understanding the described embodiments are shown and described in detail. In particular, the memory cell includes elements such as selection elements, (eg transistors or electrical connections), which will not be described in detail.

[0032] Throughout this disclosure, the term "connected" is used to indicate a direct electrical connection between circuit elements (with no intermediate elements other than conductors), while the term "coupled" is used to indicate an electrical connection between circuit elements that may be direct or that may be via one or more intermediate elements.

[0033] In the following description, when terms defining absolute positions (such as terms "front", "back", "top", "bottom", "left", "right", etc.) or terms defining relative positions (such as terms "above", "below", "upper", "lower", etc.) are mentioned, or terms defining directions (such as terms "horizontal", "vertical", etc.) are mentioned, unless otherwise specified, they refer to the orientation of the figure.

[0034] The terms "about," "substantially," "approximately," and "approximately" are used herein to indicate a tolerance of plus or minus 10%, preferably plus or minus 5%, of the value in question.

[0035] Figure 1 is a partial simplified cross-sectional view of one embodiment of a memory element 100. The memory element 100 is included in a phase change memory cell, for example.

[0036] The memory element 100 includes a resistor element 102 connected to a selection element (e.g., a transistor, not shown) via a conductive via 104. The resistor element 102 has, for example, an L-shaped cross-section, a horizontal portion of which is in contact with the conductive via 104. The resistor element 102 and the conductive via 104 are surrounded by an insulating layer 106. The thickness of the layer 106 is such that the upper surface of the vertical portion of the resistor element is coplanar with the upper surface of the insulating layer 106. The selection element is located below the layer 106.

[0037] The memory element 100 further includes a region 108 resting on the upper surface of the insulating layer 106 and on the upper surface of the vertical portion of the resistive element 102. A conductive layer 109 rests on the region 108. The conductive layer 109 forms an electrode of the memory element.

[0038] Region 108 includes a first portion 110 and a second portion 112 .

[0039] The first portion 110 comprises a stack of layers, preferably all made of amorphous materials. The layers in the stack are preferably made of chemical elements or alloys of chemical elements from Groups 13, 14, 15 or 16 of the periodic table. Group 13 includes boron, aluminum, gallium, indium and thallium. Group 14 includes carbon, silicon, germanium, tin, lead and flerovium. Group 15 includes phosphorus, arsenic, antimony, bismuth and moscovium. Group 16 includes sulfur, selenium, tellurium, polonium and livermorium.

[0040] Each layer of the stack 110 is made of materials preferably in a stoichiometric ratio. These materials are, for example, materials selected from the following list: Ge 2 Sb 2 Te 5 、GeTe、Ge、Te、Sb、Sb 2 Te 3 、Bi 2 Te 3 、GeSe、GeS 2 .

[0041] For example, the stack 110 alternately includes first layers and second layers, and the first layers and the second layers are made of different materials.

[0042] The first layer is made of, for example, an alloy of germanium, antimony and tellurium (GST), such as Ge 2 Sb 2 Te 5 , and the second layer is made of, for example, antimony or germanium. For example, the second layer is made of a material that is not a phase change material.

[0043] Each layer of the stack 110 has a thickness less than or equal to approximately 5 nm, for example, in the range of an atomic constant of the material of the layer to approximately 5 nm, preferably in the range of 2 nm to 5 nm. Preferably, each layer of the stack 110 has a thickness less than approximately 5 nm, preferably less than 5 nm.

[0044] For example, if the stack includes the same number of layers A and B made of different materials, the thickness of layers A and B is determined in the range discussed previously by solving the following equation:

[0045] [Formula 1]

[0046] T=N×(t A +t B )

[0047] [Formula 2]

[0048]

[0049] [Formula 3]

[0050]

[0051] Where T is the total thickness of the stack 110, t A is the thickness of layer A, t B is the thickness of layer B, N is the number of layers A (equal to the number of layers B), P A is the proportion of the material of layer A in the total stack (expressed in %), P B is the proportion of the material of layer B in the total stack (expressed in %).

[0052] More generally, the stack comprises at least two sets of layers, each set comprising layers made of a material different from the materials of the layers in the other sets.

[0053] The first portion 110 and the second portion 112 may be separated by a skin 114 made of one of the chemical elements of the stack 110. For example, if the stack 110 includes a GST layer and an antimony layer, the skin 114 may be made of antimony.

[0054] As will be described below, the second portion 112 is produced, for example, by fusion of the layers of the stack 110 , and is in contact with the upper surface of the layer 106 and the upper surface of the vertical portion of the resistive element 102 .

[0055] exist Figure 1 In the example of FIG. 1 , the second portion extends, for example, from the upper surface of the insulating layer 106 to the conductive layer 109 . More generally, the second portion intersects at least some layers of the stack 110 .

[0056] The second portion 112 is made of an alloy of at least some of the chemical elements of the layers of the stack 110 and / or an alloy of the chemical elements of the layers of the stack 110. The second portion 112 is made of a phase change material. The second portion 112 is preferably made of a material having a non-stoichiometric ratio. The second portion 112 is, for example, made of an alloy of germanium, antimony and tellurium, which has a germanium or antimony concentration greater than the germanium or antimony concentration of the alloy having a stoichiometric ratio.

[0057] Information written or programmed into the storage element is determined by the amorphous state or the crystalline state of at least a portion of the second portion 112 .

[0058] Figure 2 Schematically and partially shows the manufacturing Figure 1 The two structures a) and b) are obtained after the two steps of the embodiment.

[0059] The structure a) is obtained after the steps comprising:

[0060] - forming a selection element (not shown);

[0061] - forming an insulating layer 106;

[0062] - forming a conductive via 104;

[0063] - forming a resistor element 102;

[0064] - forming a stack 110 on the upper surface of the insulating layer 106 and on the upper surface of the vertical portion of the resistive element 102. The stack 110 may include any number of layers, each layer having a thickness less than or equal to 5 nm, for example, within the range of the atomic constant of the material of the layer to approximately 5 nm; and

[0065] - Forming a conductive layer 109 which covers the upper layers of the stack 110 .

[0066] The layers in the stack are formed one after the other, for example, by physical vapor deposition (PVD).

[0067] Structure b) is obtained by heating the resistive element 102 by means of a current flowing between the conductive via 104 and the conductive layer 109. Then, the temperature of the resistive element 102 becomes sufficient to transition the stack 110 through an initialization step during which the second portion 112 is made of the second alloy from the heated portion of the layers of the stack. At this step, a skin layer 114 may be formed.

[0068] Figure 3 The resistivity (ρ(au)) of two phase change materials according to temperature (T(°C)) is shown.

[0069] Curve 300 corresponds to the resistivity of a solid block (bulk) of an alloy composed of germanium, antimony, and tellurium having an antimony concentration greater than that of the alloy in stoichiometric proportions.

[0070] Curve 302 corresponds to a stack of amorphous layers (such as Figure 1 300 ) includes an alloy layer of germanium, antimony and tellurium and an antimony layer having stoichiometric proportions. The stack includes the same amount of germanium, antimony and tellurium as the bulk associated with curve 300.

[0071] It can be observed that curves 300 and 302 are similar. Therefore, the stack of blocks and layers behaves similarly when the temperature to which they are subjected increases. In particular, it can be observed that the temperature changes significantly and rapidly (at approximately 220° C.) and that the temperature corresponding to the crystallization temperature is similar for the stack of solid blocks and layers.

[0072] More generally, experiments have shown that from a macroscopic point of view, ie considering the entire stack as a single element, a stack of layers has a behavior similar to that of a solid block.

[0073] However, components of the alloy bulk that are not in stoichiometric proportions tend to reconstitute (also known as phase separation) in stoichiometric elements, particularly when they are subjected to the relatively high temperatures of the manufacturing process. This reconstitution results in variability between memory elements that are otherwise substantially identical. The described embodiments that already include layers with stoichiometric proportions are less susceptible to this reconstitution.

[0074] Similar results can be observed for stacks of layers comprising materials belonging to the aforementioned groups 14, 15 and 16.

[0075] For stacks of layers with a thickness greater than 5 nm, such a result cannot be observed. In fact, at the interface between two layers, the chemical elements of the two layers form a connection (possibly an alloy), just like different chemical elements come together in a solid block. The considered thickness of the stack of the described embodiments is such that a sufficient part of each layer is subjected to this phenomenon, so that from a macroscopic point of view, the stack behaves essentially as a solid block.

[0076] Figure 4 is a partially simplified cross-sectional view of another embodiment of a storage element. More specifically, Figure 4 Shown in Figure 2 a) Structures at the same manufacturing stage. Figure 4 The structure includes Figure 2 All components.

[0077] Figure 4 The stack 110 of the embodiment of the invention comprises a layer 120 and a layer 122. The layer 120 (the shadow layer) is doped and the layer 122 is not doped. The doping of the layer 120 is preferably performed layer by layer when forming the stack. This enables precise control of the doping in the stack.

[0078] Layer 120 is doped with, for example, one or more dopants of nitrogen, carbon, and silicon.

[0079] The layer 120 is, for example, a nitrogen-doped germanium layer, and the layer 122 is, for example, an alloy consisting of germanium, antimony and tellurium. In this example, the layers 120 are substantially equally doped.

[0080] As a variant, the stack may include a collection of multiple layers made of different materials, each of which may be doped or undoped. For example, the upper part of the stack 110 may be doped with carbon to reduce the risk of interdiffusion between the material of the layer 109 and the material of the upper layer of the stack 110, and the lower part may be doped with nitrogen to increase the crystallization temperature.

[0081] This layer-by-layer doping has the advantage of allowing interaction of the dopant with some elements of the stack, but not with all elements of the stack, while maintaining a uniform macroscopic appearance of the stack.

[0082] As a variant, the stack may comprise a set of at least one layer with a gradual doping. For example, the doping may increase between a layer of the set that is closest to a lower layer in the stack and a layer of the set that is closest to an upper layer in the stack.

[0083] Such gradual doping has the advantage of allowing, for example, tuning the resistivity of the phase change material along its height.

[0084] The advantages of the described embodiments are that Figure 4 The doping type described cannot be obtained by co-sputtering with standard deposition techniques or by ion implantation.

[0085] An advantage of the described embodiments is that the manufacturing method does not increase the variability between different simultaneously formed storage elements. Thus, storage elements of the same memory device can be in the same state when initialized, which enables an increase in the efficiency of the memory.

[0086] Another advantage of the described embodiment is that the amorphous layer of the first portion 110 forms a thermal insulator. In fact, the chemical element in its amorphous state is a poorer conductor of heat than in its crystalline state. This therefore makes it possible to limit the heat losses outside the second portion when writing such a memory cell, and therefore limit the energy losses.

[0087] Another advantage of the described embodiment is that the amorphous layer of the first portion 110 renders the portion 112 less susceptible to recrystallization phenomena that could cause loss of stored data.

[0088] Another advantage of the described embodiments is that, in case the temperature of the manufacturing process causes phase separation or recrystallization of the layers in the stack, the size of the crystals is more uniform than in the case of a solid block and this therefore enables better control of the crystallization kinetics.

[0089] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and that other variations will occur to those skilled in the art.

[0090] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

[0091] These changes, modifications and improvements are intended to be part of this disclosure and are intended to fall within the spirit and scope of the present invention. Therefore, the foregoing description is only by way of example and is not intended to be limiting. The present invention is only subject to the limitations defined by the following claims and their equivalents.

Claims

1. A phase change memory element (100), comprising a stack (110) of amorphous layers in a first portion (110), the thickness of each layer in the stack being less than or equal to 5 nm, the element comprising a second portion (112) intersecting at least some of the layers in the stack (110), which is made of an alloy of at least a portion of the components of the layers in the stack (110), in, The stack (110) includes alternations of first layers and second layers, the first layers and the second layers being made of different materials; The first layer is made of an alloy consisting of germanium, antimony and tellurium, and the second layer is made of antimony or germanium.

2. The element according to claim 1, wherein The stack (110) comprises a collection of at least two layers made of different materials.

3. The element according to claim 1 or 2, wherein: The layers in the stack (110) are made of chemical elements or alloys of chemical elements from groups 13, 14, 15 and 16 of the periodic table.

4. The element according to claim 1 or 2, wherein The materials of each layer in the stack (110) have a stoichiometric ratio.

5. The element according to claim 1 or 2, wherein: The proportions of materials in the second portion (112) are not stoichiometric.

6. The element according to claim 1 or 2, wherein The first portion (110) and the second portion (112) are separated by a skin layer (114) made of a material of one of the layers in the stack.

7. The element according to claim 1 or 2, comprising a resistive element (102) in contact with the second portion (112).

8. The element according to claim 1 or 2, wherein: The material of the second portion (112) is a phase change material.

9. The element according to claim 1 or 2, wherein: A layer (120) of the set of layers in the stack (110) is doped.

10. The element according to claim 9, wherein A layer (120) in the set of layers is doped with one or more dopants selected from the group consisting of nitrogen, carbon and silicon.

11. The element according to claim 9, wherein The doping of the layers in the set of layers is gradual.

12. The element according to claim 1, wherein The thickness of each layer is greater than 2 nm.

13. A phase change memory cell comprising the storage element (100) according to any one of claims 1 to 12.

14. A method of manufacturing a memory element (100), comprising forming a stack (110) of amorphous layers, each layer having a thickness less than or equal to 5 nm, the element comprising a second portion (112) intersecting at least some of the layers in the stack (110), which is made of an alloy of at least a portion of the components of the layers in the stack (110), in, The stack (110) includes alternations of first layers and second layers, the first layers and the second layers being made of different materials; The first layer is made of an alloy consisting of germanium, antimony and tellurium, and the second layer is made of antimony or germanium.

15. The method of claim 14, comprising the step of heating a portion (112) of the stack such that the portion comprises an alloy of at least a portion of the components of the layers in the stack (110).

16. The method according to claim 14, wherein: The thickness of each layer is greater than 2 nm.

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