Memory devices

Abstract

Embodiments of the present disclosure relate to memory devices. A phase-change memory cell includes, in at least a first portion, a stack of at least one germanium layer, the stack of at least one germanium layer being covered by at least one layer of a first alloy of germanium, antimony, and tellurium. In a programmed state, upon heating a portion of the stack to a sufficient temperature, a portion of the germanium layer and a portion of the layer of the first alloy form a second alloy of germanium, antimony, and tellurium, wherein the second alloy has a higher germanium concentration than the first alloy.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of French patent application No. 1 857390, filed on August 8, 2018, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] The present disclosure relates generally to memory devices and, more particularly, to memory devices including phase change alloys composed of germanium, antimony, and tellurium. Background Art

[0004] Phase-change materials are materials that can switch between a crystalline and an amorphous phase in response to heat. Because the electrical resistance of amorphous materials is significantly greater than that of crystalline materials, this phenomenon can be used to define two memory states (e.g., 0 and 1) distinguished by the resistance measured by the phase-change material. The most common phase-change materials used in memory are alloys composed of germanium, antimony, and tellurium.

[0005] Conventional phase-change memory is typically made from a stoichiometric alloy of germanium, antimony, and tellurium, such as Ge2Sb2Te5. The problem is that these alloys are very temperature sensitive. Specifically, their crystallization temperature is too low to withstand the temperature range of die soldering processes, particularly in the automotive industry. Soldering temperatures can cause programmed data to be altered. Summary of the Invention

[0006] One embodiment overcomes all or some of the disadvantages of known phase change memories.

[0007] In one embodiment, a phase-change memory cell includes, in at least a first portion, a stack of at least one germanium layer covered by at least one layer of a first alloy of germanium, antimony, and tellurium. To program the memory cell, a portion of the stack is brought to a sufficient temperature such that portions of the germanium layer and portions of the first alloy layer form a second alloy composed of germanium, antimony, and tellurium. In the programmed cell, the second alloy has a higher germanium concentration than the first alloy. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above features and advantages and other features and advantages will be further described in the following detailed description of specific embodiments which is given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0009] Figure 1 shows a simplified cross-sectional view of an embodiment of a portion of a phase change memory cell;

[0010] Figure 2A-2B Shown Figure 1 Simplified cross-sectional view of two steps of the manufacture and possible programming of an embodiment of the invention;

[0011] Figure 3A-Figure 3B schematically illustrate cross-sectional views of one embodiment of a memory device before and after programming, respectively;

[0012] Figure 4 schematically illustrates a cross-sectional view of another embodiment of a memory device;

[0013] Figure 5 An embodiment of a read-once memory is schematically shown. DETAILED DESCRIPTION

[0014] In the various drawings, the same features have been denoted by the same reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may be provided with the same structure, dimensions and material properties.

[0015] For the sake of clarity, only the operations and elements that are helpful for understanding the embodiments described herein are described in detail. In particular, the memory cell includes elements that are not described in detail, such as selection elements, such as transistors or electrical connections.

[0016] Throughout this disclosure, the term “connect” is used to designate a direct electrical connection between circuit elements, while the term “coupled” is used to designate an electrical connection between circuit elements that may be direct or may be via one or more intermediate elements.

[0017] In the following description, when referring to terms that define absolute positions (such as terms "front", "back", "up", "down", "left", "right", etc.) or terms that define relative positions (such as terms "above", "below", "higher", "lower", etc.) or terms that define directions (such as terms "horizontal", "vertical", etc.) are mentioned, unless otherwise specified, they refer to the direction of the drawings.

[0018] The terms "approximately," "substantially," and "about" are used herein to designate a tolerance of plus or minus 10% (preferably plus or minus 5%) of the value in question. The term "close" is used herein to designate a tolerance of plus or minus 35%.

[0019] Figure 1 A simplified cross-sectional view of a portion of an embodiment of a phase change memory cell 100 is shown.

[0020] Memory cell 100 includes a resistive element 102 connected to a select element (e.g., a transistor, not shown) via a conductive via 104. For example, resistive element 102 has an L-shaped cross-section, with its horizontal portion in contact with conductive via 104. Resistive element 102 and conductive via 104 are surrounded by an insulating layer 106. The thickness of layer 106 is such that the upper surface of the vertical portion of the resistive element is coplanar with the upper surface of insulating layer 106. The select element is located below layer 106.

[0021] Memory cell 100 further includes a stack of layers 108 located on the upper surface of insulating layer 106 and the upper surface of the vertical portion of resistive element 102. Conductive layer 109 is located on stack 108. Conductive layer 109 forms an electrode of the memory cell.

[0022] The stack 108 comprises a layer 114 made of germanium or nitrogen-doped germanium and a layer 116 made of a first alloy of germanium, antimony and tellurium. The layers of the stack 108 alternate between layers 114 and 116.

[0023] exist Figure 1 In the embodiment of FIG. 1 , stack 108 includes two germanium layers 114 and two layers 116 of the first alloy. In this example, the lower layer of stack 108 is one of layers 116 and is located on one side of layer 106 .

[0024] The first alloy is a stable alloy, i.e., the proportions of the components are close to stoichiometric. For example, the first alloy is Ge2Sb2Te5, Ge4Sb4Te7, or an alloy composed of germanium, antimony, and tellurium with atomic percentages close to Ge2Sb2Te5 or Ge4Sb4Te7. The first alloy of layer 116 is preferably in a crystalline phase. For example, layer 114 is made of undoped germanium or germanium doped with nitrogen atoms. In the case of germanium doped with nitrogen atoms, the nitrogen content is preferably less than 35% by atomic number. For example, the material of layer 114 is in an amorphous phase.

[0025] For example, the thickness of the layers of stack 108 is greater than about 4 nm, such as in the range of 4-30 nm. The thickness of layers 114 and 116 may be different.

[0026] In some embodiments, different layers 116 are made of different alloys of germanium, antimony, and tellurium selected from the examples given above for the first alloy. For example, stack 108 may include a germanium layer 114 positioned between a layer 116 made of Ge2Sb2Te5 and a layer 116 made of Ge4Sb4Te7. However, these different alloys will be referred to as first alloys in the following description.

[0027] More generally, stack 108 includes at least one germanium layer 114 and a layer 116 made of a first alloy, with layer 116 overlying layer 114. Preferably, stack 108 includes layer 114 positioned between two layers 116 made of the first alloy. Stack 108 can include any number of layers greater than two. The number of layers can be even or odd. Furthermore, the lower layer of stack 108 can be either germanium layer 114 or layer 116 made of the first alloy.

[0028] Figure 2A-2B Simplified cross-sectional views of the two steps are shown, illustrating Figure 1 The fabrication and potential programming of embodiments.

[0029] Figure 2A Step a) shown comprises obtaining Figure 1 Manufacturing steps performed in accordance with an embodiment of the present invention.

[0030] Step a) includes: - forming a selection element (not shown); - forming an insulating layer 106; - forming a conductive via 104; - forming a resistor element 102; - forming a stack 108 on the upper surface of the insulating layer 106 and the upper surface of the vertical portion of the resistor element 102. More specifically, a layer 116 made of a first alloy and a germanium layer 114 are alternately formed over the entire surface corresponding to the memory cell. Figure 1 In the embodiment of FIG. 1 , the first layer in contact with the resistive element 102 is a layer 116 made of the first alloy; and forming a conductive layer 109 covering the upper layer of the stack 108 .

[0031] As a variation, refer to Figure 1 As mentioned, the number of layers in the stack 108 can be different and have different layouts. However, the stack 108 includes at least one germanium layer 114 and one layer 116 made of the first alloy.

[0032] After step a), Figure 2B Step b) shown can be considered a manufacturing step or a programming step. Step b) includes an electrical operation called "forming." During this operation, a high current pulse (typically higher than the pulse typically applied to program a memory cell) flows between conductive via 104 and conductive layer 109 and through resistive element 102 and stack 108.

[0033] Resistive element 102 is heated to a temperature, for example, greater than 600° C., preferably greater than 900° C., which is sufficient to melt a portion of the material of layers 114 and 116. This operation forms portion 112 of a homogeneous Ge-rich alloy from the melted portions of layers 114 and 116. Portion 112 is the active area of ​​the phase-change memory. Preferably, the "forming" operation is designed so that portion 112 is in a crystalline phase at the end of the operation.

[0034] Second portion 112 is located on the upper surface of layer 106 and the upper surface of the vertical portion of resistive element 102. Thus, second portion 112 is in contact with resistive element 102. Second portion 112 has a cross-section that is substantially in the shape of a semicircle or a circular portion centered on the contact area between the second portion and resistive element 102.

[0035] Portion 112 is made of a second alloy of germanium, antimony, and tellurium, the germanium concentration of the second alloy being greater than that of the first alloy. Similar to the first alloy, the second alloy is a phase change material, such as previously described. For example, the ratios of the components of the second alloy are non-stoichiometric. For example, the ratio of germanium in the second alloy is between 1.5 and 3.5 times the ratio of germanium in the first alloy.

[0036] The amount of germanium in the second alloy compared to the amount in the first alloy depends on the amount of germanium in the heated portion, ie on the number and thickness of the germanium layers 114 .

[0037] Data written or programmed into the memory cell is determined by the amorphous or crystalline phase of at least a portion of the second portion 112 .

[0038] The inventors have determined that the second alloy has a higher crystallization temperature of the amorphous phase than the first alloy. More specifically, the more germanium the second alloy includes, the higher the crystallization temperature.

[0039] The maximum soldering temperature (of an integrated circuit chip device) in its environment (typically on a printed circuit board) is approximately 150°C, and the maximum temperature reached during bare die soldering is approximately 260°C. Therefore, memory cells with a crystallization temperature greater than 160°C and the ability to withstand temperatures greater than 200°C for several minutes are not at risk of changing their phase due to soldering temperatures. Therefore, programmed phase-change memory devices can now be assembled by soldering without losing the programmed data.

[0040] Another possibility is to deposit a layer of the second alloy directly during the manufacturing process, instead of stacking 108. However, since the second alloy does not correspond to any stable phase of the Ge-Sb-Te ternary phase diagram, the second alloy tends to segregate into a single stable phase during the following steps of the manufacturing process. Indeed, during the manufacturing process, the second alloy will be exposed to heat treatments at relatively high temperatures (e.g., equal to or higher than 380° C.). These temperatures will cause crystallization and segregation of the second alloy. Thus, although the second alloy is an amorphous uniform layer deposited, at the end of the manufacturing process and before the "forming" operation, it will be made up of randomly distributed regions of independent stable phases. For example, they will be regions of Ge and Ge2Sb2Te5, the average size of these regions will depend on the thermal budget of the manufacturing process after deposition of the layer made of the second alloy.

[0041] Afterwards, as referenced Figure 2B As mentioned above, the "form" operation will create something like Figure 2B The active region of portion 112 is shown. However, due to the random distribution of the locations and sizes of the regions, the local composition of the second alloy in the active region can vary from cell to cell. This cell-to-cell variability in the alloy composition in the active region can have a detectable effect on the distribution of cell parameters in the memory array. This effect is more significant for cells with small critical dimensions.

[0042] Reference Figure 1 and Figure 2A-2B An advantage of the described embodiments is that they do not face segregation in the layers made of the second alloy, since the materials of these layers already have a stoichiometric ratio. Consequently, all memory cells manufactured by the same method, with the same number of layers of the same thickness, and exposed simultaneously or separately to the same current pulses during the "forming" operation, are substantially identical. Consequently, such memory cells have substantially identical operation. This remains true even as the size of the memory cells decreases.

[0043] Figure 3A-Figure 3B Cross-sectional views of an embodiment of a memory device 300 are schematically and partially shown before and after programming, respectively.

[0044] Before programming (structure such as Figure 3A ), the memory device 300 only includes the reference Figure 1 The memory cell depicted is similar to cell 301 .

[0045] In the memory unit ( Figure 3B After programming, the memory device 300 includes the same Figure 2B The structure obtained after the described programming method corresponds to the cell 301 and the cell 302. The memory device 300 may include any number of memory cells 302 and any number of memory cells 301 independent of the number of memory cells 302. Figure 3A-Figure 3B In the example of FIG. 3 , only one memory cell 302 and one memory cell 301 are shown after programming.

[0046] Cells 301 and 302 correspond to a first logic state and a second logic state, respectively. For example, cell 301 corresponds to state "0," while cell 302 corresponds to state "1."

[0047] Programming of a memory cell includes a "forming" operation. The memory cell 301 that is desired to store the second logic state receives a current high enough to cause the reference Figure 2BThe "forming" operation is described, and thereby forming cell 302. Typically, an array of memory cells 301 is used, some of which are heated to form cell 302.

[0048] For example, if the temperature of the "forming" operation is chosen to be higher than the soldering temperature used, soldering will not cause any modification of the value programmed in the memory.

[0049] Figure 4 Schematically depicts a cross-sectional view of an embodiment of a memory device 400. Device 400 includes the same elements as device 300, except that device 400 includes an insulating region 402 separating adjacent cell stacks 108 from each other. Region 402 prevents the state of a cell from interfering with the resistance measurement of an adjacent cell.

[0050] The memory devices 300 and 400 described above are one-time programmable (OTP) memory devices. Figures 3A-3B and Figure 4 The "form" operation included in the programming of the embodiment is a one-time operation that irreversibly modifies the structure of memory cell 100, locally destroying the layered structure. This one-time operation is used to pre-program the code in the entire phase-change memory device or a portion thereof at the wafer level before die assembly; this code will be retained after soldering. In addition, cell 302 is a phase-change memory cell, and its phase can be switched between amorphous and crystalline states to program the logic state. If desired, cell 301 can undergo a "form" operation after die assembly and soldering to become cell 302.

[0051] Several types of memory devices can be manufactured using the described embodiments: a) read-only memory devices, where programming is performed during the "formation" operation during the manufacturing process; b) one-time memory devices, where programming (i.e., the "formation" operation) is performed after the packaging operation, for example, by the user; c) phase-change memory devices, where the user can reprogram the cell by changing the phase of the active region; d) memory devices that include a combination of the above devices formed on the same chip by the same manufacturing process and distinguished by electrical operation. For example, a chip including phase-change memory may also include read-only memory cells for memory array repair data, code ROM for the memory controller, manufacturing code, boot memory, etc.

[0052] In the case of a phase change memory device (c), some data can be pre-programmed in the memory using a "forming" operation, as in the case of read-only memory devices and one-time memory devices. The data that needs to be programmed at the wafer level is typically repair data, manufacturing codes, the code ROM of the controller of the phase change memory, and any engineering data that must be stored in the device for historical tracking purposes. This pre-programming will allow the data stored in the memory device to undergo the soldering process. The cells of the phase change memory device (c) used by the user as erasable programmable memory will undergo a "forming" operation at the wafer level during the manufacturing process in order to become reprogrammable phase change memory cells. In short, cells that need to be pre-programmed to logic "0" will not undergo a "forming" operation at the wafer level.

[0053] In the described embodiment, the crystallization temperature of the second alloy need not be as high as it would be if the data were not pre-programmed using a "forming" operation. Thus, the second alloy can advantageously include less germanium than would be the case if the data were not pre-programmed using a "forming" operation. Indeed, it has been found that increasing the proportion of germanium in an alloy of germanium, antimony, and tellurium increases the crystallization temperature, but also increases the phenomenon of "set drift."

[0054] The "set drift" phenomenon is an increase in the resistance of an alloy in the crystalline phase (set state) caused by high temperature. In alloys with stoichiometric proportions of germanium, antimony and tellurium, the "set drift" phenomenon is negligible, but in alloys rich in germanium, such as the second alloy, this phenomenon has a significant effect. In phase change memories, the "set drift" phenomenon is detrimental because it reduces the difference between the resistances of the two phases and can cause errors in reading the memory. A similar phenomenon also exists in the amorphous phase (reset state), but the increase in the resistance of the amorphous phase is not detrimental because it increases the resistance difference between the two states of the cell.

[0055] Therefore, it is advantageous to be able to tolerate bare die soldering while avoiding the "setting drift" phenomenon.

[0056] Figure 5 One embodiment of a memory 500 is schematically shown.

[0057] The memory 500 includes one or more memory devices, such as the previously described devices a), b), c) or d), and Figure 5500 is shown by block 502 (OTP). Block 502 also includes circuitry for addressing the array of memory cells; block 504 (PU) represents a data processing unit, such as a microprocessor; block 506 (MEM) represents one or more memory devices, which may be different from the memory devices in block 502. For example, the memory device in block 506 may not be a phase-change memory device, but rather a RAM, a programmable volatile memory (EEPROM, flash memory, etc.), or a phase-change memory device that cannot be soldered. For example, the memory device in block 506 is added to memory 500 after the soldering step; block 508 (FCT) includes other electronic functions, such as sensors, load control circuits, etc.; and data bus 510 enables data transmission between the various components.

[0058] As a variant, block 506 may be omitted. Then, the memory device of the memory is only a memory device such as memory devices 300 and 400. In this way, the memory is completely a read-only memory.

[0059] Various embodiments and variations have been described. It will be readily apparent to those skilled in the art that the specific features of these various embodiments and variations can be combined, and it will be readily apparent to those skilled in the art that other various embodiments can also be imagined. In particular, although reference is made to Figures 2A-2B The method described relates only to the formation of a memory cell, but it will be appreciated that the method described above is suitable for forming more memory cells simultaneously.

[0060] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

Claims

1. A phase change memory cell, comprising: an insulating layer including a resistive heating element; as well as a stack of a plurality of first layers made of a first alloy of germanium, antimony, and tellurium; wherein each first layer in the stack has a different proportion of germanium, antimony and tellurium, The stack includes a region in contact with the resistive heating element, the region being made of a second alloy of germanium, antimony, and tellurium, wherein the second alloy has a higher germanium concentration than the first alloy.

2. The unit according to claim 1, further comprising: A germanium layer is positioned between two first layers made of the first alloy, and wherein the resistive heating element is coupled to the conductive via. 3 . The cell of claim 2 , wherein the germanium layer has a thickness that is different from a thickness of each of the first layers. The cell of claim 2 , wherein the germanium layer is doped with nitrogen.

5. The cell of claim 2, wherein the plurality of first layers comprises two first layers and further comprises at least two germanium layers, wherein one of the at least two germanium layers is located between the two first layers. 6 . The cell of claim 5 , wherein the germanium layers each have a thickness different from a thickness of each of the first layers.

7. The cell of claim 5, wherein at least one of the at least two germanium layers is doped with nitrogen.

8. The unit of claim 2, further comprising: a germanium layer covered by the stack of the plurality of first layers.

9. The cell of claim 8, wherein the germanium layer has a thickness that is different from a thickness of each of the first layers.

10. The unit of claim 8, further comprising: An additional germanium layer is located between two first layers in the stack of the plurality of first layers.

11. The cell of claim 8, wherein the germanium layer is doped with nitrogen.

12. The cell of claim 1, wherein the first alloy is made of Ge2Sb2Te5.

13. The unit of claim 1, wherein the resistive heating element is in contact with a first layer in the stack of the plurality of first layers.

14. The cell of claim 1, wherein each first layer in the stack has a thickness greater than 4 nm.

15. A memory device comprising: an insulating layer including a first resistive heating element associated with the first phase change memory cell and a second resistive heating element associated with the second phase change memory cell; a stack of a plurality of first layers made of a first alloy of germanium, antimony, and tellurium, the plurality of first layers extending over the first and second resistive heating elements; wherein each first layer in the stack has a different proportion of germanium, antimony, and tellurium; as well as wherein the stack of layers includes a region in contact with the second resistive heating element, the region being made of a second alloy of germanium, antimony, and tellurium, wherein the second alloy has a higher germanium concentration than the germanium concentration of the first alloy.

16. The memory device according to claim 15, further comprising: A germanium layer is positioned between two first layers made of the first alloy, and wherein the second resistive heating element is coupled to the conductive via. 17 . The memory device of claim 16 , wherein the germanium layer has a thickness different from a thickness of each of the first layers. The memory device of claim 16 , wherein the germanium layer is doped with nitrogen.

19. The memory device of claim 15, wherein the first alloy is made of Ge2Sb2Te5.

20. A method of manufacturing a phase change memory cell, comprising: forming an insulating layer including a resistive heating element; Form a stack, including: forming a first layer of a first alloy made of germanium, antimony, and tellurium on the insulating layer over the resistive heating element; forming a second layer of the first alloy over the first layer; wherein the first layer and the second layer of the first alloy have different proportions of germanium, antimony, and tellurium; forming a germanium layer between the first layer and the second layer of the first alloy; and A portion of the stack of layers including the first and second layers and the germanium layer is heated to a temperature sufficient to cause the germanium layer and portions of the first and second layers of the first alloy to form a second alloy made of germanium, antimony, and tellurium, the second alloy having a higher germanium concentration than the germanium concentration of the first alloy.

21. The method of claim 20, wherein heating comprises heating to a temperature greater than 160°C.

22. The method of claim 20, wherein the germanium layer is doped with nitrogen.

23. The method of claim 20, wherein the first alloy is made of Ge2Sb2Te5.

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