Three-dimensional semiconductor devices

Abstract

A three-dimensional semiconductor device comprises: a stacked structure located on a lower structure; a vertical channel structure passing through the stacked structure; and a first vertical support structure passing through the stacked structure and spaced apart from the vertical channel structure. The stacked structure comprises interlayer insulating layers and gate horizontal patterns alternately stacked in a vertical direction perpendicular to the upper surface of the lower structure. The vertical channel structure and the first vertical support structure have different cross-sectional shapes. The vertical channel structure also comprises a channel semiconductor layer. The vertical channel structure comprises a first vertical region, a second vertical region, and a width variation portion located between the first vertical region and the second vertical region. The interlayer insulating layer comprises an intermediate interlayer insulating layer adjacent to the width variation portion. The intermediate interlayer insulating layer has the same thickness as the interlayer insulating layer adjacent to it in the vertical direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2018-0095906 filed on August 17, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device, and in particular, to a three-dimensional semiconductor device including gate level patterns stacked in a vertical direction. Background Art

[0004] In order to improve the price competitiveness of products, there is an increasing demand for increasing the integration of semiconductor devices. In order to increase the integration of semiconductor devices, three-dimensional semiconductor devices have been developed in which gates are stacked in a direction perpendicular to the substrate. However, as the number of stacked gates increases, problems arise. Summary of the invention

[0005] An aspect of the inventive concept is to provide a three-dimensional semiconductor device with improved integration.

[0006] According to an exemplary embodiment, the present disclosure relates to a three-dimensional semiconductor device, comprising: a stacked structure, the stacked structure being located on a lower structure and comprising interlayer insulating layers and gate horizontal patterns alternately stacked in a vertical direction, the vertical direction being perpendicular to an upper surface of the lower structure; a vertical channel structure, the vertical channel structure passing through the stacked structure in the vertical direction and comprising a channel semiconductor layer; and a first vertical support structure, the first vertical support structure passing through the stacked structure in the vertical direction and being spaced apart from the vertical channel structure in a horizontal direction, the horizontal direction being parallel to the upper surface of the lower structure, wherein a cross-sectional shape of the vertical channel structure is different from a cross-sectional shape of the first vertical support structure, wherein the vertical channel structure comprises a first vertical region, a second vertical region, and a width variation portion located between the first vertical region and the second vertical region, wherein the interlayer insulating layer comprises an intermediate interlayer insulating layer adjacent to the width variation portion, and wherein the intermediate interlayer insulating layer and the interlayer insulating layer adjacent to the intermediate interlayer insulating layer in the vertical direction have the same thickness.

[0007] According to an exemplary embodiment, the present disclosure relates to a three-dimensional semiconductor device, comprising: a stacked structure, the stacked structure being arranged on a lower structure and comprising a gate horizontal pattern; a vertical channel structure, the vertical channel structure passing through the stacked structure in a vertical direction, the vertical direction being perpendicular to an upper surface of the lower structure; and a first vertical supporting structure, the first vertical supporting structure passing through the stacked structure and being spaced apart from the vertical channel structure, wherein the gate horizontal pattern is stacked on the lower structure in the vertical direction in a first region and extends from the first region in a horizontal direction, the horizontal direction being parallel to the upper surface of the lower structure, wherein the gate horizontal pattern includes a pad region arranged in a stepped shape in a second region adjacent to the first region, wherein the gate horizontal pattern is provided at a position adjacent to the first region and ... The gate horizontal pattern includes a lower gate horizontal pattern, an upper gate horizontal pattern located on the lower gate horizontal pattern, and an intermediate gate horizontal pattern located between the lower gate horizontal pattern and the upper gate horizontal pattern, wherein the stacked structure also includes alternately stacked interlayer insulating layers, the intermediate gate horizontal pattern is inserted between the interlayer insulating layers, and each of the interlayer insulating layers has a first thickness, wherein the vertical channel structure is arranged in the first region, and the first vertical support structure is arranged in the second region, wherein the vertical channel structure includes a first vertical region, a second vertical region, and a width change portion located between the first vertical region and the second vertical region, and wherein the cross-sectional structure of the first vertical support structure is different from the cross-sectional structure of the vertical channel structure.

[0008] According to an exemplary embodiment, the present disclosure relates to a three-dimensional semiconductor device, comprising: a gate horizontal pattern, which is located on a lower structure, the gate horizontal pattern is stacked in a vertical direction in a memory array region, and extends lengthwise in a horizontal direction from the memory array region to an extension region, wherein the gate horizontal pattern has a pad region arranged in a stepped shape in the extension region; a vertical channel structure, which is arranged in the memory array region and passes through the gate horizontal pattern in the vertical direction; a first vertical support structure, which is arranged in the extension region and passes through the pad region; and a second vertical support structure, which is arranged in the memory array region and passes through the gate horizontal pattern, wherein the vertical channel structure and the second vertical support structure each include a plurality of material layers different from the material layers of the first vertical support structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1A is a schematic block diagram of a semiconductor device according to an exemplary embodiment;

[0011] Figure 1B is a circuit diagram conceptually illustrating a memory array region of a semiconductor device according to an exemplary embodiment;

[0012] Figures 2 to 8A is a view showing an example embodiment of a three-dimensional semiconductor device according to an exemplary embodiment;

[0013] Figure 8B is a cross-sectional view schematically showing a modified embodiment of a three-dimensional semiconductor device according to an exemplary embodiment;

[0014] Figure 8C is a cross-sectional view schematically showing a modified embodiment of a three-dimensional semiconductor device according to an exemplary embodiment;

[0015] Fig. 9A is a top view schematically showing a modified embodiment of a three-dimensional semiconductor device according to an exemplary embodiment;

[0016] Fig. 9B is a top view schematically showing a modified embodiment of a three-dimensional semiconductor device according to an exemplary embodiment;

[0017] Fig. 9C is a top view schematically showing a modified embodiment of a three-dimensional semiconductor device according to an exemplary embodiment;

[0018] Fig.9D is a top view schematically showing a modified embodiment of a three-dimensional semiconductor device according to an exemplary embodiment;

[0019] Fig.9E is a top view schematically showing a modified embodiment of a three-dimensional semiconductor device according to an exemplary embodiment;

[0020] Fig.9F is a top view schematically showing a modified embodiment of a three-dimensional semiconductor device according to an exemplary embodiment;

[0021] Figure 9G is a top view schematically showing a modified embodiment of a three-dimensional semiconductor device according to an exemplary embodiment;

[0022] Fig.10 is a cross-sectional view schematically showing a modified embodiment of a three-dimensional semiconductor device according to an exemplary embodiment;

[0023] Fig.11 is a cross-sectional view schematically showing a modified embodiment of a three-dimensional semiconductor device according to an exemplary embodiment;

[0024] Figures 12 to 15 is a view showing a modified embodiment of a three-dimensional semiconductor device according to an exemplary embodiment;

[0025] Fig.16 is a cross-sectional view schematically showing a modified embodiment of a three-dimensional semiconductor device according to an exemplary embodiment;

[0026] Fig.17 is a cross-sectional view schematically showing a modified embodiment of a three-dimensional semiconductor device according to an exemplary embodiment;

[0027] Fig.18 is a top view schematically showing a modified embodiment of a three-dimensional semiconductor device according to an exemplary embodiment;

[0028] Figures 19 to 21C is a view showing a modified embodiment of a three-dimensional semiconductor device according to an exemplary embodiment;

[0029] Fig. 22 is a cross-sectional view showing a modified embodiment of a three-dimensional semiconductor device according to an exemplary embodiment; and

[0030] FIG. 23A to FIG. 28B is a cross-sectional view illustrating an example embodiment of a method of forming a three-dimensional semiconductor device according to an example embodiment. DETAILED DESCRIPTION

[0031] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0032] Figure 1A is a schematic block diagram of a semiconductor device according to an exemplary embodiment.

[0033] Reference Figure 1A , the semiconductor device 1 according to the embodiment may include a memory array area MA, a row decoder 3, a page buffer 4, a column decoder 5, and a control circuit 6. The memory array area MA may include a memory block BLK. In some embodiments, the semiconductor device 1 may be a semiconductor chip formed on a die obtained from a wafer or the like, or a package formed of one or more semiconductor chips, a package substrate, and a molding layer, and the semiconductor chip may be a memory chip or a memory package.

[0034] The memory array region MA may include memory cells arranged in a plurality of rows and columns. For example, each memory block BLK of the memory array region MA may include memory cells arranged in a plurality of rows and columns. The memory cells included in the memory array region MA may be electrically connected to the row decoder 3 through word lines WL, at least one common source line CSL, a string selection line SSL, at least one ground selection line GSL, etc. In addition, the memory cells included in the memory array region MA may be electrically connected to the page buffer 4 and the column decoder 5 through bit lines BL.

[0035] In one embodiment, among the memory cells, memory cells arranged in the same row may be connected to the same word line WL, and memory cells arranged in the same column may be connected to the same bit line BL.

[0036] The row decoder 3 may be commonly connected to each memory block BLK, and may provide a driving signal to a word line WL of the memory block BLK selected according to a block selection signal. For example, the row decoder 3 may receive address information ADDR from an external source, and may decode the received address information ADDR to determine a voltage to be provided to at least a portion of the word line WL electrically connected to the memory block BLK, the common source line CSL, the string selection line SSL, and the ground selection line GSL.

[0037] The page buffer 4 may be electrically connected to the memory array region MA through the bit line BL. The page buffer 4 may be connected to the bit line BL selected according to the address decoded by the column decoder 5. According to the operation mode, the page buffer 4 may temporarily store data to be stored in the memory cell, or read out data stored in the memory cell. For example, the page buffer 4 may be used as a write driver circuit in the programming operation mode, and may be used as a sense amplifier circuit in the reading operation mode. The page buffer 4 may receive power (e.g., voltage or current) from the control circuit 6, and may provide the power to the selected bit line BL.

[0038] The column decoder 5 may provide a data transmission path between the page buffer 4 and an external device (eg, a memory controller). The column decoder 5 may decode an externally input address to select a bit line BL.

[0039] The column decoder 5 may be commonly connected to the memory blocks BLK, and may provide data information to a bit line BL of a memory block BLK selected according to a block selection signal.

[0040] The control circuit 6 may control the overall operation of the semiconductor device 1. The control circuit 6 may receive a control signal and an external voltage from an external device, and may operate according to the received control signal. The control circuit 6 may include a voltage generator that generates a voltage required for internal operation (e.g., a programming voltage, a reading voltage, an erasing voltage, etc.) using an external voltage. The control circuit 6 may control the read, write, and / or erase operations in response to the control signal.

[0041] Will refer to Figure 1B describe Figure 1A An example embodiment of a circuit of the memory array area MA in the semiconductor device 1 is shown in FIG. Figure 1B It is conceptually shown Figure 1A Circuit diagram of the storage array area MA in .

[0042] Reference Figure 1B , a semiconductor device according to an embodiment may include a common source line CSL, bit lines BL0 to BL2, and a plurality of cell strings CSTR arranged between the common source line CSL and the bit lines BL0 to BL2. A corresponding cell string in the plurality of cell strings CSTR may be connected in parallel to each of the bit lines BL0 to BL2. The plurality of cell strings CSTR may be commonly connected to the common source line CSL. Each cell string in the plurality of cell strings CSTR may include a lower selection transistor GST, a memory cell MCT, and an upper selection transistor SST that may be connected in series.

[0043] The memory cells MCT may be connected in series between a corresponding lower selection transistor GST and a corresponding upper selection transistor SST. Each memory cell MCT may include an information storage area capable of storing information.

[0044] The upper selection transistor SST may be electrically connected to one of the bit lines BL0 to BL2 , and the lower selection transistor GST may be electrically connected to the common source line CSL.

[0045] The upper selection transistors SST may be arranged in plural and may be controlled by string selection lines SSL1 to SSL2 , respectively. For example, in some embodiments, one cell string CSTR may include a plurality of upper selection transistors SST. The memory cells MCT may be controlled by a plurality of word lines WL0 to WLn, respectively.

[0046] The lower selection transistors GST may be controlled by a ground selection line GSL. A common source line CSL may be commonly connected to sources of the lower selection transistors GST.

[0047] In example embodiments, the upper selection transistor SST may be a string selection transistor, and the lower selection transistor GST may be a ground selection transistor.

[0048] Next, we will refer to Figure 2 , Figure 3 , Figure 4 , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A and Figure 7B Example embodiments of three-dimensional semiconductor devices according to embodiments are described. Figures 2 to 7B middle, Figure 2 is a conceptual top view showing a three-dimensional semiconductor device according to an exemplary embodiment; Figure 3 yes Figure 2 An enlarged view of the area indicated by 'A' in FIG. Figure 4 yes Figure 3 An enlarged view of the area indicated by 'B' in FIG. Figure 5A is along Figure 3 A cross-sectional view taken along line Ia-Ia′ in FIG. Figure 5B is along Figure 3 A cross-sectional view taken along line IIa-IIa′; Fig. 6A is along Figure 3 A cross-sectional view taken along line IIIa-IIIa′ in FIG. Figure 6B is along Figure 3 A cross-sectional view taken along line IV-IV′ in FIG. Fig. 7A is along Figure 3 A cross-sectional view taken along line Va-Va′ in FIG. Figure 7B is along Figure 3 A cross-sectional view taken along line VI-VI′.

[0049] Reference Figures 2 to 7B , the stack structure 160 may be disposed on the lower structure 103. The lower structure 103 may be a semiconductor substrate.

[0050] The stacked structure 160 may include gate horizontal patterns 158L, 158M1, 158M2, and 158U. The gate horizontal patterns 158L, 158M1, 158M2, and 158U may be stacked on the lower structure 103 in the vertical direction Z in the first region MA, and may extend lengthwise from the first region MA to the second region EA on the lower structure 103 along the first horizontal direction X. The gate horizontal patterns 158L, 158M1, 158M2, and 158U may include a pad region P arranged in a stepped shape. The pad region P is not limited to the stepped shape shown in the drawings, but may be modified to have various shapes. An item, layer, or portion of an item or layer described as extending "lengthwise" in a particular direction has a length in the particular direction and a width in a direction perpendicular to the particular direction, wherein the length is greater than the width.

[0051] The vertical direction Z may be perpendicular to the upper surface 103 s of the lower structure 103 , and the first horizontal direction X may be parallel to the upper surface 103 s of the lower structure 103 .

[0052] In an embodiment, the first area MA may be Figure 1A Therefore, for the convenience of description, hereinafter, the first area MA will be referred to as the "memory array area MA".

[0053] In an embodiment, the second area EA may be disposed on any side surface or both side surfaces of the memory array area MA in the first horizontal direction X. The second area EA may be an area where the gate horizontal patterns 158L, 158M1, 158M2, and 158U extend from the memory array area MA to form the pad area P. Therefore, the second area EA may also be referred to as an extension area. Hereinafter, the second area EA will be referred to as an "extension area EA."

[0054] The gate horizontal patterns 158L, 158M1, 158M2, and 158U may include a lower gate horizontal pattern 158L, an upper gate horizontal pattern 158U located above the lower gate horizontal pattern 158L, and intermediate gate horizontal patterns 158M1 and 158M2 located between the lower gate horizontal pattern 158L and the upper gate horizontal pattern 158U. The gate horizontal patterns 158L, 158M1, 158M2, and 158U may be arranged in the memory array region MA and may extend from the memory array region MA into the extension region EA. The floating horizontal pattern 158F spaced apart from the memory array region MA and located in the extension region EA may be disposed on a portion of the gate horizontal patterns 158L, 158M1, 158M2, and 158U.

[0055] The pad region P is an area of ​​the horizontal pattern that does not overlap with any horizontal pattern located at a relatively high position (in the third direction Z) among the gate horizontal patterns 158L, 158M1, 158M2, and 158U and the floating horizontal pattern 158F, and the pad region P located at the highest position among the pad regions P may be defined as an area of ​​the upper gate horizontal pattern 158U located in the extension area EA. For example, the pad region P may be those areas of the horizontal pattern on which no horizontal pattern is located in the third direction Z.

[0056] like Figures 3 to 6BAs shown, the step shape in which the pad area P is arranged can be a shape in which the first step, the second step, the third step and the fourth step are arranged in sequence in a direction away from the memory array area MA when viewed in the first horizontal direction X, wherein the first step reduces the first drop, the second step faces the first step and rises the first drop, the third step reduces the second drop greater than the first drop from the second step, and the fourth step reduces the first drop, as shown in FIG. Figure 5A and Figure 5B Alternatively, the pad region P is arranged in a stepped shape, when viewed in the second horizontal direction Y, may include a step that reduces the first drop in the lateral direction based on any one of the separation structures 162m, such as Fig. 6A and Figure 6B For example, refer to Figure 5A and Figure 5B , from left to right in the first horizontal direction X, the shape of the pad region P may include: a series of five steps, wherein each subsequent step is one horizontal pattern lower than the previous step; followed by a series of three steps, wherein each subsequent step is one horizontal pattern higher than the previous step; followed by a series of four steps, wherein each subsequent step is four horizontal patterns lower than the previous step; and followed by a series of three steps, wherein each subsequent step is one horizontal pattern lower than the previous step. According to example embodiments, the pad region P may be arranged not only as Figures 3 to 6B The stepped shape shown in can also be arranged into various stepped shapes.

[0057] The intermediate gate horizontal patterns 158M1 and 158M2 may include a first intermediate gate horizontal pattern 158M1 and a second intermediate gate horizontal pattern 158M2 located above the first intermediate gate horizontal pattern 158M1 .

[0058] In example embodiments, the gate horizontal patterns 158L, 158M1 , 158M2 , and 158U may be gate electrodes.

[0059] In example embodiments, the lower gate horizontal pattern 158L may be Figure 1A and Figure 1B The ground selection line GSL shown in FIG.

[0060] In example embodiments, the upper gate horizontal pattern 158U may be Figure 1A and Figure 1B The string selection line SSL shown in .

[0061] In example embodiments, the upper gate horizontal pattern 158U may be provided in plural, for example, two in number in the vertical direction Z.

[0062] In example embodiments, a portion or all of the intermediate gate horizontal patterns 158M1 and 158M2 may be Figure 1A and Figure 1B . For example, a portion of the intermediate gate horizontal patterns 158M1 and 158M2 may be dummy word lines or dummy gates. In some examples, voltages may be applied to these dummy gates to read data from memory cells of a cell string of which they form a portion. However, the dummy gates may be part of a dummy memory cell that does not operate as an external source for transmitting data to the memory device.

[0063] The stack structure 160 may include a lowermost insulating layer 106 , a lower insulating layer 110 , an interlayer insulating layer 114 , and an upper insulating layer 120 .

[0064] The lowermost insulating layer 106 , the lower insulating layer 110 , the interlayer insulating layer 114 , and the upper insulating layer 120 may be formed of an oxide-based insulating material (eg, silicon oxide).

[0065] The lowermost insulating layer 106 may be disposed between the lower gate horizontal pattern 158L and the lower structure 103. The lower insulating layer 110 may be disposed between the middle gate horizontal patterns 158M1 and 158M2 and the lower gate horizontal pattern 158L. For example, the lower insulating layer 110 may be disposed between the lowermost middle gate horizontal pattern 158M1 and the lower gate horizontal pattern 158L.

[0066] Each interlayer insulating layer 114 may be repeatedly and alternately stacked with the middle gate horizontal patterns 158M1 and 158M2. For example, the interlayer insulating layer 114 may be stacked between the corresponding middle gate horizontal patterns. Therefore, any one interlayer insulating layer 114 may be disposed between a pair of middle gate horizontal patterns adjacent to each other in the vertical direction Z among the middle gate horizontal patterns 158M1 and 158M2. In addition, the interlayer insulating layer 114 may be disposed between the topmost middle gate horizontal pattern 158M2 and the upper gate horizontal pattern 158U. When the upper gate horizontal pattern 158U is provided in plurality, the interlayer insulating layer 114 may be disposed between the corresponding upper gate horizontal patterns 158U adjacent to each other in the vertical direction Z. The upper insulating layer 120 may be disposed on the upper gate horizontal pattern 158U.

[0067] The stack structure 160 may further include an additional dielectric layer 155 that covers the upper and lower surfaces of each of the gate horizontal patterns 158L, 158M1, 158M2, and 158U and can partially extend to cover the side surfaces thereof. The additional dielectric layer 155 may be formed of a high-k dielectric such as aluminum oxide.

[0068] The first cover insulating layer 139 may be disposed on the pad region P of the gate horizontal patterns 158L, 158M1, 158M2, and 158U. The upper surface of the first cover insulating layer 139 may be formed to be coplanar with the upper surface of the upper insulating layer 120. For example, the upper insulating layer 120 may be disposed in the memory array region MA, and the first cover insulating layer 139 may be disposed in a region different from the memory array region MA, that is, in the extension region EA. The stacked structure 160 in the memory array region MA may be covered by the upper insulating layer 120, and the stacked structure 160 in the extension region EA may be covered by the first cover insulating layer 139. The boundary between the upper insulating layer 120 and the first cover insulating layer 139 may be substantially vertical and may be located near the boundary between the memory array region MA and the extension region EA.

[0069] A second cover insulating layer 142 may be provided covering the upper insulating layer 120 and the first cover insulating layer 139. A third cover insulating layer 148 may be disposed on the second cover insulating layer 142, and a fourth cover insulating layer 172 may be disposed on the third cover insulating layer 148. The first cover insulating layer 139, the second cover insulating layer 142, the third cover insulating layer 148, and the fourth cover insulating layer 172 may be formed of an oxide-based insulating material (e.g., silicon oxide).

[0070] The separation structure 162 may be disposed on the lower structure 103. The separation structure 162 may extend from the lower structure 103 in the vertical direction Z to pass through the stacked structure 160, and may have a linear shape extending lengthwise in the first horizontal direction X. Upper surfaces of the separation structures 162 may be formed to be coplanar with each other. In some embodiments, the upper surface of the separation structure 162 may be coplanar with the upper surface of the third capping insulating layer 148.

[0071] The partition structure 162 may include a main partition structure 162m and auxiliary partition structures 162s1 and 162s2. Figure 1A Each memory block BLK shown in FIG. 1 may be disposed between main partition structures 162m adjacent to each other along the second horizontal direction Y. For example, the main partition structure 162m may provide physical separation between the respective memory blocks BLK. The main partition structure 162m may pass through the memory array area MA and the extension area EA in the first horizontal direction X.

[0072] The auxiliary partition structures 162s1 and 162s2 may be disposed between the main partition structures 162m. Each of the auxiliary partition structures 162s1 and 162s2 may have a shorter length than any of the main partition structures 162m. The auxiliary partition structures 162s1 and 162s2 may include a first auxiliary partition structure 162s1 and a second auxiliary partition structure 162s2.

[0073] The first auxiliary partition structure 162s1 may pass through the storage array area MA in the first horizontal direction X and may extend into a portion of the extension area EA. The second auxiliary partition structure 162s2 may be spaced apart from the storage array area MA in the first horizontal direction X and may be disposed in the extension area EA. The end of each of a portion of the second auxiliary partition structures 162s2 may face the end of the corresponding first auxiliary partition structure 162s1. For example, the first auxiliary partition structure 162s1 may be aligned with the corresponding second auxiliary partition structure 162s2 in the first horizontal direction X. The number of second auxiliary partition structures 162s2 disposed between pairs of main partition structures 162m adjacent to each other along the second horizontal direction Y may be greater than the number of first auxiliary partition structures 162s1 disposed between the pairs of main partition structures 162m adjacent to each other along the second horizontal direction Y. Therefore, the main partition structure 162m and the first auxiliary partition structure 162s1 may include a portion disposed in the storage array area MA and may pass through the storage array area MA in the first horizontal direction X.

[0074] The main partition structure 162m may extend from the lower structure 103 in the memory array region MA along the vertical direction Z to pass through the stacked structure 160, the second cover insulating layer 142, and the third cover insulating layer 148, and may extend from the lower structure 103 in the extension region EA along the vertical direction Z to pass through the stacked structure 160, the first cover insulating layer 139, the second cover insulating layer 142, and the third cover insulating layer 148. The main partition structure 162m may pass through the memory array region MA and the extension region EA in the first horizontal direction X, and may partition the stacked structure 160 in the second horizontal direction Y. The second horizontal direction Y may be parallel to the upper surface 103s of the lower structure 103, and may be perpendicular to the first horizontal direction X. Figure 1A Each memory block BLK shown in FIG. 1 may be disposed between the main separation structures 162 m adjacent to each other. For example, one memory block BLK may be disposed between the adjacent main separation structures 162 m.

[0075] The first auxiliary separation structure 162s1 may extend from the lower structure 103 along the vertical direction Z in the memory array region MA to pass through the stack structure 160, the second cover insulating layer 142, and the third cover insulating layer 148, and may extend from the lower structure 103 along the vertical direction Z in a portion of the extension region EA adjacent to the memory array region MA to pass through the stack structure 160, the first cover insulating layer 139, the second cover insulating layer 142, and the third cover insulating layer 148. The second auxiliary separation structure 162s2 may extend from the lower structure 103 along the vertical direction Z in a portion of the extension region EA spaced apart from the memory array region MA to pass through the stack structure 160, the first cover insulating layer 139, the second cover insulating layer 142, and the third cover insulating layer 148.

[0076] Each separation structure 162 may include a first separation layer 165 and a second separation layer 168. The first separation layer 165 may be disposed on a side surface of the second separation layer 168. A top surface of the first separation layer 165 and a top surface of the second separation layer 168 may be coplanar with each other, and a lower surface of the first separation layer 165 and a lower surface of the second separation layer 168 may be coplanar with each other.

[0077] In example embodiments, the second spacer layer 168 may be formed of a conductive material (e.g., a metal nitride such as TiN or a metal such as W), and the first spacer layer 165 may be formed of an insulating material such as silicon oxide. Embodiments are not limited thereto. For example, the spacer structure 162 including the first spacer layer 165 and the second spacer layer 168 may be formed of an insulating material.

[0078] In the stacked structure 160, the separation insulating pattern 123 may be disposed to pass through the upper gate horizontal pattern 158U in the vertical direction Z, and to extend lengthwise in the first horizontal direction X to separate the upper gate horizontal pattern 158U in the second horizontal direction Y. The separation insulating pattern 123 may be disposed on the middle gate horizontal patterns 158M1 and 158M2. For example, the separation insulating pattern 123 may be formed on the uppermost middle gate horizontal pattern of the middle gate horizontal patterns 158M1 and 158M2, and under the second capping insulating layer 142. The separation insulating pattern 123 may be formed to extend from the uppermost middle gate horizontal pattern of the middle gate horizontal patterns 158M1 and 158M2 through the upper gate horizontal pattern 158U, the interlayer insulating layer 114, and the upper insulating layer 120. The upper surface of the separation insulating pattern 123 may be coplanar with the upper surface of the upper insulating layer 120. The separation insulating pattern 123 may be formed of silicon oxide.

[0079] A vertical channel structure 124 c that may lengthwise extend in the vertical direction Z may be disposed on the lower structure 103 . The vertical channel structure 124 c may be disposed in the memory array area MA. The vertical channel structure 124 c may be spaced apart from the separation structure 162 and the separation insulating pattern 123 .

[0080] Vertical support structures 145 and 124d, which may lengthwise extend in a vertical direction Z, may be disposed on the lower structure 103. The vertical support structures 145 and 124d may include a first vertical support structure 145 and a second vertical support structure 124d.

[0081] In example embodiments, the first vertical support structure 145 may be disposed in the extension area EA.

[0082] In example embodiments, the first vertical support structure 145 may pass through the stacked structure 160 in the extension area EA, and may pass through the first cover insulating layer 139 and the second cover insulating layer 142. When viewed in a top view, the first vertical support structure 145 may extend lengthwise in the second horizontal direction Y. When viewed in a cross section, the first vertical support structure 145 may extend from the lower structure 103 to the second cover insulating layer 142, and may have a top surface coplanar with a top surface of the second cover insulating layer 142.

[0083] In example embodiments, the second vertical support structure 124d may be disposed in the memory array region MA. The second vertical support structure 124d may extend from the lower structure 103 to pass through the stack structure 160. The second vertical support structure 124d may pass through the separation insulating pattern 123. The second vertical support structure 124d may contact the separation insulating pattern 123. The term "contact" as used herein refers to direct connection (i.e., touching), unless the context indicates otherwise.

[0084] The upper surface of the second vertical support structure 124d and the upper surface of the vertical channel structure 124c can be formed to be coplanar with each other. The second vertical support structure 124d and the vertical channel structure 124c can have the same cross-sectional structure and the same width as each other. For example, when viewed in a top view, the diameter of the second vertical support structure 124d can be the same as the diameter of the vertical channel structure 124c. For example, the second vertical support structure 124d and the vertical channel structure 124c can be formed by a material layer having the same cross-sectional structure.

[0085] In example embodiments, an upper surface of the first vertical support structure 145 may be located at a higher vertical height than upper surfaces of the second vertical support structure 124 d and the vertical channel structure 124 c .

[0086] The additional dielectric layer 155 may cover the upper and lower surfaces of each of the gate horizontal patterns 158L, 158M1, 158M2, and 158U, and may extend to the side surfaces of the gate horizontal patterns 158L, 158M1, 158M2, and 158U facing the first vertical support structure 145, the second vertical support structure 124d, and the vertical channel structure 124c.

[0087] The first contact plug 178 may be disposed on the pad region P. The first contact plug 178 may pass through the first cover insulating layer 139, the second cover insulating layer 142, the third cover insulating layer 148, and the fourth cover insulating layer 172, and may contact the pad region P of the gate horizontal patterns 158L, 158M1, 158M2, and 158U. The first contact plug 178 may be formed of a conductive material. The second contact plug 175 in contact with the vertical channel structure 124c may be disposed on the vertical channel structure 124c. For example, the lower surface of the second contact plug 175 may contact the upper surface of the vertical channel structure 124c. The second contact plug 175 may be formed of a conductive material. The first contact plug 178 may also be referred to as a "gate contact plug", and the second contact plug 175 may also be referred to as a "bit line contact plug".

[0088] In example embodiments, the second vertical support structure 124d and the vertical channel structure 124c may be formed of material layers having the same cross-sectional structure as each other, and the first vertical support structure 145 may be formed of a material layer having a different cross-sectional structure from the vertical channel structure 124c. Fig. 8A The first vertical support structure 145 and the vertical channel structure 124c are described as having structures different from each other. Fig. 8A 1 is a cross-sectional view schematically showing one vertical channel structure 124c and one first vertical support structure 145, for explaining the first vertical support structure 145 and the vertical channel structure 124c having different structures from each other. Therefore, hereinafter, the one vertical channel structure 124c and the one first vertical support structure 145 will be mainly described.

[0089] Reference Fig. 8A and Figures 2 to 7B The vertical channel structure 124 c may include a channel semiconductor layer 130 and a gate dielectric structure 128 disposed between the channel semiconductor layer 130 and the stack structure 160 .

[0090] In example embodiments, the vertical channel structure 124 c may further include a semiconductor pattern 126 , a vertical core pattern 132 on the semiconductor pattern 126 , and a pad pattern 134 on the vertical core pattern 132 .

[0091] The channel semiconductor layer 130 may be arranged to contact the semiconductor pattern 126 and surround the outer side surface of the vertical core pattern 132. The gate dielectric structure 128 may be arranged to surround the outer side surface of the channel semiconductor layer 130. The semiconductor pattern 126 may be an epitaxial material layer that may be formed in a SEG (selective epitaxial growth) process. The vertical core pattern 132 may be formed of an insulating material (e.g., silicon oxide, etc.). The pad pattern 134 may be formed of polysilicon having N-type conductivity, or may be a drain region. The pad pattern 134 may be arranged at a higher vertical height than the upper gate horizontal pattern 158U. For example, the lower surface of the pad pattern 134 may be at a higher vertical height than the upper surface of the uppermost upper gate horizontal pattern 158U. The pad pattern 134 of the vertical channel structure 124c may contact the second contact plug 175 described above. For example, the pad pattern 134 of the vertical channel structure 124c may be electrically connected to the second contact plug 175.

[0092] In example embodiments, the channel semiconductor layer 130 may pass through the gate horizontal patterns 158L, 158M1, 158M2, and 158U. When the vertical channel structure 124c further includes a semiconductor pattern 126, the semiconductor pattern 126 may pass through the lower gate horizontal pattern 158L, and the channel semiconductor layer 130 may pass through the middle gate horizontal patterns 158M1, 158M2, and the upper gate horizontal pattern 158U. The channel semiconductor layer 130 may be formed of a polysilicon layer. The semiconductor pattern 126 may also be referred to as a lower channel semiconductor layer.

[0093] In example embodiments, the semiconductor pattern 126 may also be referred to as a channel semiconductor layer. For example, the semiconductor pattern 126 may also be referred to as a lower channel semiconductor layer at a relatively lower portion, and the channel semiconductor layer 130 may also be referred to as an upper channel semiconductor layer at a relatively upper portion.

[0094] The gate dielectric structure 128 may include a tunnel dielectric 128c, an information storage layer 128b, and a blocking dielectric 128a. The information storage layer 128b may be disposed between the tunnel dielectric 128c and the blocking dielectric 128a. The blocking dielectric 128a may be disposed between the information storage layer 128b and the stacked structure 160. The tunnel dielectric 128c may be disposed between the information storage layer 128b and the channel semiconductor layer 130. The tunnel dielectric 128c may include silicon oxide and / or silicon oxide doped with impurities. The blocking dielectric 128a may include silicon oxide and / or a high-k dielectric. The information storage layer 128b may be formed of a material capable of storing information (e.g., silicon nitride).

[0095] The information storage layer 128b may include a semiconductor layer 130 between the channel semiconductor layer 130 and a word line (eg, Figure 1A and Figure 1BThe information storage layer 128b may be formed by a first intermediate gate horizontal pattern 158M1 and a second intermediate gate horizontal pattern 158M2 between word lines WL in the nonvolatile memory device. For example, electrons injected from the channel semiconductor layer 130 through the tunnel dielectric 128c into the information storage layer 128b may be captured and retained, or electrons captured in the information storage layer 128b may be released, depending on the operating conditions of the nonvolatile memory device (e.g., a flash memory device).

[0096] Therefore, as described above, the information storage layer 128b is located between the channel semiconductor layer 130 and the word line (eg, Figure 1A and Figure 1B The area between the first intermediate gate horizontal pattern 158M1 and the second intermediate gate horizontal pattern 158M2 of the word line WL in the word line WL can be defined as an information storage area, and these information storage areas can constitute Figure 1B The storage unit shown in (for example, Figure 1B The storage unit MCT in the device.

[0097] The interlayer insulating layer disposed between the first intermediate gate horizontal pattern 158M1a (which is located at a relatively upper portion in the first intermediate gate horizontal pattern 158M1) and the second intermediate gate horizontal pattern 158M2a (which is located at a relatively lower portion in the second intermediate gate horizontal pattern 158M2) may be referred to as an intermediate interlayer insulating layer 114a. The thickness of the intermediate interlayer insulating layer 114a may be substantially the same as the thickness of each interlayer insulating layer 114 located between the first intermediate gate horizontal patterns 158M1 and the thickness of each interlayer insulating layer 114 located between the second intermediate gate horizontal patterns 158M2. As used herein, thickness may refer to a thickness or height measured in a direction perpendicular to the top surface of the lower structure 103.

[0098] The vertical channel structure 124 c may include a first vertical region 124L, a second vertical region 124U located on the first vertical region 124L, and a width variation portion 124 v located between the first vertical region 124L and the second vertical region 124U.

[0099] In the vertical channel structure 124c, the first vertical region 124L may be a region passing through the lower gate horizontal pattern 158L and the first middle gate horizontal pattern 158M1, and the second vertical region 124U may be a region passing through the second middle gate horizontal pattern 158M2 and the upper gate horizontal pattern 158U.

[0100] The first vertical region 124L may include a lower region 124La and an upper region 124Lb located on the lower region 124La. The second vertical region 124U may include a lower region 124Ua and an upper region 124Ub located on the lower region 124Ua.

[0101] Each of the first vertical region 124L and the second vertical region 124U may have a constant regularity in the vertical direction Z away from the lower structure 103, and may have a variable width or a predictable variable width. For example, in the vertical channel structure 124c, the width of each of the first vertical region 124L and the second vertical region 124U may increase in the vertical direction away from the lower structure 103. For example, in the first vertical region 124L, the width of the lower region 124La relatively close to the lower structure 103 may be smaller than the width of the upper region 124Lb relatively far from the lower structure 103. In the second vertical region 124U, the width of the lower region 124Ua relatively close to the lower structure 103 may be smaller than the width of the upper region 124Ub relatively far from the lower structure 103.

[0102] The width of the upper region 124Lb of the first vertical region 124L may be greater than the width of the lower region 124La of the first vertical region 124L, and greater than the width of the lower region 124Ua of the second vertical region 124U. The width of the upper region 124Ub of the second vertical region 124U may be greater than the width of the lower region 124Ua of the second vertical region 124U, and greater than the width of the lower region 124La of the first vertical region 124L. In some embodiments, the width of the upper region 124Lb of the first vertical region 124L and the width of the upper region 124Ub of the second vertical region 124U may be the same, and the width of the lower region 124La of the first vertical region 124L and the width of the lower region 124Ua of the second vertical region 124U may be the same.

[0103] The upper region 124Lb of the first vertical region 124L and the lower region 124Ua of the second vertical region 124U may have different widths from each other. For example, the upper region 124Lb of the first vertical region 124L adjacent to the second vertical region 124U may have a first width W1, and the lower region 124Ua of the second vertical region 124U adjacent to the first vertical region 124L may have a second width W2 that is smaller than the first width W1.

[0104] In the vertical channel structure 124 c , the width variation portion 124 v may be a portion that varies from a first width W1 of an upper region 124Lb of the first vertical region 124L to a second width W2 of a lower region 124Ua of the second vertical region 124U.

[0105] One of the additional dielectric layers 155a of the additional dielectric layers 155 may cover the upper and lower surfaces of the first intermediate gate horizontal pattern 158M1a located at a relatively upper portion in the first intermediate gate horizontal pattern 158M1, and may cover the side surface of the first intermediate gate horizontal pattern 158M1a facing the vertical channel structure 124c. The width variation portion 124v of the vertical channel structure 124c may be disposed adjacent to a boundary between the intermediate interlayer insulating layer 114a and the additional dielectric layer 155a. For example, the upper surface of the width variation portion 124v of the vertical channel structure 124c may be coplanar with the upper surface of the additional dielectric layer 155a, and may face the lower surface of the intermediate interlayer insulating layer 114a. The intermediate interlayer insulating layer 114a may have the same thickness as the remaining interlayer insulating layers 114.

[0106] In example embodiments, the first vertical support structure 145 may have a variable width with constant regularity in a vertical direction away from the lower structure 103, or may have a predictable variable width. For example, the width of the first vertical support structure 145 may gradually increase in the vertical direction Z away from the lower structure 103. For example, when viewed in cross section, the sidewall of the first vertical support structure 145 may maintain a substantially constant angle relative to the top surface of the lower structure 103 along the entire length of the sidewall.

[0107] In example embodiments, the first vertical support structure 145 may have substantially the same width from a lower portion thereof to an upper portion thereof.For example, when viewed in cross section, the first vertical support structure 145 may have substantially vertical sidewalls.

[0108] Therefore, the first vertical support structure 145 may be formed without a width variation portion having a width varying between upper and lower regions as in the vertical channel structure 124c and thus may have a cross-sectional structure different from that of the vertical channel structure 124c.

[0109] In the interlayer insulating layer 114, the middle interlayer insulating layer 114a may be formed as a single layer. The embodiment is not limited thereto, but may be modified to include a plurality of layers. For example, Figure 8B It shows that Fig. 8A A cross-sectional view of a modified embodiment of an intermediate interlayer insulating layer 114a and a vertical channel structure 124c is shown.

[0110] In a modified embodiment, referring to Figure 8B In the interlayer insulating layer 114, the middle interlayer insulating layer (eg, Fig. 8AThe intermediate interlayer insulating layer 114a in the interlayer insulating layer 114a may be modified to include an intermediate interlayer insulating layer 114b including a first region 113a and a second region 113b located on the first region 113a. The width variation portion 124v of the vertical channel structure 124c may be arranged adjacent to the boundary between the first region 113a and the second region 113b. For example, the upper surface of the width variation portion 124v of the vertical channel structure 124c may be coplanar with the upper surface of the first region 113a and may face the lower surface of the second region 113b. The width variation portion 124v of the vertical channel structure 124c may be located at a higher vertical height than the first intermediate gate horizontal pattern 158M1. In the interlayer insulating layer 114, the intermediate interlayer insulating layer 114b including the first region 113a and the second region 113b may have the same thickness as the remaining interlayer insulating layers 114. Therefore, the interlayer insulating layers 114 may be formed to have the same thickness as each other.

[0111] Refer again Fig. 8A , the upper surface of the first vertical support structure 145 may be located at a higher vertical height than the upper surface of the vertical channel structure 124c. The embodiment is not limited thereto. Figure 8C It shows Fig. 8A sectional view of a modified embodiment of the first vertical support structure 145 in FIG.

[0112] In a modified embodiment, referring to Figure 8C , the first vertical support structure 145 may be modified to have an upper surface formed to be coplanar with an upper surface of the vertical channel structure 124c.

[0113] Refer again Figures 2 to 7B , the above-mentioned first vertical support structure 145 will be described again.

[0114] Reference Figures 2 to 7B , mainly refer to Figure 4 and Figure 6B , the first vertical support structure 145 may contact the partition structure 162. For example, the side wall of the first vertical support structure 145 may contact the side wall of the partition structure 162 over the entire vertical length of the first vertical support structure 145. When viewed in a top view, the first vertical support structure 145 may be a rectangle that contacts the partition structure 162 and extends in the width direction of the partition structure 162. The embodiment is not limited thereto. In the following, reference will be made to FIG. 9A to FIG. 9G Various modified embodiments of the first vertical supporting structure 145 are described. FIG. 9A to FIG. 9G is shown corresponding to Figure 4 145 is a top view of a plan area of ​​, used to illustrate various modified embodiments of the first vertical support structure 145.

[0115] In a modified embodiment, referring to Fig. 9AEach first vertical support structure 145a may be a pentagon, or a shape similar to a pentagon (e.g., a polygon having five linear sides). For example, each first vertical support structure 145a may extend from a portion having a first width d1 (measured as a width along the first horizontal direction X) in contact with the separation structure 162 in the second horizontal direction Y away from the separation structure 162, and may have a portion gradually decreasing from the first width d1 to the second width d2, so as to ensure as much as possible the portion of the pad region P in which the contact plug 178 is disposed.

[0116] When viewed in a plan view, the first vertical support structure 145 a may be mirror-symmetrical based on a boundary Pa between the pad regions P, and mirror-symmetrical between a pair of separation structures 162 adjacent to each other.

[0117] In another modified embodiment, referring to Fig. 9B Each of the first vertical supporting structures 145b may have a first portion d1′ and a second portion d2′, wherein the first portion d1′ has a first width, the second portion d2′ has a second width smaller than the first width and extends from a portion of the first portion d1′ in a direction away from the partition structure 162. In each of the first vertical supporting structures 145b, the first portion d1′ may be a portion in contact with the partition structure 162.

[0118] In each first vertical supporting structure 145b, the first portion d1' may be a rectangle or a shape similar to a rectangle, and the second portion d2' may be a rectangle or a shape similar to a rectangle.

[0119] In another modified embodiment, referring to Fig. 9C Each of the first vertical support structures 145c may be in a semicircular shape that is elongated in a direction away from the partition structure 162. For example, the semicircular shape of the first vertical support structure 145c may be elongated in a second horizontal direction Y that is perpendicular to the first horizontal direction X.

[0120] In another modified embodiment, referring to Fig.9D , each first vertical support structure 145d may be spaced apart from the separation structure 162. For example, the first vertical support structure 145d may not contact the separation structure 162. In a top view, each first vertical support structure 145d may be circular. In some embodiments, the first vertical support structures 145d may be symmetrically disposed around the first contact plug 178.

[0121] In another modified embodiment, referring to Fig.9E, each first vertical support structure 145e may be spaced apart from the separation structure 162 and may have an elongated elliptical shape. For example, the first vertical support structure 145e may include a first support member 145e1 and a second support member 145e2 having longitudinal axis directions different from each other. For example, the first support member 145e1 may have an elongated elliptical shape including a first short axis direction D2a and a first long axis direction D1a intersecting the first short axis direction D2a, and the second support member 145e2 may have an elongated elliptical shape including a second short axis direction D2b and a second long axis direction D1b intersecting the second short axis direction D2b. The first long axis direction D1a and the second long axis direction D1b may be directions intersecting each other. In some embodiments, the first long axis direction D1a and the second long axis direction D1b may be perpendicular to each other, and the first short axis direction D2a and the second short axis direction D2b may be perpendicular to each other. The first short axis direction D2a and the second short axis direction D2b may extend in a direction toward the adjacent first contact plug 178.

[0122] The first long axis direction D1a, the second long axis direction D1b, the first short axis direction D2a and the second short axis direction D2b may be inclined relative to both the longitudinal axis direction (e.g., the first horizontal direction X) and the width direction (e.g., the second horizontal direction Y) of the separation structure 162.

[0123] Reference Figures 2 to 7B , mainly refer to Figure 3 and Figure 4 , when viewed in a top view, the first contact plugs 178 may be sequentially arranged along an imaginary straight line in the first horizontal direction X. For example, the center points of the first contact plugs 178 between adjacent separation structures 162 may be aligned along an imaginary straight line in the first horizontal direction X. The embodiment is not limited thereto, but may be modified to have first contact plugs 178′ in a zigzag shape in the first horizontal direction X, such as Fig.9F and Figure 9G Now we will refer to Fig.9F and Figure 9G The first vertical support structure that may be modified and the first contact plug 178 ′ that may be in a zigzag shape as described above are described separately.

[0124] In a modified embodiment, referring to Fig.9F, the first contact plug 178′ may be zigzag-shaped in the first horizontal direction X. For example, between a pair of partition structures adjacent to each other in the partition structure 162 (for example, between any one of the main partition structures 162m and any one of the second auxiliary partition structures 162s2), a portion of the first contact plugs 178′ in the zigzag shape may be closer to or biased toward the main partition structure 162m, and the remaining portion thereof may be closer to or biased toward the second auxiliary partition structure 162s2. For example, assuming that an imaginary line extends along the first horizontal direction X and is centered between two adjacent partition structures 162, a first portion of the first contact plugs 178′ may be disposed between the centered imaginary line and one adjacent partition structure 162, and a second portion of the first contact plugs 178′ may be disposed between the centered imaginary line and another adjacent partition structure 162.

[0125] Each of the first vertical support structures 145 f may be spaced apart from the separation structure 162 , and may be disposed in a zigzag shape around the first contact plug 178 ′.

[0126] In example embodiments, the first vertical support structures 145 f may be elongated in the first horizontal direction X or may be rectangular in the first horizontal direction X. In some embodiments, a longitudinal axis of each first vertical support structure 145 f may extend in the first horizontal direction X and may be aligned with a center point of the first contact plug 178 ′.

[0127] In an example embodiment, each first vertical support structure 145f may overlap with the pad area P and may extend into the boundary area between the pad areas P. Each first vertical support structure 145f may overlap with two pad areas P. The area overlapping with any one of the two pad areas P may be relatively large. In this case, the term "overlap" may refer to a shape that will be observed in a top view. Therefore, when observed in the top view described herein, the area "overlap" may be understood as the area where the first vertical support structure 145f passes through the pad area P.

[0128] In example embodiments, based on one of the first contact plugs 178′, the first vertical support structures 145f arranged in the first horizontal direction X may include a pair of first vertical support structures 145f facing each other in the first horizontal direction X, wherein the first contact plug 178′ is located between the pair of first vertical support structures 145f.

[0129] In a modified embodiment, referring to Figure 9G , the first vertical support structure 145g can be arranged at Fig.9FThe first vertical support structure 145g may be disposed around the first contact plug 178' in a zigzag shape similar to the first contact plug 178' shown in FIG. 1 and may contact the separation structure 162. For example, the first vertical support structure 145g may be disposed at a position adjacent to the first contact plug 178'. Fig.9F , and may include a first portion 145g1 and a second portion 145g2, wherein the first portion 145g1 is spaced apart from the partition structure 162, and the second portion 145g2 extends from the first portion 145g1 to contact the partition structure 162 that is relatively close to the second portion 145g2. Figures 2 to 7B , each of the gate horizontal patterns 158L, 158M1, 158M2, and 158U may have substantially the same thickness as each other in the memory array region MA and the extension region EA. For example, in any one of the gate horizontal patterns 158L, 158M1, 158M2, and 158U, the thickness of the pad region located in the extension region EA may be substantially the same as the thickness of the horizontal pattern located in the memory array region MA. The embodiment is not limited thereto, and the thickness of the pad region may be greater than the thickness of other portions of the gate horizontal patterns 158L, 158M1, 158M2, and 158U. Now, reference will be made to Fig.10 Embodiments are described in which the pad region has a thickness increased in this manner. Fig.10 158M1 is a conceptual cross-sectional view illustrating a thickness of a pad region P of any one of the first and second intermediate gate horizontal patterns 158M1 and 158M2.

[0130] Reference Fig.10 In any one of the intermediate gate horizontal patterns 158M1 and 158M2, the thickness of the pad region P may be relatively increased compared to other portions. The first contact plug 178 may contact the pad region P having the increased thickness. The pad region P having the increased thickness may prevent the first contact plug 178 from passing through the pad region P.

[0131] Refer again Figures 2 to 7B , the lower structure 103 may be formed of a bulk semiconductor substrate. The embodiment is not limited thereto, and the lower structure 103 may be formed of a plurality of layers. Fig.11 An example embodiment of the lower structure 103 which may be formed of a plurality of layers as described above is described. Fig.11 It shows that it can be Figure 5A The cross-sectional view corresponds to a cross-sectional view of a modified embodiment of the lower structure 103 .

[0132] Reference Fig.11The lower structure 103 may include a lower substrate 100, a peripheral circuit structure 101a disposed on the lower substrate 100, an insulating structure 101b covering the peripheral circuit structure 101a, and an upper substrate 102 on the insulating structure 101b. The lower substrate 100 may be a single crystal silicon substrate, and the upper substrate 102 may be a polycrystalline silicon substrate.

[0133] Next, we will refer to Figures 12 to 15 A modified embodiment of a three-dimensional semiconductor device according to an example embodiment is described. Figures 12 to 15 middle, Fig.12 is a conceptual top view illustrating a three-dimensional semiconductor device according to example embodiments; Fig.13 yes Fig.12 An enlarged view of the area indicated by 'C' in FIG. Fig.14A is along Fig.13 A cross-sectional view taken along line Ib-Ib′ in FIG. Fig. 14B is along Fig.13 A cross-sectional view taken along line Vb-Vb′ in FIG. Fig.15 is a cross-sectional view conceptually showing a portion of the components. Figures 12 to 15 The three-dimensional semiconductor device described herein is similar to the Figures 2 to 7B Compared with the three-dimensional semiconductor device described above, the three-dimensional semiconductor device may also include a part of the components in a different manner and constitute the above reference Figures 2 to 7B The constituent elements of the described three-dimensional semiconductor device may be partially modified. Figures 2 to 7B The same components among the described components will be referred to without further explanation, and only modified components will be described.

[0134] Reference Figures 12 to 15 , in the first intermediate gate level pattern (eg, Figures 2 to 7B A portion of one or more first intermediate gate horizontal patterns located at a relatively upper portion of the first intermediate gate horizontal pattern 158M1 in the embodiment of the present invention may be replaced with a buffer horizontal pattern 151a. The buffer horizontal pattern 151a may be disposed between the remaining first intermediate gate horizontal patterns 158M1 and the second intermediate gate horizontal patterns 158M2.

[0135] The dummy intermediate gate horizontal pattern 158d may be disposed to have an end facing the buffer horizontal pattern 151a and may be located at the same vertical height as the buffer horizontal pattern 151a. In addition, the thickness of the buffer horizontal pattern 151a may be greater than the thickness of each of the gate horizontal patterns 158L, 158M1, 158M2, and 158U.

[0136] The protection pattern 116 may be disposed between the separation structure 162 and the buffer horizontal pattern 151a. The protection pattern 116 may be formed of a material having an etching selectivity relative to the buffer horizontal pattern 151a. For example, the buffer horizontal pattern 151a may be formed of an insulating material such as silicon nitride, and the protection pattern 116 may be formed of an insulating material such as silicon oxide. Alternatively, the buffer horizontal pattern 151a may be formed of a polysilicon material, and the protection pattern 116 may be formed of an insulating material such as silicon oxide.

[0137] In example embodiments, the protection pattern 116 may be disposed on side surfaces of the main separation structure 162 m and the first auxiliary separation structure 162 s 1 in the memory array area MA, and may extend into a portion of the extension area EA.

[0138] In example embodiments, the buffer horizontal pattern 151a may be disposed between the protection patterns 116. The upper surface of the protection pattern 116 may be coplanar with the upper surface of the uppermost buffer horizontal pattern 151a. The lower surface of the protection pattern 116 may be at a lower vertical height than the lower surface of the lowermost buffer horizontal pattern 151a.

[0139] like Fig. 14B and Fig.15 As shown in Figures 2 to 7B The width variation portion 124 v of the vertical channel structure 124 c shown in FIG. 1 may be disposed adjacent to an upper surface of the buffer horizontal pattern 151 a .

[0140] In an embodiment, Figures 2 to 7B In the first intermediate gate level pattern (eg, Figures 2 to 7B A portion of one or more first intermediate gate horizontal patterns located at a relatively upper portion in the first intermediate gate horizontal pattern 158M1 in the embodiment may be replaced with a buffer horizontal pattern 151a formed of an insulating material. Thus, it is possible to prevent the first intermediate gate horizontal pattern (e.g., Figures 2 to 7B The electrical effect or electric field effect occurring in one or more first intermediate gate horizontal patterns located relatively upper and the width variation portion 124v of the vertical channel structure 124c in the first intermediate gate horizontal pattern 158M1) can be improved, thereby improving the performance of the semiconductor device.

[0141] like Figures 2 to 7B The middle interlayer insulating layer 114a in the interlayer insulating layer 114 shown in FIG. 1 may be located between the buffer horizontal pattern 151a and the second middle gate horizontal pattern 158M2. For example, the middle interlayer insulating layer 114a in the interlayer insulating layer 114 may be disposed over the uppermost buffer horizontal pattern 151a.

[0142] In such Figures 2 to 7BIn the vertical channel structure 124c shown in FIG, the width variation portion 124v may be disposed adjacent to a boundary between the middle interlayer insulating layer 114a and the buffer horizontal pattern 151a. For example, the width variation portion 124v may be disposed adjacent to a lower surface of the middle interlayer insulating layer 114a or adjacent to an upper surface of the buffer horizontal pattern 151a.

[0143] In example embodiments, the width variation portion 124v may be disposed at substantially the same vertical height as the lower surface of the middle interlayer insulating layer 114a. For example, the upper surface of the width variation portion 124v of the vertical channel structure 124c may be coplanar with the upper surface of the buffer horizontal pattern 151a and may face the lower surface of the middle interlayer insulating layer 114a. Embodiments are not limited thereto, but may be as follows. Fig.16 Modify as shown. Fig.16 It shows Fig.15 2 is a cross-sectional view of a modified embodiment of an intermediate interlayer insulating layer 114a and a vertical channel structure 124c in FIG.

[0144] In a modified embodiment, referring to Fig.16 , in the interlayer insulating layer 114, the intermediate interlayer insulating layer 114a may be modified to include the first region 113a and the intermediate interlayer insulating layer 114b of the second region 113b located on the first region 113a, and the width variation portion 124v of the vertical channel structure 124c may be located at a higher vertical height than the upper surface of the buffer horizontal pattern 151a. For example, the width variation portion 124v of the vertical channel structure 124c may be disposed adjacent to a boundary between the first region 113a and the second region 113b. For example, the upper surface of the width variation portion 124v of the vertical channel structure 124c may be coplanar with the upper surface of the first region 113a, and may face the lower surface of the second region 113b.

[0145] Refer again Figures 12 to 15 , the vertical channel structure 124c may include a first vertical region 124L, a second vertical region 124U located on the first vertical region 124L, and a width variation portion 124v whose width varies between the first vertical region 124L and the second vertical region 124U. The embodiment is not limited thereto, and may be as follows: Fig.17 Modify as shown in . Fig.17 It shows Fig.15 2 is a cross-sectional view of a modified embodiment of the vertical channel structure 124c in FIG.

[0146] In a modified embodiment, referring to Fig.17, the vertical channel structure 124c may include a first vertical region 124L, a second vertical region 124U located on the first vertical region 124L, and a third vertical region 124M between the first vertical region 124L and the second vertical region 124U. For example, the third vertical region 124M may be on the first vertical region 124L, and the second vertical region 124U may be on the third vertical region 124M.

[0147] In an embodiment, the first vertical region 124L may be referred to as a "lower vertical region", the second vertical region 124U may be referred to as an "upper vertical region", and the third vertical region 124M may be referred to as an "intermediate vertical region". Hereinafter, the first vertical region 124L will be referred to as a "lower vertical region", the second vertical region 124U will be referred to as an "upper vertical region", and the third vertical region 124M will be referred to as an "intermediate vertical region".

[0148] The vertical channel structure 124c may include a first width variation portion 124v1 having a width variation between the middle vertical region 124M and the upper vertical region 124U and a second width variation portion 124v2 having a width variation between the middle vertical region 124M and the lower vertical region 124L. In some embodiments, the first width variation portion 124v1 may have an upper surface parallel to the upper surface of the lower structure 103 and coplanar with the upper surface of the buffer horizontal pattern 151a, and the second width variation portion 124v2 may have a lower surface parallel to the upper surface of the lower structure 103.

[0149] The lower vertical region 124L, the middle vertical region 124M, and the upper vertical region 124U may be structures whose widths tend to increase in a direction away from the lower structure 103 .

[0150] The width of the lower region of the middle vertical region 124M may be greater than the width of the upper region of the lower vertical region 124L. The width of the upper region of the middle vertical region 124M may be greater than the width of the lower region of the upper vertical region 124U.

[0151] The first width variation portion 124v1 may be a portion where the width varies from the lower region of the upper vertical region 124U having a relatively narrow width to the upper region of the middle vertical region 124M having a relatively wide width. The second width variation portion 124v2 may be a portion where the width varies from the lower region of the middle vertical region 124M having a relatively wide width to the upper region of the lower vertical region 124L having a relatively narrow width.

[0152] The first and second width variation portions 124v1 and 124v2 and the middle vertical region 124M are disposed between the first and second middle gate horizontal patterns 158M1 and 158M2. For example, the upper surface of the first width variation portion 124v1 may be at a lower vertical height than the second middle gate horizontal pattern 158M2, and the lower surface of the second width variation portion 124v2 may be at a higher vertical height than the first middle gate horizontal pattern 158M1.

[0153] Refer again Figures 12 to 15 The protection pattern 116 is formed on the side surfaces of the main separation structure 162m and the first auxiliary separation structure 162s1 in the memory array region MA, and may be spaced apart from the second auxiliary separation structure 162s2. The embodiment is not limited thereto, but may be as follows. Fig.18 Modify as shown. Fig.18 It is shown that Fig.12 1 is a top view of a plane corresponding to the plane of , used to illustrate a modified embodiment of the protection pattern 116.

[0154] In a modified embodiment, referring to Fig.18 The protection pattern 216 can be set on the side surfaces of the main separation structure 162m and the first auxiliary separation structure 162s1 in the memory array area MA, and can extend from the memory array area MA to a portion of the extension area EA to cover the side surface of the second auxiliary separation structure 162s2 in the portion of the extension area EA.

[0155] The protection pattern 216 may include a first protection pattern 216a and a second protection pattern 216b, the first protection pattern 216a is arranged on the side surface of the main separation structure 162m in the storage array area MA and extends from the storage array area MA to a portion of the extension area EA, and the second protection pattern 216b is arranged on the side surface of the first auxiliary separation structure 162s1 in the storage array area MA and extends from the storage array area MA to a portion of the extension area EA to cover the side surface of the second auxiliary separation structure 162s2 having an end facing the first auxiliary separation structure 162s1.

[0156] The protection pattern 216 may include the first protection pattern 216a and the second protection pattern 216b described above. The embodiment is not limited thereto, and may further include a third protection pattern 216c, such as Fig.19 Refer to Figures 19 to 21C Example embodiments of a three-dimensional semiconductor device including such a modifiable protection pattern 216 are described. Fig.19 It is shown that Fig.18 The top view of the plane corresponding to the plane of Fig.18 A modified embodiment of the protection pattern 216 shown in; Fig. 20 yes Fig.19 An enlarged view of the area indicated by 'D' in FIG. Fig.21A is along Fig. 20 A cross-sectional view taken along line Ib-Ib′ in FIG. Fig. 21B is along Fig. 20 A cross-sectional view taken along line IIb-IIb′; Fig. 21C is along Fig. 20 A cross-sectional view taken along line IIIb-IIIb′ in FIG. Figures 19 to 21C The three-dimensional semiconductor device described herein is similar to the Figures 2 to 7B Compared with the three-dimensional semiconductor device described above, a part of the components may be included in a different manner. Figures 12 to 15 Components of a three-dimensional semiconductor device described herein. Figures 12 to 15 Components that are the same as those described will be referred to without further explanation, and only modified portions of the components to be modified will be described.

[0157] Reference Figures 19 to 21C In addition to the first protection pattern 216a and the second protection pattern 216b described above, the protection pattern 216 may further include a third protection pattern 216c disposed on the side surface of the remaining second auxiliary separation structure 162s2 spaced apart from the second protection pattern 216b. As described above, the first protection pattern 216a and the second protection pattern 216b may extend from the memory array area MA to a portion of the extension area EA. The third protection pattern 216c may be disposed in a portion of the extension area EA and may be spaced apart from the memory array area MA.

[0158] In example embodiments, when the first vertical support structure 145 described above contacts the separation structure 162 , the first vertical support structure 145 may pass through the protection pattern 216 .

[0159] In example embodiments, in the extension area EA, the protection patterns 216 may be cut by the first vertical support structure 145 to be arranged spaced apart from each other in the first horizontal direction X, such as: Fig. 20 as shown in .

[0160] In an exemplary embodiment, when the setting is as follows Fig.9D and Fig.9E 162 is spaced apart from the partition structure 162. Fig.9D The first vertical support structure 145d in Fig.9E When the first vertical support structure 145e is formed, the protection pattern 216 can extend continuously in the first horizontal direction X, such as Fig.19 shown.

[0161] Refer to above Figures 12 to 16 The buffer level pattern described (e.g., Fig.14A The buffer horizontal pattern 151a in FIG. 1 may be modified to extend to a portion provided with a dummy horizontal pattern (eg, Fig.14A The buffer horizontal pattern 151b of the region of the dummy horizontal pattern 158d) is formed, wherein the dummy horizontal pattern is aligned with the buffer horizontal pattern (eg, Fig.14A The buffer horizontal pattern 151a) in FIG. 1 is located at the same height. Fig. 21C As shown in , the buffer horizontal pattern 151b may have a pad region P. As described above, the pad region P of the buffer horizontal pattern 151b may be a dummy pad. In example embodiments, the first contact plug 178 described above may pass through the pad region P of the buffer horizontal pattern 151b and may contact the gate horizontal patterns 158M1 and 158M2 located at a position lower than that of the buffer horizontal pattern 151b. Embodiments are not limited thereto, and may be as follows. Fig. 22 Modify as shown in . Fig. 22 It can be shown that it can correspond to Fig. 21C , and may indicate a first contact plug 178 that may be modified.

[0162] In a modified embodiment, referring to Fig. 22 , the first contact plug 178 may also make contact with the pad region P of the buffer horizontal pattern 151 b without passing through the pad region P of the buffer horizontal pattern 151 b.

[0163] As mentioned above Figures 2 to 16 As described above, the vertical channel structure 124c and the second vertical support structure 124d may have the same cross-sectional structure or the same cross-sectional shape as each other.

[0164] In some embodiments, the vertical channel structure 124 c and the second vertical support structure 124 d may have a different cross-sectional structure or cross-sectional shape from the first vertical support structure 145 .

[0165] In some embodiments, the vertical channel structure 124c and the second vertical support structure 124d may further include a plurality of material layers more than the material layers constituting the first vertical support structure 145. For example, the first vertical support structure 145 may include a silicon oxide layer, and compared with the first vertical support structure 145, the vertical channel structure 124c may further include material layers constituting the gate dielectric structure 128, the channel semiconductor layer 130, and the pad pattern 134.

[0166] In some embodiments, the interlayer insulating layer 114 may include an intermediate interlayer insulating layer 114a adjacent to the width variation portion 124v of the vertical channel structure 124c, and the intermediate interlayer insulating layer 114a may have the same thickness as the interlayer insulating layer adjacent to the intermediate interlayer insulating layer 114a in the vertical direction Z among the interlayer insulating layers 114.

[0167] In some embodiments, the upper surface of the first vertical support structure 145 can be located at a different vertical height from the upper surface of the vertical channel structure 124c. For example, the distance between the upper surface of the first vertical support structure 145 and the upper surface of the lower structure 103 can be greater than the distance between the upper surface of the vertical channel structure 124c and the upper surface of the lower structure 103.

[0168] Next, we will refer to FIG. 23A to FIG. 28B An example embodiment of a method of forming a three-dimensional semiconductor device as described above is described. FIG. 23A to FIG. 28B middle, Fig.23A , Fig.24A , Fig.25A , Fig.26A , Fig.27A and Fig.28A is along Fig. 20 A cross-sectional view taken along line Ib-Ib′ in FIG. Fig. 23B , Fig. 24B , Fig.25B , Fig.26B , Fig.27B and Fig.28B is along Fig. 20 The cross-sectional view taken along line IIIb-IIIb′ in FIG. Fig. 20 Line Ib-Ib′ and line IIIb-IIIb′ are described, but combined with FIG. 23A to FIG. 28B The disclosed method of forming a three-dimensional semiconductor device is suitable for Figures 2 to 8A Embodiments disclosed in .

[0169] Reference Fig. 20 , Fig.23A and Fig. 23B , the lowest insulating layer 106, the lowest mold layer 108, and the lower insulating layer 110 may be sequentially formed on the lower structure 103. A mold layer 112 and an interlayer insulating layer 114 alternately stacked on the lower insulating layer 110 may be formed. The lowest mold layer 108 and the mold layer 112 may be formed of the same first material as each other, and the lowest insulating layer 106, the lower insulating layer 110, and the interlayer insulating layer 114 may be formed of the same second material as each other. The second material may have an etching selectivity relative to the first material. For example, the second material may be silicon nitride, and the first material may be silicon oxide.

[0170] The protection pattern 116 may be formed through the uppermost mold layer among the mold layers 112 or through the uppermost and second uppermost mold layers among the mold layers 112. The protection pattern 116 may be formed of a material having an etch selectivity with respect to the mold layer 112, for example, silicon oxide.

[0171] A sacrificial vertical structure 118 may be formed, extending in a vertical direction on the lower structure 103 to pass through the lowermost insulating layer 106, the lowermost mold layer 108, the lower insulating layer 110, the interlayer insulating layer 114, and the mold layer 112. The sacrificial vertical structure 118 may be formed of a material having an etching selectivity with respect to the mold layer 112 and the interlayer insulating layer 114, and is not limited to a specific material.

[0172] Each of the sacrificial vertical structures 118 may be formed to increase in width in a vertical direction away from the lower structure 103 .

[0173] In example embodiments, after forming the protection pattern 116, the sacrificial vertical structure 118 may be formed. Alternatively, after forming the sacrificial vertical structure 118, the protection pattern 116 may be formed.

[0174] Reference Fig. 20 , Fig.24A and Fig. 24B Interlayer insulating layers 114 and mold layers 112 may be repeatedly stacked on the lower structure 103 on which the protection pattern 116 and the sacrificial vertical structure 118 are formed. An upper insulating layer 120 may be formed on the uppermost mold layer of the mold layers 112. The upper insulating layer 120 may be formed to be thicker than each interlayer insulating layer 114.

[0175] Reference Fig. 20 , Fig.25A and Fig.25B , it can be located at a height lower than the sacrificial vertical structure (e.g. Fig.24A The interlayer insulating layer 114, the mold layer 112, and the upper insulating layer 120 are patterned at a position higher than the sacrificial vertical structure 118 in the middle or above the position of the sacrificial vertical structure to form an exposed sacrificial vertical structure (eg, Fig.24A Each hole may be formed to have a width that decreases from the upper portion to the lower portion. The sacrificial vertical structure (e.g., Fig.24A A portion of the upper surface of the sacrificial vertical structure 118 in the embodiment may be exposed by the holes. Subsequently, the exposed sacrificial vertical structure (eg, Fig.24A The sacrificial vertical structure 118 in the hole is used to extend the hole to the lower structure 103. Subsequently, a Figures 2 to 8A The same vertical channel structure 124c as described above can be formed simultaneously with the vertical channel structure 124c. Figures 2 to 8A The second vertical support structure shown in Figure 7B The second vertical support structure 124d) may be formed with Figures 2 to 8A For example, the vertical channel structure 124c may have a width variation portion as described above (eg, Fig. 8A The width variation portion 124v).

[0176] The operation of forming the vertical channel structure 124c may include: forming a semiconductor pattern 126 in the lower area of ​​the hole; forming a gate dielectric structure 128 on the sidewall of the hole on the semiconductor pattern 126; forming a channel semiconductor layer 130 covering the inner wall of the hole; forming a vertical core pattern 132 that partially fills the hole; and forming a pad pattern 134 that fills the remaining portion of the hole.

[0177] The photolithography and etching processes for patterning the lowermost mold layer 108 and the mold layer 112 on the lower structure 103 may be repeated multiple times to form the same Figures 2 to 8A The step shape shown in FIG. 1 corresponds to the step shape formed by the pad region P. After forming such a step shape, a first capping insulating layer 139 may be formed to cover the region formed by the step shape.

[0178] A second cover insulating layer 142 may be formed to cover the upper insulating layer 120 and the first cover insulating layer 139. A first vertical support structure 145 may be formed to pass through the first and second cover insulating layers 139 and 142, and through the lowermost insulating layer 106, the lowermost mold layer 108, the lower insulating layer 110, the interlayer insulating layer 114, and the mold layer 112.

[0179] The formation operation of the first vertical support structure 145 may include forming a hole through the lowermost insulating layer 106 , the lowermost mold layer 108 , the lower insulating layer 110 , the interlayer insulating layer 114 , and the mold layer 112 ; and then filling the hole with an insulating material such as silicon oxide.

[0180] The first vertical support structure 145 may be formed after forming the vertical channel structure 124c including the width variation portion 124v described above. Therefore, the photolithography and etching processes for patterning the lowermost mold layer 108 and the mold layer 112 on the lower structure 103 may be repeated multiple times to stably form the same structure as described above without any defects. Figures 2 to 8A The step shape shown in FIG. 1 corresponds to the step shape formed by the pad area P. Therefore, the step shape shown in FIG. 1 can be formed without causing any defects. Figures 2 to 8A The reliable pad area P shown in .

[0181] According to an embodiment, each interlayer insulating layer 114 may be formed to have the same thickness. Since the interlayer insulating layers 114 are formed to have the same thickness, the lowermost mold layer 108 and the mold layer 112 on the lower structure 103 may be patterned to stably form the same structure as the lower structure 103 without causing any defects. Figures 2 to 8A The step shape shown in FIG. 1 corresponds to the step shape in which the pad areas P are arranged.

[0182] Reference Fig. 20 , Fig.26A and Fig.26B , a third cover insulating layer 148 may be formed on the second cover insulating layer 142. Figures 2 to 8A The separation groove 150 is formed in a position corresponding to the separation structure 162 shown in FIG. The separation groove 150 may pass through the protection pattern 116. For example, the separation groove 150 may be formed to penetrate the central area of ​​the protection pattern 116. The mold layer located between the protection patterns 116 may not be exposed by the separation groove 150 and may be defined as a buffer horizontal pattern 151b. The remaining mold layers 112 and the lowermost mold layer 108 may be exposed by the separation groove 150.

[0183] Reference Fig. 20 , Fig.27A and Fig.27B , the mold layer 112 and the lowermost mold layer 108 exposed by the separation groove 150 may be removed to form an empty space 152. The first vertical support structure 145, the vertical channel structure 124c, and the second vertical support structure (eg, Figure 7B The second vertical support structure 124d) in the embodiment may prevent the interlayer insulating layer 114 from collapsing or warping.

[0184] Reference Fig. 20 , Fig.28A and Fig.28B , can be in empty space (for example, Fig.27A and Fig.27B An additional dielectric layer 155 and gate horizontal patterns 158L, 158M1, 158M2, and 158U are sequentially formed in the empty space 152 in the separation trench 150. The gate horizontal patterns 158L, 158M1, 158M2, and 158U may be formed of a conductive material such as a metal nitride (e.g., TiN, etc.) and / or a metal (e.g., W, etc.). A separation structure 162 may be formed in the separation trench 150. The formation operation of the separation structure 162 may include forming a first separation layer 165 on the side surface of the separation trench 150 and forming a second separation layer 168 filling the separation trench 150.

[0185] Refer again Figures 20 to 21C, a fourth cover insulating layer 172 may be formed on the third cover insulating layer 148. Subsequently, an operation of forming a plug may be performed. For example, a second contact plug 175 may be formed to sequentially pass through the second cover insulating layer 142, the third cover insulating layer 148, and the fourth cover insulating layer 172, and to contact the upper portion of the vertical channel structure 124c. A first contact plug 178 may be formed to sequentially pass through the first cover insulating layer 139, the second cover insulating layer 142, the third cover insulating layer 148, and the fourth cover insulating layer 172 in the extension area EA, and to contact the gate horizontal patterns 158L, 158M1, 158M2, and 158U.

[0186] According to example embodiments, a three-dimensional semiconductor device may increase the number of gates stacked in a vertical direction to improve integration.

[0187] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modified embodiments and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A three-dimensional semiconductor device, comprising: Silicon substrate; A stacked structure, the stacked structure is located on the silicon substrate and includes interlayer insulating layers and gate horizontal patterns alternately stacked in a vertical direction, the vertical direction being perpendicular to an upper surface of the silicon substrate, wherein the gate horizontal pattern is stacked on the silicon substrate in the vertical direction in a first region and extends from the first region in a horizontal direction, the horizontal direction being parallel to the upper surface of the silicon substrate, wherein the gate horizontal pattern includes a pad region arranged in a staircase shape in a second region adjacent to the first region, and the gate horizontal pattern includes a first gate horizontal pattern and a second gate horizontal pattern located on the first gate horizontal pattern; a covering insulating layer, wherein the covering insulating layer is located on the stacked structure; a vertical channel structure disposed in a first hole passing through the stacked structure in the first region; a vertical support structure disposed in a second hole penetrating the cover insulating layer and the stack structure in the second region and spaced apart from the vertical channel structure in the horizontal direction; and a separation structure extending in the vertical direction to pass through the stack structure and the cover insulating layer; a buffer horizontal pattern formed of an insulating material and disposed between the first gate horizontal pattern and the second gate horizontal pattern; and a protection pattern disposed between the separation structure and the buffer horizontal pattern and formed of an insulating material different from an insulating material of the buffer horizontal pattern, Wherein, the gate horizontal pattern is arranged between the separation structures, The vertical channel structure includes a vertical core pattern, a channel layer on a side surface of the vertical core pattern, a data storage layer on an outer surface of the channel layer, and a pad pattern on the vertical core pattern. wherein the cross-sectional shape of the vertical channel structure in the vertical direction is different from the cross-sectional shape of the vertical support structure in the vertical direction, The vertical channel structure includes a first vertical region, a second vertical region, and a width variation portion between the first vertical region and the second vertical region. wherein the interlayer insulating layer includes an intermediate interlayer insulating layer adjacent to the width variation portion, wherein the middle interlayer insulating layer and the interlayer insulating layer adjacent to the middle interlayer insulating layer in the vertical direction have substantially the same thickness, wherein the vertical support structure comprises a single layer of insulating material, Wherein, the width of the vertical support structure is greater than the width of the vertical channel structure, wherein the lower end of the vertical support structure and the lower end of the vertical channel structure are located at a height lower than the upper surface of the silicon substrate, and The upper end of the side wall of the second hole is located at a height higher than the upper end of the side wall of the first hole.

2. The three-dimensional semiconductor device according to claim 1, wherein: The vertical channel structure contacts the silicon substrate, wherein the vertical support structure contacts the silicon substrate, and Wherein, the middle interlayer insulating layer contacts the upper surface of the width variation portion.

3. The three-dimensional semiconductor device according to claim 1, wherein: The lower end of the vertical channel structure is located at a different height than the lower end of the vertical support structure.

4. The three-dimensional semiconductor device according to claim 1, wherein: The first vertical region includes a lower region and an upper region located above the lower region, The second vertical region includes a lower region and an upper region located above the lower region of the second vertical region, The width of the upper region of the first vertical region is greater than the width of the lower region of the first vertical region, and A width of the upper region of the second vertical region is greater than a width of the lower region of the second vertical region.

5. The three-dimensional semiconductor device according to claim 4, wherein: The upper region of the first vertical region adjacent to the second vertical region has a first width, The lower region of the second vertical region adjacent to the first vertical region has a second width smaller than the first width, and The width change portion is a portion that changes from the first width to the second width between the upper region of the first vertical region and the lower region of the second vertical region.

6. The three-dimensional semiconductor device according to claim 1, wherein: As the first vertical region and the second vertical region extend in a direction away from the silicon substrate, a width of each of the first vertical region and the second vertical region changes regularly in the vertical direction, An upper region of the first vertical region and a lower region of the second vertical region have different widths from each other, and The width variation portion is a portion where a width varies between the upper region of the first vertical region and the lower region of the second vertical region.

7. The three-dimensional semiconductor device according to claim 1, wherein: The width of the vertical support structure varies regularly in the vertical direction away from the silicon substrate.

8. The three-dimensional semiconductor device according to claim 1, wherein: The single insulating material layer is formed of silicon oxide.

9. The three-dimensional semiconductor device according to claim 1, further comprising: Lower substrate; as well as a peripheral circuit structure, the peripheral circuit structure being located on the lower substrate, Wherein, the silicon substrate is located on the peripheral circuit structure.

10. The three-dimensional semiconductor device according to claim 1, wherein: The gate horizontal pattern is formed of a conductive material.

11. A three-dimensional semiconductor device, comprising: Silicon substrate; A stacked structure, the stacked structure is disposed on the silicon substrate and includes a gate horizontal pattern, wherein the gate horizontal pattern includes a lower gate horizontal pattern, an upper gate horizontal pattern located on the lower gate horizontal pattern, and an intermediate gate horizontal pattern located between the lower gate horizontal pattern and the upper gate horizontal pattern; a covering insulating layer, wherein the covering insulating layer is located on the stacked structure; A vertical channel structure, the vertical channel structure is disposed in a first hole passing through the stacked structure in a vertical direction, and comprises a channel semiconductor layer and a storage layer, wherein the vertical direction is perpendicular to an upper surface of the silicon substrate; a vertical support structure disposed in a second hole passing through the cover insulating layer and the stack structure and spaced apart from the vertical channel structure; a separation structure extending in the vertical direction to pass through the stack structure and the cover insulating layer; a buffer horizontal pattern formed of an insulating material and disposed between the lower gate horizontal pattern and the upper gate horizontal pattern; and a protection pattern disposed between the separation structure and the buffer horizontal pattern and formed of an insulating material different from an insulating material of the buffer horizontal pattern, Wherein, the gate horizontal pattern is arranged between the separation structures, The gate horizontal pattern is stacked on the silicon substrate in the vertical direction in the first region and extends from the first region in the horizontal direction, and the horizontal direction is parallel to the upper surface of the silicon substrate. wherein the gate horizontal pattern includes a pad region arranged in a staircase shape in a second region adjacent to the first region, The stacked structure further comprises interlayer insulating layers stacked alternately, wherein the intermediate gate horizontal pattern is inserted between the interlayer insulating layers. Wherein, the interlayer insulating layers have the same thickness, Wherein, the intermediate gate horizontal patterns have the same thickness, wherein the vertical channel structure is arranged in the first region, and the vertical support structure is arranged in the second region, The vertical channel structure includes a middle portion passing through the middle gate horizontal pattern and the interlayer insulating layer, The middle portion of the vertical channel structure includes a first vertical region, a second vertical region, and a width variation portion between the first vertical region and the second vertical region. wherein a width of the first vertical region adjacent to the second vertical region is greater than a width of the second vertical region adjacent to the first vertical region, wherein the upper surface of the width variation portion contacts a corresponding one of the interlayer insulating layers, The vertical channel structure includes a vertical core pattern, a channel layer on a side surface of the vertical core pattern, a data storage layer on an outer surface of the channel layer, and a pad pattern on the vertical core pattern. wherein the vertical support structure comprises a single layer of insulating material, Wherein, the width of the vertical support structure is greater than the width of the vertical channel structure, and wherein the lower end of the vertical support structure and the lower end of the vertical channel structure are located at a height lower than the upper surface of the silicon substrate, and The upper end of the side wall of the second hole is located at a height higher than the upper end of the side wall of the first hole.

12. The three-dimensional semiconductor device according to claim 11, wherein: The vertical channel structure contacts the silicon substrate, wherein the vertical support structure contacts the silicon substrate, and Wherein, the lower end of the vertical channel structure is located at a different height from the lower end of the vertical support structure.

13. The three-dimensional semiconductor device according to claim 11, wherein: An upper surface of the vertical support structure and an upper surface of the vertical channel structure are located at different heights.

14. The three-dimensional semiconductor device according to claim 11, wherein: A distance between an upper surface of the vertical support structure and the upper surface of the silicon substrate is greater than a distance between an upper surface of the vertical channel structure and the upper surface of the silicon substrate.

15. The three-dimensional semiconductor device according to claim 11, further comprising: Lower substrate; as well as a peripheral circuit structure, the peripheral circuit structure being located on the lower substrate, Wherein, the silicon substrate is located on the peripheral circuit structure.

16. A three-dimensional semiconductor device, comprising: Silicon substrate; A stacked structure, the stacked structure is located on the silicon substrate and includes interlayer insulating layers and gate horizontal patterns alternately stacked in a vertical direction, the vertical direction is perpendicular to an upper surface of the silicon substrate, the gate horizontal patterns are stacked in a memory array region along the vertical direction, and extend from the memory array region to an extension region in a horizontal direction, wherein the gate horizontal pattern has a pad region arranged in a staircase shape in the extension region, and the gate horizontal pattern includes a lower gate horizontal pattern and an upper gate horizontal pattern located on the lower gate horizontal pattern; a covering insulating layer, wherein the covering insulating layer is located on the stacked structure; A vertical channel structure, the vertical channel structure is disposed in the memory array region and is disposed in a first hole passing through the stack structure along the vertical direction; a first vertical support structure disposed in the extension region and disposed within a second hole passing through the cover insulating layer and the pad region of the stack structure; a separation structure, the separation structure passing through the gate horizontal pattern; a buffer horizontal pattern formed of an insulating material and disposed between the lower gate horizontal pattern and the upper gate horizontal pattern; and a protection pattern disposed between the separation structure and the buffer horizontal pattern and formed of an insulating material different from an insulating material of the buffer horizontal pattern, Wherein, the gate horizontal pattern is arranged between the separation structures, The stacking structure includes a lower stacking portion and an upper stacking portion located on the lower stacking portion. wherein the lower stacked portion includes the lower gate horizontal pattern in the gate horizontal pattern and the lower interlayer insulating layer in the interlayer insulating layer, wherein the upper stacked portion includes the upper gate horizontal pattern in the gate horizontal pattern and the upper interlayer insulating layer in the interlayer insulating layer, The vertical channel structure includes a lower vertical region passing through the lower stacking portion and an upper vertical region passing through the upper stacking portion. The vertical channel structure includes a first side surface of the lower vertical region, a second side surface of the upper vertical region, and a horizontal surface extending from the first side surface and the second side surface. The width of the lower vertical region adjacent to the upper vertical region is greater than the width of the upper vertical region adjacent to the lower vertical region. wherein the interlayer insulating layer comprises an intermediate interlayer insulating layer in contact with the horizontal surface of the vertical channel structure, wherein the middle interlayer insulating layer and the interlayer insulating layer adjacent to the middle interlayer insulating layer in the vertical direction have substantially the same thickness, The vertical channel structure includes a vertical core pattern, a channel layer on a side surface of the vertical core pattern, a data storage layer on an outer surface of the channel layer, and a pad pattern on the vertical core pattern. wherein the first vertical support structure comprises a single layer of insulating material, Wherein, the width of the first vertical support structure is greater than the width of the vertical channel structure, wherein the lower end of the first vertical support structure and the lower end of the vertical channel structure are located at a height lower than the upper surface of the silicon substrate, and The upper end of the side wall of the second hole is located at a height higher than the upper end of the side wall of the first hole.

17. The three-dimensional semiconductor device according to claim 16, further comprising: a second vertical support structure, the second vertical support structure being disposed in the memory array region and passing through the gate horizontal pattern, Wherein, the vertical channel structure and the second vertical support structure each include a plurality of material layers different from the material layers of the first vertical support structure.

18. The three-dimensional semiconductor device according to claim 16, wherein: The gate horizontal pattern and the first vertical support structure are both in contact with the separation structure.

19. The three-dimensional semiconductor device according to claim 16, wherein: The vertical channel structure contacts the silicon substrate, wherein the first vertical support structure contacts the silicon substrate, and Wherein, the lower end of the vertical channel structure is located at a different height from the lower end of the first vertical support structure.

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